1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../regd.h" 30 #include "../cam.h" 31 #include "../ps.h" 32 #include "../pci.h" 33 #include "reg.h" 34 #include "def.h" 35 #include "phy.h" 36 #include "../rtl8723com/phy_common.h" 37 #include "dm.h" 38 #include "../rtl8723com/dm_common.h" 39 #include "fw.h" 40 #include "../rtl8723com/fw_common.h" 41 #include "led.h" 42 #include "hw.h" 43 #include "../pwrseqcmd.h" 44 #include "pwrseq.h" 45 #include "btc.h" 46 47 #define LLT_CONFIG 5 48 49 static void _rtl8723e_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 50 u8 set_bits, u8 clear_bits) 51 { 52 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 53 struct rtl_priv *rtlpriv = rtl_priv(hw); 54 55 rtlpci->reg_bcn_ctrl_val |= set_bits; 56 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 57 58 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); 59 } 60 61 static void _rtl8723e_stop_tx_beacon(struct ieee80211_hw *hw) 62 { 63 struct rtl_priv *rtlpriv = rtl_priv(hw); 64 u8 tmp1byte; 65 66 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 67 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 68 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 69 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 70 tmp1byte &= ~(BIT(0)); 71 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 72 } 73 74 static void _rtl8723e_resume_tx_beacon(struct ieee80211_hw *hw) 75 { 76 struct rtl_priv *rtlpriv = rtl_priv(hw); 77 u8 tmp1byte; 78 79 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 80 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 81 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 82 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 83 tmp1byte |= BIT(1); 84 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 85 } 86 87 static void _rtl8723e_enable_bcn_sub_func(struct ieee80211_hw *hw) 88 { 89 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(1)); 90 } 91 92 static void _rtl8723e_disable_bcn_sub_func(struct ieee80211_hw *hw) 93 { 94 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(1), 0); 95 } 96 97 void rtl8723e_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 98 { 99 struct rtl_priv *rtlpriv = rtl_priv(hw); 100 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 101 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 102 103 switch (variable) { 104 case HW_VAR_RCR: 105 *((u32 *)(val)) = rtlpci->receive_config; 106 break; 107 case HW_VAR_RF_STATE: 108 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 109 break; 110 case HW_VAR_FWLPS_RF_ON:{ 111 enum rf_pwrstate rfstate; 112 u32 val_rcr; 113 114 rtlpriv->cfg->ops->get_hw_reg(hw, 115 HW_VAR_RF_STATE, 116 (u8 *)(&rfstate)); 117 if (rfstate == ERFOFF) { 118 *((bool *)(val)) = true; 119 } else { 120 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 121 val_rcr &= 0x00070000; 122 if (val_rcr) 123 *((bool *)(val)) = false; 124 else 125 *((bool *)(val)) = true; 126 } 127 break; 128 } 129 case HW_VAR_FW_PSMODE_STATUS: 130 *((bool *)(val)) = ppsc->fw_current_inpsmode; 131 break; 132 case HW_VAR_CORRECT_TSF:{ 133 u64 tsf; 134 u32 *ptsf_low = (u32 *)&tsf; 135 u32 *ptsf_high = ((u32 *)&tsf) + 1; 136 137 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 138 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 139 140 *((u64 *)(val)) = tsf; 141 142 break; 143 } 144 case HAL_DEF_WOWLAN: 145 break; 146 default: 147 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 148 "switch case %#x not processed\n", variable); 149 break; 150 } 151 } 152 153 void rtl8723e_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 154 { 155 struct rtl_priv *rtlpriv = rtl_priv(hw); 156 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 157 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 158 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 159 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 160 u8 idx; 161 162 switch (variable) { 163 case HW_VAR_ETHER_ADDR:{ 164 for (idx = 0; idx < ETH_ALEN; idx++) { 165 rtl_write_byte(rtlpriv, (REG_MACID + idx), 166 val[idx]); 167 } 168 break; 169 } 170 case HW_VAR_BASIC_RATE:{ 171 u16 b_rate_cfg = ((u16 *)val)[0]; 172 u8 rate_index = 0; 173 174 b_rate_cfg = b_rate_cfg & 0x15f; 175 b_rate_cfg |= 0x01; 176 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff); 177 rtl_write_byte(rtlpriv, REG_RRSR + 1, 178 (b_rate_cfg >> 8) & 0xff); 179 while (b_rate_cfg > 0x1) { 180 b_rate_cfg = (b_rate_cfg >> 1); 181 rate_index++; 182 } 183 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 184 rate_index); 185 break; 186 } 187 case HW_VAR_BSSID:{ 188 for (idx = 0; idx < ETH_ALEN; idx++) { 189 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 190 val[idx]); 191 } 192 break; 193 } 194 case HW_VAR_SIFS:{ 195 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 196 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); 197 198 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 199 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 200 201 if (!mac->ht_enable) 202 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 203 0x0e0e); 204 else 205 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 206 *((u16 *)val)); 207 break; 208 } 209 case HW_VAR_SLOT_TIME:{ 210 u8 e_aci; 211 212 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 213 "HW_VAR_SLOT_TIME %x\n", val[0]); 214 215 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 216 217 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 218 rtlpriv->cfg->ops->set_hw_reg(hw, 219 HW_VAR_AC_PARAM, 220 (u8 *)(&e_aci)); 221 } 222 break; 223 } 224 case HW_VAR_ACK_PREAMBLE:{ 225 u8 reg_tmp; 226 u8 short_preamble = (bool)(*(u8 *)val); 227 228 reg_tmp = (mac->cur_40_prime_sc) << 5; 229 if (short_preamble) 230 reg_tmp |= 0x80; 231 232 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 233 break; 234 } 235 case HW_VAR_AMPDU_MIN_SPACE:{ 236 u8 min_spacing_to_set; 237 u8 sec_min_space; 238 239 min_spacing_to_set = *((u8 *)val); 240 if (min_spacing_to_set <= 7) { 241 sec_min_space = 0; 242 243 if (min_spacing_to_set < sec_min_space) 244 min_spacing_to_set = sec_min_space; 245 246 mac->min_space_cfg = ((mac->min_space_cfg & 247 0xf8) | 248 min_spacing_to_set); 249 250 *val = min_spacing_to_set; 251 252 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 253 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 254 mac->min_space_cfg); 255 256 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 257 mac->min_space_cfg); 258 } 259 break; 260 } 261 case HW_VAR_SHORTGI_DENSITY:{ 262 u8 density_to_set; 263 264 density_to_set = *((u8 *)val); 265 mac->min_space_cfg |= (density_to_set << 3); 266 267 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 268 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 269 mac->min_space_cfg); 270 271 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 272 mac->min_space_cfg); 273 274 break; 275 } 276 case HW_VAR_AMPDU_FACTOR:{ 277 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 }; 278 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97}; 279 u8 factor_toset; 280 u8 *p_regtoset = NULL; 281 u8 index = 0; 282 283 if ((rtlpriv->btcoexist.bt_coexistence) && 284 (rtlpriv->btcoexist.bt_coexist_type == 285 BT_CSR_BC4)) 286 p_regtoset = regtoset_bt; 287 else 288 p_regtoset = regtoset_normal; 289 290 factor_toset = *((u8 *)val); 291 if (factor_toset <= 3) { 292 factor_toset = (1 << (factor_toset + 2)); 293 if (factor_toset > 0xf) 294 factor_toset = 0xf; 295 296 for (index = 0; index < 4; index++) { 297 if ((p_regtoset[index] & 0xf0) > 298 (factor_toset << 4)) 299 p_regtoset[index] = 300 (p_regtoset[index] & 0x0f) | 301 (factor_toset << 4); 302 303 if ((p_regtoset[index] & 0x0f) > 304 factor_toset) 305 p_regtoset[index] = 306 (p_regtoset[index] & 0xf0) | 307 (factor_toset); 308 309 rtl_write_byte(rtlpriv, 310 (REG_AGGLEN_LMT + index), 311 p_regtoset[index]); 312 } 313 314 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 315 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 316 factor_toset); 317 } 318 break; 319 } 320 case HW_VAR_AC_PARAM:{ 321 u8 e_aci = *((u8 *)val); 322 323 rtl8723_dm_init_edca_turbo(hw); 324 325 if (rtlpci->acm_method != EACMWAY2_SW) 326 rtlpriv->cfg->ops->set_hw_reg(hw, 327 HW_VAR_ACM_CTRL, 328 (u8 *)(&e_aci)); 329 break; 330 } 331 case HW_VAR_ACM_CTRL:{ 332 u8 e_aci = *((u8 *)val); 333 union aci_aifsn *p_aci_aifsn = 334 (union aci_aifsn *)(&mac->ac[0].aifs); 335 u8 acm = p_aci_aifsn->f.acm; 336 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 337 338 acm_ctrl = 339 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 340 341 if (acm) { 342 switch (e_aci) { 343 case AC0_BE: 344 acm_ctrl |= ACMHW_BEQEN; 345 break; 346 case AC2_VI: 347 acm_ctrl |= ACMHW_VIQEN; 348 break; 349 case AC3_VO: 350 acm_ctrl |= ACMHW_VOQEN; 351 break; 352 default: 353 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 354 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 355 acm); 356 break; 357 } 358 } else { 359 switch (e_aci) { 360 case AC0_BE: 361 acm_ctrl &= (~ACMHW_BEQEN); 362 break; 363 case AC2_VI: 364 acm_ctrl &= (~ACMHW_VIQEN); 365 break; 366 case AC3_VO: 367 acm_ctrl &= (~ACMHW_VOQEN); 368 break; 369 default: 370 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 371 "switch case %#x not processed\n", 372 e_aci); 373 break; 374 } 375 } 376 377 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 378 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 379 acm_ctrl); 380 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 381 break; 382 } 383 case HW_VAR_RCR:{ 384 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); 385 rtlpci->receive_config = ((u32 *)(val))[0]; 386 break; 387 } 388 case HW_VAR_RETRY_LIMIT:{ 389 u8 retry_limit = ((u8 *)(val))[0]; 390 391 rtl_write_word(rtlpriv, REG_RL, 392 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 393 retry_limit << RETRY_LIMIT_LONG_SHIFT); 394 break; 395 } 396 case HW_VAR_DUAL_TSF_RST: 397 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 398 break; 399 case HW_VAR_EFUSE_BYTES: 400 rtlefuse->efuse_usedbytes = *((u16 *)val); 401 break; 402 case HW_VAR_EFUSE_USAGE: 403 rtlefuse->efuse_usedpercentage = *((u8 *)val); 404 break; 405 case HW_VAR_IO_CMD: 406 rtl8723e_phy_set_io_cmd(hw, (*(enum io_type *)val)); 407 break; 408 case HW_VAR_WPA_CONFIG: 409 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val)); 410 break; 411 case HW_VAR_SET_RPWM:{ 412 u8 rpwm_val; 413 414 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 415 udelay(1); 416 417 if (rpwm_val & BIT(7)) { 418 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 419 (*(u8 *)val)); 420 } else { 421 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 422 ((*(u8 *)val) | BIT(7))); 423 } 424 425 break; 426 } 427 case HW_VAR_H2C_FW_PWRMODE:{ 428 u8 psmode = (*(u8 *)val); 429 430 if (psmode != FW_PS_ACTIVE_MODE) 431 rtl8723e_dm_rf_saving(hw, true); 432 433 rtl8723e_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); 434 break; 435 } 436 case HW_VAR_FW_PSMODE_STATUS: 437 ppsc->fw_current_inpsmode = *((bool *)val); 438 break; 439 case HW_VAR_H2C_FW_JOINBSSRPT:{ 440 u8 mstatus = (*(u8 *)val); 441 u8 tmp_regcr, tmp_reg422; 442 bool b_recover = false; 443 444 if (mstatus == RT_MEDIA_CONNECT) { 445 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, 446 NULL); 447 448 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 449 rtl_write_byte(rtlpriv, REG_CR + 1, 450 (tmp_regcr | BIT(0))); 451 452 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3)); 453 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0); 454 455 tmp_reg422 = 456 rtl_read_byte(rtlpriv, 457 REG_FWHW_TXQ_CTRL + 2); 458 if (tmp_reg422 & BIT(6)) 459 b_recover = true; 460 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 461 tmp_reg422 & (~BIT(6))); 462 463 rtl8723e_set_fw_rsvdpagepkt(hw, 0); 464 465 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0); 466 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4)); 467 468 if (b_recover) { 469 rtl_write_byte(rtlpriv, 470 REG_FWHW_TXQ_CTRL + 2, 471 tmp_reg422); 472 } 473 474 rtl_write_byte(rtlpriv, REG_CR + 1, 475 (tmp_regcr & ~(BIT(0)))); 476 } 477 rtl8723e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val)); 478 479 break; 480 } 481 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:{ 482 rtl8723e_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); 483 break; 484 } 485 case HW_VAR_AID:{ 486 u16 u2btmp; 487 488 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 489 u2btmp &= 0xC000; 490 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, 491 (u2btmp | mac->assoc_id)); 492 493 break; 494 } 495 case HW_VAR_CORRECT_TSF:{ 496 u8 btype_ibss = ((u8 *)(val))[0]; 497 498 if (btype_ibss) 499 _rtl8723e_stop_tx_beacon(hw); 500 501 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3)); 502 503 rtl_write_dword(rtlpriv, REG_TSFTR, 504 (u32)(mac->tsf & 0xffffffff)); 505 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 506 (u32)((mac->tsf >> 32) & 0xffffffff)); 507 508 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0); 509 510 if (btype_ibss) 511 _rtl8723e_resume_tx_beacon(hw); 512 513 break; 514 } 515 case HW_VAR_FW_LPS_ACTION:{ 516 bool b_enter_fwlps = *((bool *)val); 517 u8 rpwm_val, fw_pwrmode; 518 bool fw_current_inps; 519 520 if (b_enter_fwlps) { 521 rpwm_val = 0x02; /* RF off */ 522 fw_current_inps = true; 523 rtlpriv->cfg->ops->set_hw_reg(hw, 524 HW_VAR_FW_PSMODE_STATUS, 525 (u8 *)(&fw_current_inps)); 526 rtlpriv->cfg->ops->set_hw_reg(hw, 527 HW_VAR_H2C_FW_PWRMODE, 528 (u8 *)(&ppsc->fwctrl_psmode)); 529 530 rtlpriv->cfg->ops->set_hw_reg(hw, 531 HW_VAR_SET_RPWM, 532 (u8 *)(&rpwm_val)); 533 } else { 534 rpwm_val = 0x0C; /* RF on */ 535 fw_pwrmode = FW_PS_ACTIVE_MODE; 536 fw_current_inps = false; 537 rtlpriv->cfg->ops->set_hw_reg(hw, 538 HW_VAR_SET_RPWM, 539 (u8 *)(&rpwm_val)); 540 rtlpriv->cfg->ops->set_hw_reg(hw, 541 HW_VAR_H2C_FW_PWRMODE, 542 (u8 *)(&fw_pwrmode)); 543 544 rtlpriv->cfg->ops->set_hw_reg(hw, 545 HW_VAR_FW_PSMODE_STATUS, 546 (u8 *)(&fw_current_inps)); 547 } 548 break; 549 } 550 default: 551 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 552 "switch case %#x not processed\n", variable); 553 break; 554 } 555 } 556 557 static bool _rtl8723e_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 558 { 559 struct rtl_priv *rtlpriv = rtl_priv(hw); 560 bool status = true; 561 long count = 0; 562 u32 value = _LLT_INIT_ADDR(address) | 563 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); 564 565 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 566 567 do { 568 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 569 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 570 break; 571 572 if (count > POLLING_LLT_THRESHOLD) { 573 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 574 "Failed to polling write LLT done at address %d!\n", 575 address); 576 status = false; 577 break; 578 } 579 } while (++count); 580 581 return status; 582 } 583 584 static bool _rtl8723e_llt_table_init(struct ieee80211_hw *hw) 585 { 586 struct rtl_priv *rtlpriv = rtl_priv(hw); 587 unsigned short i; 588 u8 txpktbuf_bndy; 589 u8 maxpage; 590 bool status; 591 u8 ubyte; 592 593 #if LLT_CONFIG == 1 594 maxpage = 255; 595 txpktbuf_bndy = 252; 596 #elif LLT_CONFIG == 2 597 maxpage = 127; 598 txpktbuf_bndy = 124; 599 #elif LLT_CONFIG == 3 600 maxpage = 255; 601 txpktbuf_bndy = 174; 602 #elif LLT_CONFIG == 4 603 maxpage = 255; 604 txpktbuf_bndy = 246; 605 #elif LLT_CONFIG == 5 606 maxpage = 255; 607 txpktbuf_bndy = 246; 608 #endif 609 610 rtl_write_byte(rtlpriv, REG_CR, 0x8B); 611 612 #if LLT_CONFIG == 1 613 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c); 614 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c); 615 #elif LLT_CONFIG == 2 616 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010); 617 #elif LLT_CONFIG == 3 618 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484); 619 #elif LLT_CONFIG == 4 620 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c); 621 #elif LLT_CONFIG == 5 622 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000); 623 624 rtl_write_dword(rtlpriv, REG_RQPN, 0x80ac1c29); 625 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x03); 626 #endif 627 628 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy)); 629 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 630 631 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 632 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 633 634 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); 635 rtl_write_byte(rtlpriv, REG_PBP, 0x11); 636 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 637 638 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 639 status = _rtl8723e_llt_write(hw, i, i + 1); 640 if (true != status) 641 return status; 642 } 643 644 status = _rtl8723e_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 645 if (true != status) 646 return status; 647 648 for (i = txpktbuf_bndy; i < maxpage; i++) { 649 status = _rtl8723e_llt_write(hw, i, (i + 1)); 650 if (true != status) 651 return status; 652 } 653 654 status = _rtl8723e_llt_write(hw, maxpage, txpktbuf_bndy); 655 if (true != status) 656 return status; 657 658 rtl_write_byte(rtlpriv, REG_CR, 0xff); 659 ubyte = rtl_read_byte(rtlpriv, REG_RQPN + 3); 660 rtl_write_byte(rtlpriv, REG_RQPN + 3, ubyte | BIT(7)); 661 662 return true; 663 } 664 665 static void _rtl8723e_gen_refresh_led_state(struct ieee80211_hw *hw) 666 { 667 struct rtl_priv *rtlpriv = rtl_priv(hw); 668 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 669 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 670 struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0; 671 672 if (rtlpriv->rtlhal.up_first_time) 673 return; 674 675 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 676 rtl8723e_sw_led_on(hw, pled0); 677 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 678 rtl8723e_sw_led_on(hw, pled0); 679 else 680 rtl8723e_sw_led_off(hw, pled0); 681 } 682 683 static bool _rtl8712e_init_mac(struct ieee80211_hw *hw) 684 { 685 struct rtl_priv *rtlpriv = rtl_priv(hw); 686 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 687 688 unsigned char bytetmp; 689 unsigned short wordtmp; 690 u16 retry = 0; 691 u16 tmpu2b; 692 bool mac_func_enable; 693 694 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 695 bytetmp = rtl_read_byte(rtlpriv, REG_CR); 696 if (bytetmp == 0xFF) 697 mac_func_enable = true; 698 else 699 mac_func_enable = false; 700 701 /* HW Power on sequence */ 702 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 703 PWR_INTF_PCI_MSK, Rtl8723_NIC_ENABLE_FLOW)) 704 return false; 705 706 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2); 707 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp | BIT(4)); 708 709 /* eMAC time out function enable, 0x369[7]=1 */ 710 bytetmp = rtl_read_byte(rtlpriv, 0x369); 711 rtl_write_byte(rtlpriv, 0x369, bytetmp | BIT(7)); 712 713 /* ePHY reg 0x1e bit[4]=1 using MDIO interface, 714 * we should do this before Enabling ASPM backdoor. 715 */ 716 do { 717 rtl_write_word(rtlpriv, 0x358, 0x5e); 718 udelay(100); 719 rtl_write_word(rtlpriv, 0x356, 0xc280); 720 rtl_write_word(rtlpriv, 0x354, 0xc290); 721 rtl_write_word(rtlpriv, 0x358, 0x3e); 722 udelay(100); 723 rtl_write_word(rtlpriv, 0x358, 0x5e); 724 udelay(100); 725 tmpu2b = rtl_read_word(rtlpriv, 0x356); 726 retry++; 727 } while (tmpu2b != 0xc290 && retry < 100); 728 729 if (retry >= 100) { 730 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 731 "InitMAC(): ePHY configure fail!!!\n"); 732 return false; 733 } 734 735 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 736 rtl_write_word(rtlpriv, REG_CR + 1, 0x06); 737 738 if (!mac_func_enable) { 739 if (!_rtl8723e_llt_table_init(hw)) 740 return false; 741 } 742 743 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 744 rtl_write_byte(rtlpriv, REG_HISRE, 0xff); 745 746 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff); 747 748 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 749 wordtmp &= 0xf; 750 wordtmp |= 0xF771; 751 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 752 753 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 754 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 755 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF); 756 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); 757 758 rtl_write_byte(rtlpriv, 0x4d0, 0x0); 759 760 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 761 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) & 762 DMA_BIT_MASK(32)); 763 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 764 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma & 765 DMA_BIT_MASK(32)); 766 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 767 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 768 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 769 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 770 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 771 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 772 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 773 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 774 rtl_write_dword(rtlpriv, REG_HQ_DESA, 775 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma & 776 DMA_BIT_MASK(32)); 777 rtl_write_dword(rtlpriv, REG_RX_DESA, 778 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma & 779 DMA_BIT_MASK(32)); 780 781 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x74); 782 783 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 784 785 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 786 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); 787 do { 788 retry++; 789 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 790 } while ((retry < 200) && (bytetmp & BIT(7))); 791 792 _rtl8723e_gen_refresh_led_state(hw); 793 794 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); 795 796 return true; 797 } 798 799 static void _rtl8723e_hw_configure(struct ieee80211_hw *hw) 800 { 801 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 802 struct rtl_priv *rtlpriv = rtl_priv(hw); 803 u8 reg_bw_opmode; 804 u32 reg_ratr, reg_prsr; 805 806 reg_bw_opmode = BW_OPMODE_20MHZ; 807 reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG | 808 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; 809 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 810 811 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); 812 813 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 814 815 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr); 816 817 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 818 819 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); 820 821 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); 822 823 rtl_write_word(rtlpriv, REG_RL, 0x0707); 824 825 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); 826 827 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 828 829 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 830 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 831 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 832 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 833 834 if ((rtlpriv->btcoexist.bt_coexistence) && 835 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) 836 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431); 837 else 838 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); 839 840 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); 841 842 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); 843 844 rtlpci->reg_bcn_ctrl_val = 0x1f; 845 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 846 847 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 848 849 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 850 851 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); 852 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 853 854 if ((rtlpriv->btcoexist.bt_coexistence) && 855 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) { 856 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 857 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402); 858 } else { 859 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 860 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 861 } 862 863 if ((rtlpriv->btcoexist.bt_coexistence) && 864 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) 865 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); 866 else 867 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666); 868 869 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); 870 871 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); 872 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); 873 874 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); 875 876 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); 877 878 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); 879 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); 880 881 rtl_write_dword(rtlpriv, 0x394, 0x1); 882 } 883 884 static void _rtl8723e_enable_aspm_back_door(struct ieee80211_hw *hw) 885 { 886 struct rtl_priv *rtlpriv = rtl_priv(hw); 887 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 888 889 rtl_write_byte(rtlpriv, 0x34b, 0x93); 890 rtl_write_word(rtlpriv, 0x350, 0x870c); 891 rtl_write_byte(rtlpriv, 0x352, 0x1); 892 893 if (ppsc->support_backdoor) 894 rtl_write_byte(rtlpriv, 0x349, 0x1b); 895 else 896 rtl_write_byte(rtlpriv, 0x349, 0x03); 897 898 rtl_write_word(rtlpriv, 0x350, 0x2718); 899 rtl_write_byte(rtlpriv, 0x352, 0x1); 900 } 901 902 void rtl8723e_enable_hw_security_config(struct ieee80211_hw *hw) 903 { 904 struct rtl_priv *rtlpriv = rtl_priv(hw); 905 u8 sec_reg_value; 906 907 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 908 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 909 rtlpriv->sec.pairwise_enc_algorithm, 910 rtlpriv->sec.group_enc_algorithm); 911 912 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 913 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 914 "not open hw encryption\n"); 915 return; 916 } 917 918 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE; 919 920 if (rtlpriv->sec.use_defaultkey) { 921 sec_reg_value |= SCR_TXUSEDK; 922 sec_reg_value |= SCR_RXUSEDK; 923 } 924 925 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 926 927 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 928 929 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 930 "The SECR-value %x\n", sec_reg_value); 931 932 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 933 934 } 935 936 int rtl8723e_hw_init(struct ieee80211_hw *hw) 937 { 938 struct rtl_priv *rtlpriv = rtl_priv(hw); 939 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 940 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 941 struct rtl_phy *rtlphy = &(rtlpriv->phy); 942 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 943 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 944 bool rtstatus = true; 945 int err; 946 u8 tmp_u1b; 947 unsigned long flags; 948 949 rtlpriv->rtlhal.being_init_adapter = true; 950 /* As this function can take a very long time (up to 350 ms) 951 * and can be called with irqs disabled, reenable the irqs 952 * to let the other devices continue being serviced. 953 * 954 * It is safe doing so since our own interrupts will only be enabled 955 * in a subsequent step. 956 */ 957 local_save_flags(flags); 958 local_irq_enable(); 959 rtlhal->fw_ready = false; 960 961 rtlpriv->intf_ops->disable_aspm(hw); 962 rtstatus = _rtl8712e_init_mac(hw); 963 if (rtstatus != true) { 964 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n"); 965 err = 1; 966 goto exit; 967 } 968 969 err = rtl8723_download_fw(hw, false, FW_8723A_POLLING_TIMEOUT_COUNT); 970 if (err) { 971 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 972 "Failed to download FW. Init HW without FW now..\n"); 973 err = 1; 974 goto exit; 975 } 976 rtlhal->fw_ready = true; 977 978 rtlhal->last_hmeboxnum = 0; 979 rtl8723e_phy_mac_config(hw); 980 /* because last function modify RCR, so we update 981 * rcr var here, or TP will unstable for receive_config 982 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx 983 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 984 */ 985 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); 986 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 987 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 988 989 rtl8723e_phy_bb_config(hw); 990 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 991 rtl8723e_phy_rf_config(hw); 992 if (IS_VENDOR_UMC_A_CUT(rtlhal->version)) { 993 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); 994 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); 995 } else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) { 996 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE); 997 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31); 998 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425); 999 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200); 1000 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053); 1001 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201); 1002 } 1003 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 1004 RF_CHNLBW, RFREG_OFFSET_MASK); 1005 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 1006 RF_CHNLBW, RFREG_OFFSET_MASK); 1007 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1008 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1009 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); 1010 _rtl8723e_hw_configure(hw); 1011 rtl_cam_reset_all_entry(hw); 1012 rtl8723e_enable_hw_security_config(hw); 1013 1014 ppsc->rfpwr_state = ERFON; 1015 1016 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1017 _rtl8723e_enable_aspm_back_door(hw); 1018 rtlpriv->intf_ops->enable_aspm(hw); 1019 1020 rtl8723e_bt_hw_init(hw); 1021 1022 if (ppsc->rfpwr_state == ERFON) { 1023 rtl8723e_phy_set_rfpath_switch(hw, 1); 1024 if (rtlphy->iqk_initialized) { 1025 rtl8723e_phy_iq_calibrate(hw, true); 1026 } else { 1027 rtl8723e_phy_iq_calibrate(hw, false); 1028 rtlphy->iqk_initialized = true; 1029 } 1030 1031 rtl8723e_dm_check_txpower_tracking(hw); 1032 rtl8723e_phy_lc_calibrate(hw); 1033 } 1034 1035 tmp_u1b = efuse_read_1byte(hw, 0x1FA); 1036 if (!(tmp_u1b & BIT(0))) { 1037 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); 1038 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n"); 1039 } 1040 1041 if (!(tmp_u1b & BIT(4))) { 1042 tmp_u1b = rtl_read_byte(rtlpriv, 0x16); 1043 tmp_u1b &= 0x0F; 1044 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80); 1045 udelay(10); 1046 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90); 1047 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n"); 1048 } 1049 rtl8723e_dm_init(hw); 1050 exit: 1051 local_irq_restore(flags); 1052 rtlpriv->rtlhal.being_init_adapter = false; 1053 return err; 1054 } 1055 1056 static enum version_8723e _rtl8723e_read_chip_version(struct ieee80211_hw *hw) 1057 { 1058 struct rtl_priv *rtlpriv = rtl_priv(hw); 1059 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1060 enum version_8723e version = 0x0000; 1061 u32 value32; 1062 1063 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 1064 if (value32 & TRP_VAUX_EN) { 1065 version = (enum version_8723e)(version | 1066 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); 1067 /* RTL8723 with BT function. */ 1068 version = (enum version_8723e)(version | 1069 ((value32 & BT_FUNC) ? CHIP_8723 : 0)); 1070 1071 } else { 1072 /* Normal mass production chip. */ 1073 version = (enum version_8723e) NORMAL_CHIP; 1074 version = (enum version_8723e)(version | 1075 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); 1076 /* RTL8723 with BT function. */ 1077 version = (enum version_8723e)(version | 1078 ((value32 & BT_FUNC) ? CHIP_8723 : 0)); 1079 if (IS_CHIP_VENDOR_UMC(version)) 1080 version = (enum version_8723e)(version | 1081 ((value32 & CHIP_VER_RTL_MASK)));/* IC version (CUT) */ 1082 if (IS_8723_SERIES(version)) { 1083 value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS); 1084 /* ROM code version. */ 1085 version = (enum version_8723e)(version | 1086 ((value32 & RF_RL_ID)>>20)); 1087 } 1088 } 1089 1090 if (IS_8723_SERIES(version)) { 1091 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 1092 rtlphy->polarity_ctl = ((value32 & WL_HWPDN_SL) ? 1093 RT_POLARITY_HIGH_ACT : 1094 RT_POLARITY_LOW_ACT); 1095 } 1096 switch (version) { 1097 case VERSION_TEST_UMC_CHIP_8723: 1098 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1099 "Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n"); 1100 break; 1101 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT: 1102 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1103 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT.\n"); 1104 break; 1105 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT: 1106 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1107 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT.\n"); 1108 break; 1109 default: 1110 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1111 "Chip Version ID: Unknown. Bug?\n"); 1112 break; 1113 } 1114 1115 if (IS_8723_SERIES(version)) 1116 rtlphy->rf_type = RF_1T1R; 1117 1118 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n", 1119 (rtlphy->rf_type == RF_2T2R) ? "RF_2T2R" : "RF_1T1R"); 1120 1121 return version; 1122 } 1123 1124 static int _rtl8723e_set_media_status(struct ieee80211_hw *hw, 1125 enum nl80211_iftype type) 1126 { 1127 struct rtl_priv *rtlpriv = rtl_priv(hw); 1128 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc; 1129 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1130 u8 mode = MSR_NOLINK; 1131 1132 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0); 1133 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD, 1134 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n"); 1135 1136 switch (type) { 1137 case NL80211_IFTYPE_UNSPECIFIED: 1138 mode = MSR_NOLINK; 1139 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1140 "Set Network type to NO LINK!\n"); 1141 break; 1142 case NL80211_IFTYPE_ADHOC: 1143 mode = MSR_ADHOC; 1144 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1145 "Set Network type to Ad Hoc!\n"); 1146 break; 1147 case NL80211_IFTYPE_STATION: 1148 mode = MSR_INFRA; 1149 ledaction = LED_CTL_LINK; 1150 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1151 "Set Network type to STA!\n"); 1152 break; 1153 case NL80211_IFTYPE_AP: 1154 mode = MSR_AP; 1155 ledaction = LED_CTL_LINK; 1156 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1157 "Set Network type to AP!\n"); 1158 break; 1159 default: 1160 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1161 "Network type %d not support!\n", type); 1162 return 1; 1163 break; 1164 } 1165 1166 /* MSR_INFRA == Link in infrastructure network; 1167 * MSR_ADHOC == Link in ad hoc network; 1168 * Therefore, check link state is necessary. 1169 * 1170 * MSR_AP == AP mode; link state is not cared here. 1171 */ 1172 if (mode != MSR_AP && 1173 rtlpriv->mac80211.link_state < MAC80211_LINKED) { 1174 mode = MSR_NOLINK; 1175 ledaction = LED_CTL_NO_LINK; 1176 } 1177 if (mode == MSR_NOLINK || mode == MSR_INFRA) { 1178 _rtl8723e_stop_tx_beacon(hw); 1179 _rtl8723e_enable_bcn_sub_func(hw); 1180 } else if (mode == MSR_ADHOC || mode == MSR_AP) { 1181 _rtl8723e_resume_tx_beacon(hw); 1182 _rtl8723e_disable_bcn_sub_func(hw); 1183 } else { 1184 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1185 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 1186 mode); 1187 } 1188 1189 rtl_write_byte(rtlpriv, MSR, bt_msr | mode); 1190 rtlpriv->cfg->ops->led_control(hw, ledaction); 1191 if (mode == MSR_AP) 1192 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1193 else 1194 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1195 return 0; 1196 } 1197 1198 void rtl8723e_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1199 { 1200 struct rtl_priv *rtlpriv = rtl_priv(hw); 1201 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1202 u32 reg_rcr = rtlpci->receive_config; 1203 1204 if (rtlpriv->psc.rfpwr_state != ERFON) 1205 return; 1206 1207 if (check_bssid) { 1208 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1209 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1210 (u8 *)(®_rcr)); 1211 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1212 } else if (!check_bssid) { 1213 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1214 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0); 1215 rtlpriv->cfg->ops->set_hw_reg(hw, 1216 HW_VAR_RCR, (u8 *)(®_rcr)); 1217 } 1218 } 1219 1220 int rtl8723e_set_network_type(struct ieee80211_hw *hw, 1221 enum nl80211_iftype type) 1222 { 1223 struct rtl_priv *rtlpriv = rtl_priv(hw); 1224 1225 if (_rtl8723e_set_media_status(hw, type)) 1226 return -EOPNOTSUPP; 1227 1228 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1229 if (type != NL80211_IFTYPE_AP) 1230 rtl8723e_set_check_bssid(hw, true); 1231 } else { 1232 rtl8723e_set_check_bssid(hw, false); 1233 } 1234 1235 return 0; 1236 } 1237 1238 /* don't set REG_EDCA_BE_PARAM here 1239 * because mac80211 will send pkt when scan 1240 */ 1241 void rtl8723e_set_qos(struct ieee80211_hw *hw, int aci) 1242 { 1243 struct rtl_priv *rtlpriv = rtl_priv(hw); 1244 1245 rtl8723_dm_init_edca_turbo(hw); 1246 switch (aci) { 1247 case AC1_BK: 1248 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 1249 break; 1250 case AC0_BE: 1251 break; 1252 case AC2_VI: 1253 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 1254 break; 1255 case AC3_VO: 1256 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 1257 break; 1258 default: 1259 RT_ASSERT(false, "invalid aci: %d !\n", aci); 1260 break; 1261 } 1262 } 1263 1264 void rtl8723e_enable_interrupt(struct ieee80211_hw *hw) 1265 { 1266 struct rtl_priv *rtlpriv = rtl_priv(hw); 1267 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1268 1269 rtl_write_dword(rtlpriv, 0x3a8, rtlpci->irq_mask[0] & 0xFFFFFFFF); 1270 rtl_write_dword(rtlpriv, 0x3ac, rtlpci->irq_mask[1] & 0xFFFFFFFF); 1271 rtlpci->irq_enabled = true; 1272 } 1273 1274 void rtl8723e_disable_interrupt(struct ieee80211_hw *hw) 1275 { 1276 struct rtl_priv *rtlpriv = rtl_priv(hw); 1277 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1278 rtl_write_dword(rtlpriv, 0x3a8, IMR8190_DISABLED); 1279 rtl_write_dword(rtlpriv, 0x3ac, IMR8190_DISABLED); 1280 rtlpci->irq_enabled = false; 1281 /*synchronize_irq(rtlpci->pdev->irq);*/ 1282 } 1283 1284 static void _rtl8723e_poweroff_adapter(struct ieee80211_hw *hw) 1285 { 1286 struct rtl_priv *rtlpriv = rtl_priv(hw); 1287 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1288 u8 u1b_tmp; 1289 1290 /* Combo (PCIe + USB) Card and PCIe-MF Card */ 1291 /* 1. Run LPS WL RFOFF flow */ 1292 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1293 PWR_INTF_PCI_MSK, Rtl8723_NIC_LPS_ENTER_FLOW); 1294 1295 /* 2. 0x1F[7:0] = 0 */ 1296 /* turn off RF */ 1297 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); 1298 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && 1299 rtlhal->fw_ready) { 1300 rtl8723ae_firmware_selfreset(hw); 1301 } 1302 1303 /* Reset MCU. Suggested by Filen. */ 1304 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1); 1305 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2)))); 1306 1307 /* g. MCUFWDL 0x80[1:0]=0 */ 1308 /* reset MCU ready status */ 1309 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1310 1311 /* HW card disable configuration. */ 1312 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1313 PWR_INTF_PCI_MSK, Rtl8723_NIC_DISABLE_FLOW); 1314 1315 /* Reset MCU IO Wrapper */ 1316 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1317 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); 1318 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1319 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0)); 1320 1321 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */ 1322 /* lock ISO/CLK/Power control register */ 1323 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); 1324 } 1325 1326 void rtl8723e_card_disable(struct ieee80211_hw *hw) 1327 { 1328 struct rtl_priv *rtlpriv = rtl_priv(hw); 1329 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1330 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1331 enum nl80211_iftype opmode; 1332 1333 mac->link_state = MAC80211_NOLINK; 1334 opmode = NL80211_IFTYPE_UNSPECIFIED; 1335 _rtl8723e_set_media_status(hw, opmode); 1336 if (rtlpriv->rtlhal.driver_is_goingto_unload || 1337 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1338 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1339 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1340 _rtl8723e_poweroff_adapter(hw); 1341 1342 /* after power off we should do iqk again */ 1343 rtlpriv->phy.iqk_initialized = false; 1344 } 1345 1346 void rtl8723e_interrupt_recognized(struct ieee80211_hw *hw, 1347 u32 *p_inta, u32 *p_intb) 1348 { 1349 struct rtl_priv *rtlpriv = rtl_priv(hw); 1350 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1351 1352 *p_inta = rtl_read_dword(rtlpriv, 0x3a0) & rtlpci->irq_mask[0]; 1353 rtl_write_dword(rtlpriv, 0x3a0, *p_inta); 1354 } 1355 1356 void rtl8723e_set_beacon_related_registers(struct ieee80211_hw *hw) 1357 { 1358 1359 struct rtl_priv *rtlpriv = rtl_priv(hw); 1360 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1361 u16 bcn_interval, atim_window; 1362 1363 bcn_interval = mac->beacon_interval; 1364 atim_window = 2; /*FIX MERGE */ 1365 rtl8723e_disable_interrupt(hw); 1366 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1367 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1368 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 1369 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 1370 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 1371 rtl_write_byte(rtlpriv, 0x606, 0x30); 1372 rtl8723e_enable_interrupt(hw); 1373 } 1374 1375 void rtl8723e_set_beacon_interval(struct ieee80211_hw *hw) 1376 { 1377 struct rtl_priv *rtlpriv = rtl_priv(hw); 1378 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1379 u16 bcn_interval = mac->beacon_interval; 1380 1381 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, 1382 "beacon_interval:%d\n", bcn_interval); 1383 rtl8723e_disable_interrupt(hw); 1384 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1385 rtl8723e_enable_interrupt(hw); 1386 } 1387 1388 void rtl8723e_update_interrupt_mask(struct ieee80211_hw *hw, 1389 u32 add_msr, u32 rm_msr) 1390 { 1391 struct rtl_priv *rtlpriv = rtl_priv(hw); 1392 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1393 1394 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, 1395 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr); 1396 1397 if (add_msr) 1398 rtlpci->irq_mask[0] |= add_msr; 1399 if (rm_msr) 1400 rtlpci->irq_mask[0] &= (~rm_msr); 1401 rtl8723e_disable_interrupt(hw); 1402 rtl8723e_enable_interrupt(hw); 1403 } 1404 1405 static u8 _rtl8723e_get_chnl_group(u8 chnl) 1406 { 1407 u8 group; 1408 1409 if (chnl < 3) 1410 group = 0; 1411 else if (chnl < 9) 1412 group = 1; 1413 else 1414 group = 2; 1415 return group; 1416 } 1417 1418 static void _rtl8723e_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 1419 bool autoload_fail, 1420 u8 *hwinfo) 1421 { 1422 struct rtl_priv *rtlpriv = rtl_priv(hw); 1423 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1424 u8 rf_path, index, tempval; 1425 u16 i; 1426 1427 for (rf_path = 0; rf_path < 1; rf_path++) { 1428 for (i = 0; i < 3; i++) { 1429 if (!autoload_fail) { 1430 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] = 1431 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; 1432 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1433 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + i]; 1434 } else { 1435 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] = 1436 EEPROM_DEFAULT_TXPOWERLEVEL; 1437 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1438 EEPROM_DEFAULT_TXPOWERLEVEL; 1439 } 1440 } 1441 } 1442 1443 for (i = 0; i < 3; i++) { 1444 if (!autoload_fail) 1445 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i]; 1446 else 1447 tempval = EEPROM_DEFAULT_HT40_2SDIFF; 1448 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] = 1449 (tempval & 0xf); 1450 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] = 1451 ((tempval & 0xf0) >> 4); 1452 } 1453 1454 for (rf_path = 0; rf_path < 2; rf_path++) 1455 for (i = 0; i < 3; i++) 1456 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1457 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path, 1458 i, rtlefuse->eeprom_chnlarea_txpwr_cck 1459 [rf_path][i]); 1460 for (rf_path = 0; rf_path < 2; rf_path++) 1461 for (i = 0; i < 3; i++) 1462 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1463 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 1464 rf_path, i, 1465 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1466 [rf_path][i]); 1467 for (rf_path = 0; rf_path < 2; rf_path++) 1468 for (i = 0; i < 3; i++) 1469 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1470 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 1471 rf_path, i, 1472 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1473 [rf_path][i]); 1474 1475 for (rf_path = 0; rf_path < 2; rf_path++) { 1476 for (i = 0; i < 14; i++) { 1477 index = _rtl8723e_get_chnl_group((u8)i); 1478 1479 rtlefuse->txpwrlevel_cck[rf_path][i] = 1480 rtlefuse->eeprom_chnlarea_txpwr_cck 1481 [rf_path][index]; 1482 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 1483 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1484 [rf_path][index]; 1485 1486 if ((rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1487 [rf_path][index] - 1488 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1489 [rf_path][index]) > 0) { 1490 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 1491 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1492 [rf_path][index] - 1493 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1494 [rf_path][index]; 1495 } else { 1496 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; 1497 } 1498 } 1499 1500 for (i = 0; i < 14; i++) { 1501 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1502 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", 1503 rf_path, i, 1504 rtlefuse->txpwrlevel_cck[rf_path][i], 1505 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 1506 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 1507 } 1508 } 1509 1510 for (i = 0; i < 3; i++) { 1511 if (!autoload_fail) { 1512 rtlefuse->eeprom_pwrlimit_ht40[i] = 1513 hwinfo[EEPROM_TXPWR_GROUP + i]; 1514 rtlefuse->eeprom_pwrlimit_ht20[i] = 1515 hwinfo[EEPROM_TXPWR_GROUP + 3 + i]; 1516 } else { 1517 rtlefuse->eeprom_pwrlimit_ht40[i] = 0; 1518 rtlefuse->eeprom_pwrlimit_ht20[i] = 0; 1519 } 1520 } 1521 1522 for (rf_path = 0; rf_path < 2; rf_path++) { 1523 for (i = 0; i < 14; i++) { 1524 index = _rtl8723e_get_chnl_group((u8)i); 1525 1526 if (rf_path == RF90_PATH_A) { 1527 rtlefuse->pwrgroup_ht20[rf_path][i] = 1528 (rtlefuse->eeprom_pwrlimit_ht20[index] & 0xf); 1529 rtlefuse->pwrgroup_ht40[rf_path][i] = 1530 (rtlefuse->eeprom_pwrlimit_ht40[index] & 0xf); 1531 } else if (rf_path == RF90_PATH_B) { 1532 rtlefuse->pwrgroup_ht20[rf_path][i] = 1533 ((rtlefuse->eeprom_pwrlimit_ht20[index] & 1534 0xf0) >> 4); 1535 rtlefuse->pwrgroup_ht40[rf_path][i] = 1536 ((rtlefuse->eeprom_pwrlimit_ht40[index] & 1537 0xf0) >> 4); 1538 } 1539 1540 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1541 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", rf_path, i, 1542 rtlefuse->pwrgroup_ht20[rf_path][i]); 1543 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1544 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", rf_path, i, 1545 rtlefuse->pwrgroup_ht40[rf_path][i]); 1546 } 1547 } 1548 1549 for (i = 0; i < 14; i++) { 1550 index = _rtl8723e_get_chnl_group((u8)i); 1551 1552 if (!autoload_fail) 1553 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; 1554 else 1555 tempval = EEPROM_DEFAULT_HT20_DIFF; 1556 1557 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 1558 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 1559 ((tempval >> 4) & 0xF); 1560 1561 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) 1562 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; 1563 1564 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) 1565 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; 1566 1567 index = _rtl8723e_get_chnl_group((u8)i); 1568 1569 if (!autoload_fail) 1570 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; 1571 else 1572 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 1573 1574 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); 1575 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 1576 ((tempval >> 4) & 0xF); 1577 } 1578 1579 rtlefuse->legacy_ht_txpowerdiff = 1580 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; 1581 1582 for (i = 0; i < 14; i++) 1583 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1584 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i, 1585 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 1586 for (i = 0; i < 14; i++) 1587 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1588 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i, 1589 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 1590 for (i = 0; i < 14; i++) 1591 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1592 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i, 1593 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 1594 for (i = 0; i < 14; i++) 1595 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1596 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i, 1597 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 1598 1599 if (!autoload_fail) 1600 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); 1601 else 1602 rtlefuse->eeprom_regulatory = 0; 1603 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1604 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 1605 1606 if (!autoload_fail) 1607 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; 1608 else 1609 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; 1610 1611 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1612 "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 1613 rtlefuse->eeprom_tssi[RF90_PATH_A], 1614 rtlefuse->eeprom_tssi[RF90_PATH_B]); 1615 1616 if (!autoload_fail) 1617 tempval = hwinfo[EEPROM_THERMAL_METER]; 1618 else 1619 tempval = EEPROM_DEFAULT_THERMALMETER; 1620 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); 1621 1622 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) 1623 rtlefuse->apk_thermalmeterignore = true; 1624 1625 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 1626 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1627 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1628 } 1629 1630 static void _rtl8723e_read_adapter_info(struct ieee80211_hw *hw, 1631 bool b_pseudo_test) 1632 { 1633 struct rtl_priv *rtlpriv = rtl_priv(hw); 1634 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1635 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1636 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, 1637 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 1638 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 1639 COUNTRY_CODE_WORLD_WIDE_13}; 1640 u8 *hwinfo; 1641 1642 if (b_pseudo_test) { 1643 /* need add */ 1644 return; 1645 } 1646 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 1647 if (!hwinfo) 1648 return; 1649 1650 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 1651 goto exit; 1652 1653 _rtl8723e_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag, 1654 hwinfo); 1655 1656 rtl8723e_read_bt_coexist_info_from_hwpg(hw, 1657 rtlefuse->autoload_failflag, hwinfo); 1658 1659 if (rtlhal->oem_id != RT_CID_DEFAULT) 1660 goto exit; 1661 1662 switch (rtlefuse->eeprom_oemid) { 1663 case EEPROM_CID_DEFAULT: 1664 switch (rtlefuse->eeprom_did) { 1665 case 0x8176: 1666 switch (rtlefuse->eeprom_svid) { 1667 case 0x10EC: 1668 switch (rtlefuse->eeprom_smid) { 1669 case 0x6151 ... 0x6152: 1670 case 0x6154 ... 0x6155: 1671 case 0x6177 ... 0x6180: 1672 case 0x7151 ... 0x7152: 1673 case 0x7154 ... 0x7155: 1674 case 0x7177 ... 0x7180: 1675 case 0x8151 ... 0x8152: 1676 case 0x8154 ... 0x8155: 1677 case 0x8181 ... 0x8182: 1678 case 0x8184 ... 0x8185: 1679 case 0x9151 ... 0x9152: 1680 case 0x9154 ... 0x9155: 1681 case 0x9181 ... 0x9182: 1682 case 0x9184 ... 0x9185: 1683 rtlhal->oem_id = RT_CID_TOSHIBA; 1684 break; 1685 case 0x6191 ... 0x6193: 1686 case 0x7191 ... 0x7193: 1687 case 0x8191 ... 0x8193: 1688 case 0x9191 ... 0x9193: 1689 rtlhal->oem_id = RT_CID_819X_SAMSUNG; 1690 break; 1691 case 0x8197: 1692 case 0x9196: 1693 rtlhal->oem_id = RT_CID_819X_CLEVO; 1694 break; 1695 case 0x8203: 1696 rtlhal->oem_id = RT_CID_819X_PRONETS; 1697 break; 1698 case 0x8195: 1699 case 0x9195: 1700 case 0x7194: 1701 case 0x8200 ... 0x8202: 1702 case 0x9200: 1703 rtlhal->oem_id = RT_CID_819X_LENOVO; 1704 break; 1705 } 1706 case 0x1025: 1707 rtlhal->oem_id = RT_CID_819X_ACER; 1708 break; 1709 case 0x1028: 1710 switch (rtlefuse->eeprom_smid) { 1711 case 0x8194: 1712 case 0x8198: 1713 case 0x9197 ... 0x9198: 1714 rtlhal->oem_id = RT_CID_819X_DELL; 1715 break; 1716 } 1717 break; 1718 case 0x103C: 1719 switch (rtlefuse->eeprom_smid) { 1720 case 0x1629: 1721 rtlhal->oem_id = RT_CID_819X_HP; 1722 } 1723 break; 1724 case 0x1A32: 1725 switch (rtlefuse->eeprom_smid) { 1726 case 0x2315: 1727 rtlhal->oem_id = RT_CID_819X_QMI; 1728 break; 1729 } 1730 break; 1731 case 0x1043: 1732 switch (rtlefuse->eeprom_smid) { 1733 case 0x84B5: 1734 rtlhal->oem_id = 1735 RT_CID_819X_EDIMAX_ASUS; 1736 } 1737 break; 1738 } 1739 break; 1740 case 0x8178: 1741 switch (rtlefuse->eeprom_svid) { 1742 case 0x10ec: 1743 switch (rtlefuse->eeprom_smid) { 1744 case 0x6181 ... 0x6182: 1745 case 0x6184 ... 0x6185: 1746 case 0x7181 ... 0x7182: 1747 case 0x7184 ... 0x7185: 1748 case 0x8181 ... 0x8182: 1749 case 0x8184 ... 0x8185: 1750 case 0x9181 ... 0x9182: 1751 case 0x9184 ... 0x9185: 1752 rtlhal->oem_id = RT_CID_TOSHIBA; 1753 break; 1754 case 0x8186: 1755 rtlhal->oem_id = 1756 RT_CID_819X_PRONETS; 1757 break; 1758 } 1759 break; 1760 case 0x1025: 1761 rtlhal->oem_id = RT_CID_819X_ACER; 1762 break; 1763 case 0x1043: 1764 switch (rtlefuse->eeprom_smid) { 1765 case 0x8486: 1766 rtlhal->oem_id = 1767 RT_CID_819X_EDIMAX_ASUS; 1768 } 1769 break; 1770 } 1771 break; 1772 } 1773 break; 1774 case EEPROM_CID_TOSHIBA: 1775 rtlhal->oem_id = RT_CID_TOSHIBA; 1776 break; 1777 case EEPROM_CID_CCX: 1778 rtlhal->oem_id = RT_CID_CCX; 1779 break; 1780 case EEPROM_CID_QMI: 1781 rtlhal->oem_id = RT_CID_819X_QMI; 1782 break; 1783 case EEPROM_CID_WHQL: 1784 break; 1785 default: 1786 rtlhal->oem_id = RT_CID_DEFAULT; 1787 break; 1788 } 1789 exit: 1790 kfree(hwinfo); 1791 } 1792 1793 static void _rtl8723e_hal_customized_behavior(struct ieee80211_hw *hw) 1794 { 1795 struct rtl_priv *rtlpriv = rtl_priv(hw); 1796 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1797 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1798 1799 pcipriv->ledctl.led_opendrain = true; 1800 switch (rtlhal->oem_id) { 1801 case RT_CID_819X_HP: 1802 pcipriv->ledctl.led_opendrain = true; 1803 break; 1804 case RT_CID_819X_LENOVO: 1805 case RT_CID_DEFAULT: 1806 case RT_CID_TOSHIBA: 1807 case RT_CID_CCX: 1808 case RT_CID_819X_ACER: 1809 case RT_CID_WHQL: 1810 default: 1811 break; 1812 } 1813 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1814 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 1815 } 1816 1817 void rtl8723e_read_eeprom_info(struct ieee80211_hw *hw) 1818 { 1819 struct rtl_priv *rtlpriv = rtl_priv(hw); 1820 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1821 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1822 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1823 u8 tmp_u1b; 1824 u32 value32; 1825 1826 value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST]); 1827 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); 1828 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST], value32); 1829 1830 rtlhal->version = _rtl8723e_read_chip_version(hw); 1831 1832 if (get_rf_type(rtlphy) == RF_1T1R) 1833 rtlpriv->dm.rfpath_rxenable[0] = true; 1834 else 1835 rtlpriv->dm.rfpath_rxenable[0] = 1836 rtlpriv->dm.rfpath_rxenable[1] = true; 1837 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 1838 rtlhal->version); 1839 1840 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 1841 if (tmp_u1b & BIT(4)) { 1842 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 1843 rtlefuse->epromtype = EEPROM_93C46; 1844 } else { 1845 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 1846 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 1847 } 1848 if (tmp_u1b & BIT(5)) { 1849 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1850 rtlefuse->autoload_failflag = false; 1851 _rtl8723e_read_adapter_info(hw, false); 1852 } else { 1853 rtlefuse->autoload_failflag = true; 1854 _rtl8723e_read_adapter_info(hw, false); 1855 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n"); 1856 } 1857 _rtl8723e_hal_customized_behavior(hw); 1858 } 1859 1860 static void rtl8723e_update_hal_rate_table(struct ieee80211_hw *hw, 1861 struct ieee80211_sta *sta) 1862 { 1863 struct rtl_priv *rtlpriv = rtl_priv(hw); 1864 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1865 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1866 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1867 u32 ratr_value; 1868 u8 ratr_index = 0; 1869 u8 b_nmode = mac->ht_enable; 1870 u16 shortgi_rate; 1871 u32 tmp_ratr_value; 1872 u8 curtxbw_40mhz = mac->bw_40; 1873 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1874 1 : 0; 1875 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1876 1 : 0; 1877 enum wireless_mode wirelessmode = mac->mode; 1878 u32 ratr_mask; 1879 1880 if (rtlhal->current_bandtype == BAND_ON_5G) 1881 ratr_value = sta->supp_rates[1] << 4; 1882 else 1883 ratr_value = sta->supp_rates[0]; 1884 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1885 ratr_value = 0xfff; 1886 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1887 sta->ht_cap.mcs.rx_mask[0] << 12); 1888 switch (wirelessmode) { 1889 case WIRELESS_MODE_B: 1890 if (ratr_value & 0x0000000c) 1891 ratr_value &= 0x0000000d; 1892 else 1893 ratr_value &= 0x0000000f; 1894 break; 1895 case WIRELESS_MODE_G: 1896 ratr_value &= 0x00000FF5; 1897 break; 1898 case WIRELESS_MODE_N_24G: 1899 case WIRELESS_MODE_N_5G: 1900 b_nmode = 1; 1901 if (get_rf_type(rtlphy) == RF_1T2R || 1902 get_rf_type(rtlphy) == RF_1T1R) 1903 ratr_mask = 0x000ff005; 1904 else 1905 ratr_mask = 0x0f0ff005; 1906 1907 ratr_value &= ratr_mask; 1908 break; 1909 default: 1910 if (rtlphy->rf_type == RF_1T2R) 1911 ratr_value &= 0x000ff0ff; 1912 else 1913 ratr_value &= 0x0f0ff0ff; 1914 1915 break; 1916 } 1917 1918 if ((rtlpriv->btcoexist.bt_coexistence) && 1919 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) && 1920 (rtlpriv->btcoexist.bt_cur_state) && 1921 (rtlpriv->btcoexist.bt_ant_isolation) && 1922 ((rtlpriv->btcoexist.bt_service == BT_SCO) || 1923 (rtlpriv->btcoexist.bt_service == BT_BUSY))) 1924 ratr_value &= 0x0fffcfc0; 1925 else 1926 ratr_value &= 0x0FFFFFFF; 1927 1928 if (b_nmode && 1929 ((curtxbw_40mhz && curshortgi_40mhz) || 1930 (!curtxbw_40mhz && curshortgi_20mhz))) { 1931 ratr_value |= 0x10000000; 1932 tmp_ratr_value = (ratr_value >> 12); 1933 1934 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 1935 if ((1 << shortgi_rate) & tmp_ratr_value) 1936 break; 1937 } 1938 1939 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 1940 (shortgi_rate << 4) | (shortgi_rate); 1941 } 1942 1943 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 1944 1945 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 1946 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)); 1947 } 1948 1949 static void rtl8723e_update_hal_rate_mask(struct ieee80211_hw *hw, 1950 struct ieee80211_sta *sta, 1951 u8 rssi_level) 1952 { 1953 struct rtl_priv *rtlpriv = rtl_priv(hw); 1954 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1955 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1956 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1957 struct rtl_sta_info *sta_entry = NULL; 1958 u32 ratr_bitmap; 1959 u8 ratr_index; 1960 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) 1961 ? 1 : 0; 1962 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1963 1 : 0; 1964 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1965 1 : 0; 1966 enum wireless_mode wirelessmode = 0; 1967 bool shortgi = false; 1968 u8 rate_mask[5]; 1969 u8 macid = 0; 1970 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/ 1971 1972 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 1973 wirelessmode = sta_entry->wireless_mode; 1974 if (mac->opmode == NL80211_IFTYPE_STATION) 1975 curtxbw_40mhz = mac->bw_40; 1976 else if (mac->opmode == NL80211_IFTYPE_AP || 1977 mac->opmode == NL80211_IFTYPE_ADHOC) 1978 macid = sta->aid + 1; 1979 1980 if (rtlhal->current_bandtype == BAND_ON_5G) 1981 ratr_bitmap = sta->supp_rates[1] << 4; 1982 else 1983 ratr_bitmap = sta->supp_rates[0]; 1984 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1985 ratr_bitmap = 0xfff; 1986 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1987 sta->ht_cap.mcs.rx_mask[0] << 12); 1988 switch (wirelessmode) { 1989 case WIRELESS_MODE_B: 1990 ratr_index = RATR_INX_WIRELESS_B; 1991 if (ratr_bitmap & 0x0000000c) 1992 ratr_bitmap &= 0x0000000d; 1993 else 1994 ratr_bitmap &= 0x0000000f; 1995 break; 1996 case WIRELESS_MODE_G: 1997 ratr_index = RATR_INX_WIRELESS_GB; 1998 1999 if (rssi_level == 1) 2000 ratr_bitmap &= 0x00000f00; 2001 else if (rssi_level == 2) 2002 ratr_bitmap &= 0x00000ff0; 2003 else 2004 ratr_bitmap &= 0x00000ff5; 2005 break; 2006 case WIRELESS_MODE_A: 2007 ratr_index = RATR_INX_WIRELESS_G; 2008 ratr_bitmap &= 0x00000ff0; 2009 break; 2010 case WIRELESS_MODE_N_24G: 2011 case WIRELESS_MODE_N_5G: 2012 ratr_index = RATR_INX_WIRELESS_NGB; 2013 if (rtlphy->rf_type == RF_1T2R || 2014 rtlphy->rf_type == RF_1T1R) { 2015 if (curtxbw_40mhz) { 2016 if (rssi_level == 1) 2017 ratr_bitmap &= 0x000f0000; 2018 else if (rssi_level == 2) 2019 ratr_bitmap &= 0x000ff000; 2020 else 2021 ratr_bitmap &= 0x000ff015; 2022 } else { 2023 if (rssi_level == 1) 2024 ratr_bitmap &= 0x000f0000; 2025 else if (rssi_level == 2) 2026 ratr_bitmap &= 0x000ff000; 2027 else 2028 ratr_bitmap &= 0x000ff005; 2029 } 2030 } else { 2031 if (curtxbw_40mhz) { 2032 if (rssi_level == 1) 2033 ratr_bitmap &= 0x0f0f0000; 2034 else if (rssi_level == 2) 2035 ratr_bitmap &= 0x0f0ff000; 2036 else 2037 ratr_bitmap &= 0x0f0ff015; 2038 } else { 2039 if (rssi_level == 1) 2040 ratr_bitmap &= 0x0f0f0000; 2041 else if (rssi_level == 2) 2042 ratr_bitmap &= 0x0f0ff000; 2043 else 2044 ratr_bitmap &= 0x0f0ff005; 2045 } 2046 } 2047 2048 if ((curtxbw_40mhz && curshortgi_40mhz) || 2049 (!curtxbw_40mhz && curshortgi_20mhz)) { 2050 if (macid == 0) 2051 shortgi = true; 2052 else if (macid == 1) 2053 shortgi = false; 2054 } 2055 break; 2056 default: 2057 ratr_index = RATR_INX_WIRELESS_NGB; 2058 2059 if (rtlphy->rf_type == RF_1T2R) 2060 ratr_bitmap &= 0x000ff0ff; 2061 else 2062 ratr_bitmap &= 0x0f0ff0ff; 2063 break; 2064 } 2065 sta_entry->ratr_index = ratr_index; 2066 2067 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2068 "ratr_bitmap :%x\n", ratr_bitmap); 2069 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 2070 (ratr_index << 28); 2071 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; 2072 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2073 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n", 2074 ratr_index, ratr_bitmap, 2075 rate_mask[0], rate_mask[1], 2076 rate_mask[2], rate_mask[3], 2077 rate_mask[4]); 2078 rtl8723e_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask); 2079 } 2080 2081 void rtl8723e_update_hal_rate_tbl(struct ieee80211_hw *hw, 2082 struct ieee80211_sta *sta, u8 rssi_level) 2083 { 2084 struct rtl_priv *rtlpriv = rtl_priv(hw); 2085 2086 if (rtlpriv->dm.useramask) 2087 rtl8723e_update_hal_rate_mask(hw, sta, rssi_level); 2088 else 2089 rtl8723e_update_hal_rate_table(hw, sta); 2090 } 2091 2092 void rtl8723e_update_channel_access_setting(struct ieee80211_hw *hw) 2093 { 2094 struct rtl_priv *rtlpriv = rtl_priv(hw); 2095 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2096 u16 sifs_timer; 2097 2098 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time); 2099 if (!mac->ht_enable) 2100 sifs_timer = 0x0a0a; 2101 else 2102 sifs_timer = 0x1010; 2103 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2104 } 2105 2106 bool rtl8723e_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2107 { 2108 struct rtl_priv *rtlpriv = rtl_priv(hw); 2109 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2110 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2111 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate; 2112 u8 u1tmp; 2113 bool b_actuallyset = false; 2114 2115 if (rtlpriv->rtlhal.being_init_adapter) 2116 return false; 2117 2118 if (ppsc->swrf_processing) 2119 return false; 2120 2121 spin_lock(&rtlpriv->locks.rf_ps_lock); 2122 if (ppsc->rfchange_inprogress) { 2123 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2124 return false; 2125 } else { 2126 ppsc->rfchange_inprogress = true; 2127 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2128 } 2129 2130 cur_rfstate = ppsc->rfpwr_state; 2131 2132 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2, 2133 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2)&~(BIT(1))); 2134 2135 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2); 2136 2137 if (rtlphy->polarity_ctl) 2138 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON; 2139 else 2140 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF; 2141 2142 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) { 2143 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2144 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2145 2146 e_rfpowerstate_toset = ERFON; 2147 ppsc->hwradiooff = false; 2148 b_actuallyset = true; 2149 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) { 2150 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2151 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 2152 2153 e_rfpowerstate_toset = ERFOFF; 2154 ppsc->hwradiooff = true; 2155 b_actuallyset = true; 2156 } 2157 2158 if (b_actuallyset) { 2159 spin_lock(&rtlpriv->locks.rf_ps_lock); 2160 ppsc->rfchange_inprogress = false; 2161 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2162 } else { 2163 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 2164 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2165 2166 spin_lock(&rtlpriv->locks.rf_ps_lock); 2167 ppsc->rfchange_inprogress = false; 2168 spin_unlock(&rtlpriv->locks.rf_ps_lock); 2169 } 2170 2171 *valid = 1; 2172 return !ppsc->hwradiooff; 2173 2174 } 2175 2176 void rtl8723e_set_key(struct ieee80211_hw *hw, u32 key_index, 2177 u8 *p_macaddr, bool is_group, u8 enc_algo, 2178 bool is_wepkey, bool clear_all) 2179 { 2180 struct rtl_priv *rtlpriv = rtl_priv(hw); 2181 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2182 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2183 u8 *macaddr = p_macaddr; 2184 u32 entry_id = 0; 2185 bool is_pairwise = false; 2186 2187 static u8 cam_const_addr[4][6] = { 2188 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2189 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2190 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2191 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2192 }; 2193 static u8 cam_const_broad[] = { 2194 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2195 }; 2196 2197 if (clear_all) { 2198 u8 idx = 0; 2199 u8 cam_offset = 0; 2200 u8 clear_number = 5; 2201 2202 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2203 2204 for (idx = 0; idx < clear_number; idx++) { 2205 rtl_cam_mark_invalid(hw, cam_offset + idx); 2206 rtl_cam_empty_entry(hw, cam_offset + idx); 2207 2208 if (idx < 5) { 2209 memset(rtlpriv->sec.key_buf[idx], 0, 2210 MAX_KEY_LEN); 2211 rtlpriv->sec.key_len[idx] = 0; 2212 } 2213 } 2214 2215 } else { 2216 switch (enc_algo) { 2217 case WEP40_ENCRYPTION: 2218 enc_algo = CAM_WEP40; 2219 break; 2220 case WEP104_ENCRYPTION: 2221 enc_algo = CAM_WEP104; 2222 break; 2223 case TKIP_ENCRYPTION: 2224 enc_algo = CAM_TKIP; 2225 break; 2226 case AESCCMP_ENCRYPTION: 2227 enc_algo = CAM_AES; 2228 break; 2229 default: 2230 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, 2231 "switch case %#x not processed\n", enc_algo); 2232 enc_algo = CAM_TKIP; 2233 break; 2234 } 2235 2236 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2237 macaddr = cam_const_addr[key_index]; 2238 entry_id = key_index; 2239 } else { 2240 if (is_group) { 2241 macaddr = cam_const_broad; 2242 entry_id = key_index; 2243 } else { 2244 if (mac->opmode == NL80211_IFTYPE_AP) { 2245 entry_id = 2246 rtl_cam_get_free_entry(hw, p_macaddr); 2247 if (entry_id >= TOTAL_CAM_ENTRY) { 2248 RT_TRACE(rtlpriv, COMP_SEC, 2249 DBG_EMERG, 2250 "Can not find free hw security cam entry\n"); 2251 return; 2252 } 2253 } else { 2254 entry_id = CAM_PAIRWISE_KEY_POSITION; 2255 } 2256 2257 key_index = PAIRWISE_KEYIDX; 2258 is_pairwise = true; 2259 } 2260 } 2261 2262 if (rtlpriv->sec.key_len[key_index] == 0) { 2263 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2264 "delete one entry, entry_id is %d\n", 2265 entry_id); 2266 if (mac->opmode == NL80211_IFTYPE_AP) 2267 rtl_cam_del_entry(hw, p_macaddr); 2268 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2269 } else { 2270 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2271 "add one entry\n"); 2272 if (is_pairwise) { 2273 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2274 "set Pairwiase key\n"); 2275 2276 rtl_cam_add_one_entry(hw, macaddr, key_index, 2277 entry_id, enc_algo, 2278 CAM_CONFIG_NO_USEDK, 2279 rtlpriv->sec.key_buf[key_index]); 2280 } else { 2281 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2282 "set group key\n"); 2283 2284 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2285 rtl_cam_add_one_entry(hw, 2286 rtlefuse->dev_addr, 2287 PAIRWISE_KEYIDX, 2288 CAM_PAIRWISE_KEY_POSITION, 2289 enc_algo, 2290 CAM_CONFIG_NO_USEDK, 2291 rtlpriv->sec.key_buf 2292 [entry_id]); 2293 } 2294 2295 rtl_cam_add_one_entry(hw, macaddr, key_index, 2296 entry_id, enc_algo, 2297 CAM_CONFIG_NO_USEDK, 2298 rtlpriv->sec.key_buf[entry_id]); 2299 } 2300 2301 } 2302 } 2303 } 2304 2305 static void rtl8723e_bt_var_init(struct ieee80211_hw *hw) 2306 { 2307 struct rtl_priv *rtlpriv = rtl_priv(hw); 2308 2309 rtlpriv->btcoexist.bt_coexistence = 2310 rtlpriv->btcoexist.eeprom_bt_coexist; 2311 rtlpriv->btcoexist.bt_ant_num = 2312 rtlpriv->btcoexist.eeprom_bt_ant_num; 2313 rtlpriv->btcoexist.bt_coexist_type = 2314 rtlpriv->btcoexist.eeprom_bt_type; 2315 2316 rtlpriv->btcoexist.bt_ant_isolation = 2317 rtlpriv->btcoexist.eeprom_bt_ant_isol; 2318 2319 rtlpriv->btcoexist.bt_radio_shared_type = 2320 rtlpriv->btcoexist.eeprom_bt_radio_shared; 2321 2322 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2323 "BT Coexistance = 0x%x\n", 2324 rtlpriv->btcoexist.bt_coexistence); 2325 2326 if (rtlpriv->btcoexist.bt_coexistence) { 2327 rtlpriv->btcoexist.bt_busy_traffic = false; 2328 rtlpriv->btcoexist.bt_traffic_mode_set = false; 2329 rtlpriv->btcoexist.bt_non_traffic_mode_set = false; 2330 2331 rtlpriv->btcoexist.cstate = 0; 2332 rtlpriv->btcoexist.previous_state = 0; 2333 2334 if (rtlpriv->btcoexist.bt_ant_num == ANT_X2) { 2335 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2336 "BlueTooth BT_Ant_Num = Antx2\n"); 2337 } else if (rtlpriv->btcoexist.bt_ant_num == ANT_X1) { 2338 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2339 "BlueTooth BT_Ant_Num = Antx1\n"); 2340 } 2341 switch (rtlpriv->btcoexist.bt_coexist_type) { 2342 case BT_2WIRE: 2343 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2344 "BlueTooth BT_CoexistType = BT_2Wire\n"); 2345 break; 2346 case BT_ISSC_3WIRE: 2347 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2348 "BlueTooth BT_CoexistType = BT_ISSC_3Wire\n"); 2349 break; 2350 case BT_ACCEL: 2351 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2352 "BlueTooth BT_CoexistType = BT_ACCEL\n"); 2353 break; 2354 case BT_CSR_BC4: 2355 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2356 "BlueTooth BT_CoexistType = BT_CSR_BC4\n"); 2357 break; 2358 case BT_CSR_BC8: 2359 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2360 "BlueTooth BT_CoexistType = BT_CSR_BC8\n"); 2361 break; 2362 case BT_RTL8756: 2363 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2364 "BlueTooth BT_CoexistType = BT_RTL8756\n"); 2365 break; 2366 default: 2367 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2368 "BlueTooth BT_CoexistType = Unknown\n"); 2369 break; 2370 } 2371 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2372 "BlueTooth BT_Ant_isolation = %d\n", 2373 rtlpriv->btcoexist.bt_ant_isolation); 2374 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_TRACE, 2375 "BT_RadioSharedType = 0x%x\n", 2376 rtlpriv->btcoexist.bt_radio_shared_type); 2377 rtlpriv->btcoexist.bt_active_zero_cnt = 0; 2378 rtlpriv->btcoexist.cur_bt_disabled = false; 2379 rtlpriv->btcoexist.pre_bt_disabled = false; 2380 } 2381 } 2382 2383 void rtl8723e_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 2384 bool auto_load_fail, u8 *hwinfo) 2385 { 2386 struct rtl_priv *rtlpriv = rtl_priv(hw); 2387 u8 value; 2388 u32 tmpu_32; 2389 2390 if (!auto_load_fail) { 2391 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL); 2392 if (tmpu_32 & BIT(18)) 2393 rtlpriv->btcoexist.eeprom_bt_coexist = 1; 2394 else 2395 rtlpriv->btcoexist.eeprom_bt_coexist = 0; 2396 value = hwinfo[RF_OPTION4]; 2397 rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A; 2398 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1); 2399 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4); 2400 rtlpriv->btcoexist.eeprom_bt_radio_shared = 2401 ((value & 0x20) >> 5); 2402 } else { 2403 rtlpriv->btcoexist.eeprom_bt_coexist = 0; 2404 rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A; 2405 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2; 2406 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0; 2407 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED; 2408 } 2409 2410 rtl8723e_bt_var_init(hw); 2411 } 2412 2413 void rtl8723e_bt_reg_init(struct ieee80211_hw *hw) 2414 { 2415 struct rtl_priv *rtlpriv = rtl_priv(hw); 2416 2417 /* 0:Low, 1:High, 2:From Efuse. */ 2418 rtlpriv->btcoexist.reg_bt_iso = 2; 2419 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 2420 rtlpriv->btcoexist.reg_bt_sco = 3; 2421 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 2422 rtlpriv->btcoexist.reg_bt_sco = 0; 2423 } 2424 2425 void rtl8723e_bt_hw_init(struct ieee80211_hw *hw) 2426 { 2427 struct rtl_priv *rtlpriv = rtl_priv(hw); 2428 2429 if (rtlpriv->cfg->ops->get_btc_status()) 2430 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv); 2431 } 2432 2433 void rtl8723e_suspend(struct ieee80211_hw *hw) 2434 { 2435 } 2436 2437 void rtl8723e_resume(struct ieee80211_hw *hw) 2438 { 2439 } 2440