1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4 #include "../wifi.h" 5 #include "../base.h" 6 #include "../pci.h" 7 #include "../core.h" 8 #include "reg.h" 9 #include "def.h" 10 #include "phy.h" 11 #include "dm.h" 12 #include "../rtl8723com/dm_common.h" 13 #include "fw.h" 14 #include "hal_btc.h" 15 16 static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = { 17 0x7f8001fe, 18 0x788001e2, 19 0x71c001c7, 20 0x6b8001ae, 21 0x65400195, 22 0x5fc0017f, 23 0x5a400169, 24 0x55400155, 25 0x50800142, 26 0x4c000130, 27 0x47c0011f, 28 0x43c0010f, 29 0x40000100, 30 0x3c8000f2, 31 0x390000e4, 32 0x35c000d7, 33 0x32c000cb, 34 0x300000c0, 35 0x2d4000b5, 36 0x2ac000ab, 37 0x288000a2, 38 0x26000098, 39 0x24000090, 40 0x22000088, 41 0x20000080, 42 0x1e400079, 43 0x1c800072, 44 0x1b00006c, 45 0x19800066, 46 0x18000060, 47 0x16c0005b, 48 0x15800056, 49 0x14400051, 50 0x1300004c, 51 0x12000048, 52 0x11000044, 53 0x10000040, 54 }; 55 56 static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = { 57 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, 58 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, 59 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, 60 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, 61 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, 62 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, 63 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, 64 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, 65 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, 66 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, 67 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, 68 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, 69 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, 70 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, 71 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, 72 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, 73 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, 74 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, 75 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, 76 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, 77 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, 78 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, 79 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, 80 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, 81 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, 82 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, 83 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, 84 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, 85 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, 86 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, 87 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, 88 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, 89 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} 90 }; 91 92 static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = { 93 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, 94 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, 95 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, 96 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, 97 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, 98 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, 99 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, 100 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, 101 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, 102 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, 103 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, 104 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, 105 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, 106 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, 107 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, 108 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, 109 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, 110 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, 111 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, 112 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, 113 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, 114 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, 115 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, 116 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, 117 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, 118 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, 119 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, 120 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, 121 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, 122 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, 123 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, 124 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, 125 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} 126 }; 127 128 static u8 rtl8723e_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw) 129 { 130 struct rtl_priv *rtlpriv = rtl_priv(hw); 131 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 132 struct rtl_mac *mac = rtl_mac(rtlpriv); 133 long rssi_val_min = 0; 134 135 if (mac->link_state == MAC80211_LINKED && 136 mac->opmode == NL80211_IFTYPE_STATION && 137 rtlpriv->link_info.bcn_rx_inperiod == 0) 138 return 0; 139 140 if ((dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) && 141 (dm_digtable->cursta_cstate == DIG_STA_CONNECT)) { 142 if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0) 143 rssi_val_min = 144 (rtlpriv->dm.entry_min_undec_sm_pwdb > 145 rtlpriv->dm.undec_sm_pwdb) ? 146 rtlpriv->dm.undec_sm_pwdb : 147 rtlpriv->dm.entry_min_undec_sm_pwdb; 148 else 149 rssi_val_min = rtlpriv->dm.undec_sm_pwdb; 150 } else if (dm_digtable->cursta_cstate == DIG_STA_CONNECT || 151 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT) { 152 rssi_val_min = rtlpriv->dm.undec_sm_pwdb; 153 } else if (dm_digtable->curmultista_cstate == 154 DIG_MULTISTA_CONNECT) { 155 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb; 156 } 157 158 return (u8) rssi_val_min; 159 } 160 161 static void rtl8723e_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) 162 { 163 u32 ret_value; 164 struct rtl_priv *rtlpriv = rtl_priv(hw); 165 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt); 166 167 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); 168 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); 169 170 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); 171 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); 172 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); 173 174 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); 175 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); 176 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + 177 falsealm_cnt->cnt_rate_illegal + 178 falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail; 179 180 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1); 181 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); 182 falsealm_cnt->cnt_cck_fail = ret_value; 183 184 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3); 185 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; 186 falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail + 187 falsealm_cnt->cnt_rate_illegal + 188 falsealm_cnt->cnt_crc8_fail + 189 falsealm_cnt->cnt_mcs_fail + 190 falsealm_cnt->cnt_cck_fail); 191 192 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1); 193 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0); 194 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0); 195 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2); 196 197 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 198 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n", 199 falsealm_cnt->cnt_parity_fail, 200 falsealm_cnt->cnt_rate_illegal, 201 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail); 202 203 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 204 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n", 205 falsealm_cnt->cnt_ofdm_fail, 206 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all); 207 } 208 209 static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw) 210 { 211 struct rtl_priv *rtlpriv = rtl_priv(hw); 212 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 213 u8 value_igi = dm_digtable->cur_igvalue; 214 215 if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0) 216 value_igi--; 217 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1) 218 value_igi += 0; 219 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2) 220 value_igi++; 221 else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2) 222 value_igi += 2; 223 if (value_igi > DM_DIG_FA_UPPER) 224 value_igi = DM_DIG_FA_UPPER; 225 else if (value_igi < DM_DIG_FA_LOWER) 226 value_igi = DM_DIG_FA_LOWER; 227 if (rtlpriv->falsealm_cnt.cnt_all > 10000) 228 value_igi = 0x32; 229 230 dm_digtable->cur_igvalue = value_igi; 231 rtl8723e_dm_write_dig(hw); 232 } 233 234 static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw) 235 { 236 struct rtl_priv *rtlpriv = rtl_priv(hw); 237 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 238 239 if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable->fa_highthresh) { 240 if ((dm_digtable->back_val - 2) < 241 dm_digtable->back_range_min) 242 dm_digtable->back_val = 243 dm_digtable->back_range_min; 244 else 245 dm_digtable->back_val -= 2; 246 } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable->fa_lowthresh) { 247 if ((dm_digtable->back_val + 2) > 248 dm_digtable->back_range_max) 249 dm_digtable->back_val = 250 dm_digtable->back_range_max; 251 else 252 dm_digtable->back_val += 2; 253 } 254 255 if ((dm_digtable->rssi_val_min + 10 - dm_digtable->back_val) > 256 dm_digtable->rx_gain_max) 257 dm_digtable->cur_igvalue = dm_digtable->rx_gain_max; 258 else if ((dm_digtable->rssi_val_min + 10 - 259 dm_digtable->back_val) < dm_digtable->rx_gain_min) 260 dm_digtable->cur_igvalue = dm_digtable->rx_gain_min; 261 else 262 dm_digtable->cur_igvalue = dm_digtable->rssi_val_min + 10 - 263 dm_digtable->back_val; 264 265 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 266 "rssi_val_min = %x back_val %x\n", 267 dm_digtable->rssi_val_min, dm_digtable->back_val); 268 269 rtl8723e_dm_write_dig(hw); 270 } 271 272 static void rtl8723e_dm_initial_gain_multi_sta(struct ieee80211_hw *hw) 273 { 274 static u8 binitialized; 275 struct rtl_priv *rtlpriv = rtl_priv(hw); 276 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 277 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 278 long rssi_strength = rtlpriv->dm.entry_min_undec_sm_pwdb; 279 bool multi_sta = false; 280 281 if (mac->opmode == NL80211_IFTYPE_ADHOC) 282 multi_sta = true; 283 284 if (!multi_sta || (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT)) { 285 binitialized = false; 286 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX; 287 return; 288 } else if (!binitialized) { 289 binitialized = true; 290 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0; 291 dm_digtable->cur_igvalue = 0x20; 292 rtl8723e_dm_write_dig(hw); 293 } 294 295 if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) { 296 if ((rssi_strength < dm_digtable->rssi_lowthresh) && 297 (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) { 298 299 if (dm_digtable->dig_ext_port_stage == 300 DIG_EXT_PORT_STAGE_2) { 301 dm_digtable->cur_igvalue = 0x20; 302 rtl8723e_dm_write_dig(hw); 303 } 304 305 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1; 306 } else if (rssi_strength > dm_digtable->rssi_highthresh) { 307 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_2; 308 rtl92c_dm_ctrl_initgain_by_fa(hw); 309 } 310 } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) { 311 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0; 312 dm_digtable->cur_igvalue = 0x20; 313 rtl8723e_dm_write_dig(hw); 314 } 315 316 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 317 "curmultista_cstate = %x dig_ext_port_stage %x\n", 318 dm_digtable->curmultista_cstate, 319 dm_digtable->dig_ext_port_stage); 320 } 321 322 static void rtl8723e_dm_initial_gain_sta(struct ieee80211_hw *hw) 323 { 324 struct rtl_priv *rtlpriv = rtl_priv(hw); 325 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 326 327 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 328 "presta_cstate = %x, cursta_cstate = %x\n", 329 dm_digtable->presta_cstate, 330 dm_digtable->cursta_cstate); 331 332 if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate || 333 dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT || 334 dm_digtable->cursta_cstate == DIG_STA_CONNECT) { 335 if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) { 336 dm_digtable->rssi_val_min = 337 rtl8723e_dm_initial_gain_min_pwdb(hw); 338 rtl92c_dm_ctrl_initgain_by_rssi(hw); 339 } 340 } else { 341 dm_digtable->rssi_val_min = 0; 342 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX; 343 dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT; 344 dm_digtable->cur_igvalue = 0x20; 345 dm_digtable->pre_igvalue = 0; 346 rtl8723e_dm_write_dig(hw); 347 } 348 } 349 350 static void rtl8723e_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) 351 { 352 struct rtl_priv *rtlpriv = rtl_priv(hw); 353 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 354 355 if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) { 356 dm_digtable->rssi_val_min = rtl8723e_dm_initial_gain_min_pwdb(hw); 357 358 if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { 359 if (dm_digtable->rssi_val_min <= 25) 360 dm_digtable->cur_cck_pd_state = 361 CCK_PD_STAGE_LOWRSSI; 362 else 363 dm_digtable->cur_cck_pd_state = 364 CCK_PD_STAGE_HIGHRSSI; 365 } else { 366 if (dm_digtable->rssi_val_min <= 20) 367 dm_digtable->cur_cck_pd_state = 368 CCK_PD_STAGE_LOWRSSI; 369 else 370 dm_digtable->cur_cck_pd_state = 371 CCK_PD_STAGE_HIGHRSSI; 372 } 373 } else { 374 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX; 375 } 376 377 if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) { 378 if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { 379 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800) 380 dm_digtable->cur_cck_fa_state = 381 CCK_FA_STAGE_HIGH; 382 else 383 dm_digtable->cur_cck_fa_state = 384 CCK_FA_STAGE_LOW; 385 if (dm_digtable->pre_cck_fa_state != 386 dm_digtable->cur_cck_fa_state) { 387 if (dm_digtable->cur_cck_fa_state == 388 CCK_FA_STAGE_LOW) 389 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 390 0x83); 391 else 392 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 393 0xcd); 394 395 dm_digtable->pre_cck_fa_state = 396 dm_digtable->cur_cck_fa_state; 397 } 398 399 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40); 400 401 } else { 402 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); 403 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47); 404 dm_digtable->pre_cck_fa_state = 0; 405 dm_digtable->cur_cck_fa_state = 0; 406 407 } 408 dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state; 409 } 410 411 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, 412 "CCKPDStage=%x\n", dm_digtable->cur_cck_pd_state); 413 414 } 415 416 static void rtl8723e_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw) 417 { 418 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 419 struct rtl_priv *rtlpriv = rtl_priv(hw); 420 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 421 422 if (mac->act_scanning) 423 return; 424 425 if (mac->link_state >= MAC80211_LINKED) 426 dm_digtable->cursta_cstate = DIG_STA_CONNECT; 427 else 428 dm_digtable->cursta_cstate = DIG_STA_DISCONNECT; 429 430 rtl8723e_dm_initial_gain_sta(hw); 431 rtl8723e_dm_initial_gain_multi_sta(hw); 432 rtl8723e_dm_cck_packet_detection_thresh(hw); 433 434 dm_digtable->presta_cstate = dm_digtable->cursta_cstate; 435 436 } 437 438 static void rtl8723e_dm_dig(struct ieee80211_hw *hw) 439 { 440 struct rtl_priv *rtlpriv = rtl_priv(hw); 441 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 442 443 if (!rtlpriv->dm.dm_initialgain_enable) 444 return; 445 if (!dm_digtable->dig_enable_flag) 446 return; 447 448 rtl8723e_dm_ctrl_initgain_by_twoport(hw); 449 450 } 451 452 static void rtl8723e_dm_dynamic_txpower(struct ieee80211_hw *hw) 453 { 454 struct rtl_priv *rtlpriv = rtl_priv(hw); 455 struct rtl_phy *rtlphy = &(rtlpriv->phy); 456 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 457 long undec_sm_pwdb; 458 459 if (!rtlpriv->dm.dynamic_txpower_enable) 460 return; 461 462 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) { 463 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 464 return; 465 } 466 467 if ((mac->link_state < MAC80211_LINKED) && 468 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) { 469 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 470 "Not connected to any\n"); 471 472 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 473 474 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL; 475 return; 476 } 477 478 if (mac->link_state >= MAC80211_LINKED) { 479 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 480 undec_sm_pwdb = 481 rtlpriv->dm.entry_min_undec_sm_pwdb; 482 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 483 "AP Client PWDB = 0x%lx\n", 484 undec_sm_pwdb); 485 } else { 486 undec_sm_pwdb = 487 rtlpriv->dm.undec_sm_pwdb; 488 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 489 "STA Default Port PWDB = 0x%lx\n", 490 undec_sm_pwdb); 491 } 492 } else { 493 undec_sm_pwdb = 494 rtlpriv->dm.entry_min_undec_sm_pwdb; 495 496 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 497 "AP Ext Port PWDB = 0x%lx\n", 498 undec_sm_pwdb); 499 } 500 501 if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) { 502 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1; 503 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 504 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"); 505 } else if ((undec_sm_pwdb < 506 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) && 507 (undec_sm_pwdb >= 508 TX_POWER_NEAR_FIELD_THRESH_LVL1)) { 509 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1; 510 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 511 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n"); 512 } else if (undec_sm_pwdb < 513 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) { 514 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL; 515 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 516 "TXHIGHPWRLEVEL_NORMAL\n"); 517 } 518 519 if (rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl) { 520 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 521 "PHY_SetTxPowerLevel8192S() Channel = %d\n", 522 rtlphy->current_channel); 523 rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel); 524 } 525 526 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl; 527 } 528 529 void rtl8723e_dm_write_dig(struct ieee80211_hw *hw) 530 { 531 struct rtl_priv *rtlpriv = rtl_priv(hw); 532 struct dig_t *dm_digtable = &rtlpriv->dm_digtable; 533 534 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, 535 "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n", 536 dm_digtable->cur_igvalue, dm_digtable->pre_igvalue, 537 dm_digtable->back_val); 538 539 if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) { 540 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, 541 dm_digtable->cur_igvalue); 542 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, 543 dm_digtable->cur_igvalue); 544 545 dm_digtable->pre_igvalue = dm_digtable->cur_igvalue; 546 } 547 } 548 549 static void rtl8723e_dm_pwdb_monitor(struct ieee80211_hw *hw) 550 { 551 } 552 553 static void rtl8723e_dm_check_edca_turbo(struct ieee80211_hw *hw) 554 { 555 struct rtl_priv *rtlpriv = rtl_priv(hw); 556 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 557 558 static u64 last_txok_cnt; 559 static u64 last_rxok_cnt; 560 static u32 last_bt_edca_ul; 561 static u32 last_bt_edca_dl; 562 u64 cur_txok_cnt = 0; 563 u64 cur_rxok_cnt = 0; 564 u32 edca_be_ul = 0x5ea42b; 565 u32 edca_be_dl = 0x5ea42b; 566 bool bt_change_edca = false; 567 568 if ((last_bt_edca_ul != rtlpriv->btcoexist.bt_edca_ul) || 569 (last_bt_edca_dl != rtlpriv->btcoexist.bt_edca_dl)) { 570 rtlpriv->dm.current_turbo_edca = false; 571 last_bt_edca_ul = rtlpriv->btcoexist.bt_edca_ul; 572 last_bt_edca_dl = rtlpriv->btcoexist.bt_edca_dl; 573 } 574 575 if (rtlpriv->btcoexist.bt_edca_ul != 0) { 576 edca_be_ul = rtlpriv->btcoexist.bt_edca_ul; 577 bt_change_edca = true; 578 } 579 580 if (rtlpriv->btcoexist.bt_edca_dl != 0) { 581 edca_be_ul = rtlpriv->btcoexist.bt_edca_dl; 582 bt_change_edca = true; 583 } 584 585 if (mac->link_state != MAC80211_LINKED) { 586 rtlpriv->dm.current_turbo_edca = false; 587 return; 588 } 589 if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) && 590 (!rtlpriv->dm.disable_framebursting))) { 591 592 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt; 593 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt; 594 595 if (cur_rxok_cnt > 4 * cur_txok_cnt) { 596 if (!rtlpriv->dm.is_cur_rdlstate || 597 !rtlpriv->dm.current_turbo_edca) { 598 rtl_write_dword(rtlpriv, 599 REG_EDCA_BE_PARAM, 600 edca_be_dl); 601 rtlpriv->dm.is_cur_rdlstate = true; 602 } 603 } else { 604 if (rtlpriv->dm.is_cur_rdlstate || 605 !rtlpriv->dm.current_turbo_edca) { 606 rtl_write_dword(rtlpriv, 607 REG_EDCA_BE_PARAM, 608 edca_be_ul); 609 rtlpriv->dm.is_cur_rdlstate = false; 610 } 611 } 612 rtlpriv->dm.current_turbo_edca = true; 613 } else { 614 if (rtlpriv->dm.current_turbo_edca) { 615 u8 tmp = AC0_BE; 616 rtlpriv->cfg->ops->set_hw_reg(hw, 617 HW_VAR_AC_PARAM, 618 (u8 *)(&tmp)); 619 rtlpriv->dm.current_turbo_edca = false; 620 } 621 } 622 623 rtlpriv->dm.is_any_nonbepkts = false; 624 last_txok_cnt = rtlpriv->stats.txbytesunicast; 625 last_rxok_cnt = rtlpriv->stats.rxbytesunicast; 626 } 627 628 static void rtl8723e_dm_initialize_txpower_tracking_thermalmeter( 629 struct ieee80211_hw *hw) 630 { 631 struct rtl_priv *rtlpriv = rtl_priv(hw); 632 633 rtlpriv->dm.txpower_tracking = true; 634 rtlpriv->dm.txpower_trackinginit = false; 635 636 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 637 "pMgntInfo->txpower_tracking = %d\n", 638 rtlpriv->dm.txpower_tracking); 639 } 640 641 static void rtl8723e_dm_initialize_txpower_tracking(struct ieee80211_hw *hw) 642 { 643 rtl8723e_dm_initialize_txpower_tracking_thermalmeter(hw); 644 } 645 646 void rtl8723e_dm_check_txpower_tracking(struct ieee80211_hw *hw) 647 { 648 return; 649 } 650 651 void rtl8723e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw) 652 { 653 struct rtl_priv *rtlpriv = rtl_priv(hw); 654 struct rate_adaptive *p_ra = &rtlpriv->ra; 655 656 p_ra->ratr_state = DM_RATR_STA_INIT; 657 p_ra->pre_ratr_state = DM_RATR_STA_INIT; 658 659 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) 660 rtlpriv->dm.useramask = true; 661 else 662 rtlpriv->dm.useramask = false; 663 664 } 665 666 static void rtl8723e_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw) 667 { 668 struct rtl_priv *rtlpriv = rtl_priv(hw); 669 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 670 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 671 struct rate_adaptive *p_ra = &rtlpriv->ra; 672 u32 low_rssithresh_for_ra, high_rssithresh_for_ra; 673 struct ieee80211_sta *sta = NULL; 674 675 if (is_hal_stop(rtlhal)) { 676 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 677 " driver is going to unload\n"); 678 return; 679 } 680 681 if (!rtlpriv->dm.useramask) { 682 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 683 " driver does not control rate adaptive mask\n"); 684 return; 685 } 686 687 if (mac->link_state == MAC80211_LINKED && 688 mac->opmode == NL80211_IFTYPE_STATION) { 689 switch (p_ra->pre_ratr_state) { 690 case DM_RATR_STA_HIGH: 691 high_rssithresh_for_ra = 50; 692 low_rssithresh_for_ra = 20; 693 break; 694 case DM_RATR_STA_MIDDLE: 695 high_rssithresh_for_ra = 55; 696 low_rssithresh_for_ra = 20; 697 break; 698 case DM_RATR_STA_LOW: 699 high_rssithresh_for_ra = 60; 700 low_rssithresh_for_ra = 25; 701 break; 702 default: 703 high_rssithresh_for_ra = 50; 704 low_rssithresh_for_ra = 20; 705 break; 706 } 707 708 if (rtlpriv->link_info.bcn_rx_inperiod == 0) 709 switch (p_ra->pre_ratr_state) { 710 case DM_RATR_STA_HIGH: 711 default: 712 p_ra->ratr_state = DM_RATR_STA_MIDDLE; 713 break; 714 case DM_RATR_STA_MIDDLE: 715 case DM_RATR_STA_LOW: 716 p_ra->ratr_state = DM_RATR_STA_LOW; 717 break; 718 } 719 else if (rtlpriv->dm.undec_sm_pwdb > high_rssithresh_for_ra) 720 p_ra->ratr_state = DM_RATR_STA_HIGH; 721 else if (rtlpriv->dm.undec_sm_pwdb > low_rssithresh_for_ra) 722 p_ra->ratr_state = DM_RATR_STA_MIDDLE; 723 else 724 p_ra->ratr_state = DM_RATR_STA_LOW; 725 726 if (p_ra->pre_ratr_state != p_ra->ratr_state) { 727 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 728 "RSSI = %ld\n", 729 rtlpriv->dm.undec_sm_pwdb); 730 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 731 "RSSI_LEVEL = %d\n", p_ra->ratr_state); 732 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 733 "PreState = %d, CurState = %d\n", 734 p_ra->pre_ratr_state, p_ra->ratr_state); 735 736 rcu_read_lock(); 737 sta = rtl_find_sta(hw, mac->bssid); 738 if (sta) 739 rtlpriv->cfg->ops->update_rate_tbl(hw, sta, 740 p_ra->ratr_state, 741 true); 742 rcu_read_unlock(); 743 744 p_ra->pre_ratr_state = p_ra->ratr_state; 745 } 746 } 747 } 748 749 void rtl8723e_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal) 750 { 751 struct rtl_priv *rtlpriv = rtl_priv(hw); 752 struct ps_t *dm_pstable = &rtlpriv->dm_pstable; 753 static u8 initialize; 754 static u32 reg_874, reg_c70, reg_85c, reg_a74; 755 756 if (initialize == 0) { 757 reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 758 MASKDWORD) & 0x1CC000) >> 14; 759 760 reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1, 761 MASKDWORD) & BIT(3)) >> 3; 762 763 reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 764 MASKDWORD) & 0xFF000000) >> 24; 765 766 reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12; 767 768 initialize = 1; 769 } 770 771 if (!bforce_in_normal) { 772 if (dm_pstable->rssi_val_min != 0) { 773 if (dm_pstable->pre_rfstate == RF_NORMAL) { 774 if (dm_pstable->rssi_val_min >= 30) 775 dm_pstable->cur_rfstate = RF_SAVE; 776 else 777 dm_pstable->cur_rfstate = RF_NORMAL; 778 } else { 779 if (dm_pstable->rssi_val_min <= 25) 780 dm_pstable->cur_rfstate = RF_NORMAL; 781 else 782 dm_pstable->cur_rfstate = RF_SAVE; 783 } 784 } else { 785 dm_pstable->cur_rfstate = RF_MAX; 786 } 787 } else { 788 dm_pstable->cur_rfstate = RF_NORMAL; 789 } 790 791 if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) { 792 if (dm_pstable->cur_rfstate == RF_SAVE) { 793 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 794 BIT(5), 0x1); 795 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 796 0x1C0000, 0x2); 797 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0); 798 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 799 0xFF000000, 0x63); 800 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 801 0xC000, 0x2); 802 rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3); 803 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); 804 rtl_set_bbreg(hw, 0x818, BIT(28), 0x1); 805 } else { 806 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 807 0x1CC000, reg_874); 808 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 809 reg_c70); 810 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000, 811 reg_85c); 812 rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74); 813 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0); 814 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, 815 BIT(5), 0x0); 816 } 817 818 dm_pstable->pre_rfstate = dm_pstable->cur_rfstate; 819 } 820 } 821 822 static void rtl8723e_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw) 823 { 824 struct rtl_priv *rtlpriv = rtl_priv(hw); 825 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 826 struct ps_t *dm_pstable = &rtlpriv->dm_pstable; 827 828 if (((mac->link_state == MAC80211_NOLINK)) && 829 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) { 830 dm_pstable->rssi_val_min = 0; 831 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 832 "Not connected to any\n"); 833 } 834 835 if (mac->link_state == MAC80211_LINKED) { 836 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 837 dm_pstable->rssi_val_min = 838 rtlpriv->dm.entry_min_undec_sm_pwdb; 839 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 840 "AP Client PWDB = 0x%lx\n", 841 dm_pstable->rssi_val_min); 842 } else { 843 dm_pstable->rssi_val_min = 844 rtlpriv->dm.undec_sm_pwdb; 845 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 846 "STA Default Port PWDB = 0x%lx\n", 847 dm_pstable->rssi_val_min); 848 } 849 } else { 850 dm_pstable->rssi_val_min = 851 rtlpriv->dm.entry_min_undec_sm_pwdb; 852 853 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, 854 "AP Ext Port PWDB = 0x%lx\n", 855 dm_pstable->rssi_val_min); 856 } 857 858 rtl8723e_dm_rf_saving(hw, false); 859 } 860 861 void rtl8723e_dm_init(struct ieee80211_hw *hw) 862 { 863 struct rtl_priv *rtlpriv = rtl_priv(hw); 864 865 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER; 866 rtl_dm_diginit(hw, 0x20); 867 rtl8723_dm_init_dynamic_txpower(hw); 868 rtl8723_dm_init_edca_turbo(hw); 869 rtl8723e_dm_init_rate_adaptive_mask(hw); 870 rtl8723e_dm_initialize_txpower_tracking(hw); 871 rtl8723_dm_init_dynamic_bb_powersaving(hw); 872 } 873 874 void rtl8723e_dm_watchdog(struct ieee80211_hw *hw) 875 { 876 struct rtl_priv *rtlpriv = rtl_priv(hw); 877 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 878 bool fw_current_inpsmode = false; 879 bool fw_ps_awake = true; 880 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 881 (u8 *)(&fw_current_inpsmode)); 882 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON, 883 (u8 *)(&fw_ps_awake)); 884 885 if (ppsc->p2p_ps_info.p2p_ps_mode) 886 fw_ps_awake = false; 887 888 spin_lock(&rtlpriv->locks.rf_ps_lock); 889 if ((ppsc->rfpwr_state == ERFON) && 890 ((!fw_current_inpsmode) && fw_ps_awake) && 891 (!ppsc->rfchange_inprogress)) { 892 rtl8723e_dm_pwdb_monitor(hw); 893 rtl8723e_dm_dig(hw); 894 rtl8723e_dm_false_alarm_counter_statistics(hw); 895 rtl8723e_dm_dynamic_bb_powersaving(hw); 896 rtl8723e_dm_dynamic_txpower(hw); 897 rtl8723e_dm_check_txpower_tracking(hw); 898 rtl8723e_dm_refresh_rate_adaptive_mask(hw); 899 rtl8723e_dm_bt_coexist(hw); 900 rtl8723e_dm_check_edca_turbo(hw); 901 } 902 spin_unlock(&rtlpriv->locks.rf_ps_lock); 903 if (rtlpriv->btcoexist.init_set) 904 rtl_write_byte(rtlpriv, 0x76e, 0xc); 905 } 906 907 static void rtl8723e_dm_init_bt_coexist(struct ieee80211_hw *hw) 908 { 909 struct rtl_priv *rtlpriv = rtl_priv(hw); 910 911 rtlpriv->btcoexist.bt_rfreg_origin_1e 912 = rtl_get_rfreg(hw, (enum radio_path)0, RF_RCK1, 0xfffff); 913 rtlpriv->btcoexist.bt_rfreg_origin_1f 914 = rtl_get_rfreg(hw, (enum radio_path)0, RF_RCK2, 0xf0); 915 916 rtlpriv->btcoexist.cstate = 0; 917 rtlpriv->btcoexist.previous_state = 0; 918 rtlpriv->btcoexist.cstate_h = 0; 919 rtlpriv->btcoexist.previous_state_h = 0; 920 rtlpriv->btcoexist.lps_counter = 0; 921 922 /* Enable counter statistics */ 923 rtl_write_byte(rtlpriv, 0x76e, 0x4); 924 rtl_write_byte(rtlpriv, 0x778, 0x3); 925 rtl_write_byte(rtlpriv, 0x40, 0x20); 926 927 rtlpriv->btcoexist.init_set = true; 928 } 929 930 void rtl8723e_dm_bt_coexist(struct ieee80211_hw *hw) 931 { 932 struct rtl_priv *rtlpriv = rtl_priv(hw); 933 u8 tmp_byte = 0; 934 if (!rtlpriv->btcoexist.bt_coexistence) { 935 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 936 "[DM]{BT], BT not exist!!\n"); 937 return; 938 } 939 940 if (!rtlpriv->btcoexist.init_set) { 941 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 942 "[DM][BT], rtl8723e_dm_bt_coexist()\n"); 943 rtl8723e_dm_init_bt_coexist(hw); 944 } 945 946 tmp_byte = rtl_read_byte(rtlpriv, 0x40); 947 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, 948 "[DM][BT], 0x40 is 0x%x\n", tmp_byte); 949 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, 950 "[DM][BT], bt_dm_coexist start\n"); 951 rtl8723e_dm_bt_coexist_8723(hw); 952 } 953