1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4 #ifndef __RTL8723E_DEF_H__ 5 #define __RTL8723E_DEF_H__ 6 7 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 8 #define HAL_PRIME_CHNL_OFFSET_LOWER 1 9 #define HAL_PRIME_CHNL_OFFSET_UPPER 2 10 11 #define RX_MPDU_QUEUE 0 12 #define RX_CMD_QUEUE 1 13 14 #define C2H_RX_CMD_HDR_LEN 8 15 #define GET_C2H_CMD_CMD_LEN(__prxhdr) \ 16 LE_BITS_TO_4BYTE((__prxhdr), 0, 16) 17 #define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \ 18 LE_BITS_TO_4BYTE((__prxhdr), 16, 8) 19 #define GET_C2H_CMD_CMD_SEQ(__prxhdr) \ 20 LE_BITS_TO_4BYTE((__prxhdr), 24, 7) 21 #define GET_C2H_CMD_CONTINUE(__prxhdr) \ 22 LE_BITS_TO_4BYTE((__prxhdr), 31, 1) 23 #define GET_C2H_CMD_CONTENT(__prxhdr) \ 24 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN) 25 26 #define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \ 27 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8) 28 #define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \ 29 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8) 30 #define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \ 31 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16) 32 #define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \ 33 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5) 34 #define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \ 35 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1) 36 #define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \ 37 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5) 38 #define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \ 39 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1) 40 #define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \ 41 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4) 42 #define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \ 43 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12) 44 45 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) 46 #define CHIP_BONDING_92C_1T2R 0x1 47 48 #define CHIP_8723 BIT(0) 49 #define NORMAL_CHIP BIT(3) 50 #define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6))) 51 #define RF_TYPE_1T2R BIT(4) 52 #define RF_TYPE_2T2R BIT(5) 53 #define CHIP_VENDOR_UMC BIT(7) 54 #define B_CUT_VERSION BIT(12) 55 #define C_CUT_VERSION BIT(13) 56 #define D_CUT_VERSION ((BIT(12)|BIT(13))) 57 #define E_CUT_VERSION BIT(14) 58 #define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) 59 60 /* MASK */ 61 #define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2)) 62 #define CHIP_TYPE_MASK BIT(3) 63 #define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6)) 64 #define MANUFACTUER_MASK BIT(7) 65 #define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8)) 66 #define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12)) 67 68 /* Get element */ 69 #define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK) 70 #define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK) 71 #define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK) 72 #define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK) 73 #define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK) 74 #define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK) 75 76 #define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0) ?\ 77 true : false) 78 #define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723) ? \ 79 true : false) 80 #define IS_1T1R(version) ((GET_CVID_RF_TYPE(version)) ? false : true) 81 #define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\ 82 ? true : false) 83 #define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\ 84 ? true : false) 85 #define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version)) ? \ 86 true : false) 87 88 #define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version))\ 89 ? ((GET_CVID_CUT_VERSION(version)) ? \ 90 false : true) : false) 91 #define IS_VENDOR_8723_A_CUT(version) ((IS_8723_SERIES(version))\ 92 ? ((GET_CVID_CUT_VERSION(version)) ? \ 93 false : true) : false) 94 #define IS_VENDOR_8723A_B_CUT(version) ((IS_8723_SERIES(version))\ 95 ? ((GET_CVID_CUT_VERSION(version) == \ 96 B_CUT_VERSION) ? true : false) : false) 97 #define IS_81XXC_VENDOR_UMC_B_CUT(version) ((IS_CHIP_VENDOR_UMC(version))\ 98 ? ((GET_CVID_CUT_VERSION(version) == \ 99 B_CUT_VERSION) ? true : false) : false) 100 101 enum rf_optype { 102 RF_OP_BY_SW_3WIRE = 0, 103 RF_OP_BY_FW, 104 RF_OP_MAX 105 }; 106 107 enum rf_power_state { 108 RF_ON, 109 RF_OFF, 110 RF_SLEEP, 111 RF_SHUT_DOWN, 112 }; 113 114 enum power_save_mode { 115 POWER_SAVE_MODE_ACTIVE, 116 POWER_SAVE_MODE_SAVE, 117 }; 118 119 enum power_policy_config { 120 POWERCFG_MAX_POWER_SAVINGS, 121 POWERCFG_GLOBAL_POWER_SAVINGS, 122 POWERCFG_LOCAL_POWER_SAVINGS, 123 POWERCFG_LENOVO, 124 }; 125 126 enum interface_select_pci { 127 INTF_SEL1_MINICARD = 0, 128 INTF_SEL0_PCIE = 1, 129 INTF_SEL2_RSV = 2, 130 INTF_SEL3_RSV = 3, 131 }; 132 133 enum rtl_desc_qsel { 134 QSLT_BK = 0x2, 135 QSLT_BE = 0x0, 136 QSLT_VI = 0x5, 137 QSLT_VO = 0x7, 138 QSLT_BEACON = 0x10, 139 QSLT_HIGH = 0x11, 140 QSLT_MGNT = 0x12, 141 QSLT_CMD = 0x13, 142 }; 143 144 enum rtl_desc8723e_rate { 145 DESC92C_RATE1M = 0x00, 146 DESC92C_RATE2M = 0x01, 147 DESC92C_RATE5_5M = 0x02, 148 DESC92C_RATE11M = 0x03, 149 150 DESC92C_RATE6M = 0x04, 151 DESC92C_RATE9M = 0x05, 152 DESC92C_RATE12M = 0x06, 153 DESC92C_RATE18M = 0x07, 154 DESC92C_RATE24M = 0x08, 155 DESC92C_RATE36M = 0x09, 156 DESC92C_RATE48M = 0x0a, 157 DESC92C_RATE54M = 0x0b, 158 159 DESC92C_RATEMCS0 = 0x0c, 160 DESC92C_RATEMCS1 = 0x0d, 161 DESC92C_RATEMCS2 = 0x0e, 162 DESC92C_RATEMCS3 = 0x0f, 163 DESC92C_RATEMCS4 = 0x10, 164 DESC92C_RATEMCS5 = 0x11, 165 DESC92C_RATEMCS6 = 0x12, 166 DESC92C_RATEMCS7 = 0x13, 167 DESC92C_RATEMCS8 = 0x14, 168 DESC92C_RATEMCS9 = 0x15, 169 DESC92C_RATEMCS10 = 0x16, 170 DESC92C_RATEMCS11 = 0x17, 171 DESC92C_RATEMCS12 = 0x18, 172 DESC92C_RATEMCS13 = 0x19, 173 DESC92C_RATEMCS14 = 0x1a, 174 DESC92C_RATEMCS15 = 0x1b, 175 DESC92C_RATEMCS15_SG = 0x1c, 176 DESC92C_RATEMCS32 = 0x20, 177 }; 178 179 struct phy_sts_cck_8723e_t { 180 u8 adc_pwdb_X[4]; 181 u8 sq_rpt; 182 u8 cck_agc_rpt; 183 }; 184 185 struct h2c_cmd_8723e { 186 u8 element_id; 187 u32 cmd_len; 188 u8 *p_cmdbuffer; 189 }; 190 191 #endif 192