1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../core.h"
6 #include "../base.h"
7 #include "../pci.h"
8 #include "reg.h"
9 #include "def.h"
10 #include "phy.h"
11 #include "dm.h"
12 #include "fw.h"
13 #include "hw.h"
14 #include "trx.h"
15 #include "led.h"
16 
17 #include <linux/module.h>
18 
19 static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw)
20 {
21 	struct rtl_priv *rtlpriv = rtl_priv(hw);
22 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
23 
24 	/*close ASPM for AMD defaultly */
25 	rtlpci->const_amdpci_aspm = 0;
26 
27 	/* ASPM PS mode.
28 	 * 0 - Disable ASPM,
29 	 * 1 - Enable ASPM without Clock Req,
30 	 * 2 - Enable ASPM with Clock Req,
31 	 * 3 - Alwyas Enable ASPM with Clock Req,
32 	 * 4 - Always Enable ASPM without Clock Req.
33 	 * set defult to RTL8192CE:3 RTL8192E:2
34 	 * */
35 	rtlpci->const_pci_aspm = 2;
36 
37 	/*Setting for PCI-E device */
38 	rtlpci->const_devicepci_aspm_setting = 0x03;
39 
40 	/*Setting for PCI-E bridge */
41 	rtlpci->const_hostpci_aspm_setting = 0x02;
42 
43 	/* In Hw/Sw Radio Off situation.
44 	 * 0 - Default,
45 	 * 1 - From ASPM setting without low Mac Pwr,
46 	 * 2 - From ASPM setting with low Mac Pwr,
47 	 * 3 - Bus D3
48 	 * set default to RTL8192CE:0 RTL8192SE:2
49 	 */
50 	rtlpci->const_hwsw_rfoff_d3 = 2;
51 
52 	/* This setting works for those device with
53 	 * backdoor ASPM setting such as EPHY setting.
54 	 * 0 - Not support ASPM,
55 	 * 1 - Support ASPM,
56 	 * 2 - According to chipset.
57 	 */
58 	rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
59 }
60 
61 static void rtl92se_fw_cb(const struct firmware *firmware, void *context)
62 {
63 	struct ieee80211_hw *hw = context;
64 	struct rtl_priv *rtlpriv = rtl_priv(hw);
65 	struct rt_firmware *pfirmware = NULL;
66 	char *fw_name = "rtlwifi/rtl8192sefw.bin";
67 
68 	RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
69 			 "Firmware callback routine entered!\n");
70 	complete(&rtlpriv->firmware_loading_complete);
71 	if (!firmware) {
72 		pr_err("Firmware %s not available\n", fw_name);
73 		rtlpriv->max_fw_size = 0;
74 		return;
75 	}
76 	if (firmware->size > rtlpriv->max_fw_size) {
77 		pr_err("Firmware is too big!\n");
78 		rtlpriv->max_fw_size = 0;
79 		release_firmware(firmware);
80 		return;
81 	}
82 	pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware;
83 	memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size);
84 	pfirmware->sz_fw_tmpbufferlen = firmware->size;
85 	release_firmware(firmware);
86 }
87 
88 static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)
89 {
90 	struct rtl_priv *rtlpriv = rtl_priv(hw);
91 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
92 	int err = 0;
93 	u16 earlyrxthreshold = 7;
94 	char *fw_name = "rtlwifi/rtl8192sefw.bin";
95 
96 	rtlpriv->dm.dm_initialgain_enable = true;
97 	rtlpriv->dm.dm_flag = 0;
98 	rtlpriv->dm.disable_framebursting = false;
99 	rtlpriv->dm.thermalvalue = 0;
100 	rtlpriv->dm.useramask = true;
101 
102 	/* compatible 5G band 91se just 2.4G band & smsp */
103 	rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
104 	rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
105 	rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
106 
107 	rtlpci->transmit_config = 0;
108 
109 	rtlpci->receive_config =
110 			RCR_APPFCS |
111 			RCR_APWRMGT |
112 			/*RCR_ADD3 |*/
113 			RCR_AMF	|
114 			RCR_ADF |
115 			RCR_APP_MIC |
116 			RCR_APP_ICV |
117 			RCR_AICV |
118 			/* Accept ICV error, CRC32 Error */
119 			RCR_ACRC32 |
120 			RCR_AB |
121 			/* Accept Broadcast, Multicast */
122 			RCR_AM	|
123 			/* Accept Physical match */
124 			RCR_APM |
125 			/* Accept Destination Address packets */
126 			/*RCR_AAP |*/
127 			RCR_APP_PHYST_STAFF |
128 			/* Accept PHY status */
129 			RCR_APP_PHYST_RXFF |
130 			(earlyrxthreshold << RCR_FIFO_OFFSET);
131 
132 	rtlpci->irq_mask[0] = (u32)
133 			(IMR_ROK |
134 			IMR_VODOK |
135 			IMR_VIDOK |
136 			IMR_BEDOK |
137 			IMR_BKDOK |
138 			IMR_HCCADOK |
139 			IMR_MGNTDOK |
140 			IMR_COMDOK |
141 			IMR_HIGHDOK |
142 			IMR_BDOK |
143 			IMR_RXCMDOK |
144 			/*IMR_TIMEOUT0 |*/
145 			IMR_RDU |
146 			IMR_RXFOVW	|
147 			IMR_BCNINT
148 			/*| IMR_TXFOVW*/
149 			/*| IMR_TBDOK |
150 			IMR_TBDER*/);
151 
152 	rtlpci->irq_mask[1] = (u32) 0;
153 
154 	rtlpci->shortretry_limit = 0x30;
155 	rtlpci->longretry_limit = 0x30;
156 
157 	rtlpci->first_init = true;
158 
159 	/* for LPS & IPS */
160 	rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
161 	rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
162 	rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
163 	if (!rtlpriv->psc.inactiveps)
164 		pr_info("Power Save off (module option)\n");
165 	if (!rtlpriv->psc.fwctrl_lps)
166 		pr_info("FW Power Save off (module option)\n");
167 	rtlpriv->psc.reg_fwctrl_lps = 3;
168 	rtlpriv->psc.reg_max_lps_awakeintvl = 5;
169 	/* for ASPM, you can close aspm through
170 	 * set const_support_pciaspm = 0 */
171 	rtl92s_init_aspm_vars(hw);
172 
173 	if (rtlpriv->psc.reg_fwctrl_lps == 1)
174 		rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
175 	else if (rtlpriv->psc.reg_fwctrl_lps == 2)
176 		rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
177 	else if (rtlpriv->psc.reg_fwctrl_lps == 3)
178 		rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
179 
180 	/* for firmware buf */
181 	rtlpriv->rtlhal.pfirmware = vzalloc(sizeof(struct rt_firmware));
182 	if (!rtlpriv->rtlhal.pfirmware)
183 		return 1;
184 
185 	rtlpriv->max_fw_size = RTL8190_MAX_FIRMWARE_CODE_SIZE*2 +
186 			       sizeof(struct fw_hdr);
187 	pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n"
188 		"Loading firmware %s\n", fw_name);
189 	/* request fw */
190 	err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
191 				      rtlpriv->io.dev, GFP_KERNEL, hw,
192 				      rtl92se_fw_cb);
193 	if (err) {
194 		pr_err("Failed to request firmware!\n");
195 		vfree(rtlpriv->rtlhal.pfirmware);
196 		rtlpriv->rtlhal.pfirmware = NULL;
197 		return 1;
198 	}
199 
200 	return err;
201 }
202 
203 static void rtl92s_deinit_sw_vars(struct ieee80211_hw *hw)
204 {
205 	struct rtl_priv *rtlpriv = rtl_priv(hw);
206 
207 	if (rtlpriv->rtlhal.pfirmware) {
208 		vfree(rtlpriv->rtlhal.pfirmware);
209 		rtlpriv->rtlhal.pfirmware = NULL;
210 	}
211 }
212 
213 static bool rtl92se_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue,
214 				      u16 index)
215 {
216 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
217 	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
218 	u8 *entry = (u8 *)(&ring->desc[ring->idx]);
219 	u8 own = (u8)rtl92se_get_desc(hw, entry, true, HW_DESC_OWN);
220 
221 	if (own)
222 		return false;
223 	return true;
224 }
225 
226 static struct rtl_hal_ops rtl8192se_hal_ops = {
227 	.init_sw_vars = rtl92s_init_sw_vars,
228 	.deinit_sw_vars = rtl92s_deinit_sw_vars,
229 	.read_eeprom_info = rtl92se_read_eeprom_info,
230 	.interrupt_recognized = rtl92se_interrupt_recognized,
231 	.hw_init = rtl92se_hw_init,
232 	.hw_disable = rtl92se_card_disable,
233 	.hw_suspend = rtl92se_suspend,
234 	.hw_resume = rtl92se_resume,
235 	.enable_interrupt = rtl92se_enable_interrupt,
236 	.disable_interrupt = rtl92se_disable_interrupt,
237 	.set_network_type = rtl92se_set_network_type,
238 	.set_chk_bssid = rtl92se_set_check_bssid,
239 	.set_qos = rtl92se_set_qos,
240 	.set_bcn_reg = rtl92se_set_beacon_related_registers,
241 	.set_bcn_intv = rtl92se_set_beacon_interval,
242 	.update_interrupt_mask = rtl92se_update_interrupt_mask,
243 	.get_hw_reg = rtl92se_get_hw_reg,
244 	.set_hw_reg = rtl92se_set_hw_reg,
245 	.update_rate_tbl = rtl92se_update_hal_rate_tbl,
246 	.fill_tx_desc = rtl92se_tx_fill_desc,
247 	.fill_tx_cmddesc = rtl92se_tx_fill_cmddesc,
248 	.query_rx_desc = rtl92se_rx_query_desc,
249 	.set_channel_access = rtl92se_update_channel_access_setting,
250 	.radio_onoff_checking = rtl92se_gpio_radio_on_off_checking,
251 	.set_bw_mode = rtl92s_phy_set_bw_mode,
252 	.switch_channel = rtl92s_phy_sw_chnl,
253 	.dm_watchdog = rtl92s_dm_watchdog,
254 	.scan_operation_backup = rtl92s_phy_scan_operation_backup,
255 	.set_rf_power_state = rtl92s_phy_set_rf_power_state,
256 	.led_control = rtl92se_led_control,
257 	.set_desc = rtl92se_set_desc,
258 	.get_desc = rtl92se_get_desc,
259 	.is_tx_desc_closed = rtl92se_is_tx_desc_closed,
260 	.tx_polling = rtl92se_tx_polling,
261 	.enable_hw_sec = rtl92se_enable_hw_security_config,
262 	.set_key = rtl92se_set_key,
263 	.init_sw_leds = rtl92se_init_sw_leds,
264 	.get_bbreg = rtl92s_phy_query_bb_reg,
265 	.set_bbreg = rtl92s_phy_set_bb_reg,
266 	.get_rfreg = rtl92s_phy_query_rf_reg,
267 	.set_rfreg = rtl92s_phy_set_rf_reg,
268 	.get_btc_status = rtl_btc_status_false,
269 };
270 
271 static struct rtl_mod_params rtl92se_mod_params = {
272 	.sw_crypto = false,
273 	.inactiveps = true,
274 	.swctrl_lps = true,
275 	.fwctrl_lps = false,
276 	.aspm_support = 2,
277 	.debug_level = 0,
278 	.debug_mask = 0,
279 };
280 
281 /* Because memory R/W bursting will cause system hang/crash
282  * for 92se, so we don't read back after every write action */
283 static const struct rtl_hal_cfg rtl92se_hal_cfg = {
284 	.bar_id = 1,
285 	.write_readback = false,
286 	.name = "rtl92s_pci",
287 	.ops = &rtl8192se_hal_ops,
288 	.mod_params = &rtl92se_mod_params,
289 
290 	.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
291 	.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
292 	.maps[SYS_CLK] = SYS_CLKR,
293 	.maps[MAC_RCR_AM] = RCR_AM,
294 	.maps[MAC_RCR_AB] = RCR_AB,
295 	.maps[MAC_RCR_ACRC32] = RCR_ACRC32,
296 	.maps[MAC_RCR_ACF] = RCR_ACF,
297 	.maps[MAC_RCR_AAP] = RCR_AAP,
298 	.maps[MAC_HIMR] = INTA_MASK,
299 	.maps[MAC_HIMRE] = INTA_MASK + 4,
300 
301 	.maps[EFUSE_TEST] = REG_EFUSE_TEST,
302 	.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
303 	.maps[EFUSE_CLK] = REG_EFUSE_CLK,
304 	.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
305 	.maps[EFUSE_PWC_EV12V] = 0, /* nouse for 8192se */
306 	.maps[EFUSE_FEN_ELDR] = 0, /* nouse for 8192se */
307 	.maps[EFUSE_LOADER_CLK_EN] = 0,/* nouse for 8192se */
308 	.maps[EFUSE_ANA8M] = EFUSE_ANA8M,
309 	.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE_92S,
310 	.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
311 	.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
312 	.maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
313 
314 	.maps[RWCAM] = REG_RWCAM,
315 	.maps[WCAMI] = REG_WCAMI,
316 	.maps[RCAMO] = REG_RCAMO,
317 	.maps[CAMDBG] = REG_CAMDBG,
318 	.maps[SECR] = REG_SECR,
319 	.maps[SEC_CAM_NONE] = CAM_NONE,
320 	.maps[SEC_CAM_WEP40] = CAM_WEP40,
321 	.maps[SEC_CAM_TKIP] = CAM_TKIP,
322 	.maps[SEC_CAM_AES] = CAM_AES,
323 	.maps[SEC_CAM_WEP104] = CAM_WEP104,
324 
325 	.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
326 	.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
327 	.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
328 	.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
329 	.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
330 	.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
331 	.maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
332 	.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
333 	.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
334 	.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
335 	.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
336 	.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
337 	.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
338 	.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
339 	.maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
340 	.maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
341 
342 	.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
343 	.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
344 	.maps[RTL_IMR_BCNINT] = IMR_BCNINT,
345 	.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
346 	.maps[RTL_IMR_RDU] = IMR_RDU,
347 	.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
348 	.maps[RTL_IMR_BDOK] = IMR_BDOK,
349 	.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
350 	.maps[RTL_IMR_TBDER] = IMR_TBDER,
351 	.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
352 	.maps[RTL_IMR_COMDOK] = IMR_COMDOK,
353 	.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
354 	.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
355 	.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
356 	.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
357 	.maps[RTL_IMR_VODOK] = IMR_VODOK,
358 	.maps[RTL_IMR_ROK] = IMR_ROK,
359 	.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
360 
361 	.maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
362 	.maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
363 	.maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
364 	.maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
365 	.maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
366 	.maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
367 	.maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
368 	.maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
369 	.maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
370 	.maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
371 	.maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
372 	.maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
373 
374 	.maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
375 	.maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
376 };
377 
378 static const struct pci_device_id rtl92se_pci_ids[] = {
379 	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8192, rtl92se_hal_cfg)},
380 	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8171, rtl92se_hal_cfg)},
381 	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8172, rtl92se_hal_cfg)},
382 	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8173, rtl92se_hal_cfg)},
383 	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8174, rtl92se_hal_cfg)},
384 	{},
385 };
386 
387 MODULE_DEVICE_TABLE(pci, rtl92se_pci_ids);
388 
389 MODULE_AUTHOR("lizhaoming	<chaoming_li@realsil.com.cn>");
390 MODULE_AUTHOR("Realtek WlanFAE	<wlanfae@realtek.com>");
391 MODULE_AUTHOR("Larry Finger	<Larry.Finger@lwfinger.net>");
392 MODULE_LICENSE("GPL");
393 MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless");
394 MODULE_FIRMWARE("rtlwifi/rtl8192sefw.bin");
395 
396 module_param_named(swenc, rtl92se_mod_params.sw_crypto, bool, 0444);
397 module_param_named(debug_level, rtl92se_mod_params.debug_level, int, 0644);
398 module_param_named(debug_mask, rtl92se_mod_params.debug_mask, ullong, 0644);
399 module_param_named(ips, rtl92se_mod_params.inactiveps, bool, 0444);
400 module_param_named(swlps, rtl92se_mod_params.swctrl_lps, bool, 0444);
401 module_param_named(fwlps, rtl92se_mod_params.fwctrl_lps, bool, 0444);
402 module_param_named(aspm, rtl92se_mod_params.aspm_support, int, 0444);
403 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
404 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
405 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n");
406 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 0)\n");
407 MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
408 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
409 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
410 
411 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
412 
413 static struct pci_driver rtl92se_driver = {
414 	.name = KBUILD_MODNAME,
415 	.id_table = rtl92se_pci_ids,
416 	.probe = rtl_pci_probe,
417 	.remove = rtl_pci_disconnect,
418 	.driver.pm = &rtlwifi_pm_ops,
419 };
420 
421 module_pci_driver(rtl92se_driver);
422