1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30 #include "../wifi.h" 31 #include "../pci.h" 32 #include "../ps.h" 33 #include "../core.h" 34 #include "reg.h" 35 #include "def.h" 36 #include "phy.h" 37 #include "rf.h" 38 #include "dm.h" 39 #include "fw.h" 40 #include "hw.h" 41 #include "table.h" 42 43 static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask) 44 { 45 u32 i; 46 47 for (i = 0; i <= 31; i++) { 48 if (((bitmask >> i) & 0x1) == 1) 49 break; 50 } 51 52 return i; 53 } 54 55 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) 56 { 57 struct rtl_priv *rtlpriv = rtl_priv(hw); 58 u32 returnvalue = 0, originalvalue, bitshift; 59 60 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n", 61 regaddr, bitmask); 62 63 originalvalue = rtl_read_dword(rtlpriv, regaddr); 64 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); 65 returnvalue = (originalvalue & bitmask) >> bitshift; 66 67 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n", 68 bitmask, regaddr, originalvalue); 69 70 return returnvalue; 71 72 } 73 74 void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, 75 u32 data) 76 { 77 struct rtl_priv *rtlpriv = rtl_priv(hw); 78 u32 originalvalue, bitshift; 79 80 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 81 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 82 regaddr, bitmask, data); 83 84 if (bitmask != MASKDWORD) { 85 originalvalue = rtl_read_dword(rtlpriv, regaddr); 86 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); 87 data = ((originalvalue & (~bitmask)) | (data << bitshift)); 88 } 89 90 rtl_write_dword(rtlpriv, regaddr, data); 91 92 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 93 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 94 regaddr, bitmask, data); 95 96 } 97 98 static u32 _rtl92s_phy_rf_serial_read(struct ieee80211_hw *hw, 99 enum radio_path rfpath, u32 offset) 100 { 101 102 struct rtl_priv *rtlpriv = rtl_priv(hw); 103 struct rtl_phy *rtlphy = &(rtlpriv->phy); 104 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 105 u32 newoffset; 106 u32 tmplong, tmplong2; 107 u8 rfpi_enable = 0; 108 u32 retvalue = 0; 109 110 offset &= 0x3f; 111 newoffset = offset; 112 113 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); 114 115 if (rfpath == RF90_PATH_A) 116 tmplong2 = tmplong; 117 else 118 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); 119 120 tmplong2 = (tmplong2 & (~BLSSI_READADDRESS)) | (newoffset << 23) | 121 BLSSI_READEDGE; 122 123 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 124 tmplong & (~BLSSI_READEDGE)); 125 126 mdelay(1); 127 128 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); 129 mdelay(1); 130 131 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong | 132 BLSSI_READEDGE); 133 mdelay(1); 134 135 if (rfpath == RF90_PATH_A) 136 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, 137 BIT(8)); 138 else if (rfpath == RF90_PATH_B) 139 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, 140 BIT(8)); 141 142 if (rfpi_enable) 143 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, 144 BLSSI_READBACK_DATA); 145 else 146 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 147 BLSSI_READBACK_DATA); 148 149 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 150 BLSSI_READBACK_DATA); 151 152 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n", 153 rfpath, pphyreg->rf_rb, retvalue); 154 155 return retvalue; 156 157 } 158 159 static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw *hw, 160 enum radio_path rfpath, u32 offset, 161 u32 data) 162 { 163 struct rtl_priv *rtlpriv = rtl_priv(hw); 164 struct rtl_phy *rtlphy = &(rtlpriv->phy); 165 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 166 u32 data_and_addr = 0; 167 u32 newoffset; 168 169 offset &= 0x3f; 170 newoffset = offset; 171 172 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 173 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 174 175 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", 176 rfpath, pphyreg->rf3wire_offset, data_and_addr); 177 } 178 179 180 u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, 181 u32 regaddr, u32 bitmask) 182 { 183 struct rtl_priv *rtlpriv = rtl_priv(hw); 184 u32 original_value, readback_value, bitshift; 185 186 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 187 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", 188 regaddr, rfpath, bitmask); 189 190 spin_lock(&rtlpriv->locks.rf_lock); 191 192 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr); 193 194 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); 195 readback_value = (original_value & bitmask) >> bitshift; 196 197 spin_unlock(&rtlpriv->locks.rf_lock); 198 199 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 200 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", 201 regaddr, rfpath, bitmask, original_value); 202 203 return readback_value; 204 } 205 206 void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, 207 u32 regaddr, u32 bitmask, u32 data) 208 { 209 struct rtl_priv *rtlpriv = rtl_priv(hw); 210 struct rtl_phy *rtlphy = &(rtlpriv->phy); 211 u32 original_value, bitshift; 212 213 if (!((rtlphy->rf_pathmap >> rfpath) & 0x1)) 214 return; 215 216 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 217 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 218 regaddr, bitmask, data, rfpath); 219 220 spin_lock(&rtlpriv->locks.rf_lock); 221 222 if (bitmask != RFREG_OFFSET_MASK) { 223 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, 224 regaddr); 225 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); 226 data = ((original_value & (~bitmask)) | (data << bitshift)); 227 } 228 229 _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data); 230 231 spin_unlock(&rtlpriv->locks.rf_lock); 232 233 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 234 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 235 regaddr, bitmask, data, rfpath); 236 237 } 238 239 void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw, 240 u8 operation) 241 { 242 struct rtl_priv *rtlpriv = rtl_priv(hw); 243 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 244 245 if (!is_hal_stop(rtlhal)) { 246 switch (operation) { 247 case SCAN_OPT_BACKUP: 248 rtl92s_phy_set_fw_cmd(hw, FW_CMD_PAUSE_DM_BY_SCAN); 249 break; 250 case SCAN_OPT_RESTORE: 251 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RESUME_DM_BY_SCAN); 252 break; 253 default: 254 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 255 "Unknown operation\n"); 256 break; 257 } 258 } 259 } 260 261 void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw, 262 enum nl80211_channel_type ch_type) 263 { 264 struct rtl_priv *rtlpriv = rtl_priv(hw); 265 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 266 struct rtl_phy *rtlphy = &(rtlpriv->phy); 267 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 268 u8 reg_bw_opmode; 269 270 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n", 271 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 272 "20MHz" : "40MHz"); 273 274 if (rtlphy->set_bwmode_inprogress) 275 return; 276 if (is_hal_stop(rtlhal)) 277 return; 278 279 rtlphy->set_bwmode_inprogress = true; 280 281 reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE); 282 /* dummy read */ 283 rtl_read_byte(rtlpriv, RRSR + 2); 284 285 switch (rtlphy->current_chan_bw) { 286 case HT_CHANNEL_WIDTH_20: 287 reg_bw_opmode |= BW_OPMODE_20MHZ; 288 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode); 289 break; 290 case HT_CHANNEL_WIDTH_20_40: 291 reg_bw_opmode &= ~BW_OPMODE_20MHZ; 292 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode); 293 break; 294 default: 295 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 296 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); 297 break; 298 } 299 300 switch (rtlphy->current_chan_bw) { 301 case HT_CHANNEL_WIDTH_20: 302 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); 303 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); 304 305 if (rtlhal->version >= VERSION_8192S_BCUT) 306 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58); 307 break; 308 case HT_CHANNEL_WIDTH_20_40: 309 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); 310 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); 311 312 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, 313 (mac->cur_40_prime_sc >> 1)); 314 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); 315 316 if (rtlhal->version >= VERSION_8192S_BCUT) 317 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18); 318 break; 319 default: 320 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 321 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); 322 break; 323 } 324 325 rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 326 rtlphy->set_bwmode_inprogress = false; 327 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 328 } 329 330 static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, 331 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid, 332 u32 para1, u32 para2, u32 msdelay) 333 { 334 struct swchnlcmd *pcmd; 335 336 if (cmdtable == NULL) { 337 RT_ASSERT(false, "cmdtable cannot be NULL\n"); 338 return false; 339 } 340 341 if (cmdtableidx >= cmdtablesz) 342 return false; 343 344 pcmd = cmdtable + cmdtableidx; 345 pcmd->cmdid = cmdid; 346 pcmd->para1 = para1; 347 pcmd->para2 = para2; 348 pcmd->msdelay = msdelay; 349 350 return true; 351 } 352 353 static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 354 u8 channel, u8 *stage, u8 *step, u32 *delay) 355 { 356 struct rtl_priv *rtlpriv = rtl_priv(hw); 357 struct rtl_phy *rtlphy = &(rtlpriv->phy); 358 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT]; 359 u32 precommoncmdcnt; 360 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT]; 361 u32 postcommoncmdcnt; 362 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT]; 363 u32 rfdependcmdcnt; 364 struct swchnlcmd *currentcmd = NULL; 365 u8 rfpath; 366 u8 num_total_rfpath = rtlphy->num_total_rfpath; 367 368 precommoncmdcnt = 0; 369 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 370 MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); 371 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 372 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); 373 374 postcommoncmdcnt = 0; 375 376 _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, 377 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); 378 379 rfdependcmdcnt = 0; 380 381 RT_ASSERT((channel >= 1 && channel <= 14), 382 "invalid channel for Zebra: %d\n", channel); 383 384 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 385 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, 386 RF_CHNLBW, channel, 10); 387 388 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 389 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0); 390 391 do { 392 switch (*stage) { 393 case 0: 394 currentcmd = &precommoncmd[*step]; 395 break; 396 case 1: 397 currentcmd = &rfdependcmd[*step]; 398 break; 399 case 2: 400 currentcmd = &postcommoncmd[*step]; 401 break; 402 default: 403 return true; 404 } 405 406 if (currentcmd->cmdid == CMDID_END) { 407 if ((*stage) == 2) { 408 return true; 409 } else { 410 (*stage)++; 411 (*step) = 0; 412 continue; 413 } 414 } 415 416 switch (currentcmd->cmdid) { 417 case CMDID_SET_TXPOWEROWER_LEVEL: 418 rtl92s_phy_set_txpower(hw, channel); 419 break; 420 case CMDID_WRITEPORT_ULONG: 421 rtl_write_dword(rtlpriv, currentcmd->para1, 422 currentcmd->para2); 423 break; 424 case CMDID_WRITEPORT_USHORT: 425 rtl_write_word(rtlpriv, currentcmd->para1, 426 (u16)currentcmd->para2); 427 break; 428 case CMDID_WRITEPORT_UCHAR: 429 rtl_write_byte(rtlpriv, currentcmd->para1, 430 (u8)currentcmd->para2); 431 break; 432 case CMDID_RF_WRITEREG: 433 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { 434 rtlphy->rfreg_chnlval[rfpath] = 435 ((rtlphy->rfreg_chnlval[rfpath] & 436 0xfffffc00) | currentcmd->para2); 437 rtl_set_rfreg(hw, (enum radio_path)rfpath, 438 currentcmd->para1, 439 RFREG_OFFSET_MASK, 440 rtlphy->rfreg_chnlval[rfpath]); 441 } 442 break; 443 default: 444 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 445 "switch case not processed\n"); 446 break; 447 } 448 449 break; 450 } while (true); 451 452 (*delay) = currentcmd->msdelay; 453 (*step)++; 454 return false; 455 } 456 457 u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw) 458 { 459 struct rtl_priv *rtlpriv = rtl_priv(hw); 460 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 461 struct rtl_phy *rtlphy = &(rtlpriv->phy); 462 u32 delay; 463 bool ret; 464 465 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n", 466 rtlphy->current_channel); 467 468 if (rtlphy->sw_chnl_inprogress) 469 return 0; 470 471 if (rtlphy->set_bwmode_inprogress) 472 return 0; 473 474 if (is_hal_stop(rtlhal)) 475 return 0; 476 477 rtlphy->sw_chnl_inprogress = true; 478 rtlphy->sw_chnl_stage = 0; 479 rtlphy->sw_chnl_step = 0; 480 481 do { 482 if (!rtlphy->sw_chnl_inprogress) 483 break; 484 485 ret = _rtl92s_phy_sw_chnl_step_by_step(hw, 486 rtlphy->current_channel, 487 &rtlphy->sw_chnl_stage, 488 &rtlphy->sw_chnl_step, &delay); 489 if (!ret) { 490 if (delay > 0) 491 mdelay(delay); 492 else 493 continue; 494 } else { 495 rtlphy->sw_chnl_inprogress = false; 496 } 497 break; 498 } while (true); 499 500 rtlphy->sw_chnl_inprogress = false; 501 502 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 503 504 return 1; 505 } 506 507 static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw *hw) 508 { 509 struct rtl_priv *rtlpriv = rtl_priv(hw); 510 u8 u1btmp; 511 512 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL); 513 u1btmp |= BIT(0); 514 515 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp); 516 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0); 517 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF); 518 rtl_write_word(rtlpriv, CMDR, 0x57FC); 519 udelay(100); 520 521 rtl_write_word(rtlpriv, CMDR, 0x77FC); 522 rtl_write_byte(rtlpriv, PHY_CCA, 0x0); 523 udelay(10); 524 525 rtl_write_word(rtlpriv, CMDR, 0x37FC); 526 udelay(10); 527 528 rtl_write_word(rtlpriv, CMDR, 0x77FC); 529 udelay(10); 530 531 rtl_write_word(rtlpriv, CMDR, 0x57FC); 532 533 /* we should chnge GPIO to input mode 534 * this will drop away current about 25mA*/ 535 rtl8192se_gpiobit3_cfg_inputmode(hw); 536 } 537 538 bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw, 539 enum rf_pwrstate rfpwr_state) 540 { 541 struct rtl_priv *rtlpriv = rtl_priv(hw); 542 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 543 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 544 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 545 bool bresult = true; 546 u8 i, queue_id; 547 struct rtl8192_tx_ring *ring = NULL; 548 549 if (rfpwr_state == ppsc->rfpwr_state) 550 return false; 551 552 switch (rfpwr_state) { 553 case ERFON:{ 554 if ((ppsc->rfpwr_state == ERFOFF) && 555 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 556 557 bool rtstatus; 558 u32 InitializeCount = 0; 559 do { 560 InitializeCount++; 561 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 562 "IPS Set eRf nic enable\n"); 563 rtstatus = rtl_ps_enable_nic(hw); 564 } while (!rtstatus && (InitializeCount < 10)); 565 566 RT_CLEAR_PS_LEVEL(ppsc, 567 RT_RF_OFF_LEVL_HALT_NIC); 568 } else { 569 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 570 "awake, sleeped:%d ms state_inap:%x\n", 571 jiffies_to_msecs(jiffies - 572 ppsc-> 573 last_sleep_jiffies), 574 rtlpriv->psc.state_inap); 575 ppsc->last_awake_jiffies = jiffies; 576 rtl_write_word(rtlpriv, CMDR, 0x37FC); 577 rtl_write_byte(rtlpriv, TXPAUSE, 0x00); 578 rtl_write_byte(rtlpriv, PHY_CCA, 0x3); 579 } 580 581 if (mac->link_state == MAC80211_LINKED) 582 rtlpriv->cfg->ops->led_control(hw, 583 LED_CTL_LINK); 584 else 585 rtlpriv->cfg->ops->led_control(hw, 586 LED_CTL_NO_LINK); 587 break; 588 } 589 case ERFOFF:{ 590 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 591 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 592 "IPS Set eRf nic disable\n"); 593 rtl_ps_disable_nic(hw); 594 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 595 } else { 596 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 597 rtlpriv->cfg->ops->led_control(hw, 598 LED_CTL_NO_LINK); 599 else 600 rtlpriv->cfg->ops->led_control(hw, 601 LED_CTL_POWER_OFF); 602 } 603 break; 604 } 605 case ERFSLEEP: 606 if (ppsc->rfpwr_state == ERFOFF) 607 return false; 608 609 for (queue_id = 0, i = 0; 610 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 611 ring = &pcipriv->dev.tx_ring[queue_id]; 612 if (skb_queue_len(&ring->queue) == 0 || 613 queue_id == BEACON_QUEUE) { 614 queue_id++; 615 continue; 616 } else { 617 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 618 "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n", 619 i + 1, queue_id, 620 skb_queue_len(&ring->queue)); 621 622 udelay(10); 623 i++; 624 } 625 626 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 627 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 628 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n", 629 MAX_DOZE_WAITING_TIMES_9x, 630 queue_id, 631 skb_queue_len(&ring->queue)); 632 break; 633 } 634 } 635 636 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 637 "Set ERFSLEEP awaked:%d ms\n", 638 jiffies_to_msecs(jiffies - 639 ppsc->last_awake_jiffies)); 640 641 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 642 "sleep awaked:%d ms state_inap:%x\n", 643 jiffies_to_msecs(jiffies - 644 ppsc->last_awake_jiffies), 645 rtlpriv->psc.state_inap); 646 ppsc->last_sleep_jiffies = jiffies; 647 _rtl92se_phy_set_rf_sleep(hw); 648 break; 649 default: 650 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 651 "switch case not processed\n"); 652 bresult = false; 653 break; 654 } 655 656 if (bresult) 657 ppsc->rfpwr_state = rfpwr_state; 658 659 return bresult; 660 } 661 662 static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw *hw, 663 enum radio_path rfpath) 664 { 665 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 666 bool rtstatus = true; 667 u32 tmpval = 0; 668 669 /* If inferiority IC, we have to increase the PA bias current */ 670 if (rtlhal->ic_class != IC_INFERIORITY_A) { 671 tmpval = rtl92s_phy_query_rf_reg(hw, rfpath, RF_IPA, 0xf); 672 rtl92s_phy_set_rf_reg(hw, rfpath, RF_IPA, 0xf, tmpval + 1); 673 } 674 675 return rtstatus; 676 } 677 678 static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, 679 u32 reg_addr, u32 bitmask, u32 data) 680 { 681 struct rtl_priv *rtlpriv = rtl_priv(hw); 682 struct rtl_phy *rtlphy = &(rtlpriv->phy); 683 int index; 684 685 if (reg_addr == RTXAGC_RATE18_06) 686 index = 0; 687 else if (reg_addr == RTXAGC_RATE54_24) 688 index = 1; 689 else if (reg_addr == RTXAGC_CCK_MCS32) 690 index = 6; 691 else if (reg_addr == RTXAGC_MCS03_MCS00) 692 index = 2; 693 else if (reg_addr == RTXAGC_MCS07_MCS04) 694 index = 3; 695 else if (reg_addr == RTXAGC_MCS11_MCS08) 696 index = 4; 697 else if (reg_addr == RTXAGC_MCS15_MCS12) 698 index = 5; 699 else 700 return; 701 702 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; 703 if (index == 5) 704 rtlphy->pwrgroup_cnt++; 705 } 706 707 static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw) 708 { 709 struct rtl_priv *rtlpriv = rtl_priv(hw); 710 struct rtl_phy *rtlphy = &(rtlpriv->phy); 711 712 /*RF Interface Sowrtware Control */ 713 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; 714 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; 715 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; 716 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; 717 718 /* RF Interface Readback Value */ 719 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; 720 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; 721 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; 722 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; 723 724 /* RF Interface Output (and Enable) */ 725 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; 726 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; 727 rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE; 728 rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE; 729 730 /* RF Interface (Output and) Enable */ 731 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; 732 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; 733 rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE; 734 rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE; 735 736 /* Addr of LSSI. Wirte RF register by driver */ 737 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = 738 RFPGA0_XA_LSSIPARAMETER; 739 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = 740 RFPGA0_XB_LSSIPARAMETER; 741 rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset = 742 RFPGA0_XC_LSSIPARAMETER; 743 rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset = 744 RFPGA0_XD_LSSIPARAMETER; 745 746 /* RF parameter */ 747 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; 748 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; 749 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; 750 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; 751 752 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ 753 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; 754 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; 755 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; 756 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; 757 758 /* Tranceiver A~D HSSI Parameter-1 */ 759 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; 760 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; 761 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1; 762 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1; 763 764 /* Tranceiver A~D HSSI Parameter-2 */ 765 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; 766 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; 767 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2; 768 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2; 769 770 /* RF switch Control */ 771 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 772 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 773 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 774 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 775 776 /* AGC control 1 */ 777 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; 778 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; 779 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; 780 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; 781 782 /* AGC control 2 */ 783 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; 784 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; 785 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; 786 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; 787 788 /* RX AFE control 1 */ 789 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; 790 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; 791 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE; 792 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; 793 794 /* RX AFE control 1 */ 795 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; 796 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; 797 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; 798 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; 799 800 /* Tx AFE control 1 */ 801 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; 802 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; 803 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; 804 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; 805 806 /* Tx AFE control 2 */ 807 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; 808 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; 809 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE; 810 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE; 811 812 /* Tranceiver LSSI Readback */ 813 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; 814 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; 815 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; 816 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; 817 818 /* Tranceiver LSSI Readback PI mode */ 819 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK; 820 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK; 821 } 822 823 824 static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype) 825 { 826 int i; 827 u32 *phy_reg_table; 828 u32 *agc_table; 829 u16 phy_reg_len, agc_len; 830 831 agc_len = AGCTAB_ARRAYLENGTH; 832 agc_table = rtl8192seagctab_array; 833 /* Default RF_type: 2T2R */ 834 phy_reg_len = PHY_REG_2T2RARRAYLENGTH; 835 phy_reg_table = rtl8192sephy_reg_2t2rarray; 836 837 if (configtype == BASEBAND_CONFIG_PHY_REG) { 838 for (i = 0; i < phy_reg_len; i = i + 2) { 839 rtl_addr_delay(phy_reg_table[i]); 840 841 /* Add delay for ECS T20 & LG malow platform, */ 842 udelay(1); 843 844 rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD, 845 phy_reg_table[i + 1]); 846 } 847 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 848 for (i = 0; i < agc_len; i = i + 2) { 849 rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD, 850 agc_table[i + 1]); 851 852 /* Add delay for ECS T20 & LG malow platform */ 853 udelay(1); 854 } 855 } 856 857 return true; 858 } 859 860 static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw, 861 u8 configtype) 862 { 863 struct rtl_priv *rtlpriv = rtl_priv(hw); 864 struct rtl_phy *rtlphy = &(rtlpriv->phy); 865 u32 *phy_regarray2xtxr_table; 866 u16 phy_regarray2xtxr_len; 867 int i; 868 869 if (rtlphy->rf_type == RF_1T1R) { 870 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t1rarray; 871 phy_regarray2xtxr_len = PHY_CHANGETO_1T1RARRAYLENGTH; 872 } else if (rtlphy->rf_type == RF_1T2R) { 873 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t2rarray; 874 phy_regarray2xtxr_len = PHY_CHANGETO_1T2RARRAYLENGTH; 875 } else { 876 return false; 877 } 878 879 if (configtype == BASEBAND_CONFIG_PHY_REG) { 880 for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) { 881 rtl_addr_delay(phy_regarray2xtxr_table[i]); 882 883 rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i], 884 phy_regarray2xtxr_table[i + 1], 885 phy_regarray2xtxr_table[i + 2]); 886 } 887 } 888 889 return true; 890 } 891 892 static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw, 893 u8 configtype) 894 { 895 int i; 896 u32 *phy_table_pg; 897 u16 phy_pg_len; 898 899 phy_pg_len = PHY_REG_ARRAY_PGLENGTH; 900 phy_table_pg = rtl8192sephy_reg_array_pg; 901 902 if (configtype == BASEBAND_CONFIG_PHY_REG) { 903 for (i = 0; i < phy_pg_len; i = i + 3) { 904 rtl_addr_delay(phy_table_pg[i]); 905 906 _rtl92s_store_pwrindex_diffrate_offset(hw, 907 phy_table_pg[i], 908 phy_table_pg[i + 1], 909 phy_table_pg[i + 2]); 910 rtl92s_phy_set_bb_reg(hw, phy_table_pg[i], 911 phy_table_pg[i + 1], 912 phy_table_pg[i + 2]); 913 } 914 } 915 916 return true; 917 } 918 919 static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw) 920 { 921 struct rtl_priv *rtlpriv = rtl_priv(hw); 922 struct rtl_phy *rtlphy = &(rtlpriv->phy); 923 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 924 bool rtstatus = true; 925 926 /* 1. Read PHY_REG.TXT BB INIT!! */ 927 /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */ 928 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R || 929 rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) { 930 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG); 931 932 if (rtlphy->rf_type != RF_2T2R && 933 rtlphy->rf_type != RF_2T2R_GREEN) 934 /* so we should reconfig BB reg with the right 935 * PHY parameters. */ 936 rtstatus = _rtl92s_phy_set_bb_to_diff_rf(hw, 937 BASEBAND_CONFIG_PHY_REG); 938 } else { 939 rtstatus = false; 940 } 941 942 if (!rtstatus) { 943 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, 944 "Write BB Reg Fail!!\n"); 945 goto phy_BB8190_Config_ParaFile_Fail; 946 } 947 948 /* 2. If EEPROM or EFUSE autoload OK, We must config by 949 * PHY_REG_PG.txt */ 950 if (rtlefuse->autoload_failflag == false) { 951 rtlphy->pwrgroup_cnt = 0; 952 953 rtstatus = _rtl92s_phy_config_bb_with_pg(hw, 954 BASEBAND_CONFIG_PHY_REG); 955 } 956 if (!rtstatus) { 957 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, 958 "_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n"); 959 goto phy_BB8190_Config_ParaFile_Fail; 960 } 961 962 /* 3. BB AGC table Initialization */ 963 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB); 964 965 if (!rtstatus) { 966 pr_err("%s(): AGC Table Fail\n", __func__); 967 goto phy_BB8190_Config_ParaFile_Fail; 968 } 969 970 /* Check if the CCK HighPower is turned ON. */ 971 /* This is used to calculate PWDB. */ 972 rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw, 973 RFPGA0_XA_HSSIPARAMETER2, 0x200)); 974 975 phy_BB8190_Config_ParaFile_Fail: 976 return rtstatus; 977 } 978 979 u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath) 980 { 981 struct rtl_priv *rtlpriv = rtl_priv(hw); 982 struct rtl_phy *rtlphy = &(rtlpriv->phy); 983 int i; 984 bool rtstatus = true; 985 u32 *radio_a_table; 986 u32 *radio_b_table; 987 u16 radio_a_tblen, radio_b_tblen; 988 989 radio_a_tblen = RADIOA_1T_ARRAYLENGTH; 990 radio_a_table = rtl8192seradioa_1t_array; 991 992 /* Using Green mode array table for RF_2T2R_GREEN */ 993 if (rtlphy->rf_type == RF_2T2R_GREEN) { 994 radio_b_table = rtl8192seradiob_gm_array; 995 radio_b_tblen = RADIOB_GM_ARRAYLENGTH; 996 } else { 997 radio_b_table = rtl8192seradiob_array; 998 radio_b_tblen = RADIOB_ARRAYLENGTH; 999 } 1000 1001 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath); 1002 rtstatus = true; 1003 1004 switch (rfpath) { 1005 case RF90_PATH_A: 1006 for (i = 0; i < radio_a_tblen; i = i + 2) { 1007 rtl_rfreg_delay(hw, rfpath, radio_a_table[i], 1008 MASK20BITS, radio_a_table[i + 1]); 1009 1010 } 1011 1012 /* PA Bias current for inferiority IC */ 1013 _rtl92s_phy_config_rfpa_bias_current(hw, rfpath); 1014 break; 1015 case RF90_PATH_B: 1016 for (i = 0; i < radio_b_tblen; i = i + 2) { 1017 rtl_rfreg_delay(hw, rfpath, radio_b_table[i], 1018 MASK20BITS, radio_b_table[i + 1]); 1019 } 1020 break; 1021 case RF90_PATH_C: 1022 ; 1023 break; 1024 case RF90_PATH_D: 1025 ; 1026 break; 1027 default: 1028 break; 1029 } 1030 1031 return rtstatus; 1032 } 1033 1034 1035 bool rtl92s_phy_mac_config(struct ieee80211_hw *hw) 1036 { 1037 struct rtl_priv *rtlpriv = rtl_priv(hw); 1038 u32 i; 1039 u32 arraylength; 1040 u32 *ptraArray; 1041 1042 arraylength = MAC_2T_ARRAYLENGTH; 1043 ptraArray = rtl8192semac_2t_array; 1044 1045 for (i = 0; i < arraylength; i = i + 2) 1046 rtl_write_byte(rtlpriv, ptraArray[i], (u8)ptraArray[i + 1]); 1047 1048 return true; 1049 } 1050 1051 1052 bool rtl92s_phy_bb_config(struct ieee80211_hw *hw) 1053 { 1054 struct rtl_priv *rtlpriv = rtl_priv(hw); 1055 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1056 bool rtstatus = true; 1057 u8 pathmap, index, rf_num = 0; 1058 u8 path1, path2; 1059 1060 _rtl92s_phy_init_register_definition(hw); 1061 1062 /* Config BB and AGC */ 1063 rtstatus = _rtl92s_phy_bb_config_parafile(hw); 1064 1065 1066 /* Check BB/RF confiuration setting. */ 1067 /* We only need to configure RF which is turned on. */ 1068 path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf)); 1069 mdelay(10); 1070 path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf)); 1071 pathmap = path1 | path2; 1072 1073 rtlphy->rf_pathmap = pathmap; 1074 for (index = 0; index < 4; index++) { 1075 if ((pathmap >> index) & 0x1) 1076 rf_num++; 1077 } 1078 1079 if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) || 1080 (rtlphy->rf_type == RF_1T2R && rf_num != 2) || 1081 (rtlphy->rf_type == RF_2T2R && rf_num != 2) || 1082 (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) { 1083 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, 1084 "RF_Type(%x) does not match RF_Num(%x)!!\n", 1085 rtlphy->rf_type, rf_num); 1086 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, 1087 "path1 0x%x, path2 0x%x, pathmap 0x%x\n", 1088 path1, path2, pathmap); 1089 } 1090 1091 return rtstatus; 1092 } 1093 1094 bool rtl92s_phy_rf_config(struct ieee80211_hw *hw) 1095 { 1096 struct rtl_priv *rtlpriv = rtl_priv(hw); 1097 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1098 1099 /* Initialize general global value */ 1100 if (rtlphy->rf_type == RF_1T1R) 1101 rtlphy->num_total_rfpath = 1; 1102 else 1103 rtlphy->num_total_rfpath = 2; 1104 1105 /* Config BB and RF */ 1106 return rtl92s_phy_rf6052_config(hw); 1107 } 1108 1109 void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 1110 { 1111 struct rtl_priv *rtlpriv = rtl_priv(hw); 1112 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1113 1114 /* read rx initial gain */ 1115 rtlphy->default_initialgain[0] = rtl_get_bbreg(hw, 1116 ROFDM0_XAAGCCORE1, MASKBYTE0); 1117 rtlphy->default_initialgain[1] = rtl_get_bbreg(hw, 1118 ROFDM0_XBAGCCORE1, MASKBYTE0); 1119 rtlphy->default_initialgain[2] = rtl_get_bbreg(hw, 1120 ROFDM0_XCAGCCORE1, MASKBYTE0); 1121 rtlphy->default_initialgain[3] = rtl_get_bbreg(hw, 1122 ROFDM0_XDAGCCORE1, MASKBYTE0); 1123 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1124 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n", 1125 rtlphy->default_initialgain[0], 1126 rtlphy->default_initialgain[1], 1127 rtlphy->default_initialgain[2], 1128 rtlphy->default_initialgain[3]); 1129 1130 /* read framesync */ 1131 rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0); 1132 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, 1133 MASKDWORD); 1134 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1135 "Default framesync (0x%x) = 0x%x\n", 1136 ROFDM0_RXDETECTOR3, rtlphy->framesync); 1137 1138 } 1139 1140 static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel, 1141 u8 *cckpowerlevel, u8 *ofdmpowerLevel) 1142 { 1143 struct rtl_priv *rtlpriv = rtl_priv(hw); 1144 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1145 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1146 u8 index = (channel - 1); 1147 1148 /* 1. CCK */ 1149 /* RF-A */ 1150 cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index]; 1151 /* RF-B */ 1152 cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index]; 1153 1154 /* 2. OFDM for 1T or 2T */ 1155 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) { 1156 /* Read HT 40 OFDM TX power */ 1157 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index]; 1158 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index]; 1159 } else if (rtlphy->rf_type == RF_2T2R) { 1160 /* Read HT 40 OFDM TX power */ 1161 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index]; 1162 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index]; 1163 } else { 1164 ofdmpowerLevel[0] = 0; 1165 ofdmpowerLevel[1] = 0; 1166 } 1167 } 1168 1169 static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw, 1170 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel) 1171 { 1172 struct rtl_priv *rtlpriv = rtl_priv(hw); 1173 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1174 1175 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; 1176 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; 1177 } 1178 1179 void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel) 1180 { 1181 struct rtl_priv *rtlpriv = rtl_priv(hw); 1182 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1183 /* [0]:RF-A, [1]:RF-B */ 1184 u8 cckpowerlevel[2], ofdmpowerLevel[2]; 1185 1186 if (!rtlefuse->txpwr_fromeprom) 1187 return; 1188 1189 /* Mainly we use RF-A Tx Power to write the Tx Power registers, 1190 * but the RF-B Tx Power must be calculated by the antenna diff. 1191 * So we have to rewrite Antenna gain offset register here. 1192 * Please refer to BB register 0x80c 1193 * 1. For CCK. 1194 * 2. For OFDM 1T or 2T */ 1195 _rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0], 1196 &ofdmpowerLevel[0]); 1197 1198 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1199 "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n", 1200 channel, cckpowerlevel[0], cckpowerlevel[1], 1201 ofdmpowerLevel[0], ofdmpowerLevel[1]); 1202 1203 _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0], 1204 &ofdmpowerLevel[0]); 1205 1206 rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]); 1207 rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerLevel[0], channel); 1208 1209 } 1210 1211 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw) 1212 { 1213 struct rtl_priv *rtlpriv = rtl_priv(hw); 1214 u16 pollingcnt = 10000; 1215 u32 tmpvalue; 1216 1217 /* Make sure that CMD IO has be accepted by FW. */ 1218 do { 1219 udelay(10); 1220 1221 tmpvalue = rtl_read_dword(rtlpriv, WFM5); 1222 if (tmpvalue == 0) 1223 break; 1224 } while (--pollingcnt); 1225 1226 if (pollingcnt == 0) 1227 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Set FW Cmd fail!!\n"); 1228 } 1229 1230 1231 static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw) 1232 { 1233 struct rtl_priv *rtlpriv = rtl_priv(hw); 1234 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1235 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1236 u32 input, current_aid = 0; 1237 1238 if (is_hal_stop(rtlhal)) 1239 return; 1240 1241 if (hal_get_firmwareversion(rtlpriv) < 0x34) 1242 goto skip; 1243 /* We re-map RA related CMD IO to combinational ones */ 1244 /* if FW version is v.52 or later. */ 1245 switch (rtlhal->current_fwcmd_io) { 1246 case FW_CMD_RA_REFRESH_N: 1247 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_N_COMB; 1248 break; 1249 case FW_CMD_RA_REFRESH_BG: 1250 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_BG_COMB; 1251 break; 1252 default: 1253 break; 1254 } 1255 1256 skip: 1257 switch (rtlhal->current_fwcmd_io) { 1258 case FW_CMD_RA_RESET: 1259 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n"); 1260 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET); 1261 rtl92s_phy_chk_fwcmd_iodone(hw); 1262 break; 1263 case FW_CMD_RA_ACTIVE: 1264 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n"); 1265 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE); 1266 rtl92s_phy_chk_fwcmd_iodone(hw); 1267 break; 1268 case FW_CMD_RA_REFRESH_N: 1269 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n"); 1270 input = FW_RA_REFRESH; 1271 rtl_write_dword(rtlpriv, WFM5, input); 1272 rtl92s_phy_chk_fwcmd_iodone(hw); 1273 rtl_write_dword(rtlpriv, WFM5, FW_RA_ENABLE_RSSI_MASK); 1274 rtl92s_phy_chk_fwcmd_iodone(hw); 1275 break; 1276 case FW_CMD_RA_REFRESH_BG: 1277 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, 1278 "FW_CMD_RA_REFRESH_BG\n"); 1279 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH); 1280 rtl92s_phy_chk_fwcmd_iodone(hw); 1281 rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK); 1282 rtl92s_phy_chk_fwcmd_iodone(hw); 1283 break; 1284 case FW_CMD_RA_REFRESH_N_COMB: 1285 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, 1286 "FW_CMD_RA_REFRESH_N_COMB\n"); 1287 input = FW_RA_IOT_N_COMB; 1288 rtl_write_dword(rtlpriv, WFM5, input); 1289 rtl92s_phy_chk_fwcmd_iodone(hw); 1290 break; 1291 case FW_CMD_RA_REFRESH_BG_COMB: 1292 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, 1293 "FW_CMD_RA_REFRESH_BG_COMB\n"); 1294 input = FW_RA_IOT_BG_COMB; 1295 rtl_write_dword(rtlpriv, WFM5, input); 1296 rtl92s_phy_chk_fwcmd_iodone(hw); 1297 break; 1298 case FW_CMD_IQK_ENABLE: 1299 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n"); 1300 rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE); 1301 rtl92s_phy_chk_fwcmd_iodone(hw); 1302 break; 1303 case FW_CMD_PAUSE_DM_BY_SCAN: 1304 /* Lower initial gain */ 1305 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17); 1306 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17); 1307 /* CCA threshold */ 1308 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40); 1309 break; 1310 case FW_CMD_RESUME_DM_BY_SCAN: 1311 /* CCA threshold */ 1312 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); 1313 rtl92s_phy_set_txpower(hw, rtlphy->current_channel); 1314 break; 1315 case FW_CMD_HIGH_PWR_DISABLE: 1316 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) 1317 break; 1318 1319 /* Lower initial gain */ 1320 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17); 1321 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17); 1322 /* CCA threshold */ 1323 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40); 1324 break; 1325 case FW_CMD_HIGH_PWR_ENABLE: 1326 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) || 1327 rtlpriv->dm.dynamic_txpower_enable) 1328 break; 1329 1330 /* CCA threshold */ 1331 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); 1332 break; 1333 case FW_CMD_LPS_ENTER: 1334 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n"); 1335 current_aid = rtlpriv->mac80211.assoc_id; 1336 rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER | 1337 ((current_aid | 0xc000) << 8))); 1338 rtl92s_phy_chk_fwcmd_iodone(hw); 1339 /* FW set TXOP disable here, so disable EDCA 1340 * turbo mode until driver leave LPS */ 1341 break; 1342 case FW_CMD_LPS_LEAVE: 1343 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n"); 1344 rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE); 1345 rtl92s_phy_chk_fwcmd_iodone(hw); 1346 break; 1347 case FW_CMD_ADD_A2_ENTRY: 1348 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n"); 1349 rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY); 1350 rtl92s_phy_chk_fwcmd_iodone(hw); 1351 break; 1352 case FW_CMD_CTRL_DM_BY_DRIVER: 1353 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 1354 "FW_CMD_CTRL_DM_BY_DRIVER\n"); 1355 rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER); 1356 rtl92s_phy_chk_fwcmd_iodone(hw); 1357 break; 1358 1359 default: 1360 break; 1361 } 1362 1363 rtl92s_phy_chk_fwcmd_iodone(hw); 1364 1365 /* Clear FW CMD operation flag. */ 1366 rtlhal->set_fwcmd_inprogress = false; 1367 } 1368 1369 bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio) 1370 { 1371 struct rtl_priv *rtlpriv = rtl_priv(hw); 1372 struct dig_t *digtable = &rtlpriv->dm_digtable; 1373 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1374 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1375 u32 fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv); 1376 u16 fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv); 1377 bool postprocessing = false; 1378 1379 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 1380 "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n", 1381 fw_cmdio, rtlhal->set_fwcmd_inprogress); 1382 1383 do { 1384 /* We re-map to combined FW CMD ones if firmware version */ 1385 /* is v.53 or later. */ 1386 if (hal_get_firmwareversion(rtlpriv) >= 0x35) { 1387 switch (fw_cmdio) { 1388 case FW_CMD_RA_REFRESH_N: 1389 fw_cmdio = FW_CMD_RA_REFRESH_N_COMB; 1390 break; 1391 case FW_CMD_RA_REFRESH_BG: 1392 fw_cmdio = FW_CMD_RA_REFRESH_BG_COMB; 1393 break; 1394 default: 1395 break; 1396 } 1397 } else { 1398 if ((fw_cmdio == FW_CMD_IQK_ENABLE) || 1399 (fw_cmdio == FW_CMD_RA_REFRESH_N) || 1400 (fw_cmdio == FW_CMD_RA_REFRESH_BG)) { 1401 postprocessing = true; 1402 break; 1403 } 1404 } 1405 1406 /* If firmware version is v.62 or later, 1407 * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */ 1408 if (hal_get_firmwareversion(rtlpriv) >= 0x3E) { 1409 if (fw_cmdio == FW_CMD_CTRL_DM_BY_DRIVER) 1410 fw_cmdio = FW_CMD_CTRL_DM_BY_DRIVER_NEW; 1411 } 1412 1413 1414 /* We shall revise all FW Cmd IO into Reg0x364 1415 * DM map table in the future. */ 1416 switch (fw_cmdio) { 1417 case FW_CMD_RA_INIT: 1418 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n"); 1419 fw_cmdmap |= FW_RA_INIT_CTL; 1420 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1421 /* Clear control flag to sync with FW. */ 1422 FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL); 1423 break; 1424 case FW_CMD_DIG_DISABLE: 1425 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 1426 "Set DIG disable!!\n"); 1427 fw_cmdmap &= ~FW_DIG_ENABLE_CTL; 1428 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1429 break; 1430 case FW_CMD_DIG_ENABLE: 1431 case FW_CMD_DIG_RESUME: 1432 if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) { 1433 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 1434 "Set DIG enable or resume!!\n"); 1435 fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL); 1436 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1437 } 1438 break; 1439 case FW_CMD_DIG_HALT: 1440 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 1441 "Set DIG halt!!\n"); 1442 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL); 1443 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1444 break; 1445 case FW_CMD_TXPWR_TRACK_THERMAL: { 1446 u8 thermalval = 0; 1447 fw_cmdmap |= FW_PWR_TRK_CTL; 1448 1449 /* Clear FW parameter in terms of thermal parts. */ 1450 fw_param &= FW_PWR_TRK_PARAM_CLR; 1451 1452 thermalval = rtlpriv->dm.thermalvalue; 1453 fw_param |= ((thermalval << 24) | 1454 (rtlefuse->thermalmeter[0] << 16)); 1455 1456 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 1457 "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n", 1458 fw_cmdmap, fw_param); 1459 1460 FW_CMD_PARA_SET(rtlpriv, fw_param); 1461 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1462 1463 /* Clear control flag to sync with FW. */ 1464 FW_CMD_IO_CLR(rtlpriv, FW_PWR_TRK_CTL); 1465 } 1466 break; 1467 /* The following FW CMDs are only compatible to 1468 * v.53 or later. */ 1469 case FW_CMD_RA_REFRESH_N_COMB: 1470 fw_cmdmap |= FW_RA_N_CTL; 1471 1472 /* Clear RA BG mode control. */ 1473 fw_cmdmap &= ~(FW_RA_BG_CTL | FW_RA_INIT_CTL); 1474 1475 /* Clear FW parameter in terms of RA parts. */ 1476 fw_param &= FW_RA_PARAM_CLR; 1477 1478 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 1479 "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n", 1480 fw_cmdmap, fw_param); 1481 1482 FW_CMD_PARA_SET(rtlpriv, fw_param); 1483 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1484 1485 /* Clear control flag to sync with FW. */ 1486 FW_CMD_IO_CLR(rtlpriv, FW_RA_N_CTL); 1487 break; 1488 case FW_CMD_RA_REFRESH_BG_COMB: 1489 fw_cmdmap |= FW_RA_BG_CTL; 1490 1491 /* Clear RA n-mode control. */ 1492 fw_cmdmap &= ~(FW_RA_N_CTL | FW_RA_INIT_CTL); 1493 /* Clear FW parameter in terms of RA parts. */ 1494 fw_param &= FW_RA_PARAM_CLR; 1495 1496 FW_CMD_PARA_SET(rtlpriv, fw_param); 1497 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1498 1499 /* Clear control flag to sync with FW. */ 1500 FW_CMD_IO_CLR(rtlpriv, FW_RA_BG_CTL); 1501 break; 1502 case FW_CMD_IQK_ENABLE: 1503 fw_cmdmap |= FW_IQK_CTL; 1504 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1505 /* Clear control flag to sync with FW. */ 1506 FW_CMD_IO_CLR(rtlpriv, FW_IQK_CTL); 1507 break; 1508 /* The following FW CMD is compatible to v.62 or later. */ 1509 case FW_CMD_CTRL_DM_BY_DRIVER_NEW: 1510 fw_cmdmap |= FW_DRIVER_CTRL_DM_CTL; 1511 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1512 break; 1513 /* The followed FW Cmds needs post-processing later. */ 1514 case FW_CMD_RESUME_DM_BY_SCAN: 1515 fw_cmdmap |= (FW_DIG_ENABLE_CTL | 1516 FW_HIGH_PWR_ENABLE_CTL | 1517 FW_SS_CTL); 1518 1519 if (rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE || 1520 !digtable->dig_enable_flag) 1521 fw_cmdmap &= ~FW_DIG_ENABLE_CTL; 1522 1523 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) || 1524 rtlpriv->dm.dynamic_txpower_enable) 1525 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL; 1526 1527 if ((digtable->dig_ext_port_stage == 1528 DIG_EXT_PORT_STAGE_0) || 1529 (digtable->dig_ext_port_stage == 1530 DIG_EXT_PORT_STAGE_1)) 1531 fw_cmdmap &= ~FW_DIG_ENABLE_CTL; 1532 1533 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1534 postprocessing = true; 1535 break; 1536 case FW_CMD_PAUSE_DM_BY_SCAN: 1537 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | 1538 FW_HIGH_PWR_ENABLE_CTL | 1539 FW_SS_CTL); 1540 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1541 postprocessing = true; 1542 break; 1543 case FW_CMD_HIGH_PWR_DISABLE: 1544 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL; 1545 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1546 postprocessing = true; 1547 break; 1548 case FW_CMD_HIGH_PWR_ENABLE: 1549 if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) && 1550 !rtlpriv->dm.dynamic_txpower_enable) { 1551 fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL | 1552 FW_SS_CTL); 1553 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1554 postprocessing = true; 1555 } 1556 break; 1557 case FW_CMD_DIG_MODE_FA: 1558 fw_cmdmap |= FW_FA_CTL; 1559 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1560 break; 1561 case FW_CMD_DIG_MODE_SS: 1562 fw_cmdmap &= ~FW_FA_CTL; 1563 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1564 break; 1565 case FW_CMD_PAPE_CONTROL: 1566 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 1567 "[FW CMD] Set PAPE Control\n"); 1568 fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW; 1569 1570 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1571 break; 1572 default: 1573 /* Pass to original FW CMD processing callback 1574 * routine. */ 1575 postprocessing = true; 1576 break; 1577 } 1578 } while (false); 1579 1580 /* We shall post processing these FW CMD if 1581 * variable postprocessing is set. 1582 */ 1583 if (postprocessing && !rtlhal->set_fwcmd_inprogress) { 1584 rtlhal->set_fwcmd_inprogress = true; 1585 /* Update current FW Cmd for callback use. */ 1586 rtlhal->current_fwcmd_io = fw_cmdio; 1587 } else { 1588 return false; 1589 } 1590 1591 _rtl92s_phy_set_fwcmd_io(hw); 1592 return true; 1593 } 1594 1595 static void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw *hw) 1596 { 1597 struct rtl_priv *rtlpriv = rtl_priv(hw); 1598 u32 delay = 100; 1599 u8 regu1; 1600 1601 regu1 = rtl_read_byte(rtlpriv, 0x554); 1602 while ((regu1 & BIT(5)) && (delay > 0)) { 1603 regu1 = rtl_read_byte(rtlpriv, 0x554); 1604 delay--; 1605 /* We delay only 50us to prevent 1606 * being scheduled out. */ 1607 udelay(50); 1608 } 1609 } 1610 1611 void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw) 1612 { 1613 struct rtl_priv *rtlpriv = rtl_priv(hw); 1614 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1615 1616 /* The way to be capable to switch clock request 1617 * when the PG setting does not support clock request. 1618 * This is the backdoor solution to switch clock 1619 * request before ASPM or D3. */ 1620 rtl_write_dword(rtlpriv, 0x540, 0x73c11); 1621 rtl_write_dword(rtlpriv, 0x548, 0x2407c); 1622 1623 /* Switch EPHY parameter!!!! */ 1624 rtl_write_word(rtlpriv, 0x550, 0x1000); 1625 rtl_write_byte(rtlpriv, 0x554, 0x20); 1626 _rtl92s_phy_check_ephy_switchready(hw); 1627 1628 rtl_write_word(rtlpriv, 0x550, 0xa0eb); 1629 rtl_write_byte(rtlpriv, 0x554, 0x3e); 1630 _rtl92s_phy_check_ephy_switchready(hw); 1631 1632 rtl_write_word(rtlpriv, 0x550, 0xff80); 1633 rtl_write_byte(rtlpriv, 0x554, 0x39); 1634 _rtl92s_phy_check_ephy_switchready(hw); 1635 1636 /* Delay L1 enter time */ 1637 if (ppsc->support_aspm && !ppsc->support_backdoor) 1638 rtl_write_byte(rtlpriv, 0x560, 0x40); 1639 else 1640 rtl_write_byte(rtlpriv, 0x560, 0x00); 1641 1642 } 1643 1644 void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval) 1645 { 1646 struct rtl_priv *rtlpriv = rtl_priv(hw); 1647 u32 new_bcn_num = 0; 1648 1649 if (hal_get_firmwareversion(rtlpriv) >= 0x33) { 1650 /* Fw v.51 and later. */ 1651 rtl_write_dword(rtlpriv, WFM5, 0xF1000000 | 1652 (beaconinterval << 8)); 1653 } else { 1654 new_bcn_num = beaconinterval * 32 - 64; 1655 rtl_write_dword(rtlpriv, WFM3 + 4, new_bcn_num); 1656 rtl_write_dword(rtlpriv, WFM3, 0xB026007C); 1657 } 1658 } 1659