1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../pci.h" 28 #include "../ps.h" 29 #include "../core.h" 30 #include "reg.h" 31 #include "def.h" 32 #include "phy.h" 33 #include "rf.h" 34 #include "dm.h" 35 #include "fw.h" 36 #include "hw.h" 37 #include "table.h" 38 39 static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask) 40 { 41 u32 i; 42 43 for (i = 0; i <= 31; i++) { 44 if (((bitmask >> i) & 0x1) == 1) 45 break; 46 } 47 48 return i; 49 } 50 51 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) 52 { 53 struct rtl_priv *rtlpriv = rtl_priv(hw); 54 u32 returnvalue = 0, originalvalue, bitshift; 55 56 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n", 57 regaddr, bitmask); 58 59 originalvalue = rtl_read_dword(rtlpriv, regaddr); 60 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); 61 returnvalue = (originalvalue & bitmask) >> bitshift; 62 63 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n", 64 bitmask, regaddr, originalvalue); 65 66 return returnvalue; 67 68 } 69 70 void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, 71 u32 data) 72 { 73 struct rtl_priv *rtlpriv = rtl_priv(hw); 74 u32 originalvalue, bitshift; 75 76 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 77 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 78 regaddr, bitmask, data); 79 80 if (bitmask != MASKDWORD) { 81 originalvalue = rtl_read_dword(rtlpriv, regaddr); 82 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); 83 data = ((originalvalue & (~bitmask)) | (data << bitshift)); 84 } 85 86 rtl_write_dword(rtlpriv, regaddr, data); 87 88 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 89 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 90 regaddr, bitmask, data); 91 92 } 93 94 static u32 _rtl92s_phy_rf_serial_read(struct ieee80211_hw *hw, 95 enum radio_path rfpath, u32 offset) 96 { 97 98 struct rtl_priv *rtlpriv = rtl_priv(hw); 99 struct rtl_phy *rtlphy = &(rtlpriv->phy); 100 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 101 u32 newoffset; 102 u32 tmplong, tmplong2; 103 u8 rfpi_enable = 0; 104 u32 retvalue = 0; 105 106 offset &= 0x3f; 107 newoffset = offset; 108 109 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); 110 111 if (rfpath == RF90_PATH_A) 112 tmplong2 = tmplong; 113 else 114 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); 115 116 tmplong2 = (tmplong2 & (~BLSSI_READADDRESS)) | (newoffset << 23) | 117 BLSSI_READEDGE; 118 119 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 120 tmplong & (~BLSSI_READEDGE)); 121 122 mdelay(1); 123 124 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); 125 mdelay(1); 126 127 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong | 128 BLSSI_READEDGE); 129 mdelay(1); 130 131 if (rfpath == RF90_PATH_A) 132 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, 133 BIT(8)); 134 else if (rfpath == RF90_PATH_B) 135 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, 136 BIT(8)); 137 138 if (rfpi_enable) 139 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, 140 BLSSI_READBACK_DATA); 141 else 142 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 143 BLSSI_READBACK_DATA); 144 145 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 146 BLSSI_READBACK_DATA); 147 148 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n", 149 rfpath, pphyreg->rf_rb, retvalue); 150 151 return retvalue; 152 153 } 154 155 static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw *hw, 156 enum radio_path rfpath, u32 offset, 157 u32 data) 158 { 159 struct rtl_priv *rtlpriv = rtl_priv(hw); 160 struct rtl_phy *rtlphy = &(rtlpriv->phy); 161 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 162 u32 data_and_addr = 0; 163 u32 newoffset; 164 165 offset &= 0x3f; 166 newoffset = offset; 167 168 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 169 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 170 171 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", 172 rfpath, pphyreg->rf3wire_offset, data_and_addr); 173 } 174 175 176 u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, 177 u32 regaddr, u32 bitmask) 178 { 179 struct rtl_priv *rtlpriv = rtl_priv(hw); 180 u32 original_value, readback_value, bitshift; 181 182 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 183 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", 184 regaddr, rfpath, bitmask); 185 186 spin_lock(&rtlpriv->locks.rf_lock); 187 188 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr); 189 190 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); 191 readback_value = (original_value & bitmask) >> bitshift; 192 193 spin_unlock(&rtlpriv->locks.rf_lock); 194 195 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 196 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", 197 regaddr, rfpath, bitmask, original_value); 198 199 return readback_value; 200 } 201 202 void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, 203 u32 regaddr, u32 bitmask, u32 data) 204 { 205 struct rtl_priv *rtlpriv = rtl_priv(hw); 206 struct rtl_phy *rtlphy = &(rtlpriv->phy); 207 u32 original_value, bitshift; 208 209 if (!((rtlphy->rf_pathmap >> rfpath) & 0x1)) 210 return; 211 212 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 213 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 214 regaddr, bitmask, data, rfpath); 215 216 spin_lock(&rtlpriv->locks.rf_lock); 217 218 if (bitmask != RFREG_OFFSET_MASK) { 219 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, 220 regaddr); 221 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); 222 data = ((original_value & (~bitmask)) | (data << bitshift)); 223 } 224 225 _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data); 226 227 spin_unlock(&rtlpriv->locks.rf_lock); 228 229 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 230 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 231 regaddr, bitmask, data, rfpath); 232 233 } 234 235 void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw, 236 u8 operation) 237 { 238 struct rtl_priv *rtlpriv = rtl_priv(hw); 239 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 240 241 if (!is_hal_stop(rtlhal)) { 242 switch (operation) { 243 case SCAN_OPT_BACKUP: 244 rtl92s_phy_set_fw_cmd(hw, FW_CMD_PAUSE_DM_BY_SCAN); 245 break; 246 case SCAN_OPT_RESTORE: 247 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RESUME_DM_BY_SCAN); 248 break; 249 default: 250 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 251 "Unknown operation\n"); 252 break; 253 } 254 } 255 } 256 257 void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw, 258 enum nl80211_channel_type ch_type) 259 { 260 struct rtl_priv *rtlpriv = rtl_priv(hw); 261 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 262 struct rtl_phy *rtlphy = &(rtlpriv->phy); 263 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 264 u8 reg_bw_opmode; 265 266 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n", 267 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 268 "20MHz" : "40MHz"); 269 270 if (rtlphy->set_bwmode_inprogress) 271 return; 272 if (is_hal_stop(rtlhal)) 273 return; 274 275 rtlphy->set_bwmode_inprogress = true; 276 277 reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE); 278 /* dummy read */ 279 rtl_read_byte(rtlpriv, RRSR + 2); 280 281 switch (rtlphy->current_chan_bw) { 282 case HT_CHANNEL_WIDTH_20: 283 reg_bw_opmode |= BW_OPMODE_20MHZ; 284 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode); 285 break; 286 case HT_CHANNEL_WIDTH_20_40: 287 reg_bw_opmode &= ~BW_OPMODE_20MHZ; 288 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode); 289 break; 290 default: 291 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 292 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); 293 break; 294 } 295 296 switch (rtlphy->current_chan_bw) { 297 case HT_CHANNEL_WIDTH_20: 298 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); 299 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); 300 301 if (rtlhal->version >= VERSION_8192S_BCUT) 302 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58); 303 break; 304 case HT_CHANNEL_WIDTH_20_40: 305 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); 306 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); 307 308 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, 309 (mac->cur_40_prime_sc >> 1)); 310 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); 311 312 if (rtlhal->version >= VERSION_8192S_BCUT) 313 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18); 314 break; 315 default: 316 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 317 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); 318 break; 319 } 320 321 rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 322 rtlphy->set_bwmode_inprogress = false; 323 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 324 } 325 326 static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, 327 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid, 328 u32 para1, u32 para2, u32 msdelay) 329 { 330 struct swchnlcmd *pcmd; 331 332 if (cmdtable == NULL) { 333 RT_ASSERT(false, "cmdtable cannot be NULL\n"); 334 return false; 335 } 336 337 if (cmdtableidx >= cmdtablesz) 338 return false; 339 340 pcmd = cmdtable + cmdtableidx; 341 pcmd->cmdid = cmdid; 342 pcmd->para1 = para1; 343 pcmd->para2 = para2; 344 pcmd->msdelay = msdelay; 345 346 return true; 347 } 348 349 static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 350 u8 channel, u8 *stage, u8 *step, u32 *delay) 351 { 352 struct rtl_priv *rtlpriv = rtl_priv(hw); 353 struct rtl_phy *rtlphy = &(rtlpriv->phy); 354 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT]; 355 u32 precommoncmdcnt; 356 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT]; 357 u32 postcommoncmdcnt; 358 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT]; 359 u32 rfdependcmdcnt; 360 struct swchnlcmd *currentcmd = NULL; 361 u8 rfpath; 362 u8 num_total_rfpath = rtlphy->num_total_rfpath; 363 364 precommoncmdcnt = 0; 365 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 366 MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); 367 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 368 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); 369 370 postcommoncmdcnt = 0; 371 372 _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, 373 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); 374 375 rfdependcmdcnt = 0; 376 377 RT_ASSERT((channel >= 1 && channel <= 14), 378 "invalid channel for Zebra: %d\n", channel); 379 380 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 381 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, 382 RF_CHNLBW, channel, 10); 383 384 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 385 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0); 386 387 do { 388 switch (*stage) { 389 case 0: 390 currentcmd = &precommoncmd[*step]; 391 break; 392 case 1: 393 currentcmd = &rfdependcmd[*step]; 394 break; 395 case 2: 396 currentcmd = &postcommoncmd[*step]; 397 break; 398 default: 399 return true; 400 } 401 402 if (currentcmd->cmdid == CMDID_END) { 403 if ((*stage) == 2) { 404 return true; 405 } else { 406 (*stage)++; 407 (*step) = 0; 408 continue; 409 } 410 } 411 412 switch (currentcmd->cmdid) { 413 case CMDID_SET_TXPOWEROWER_LEVEL: 414 rtl92s_phy_set_txpower(hw, channel); 415 break; 416 case CMDID_WRITEPORT_ULONG: 417 rtl_write_dword(rtlpriv, currentcmd->para1, 418 currentcmd->para2); 419 break; 420 case CMDID_WRITEPORT_USHORT: 421 rtl_write_word(rtlpriv, currentcmd->para1, 422 (u16)currentcmd->para2); 423 break; 424 case CMDID_WRITEPORT_UCHAR: 425 rtl_write_byte(rtlpriv, currentcmd->para1, 426 (u8)currentcmd->para2); 427 break; 428 case CMDID_RF_WRITEREG: 429 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { 430 rtlphy->rfreg_chnlval[rfpath] = 431 ((rtlphy->rfreg_chnlval[rfpath] & 432 0xfffffc00) | currentcmd->para2); 433 rtl_set_rfreg(hw, (enum radio_path)rfpath, 434 currentcmd->para1, 435 RFREG_OFFSET_MASK, 436 rtlphy->rfreg_chnlval[rfpath]); 437 } 438 break; 439 default: 440 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 441 "switch case %#x not processed\n", 442 currentcmd->cmdid); 443 break; 444 } 445 446 break; 447 } while (true); 448 449 (*delay) = currentcmd->msdelay; 450 (*step)++; 451 return false; 452 } 453 454 u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw) 455 { 456 struct rtl_priv *rtlpriv = rtl_priv(hw); 457 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 458 struct rtl_phy *rtlphy = &(rtlpriv->phy); 459 u32 delay; 460 bool ret; 461 462 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n", 463 rtlphy->current_channel); 464 465 if (rtlphy->sw_chnl_inprogress) 466 return 0; 467 468 if (rtlphy->set_bwmode_inprogress) 469 return 0; 470 471 if (is_hal_stop(rtlhal)) 472 return 0; 473 474 rtlphy->sw_chnl_inprogress = true; 475 rtlphy->sw_chnl_stage = 0; 476 rtlphy->sw_chnl_step = 0; 477 478 do { 479 if (!rtlphy->sw_chnl_inprogress) 480 break; 481 482 ret = _rtl92s_phy_sw_chnl_step_by_step(hw, 483 rtlphy->current_channel, 484 &rtlphy->sw_chnl_stage, 485 &rtlphy->sw_chnl_step, &delay); 486 if (!ret) { 487 if (delay > 0) 488 mdelay(delay); 489 else 490 continue; 491 } else { 492 rtlphy->sw_chnl_inprogress = false; 493 } 494 break; 495 } while (true); 496 497 rtlphy->sw_chnl_inprogress = false; 498 499 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 500 501 return 1; 502 } 503 504 static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw *hw) 505 { 506 struct rtl_priv *rtlpriv = rtl_priv(hw); 507 u8 u1btmp; 508 509 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL); 510 u1btmp |= BIT(0); 511 512 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp); 513 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0); 514 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF); 515 rtl_write_word(rtlpriv, CMDR, 0x57FC); 516 udelay(100); 517 518 rtl_write_word(rtlpriv, CMDR, 0x77FC); 519 rtl_write_byte(rtlpriv, PHY_CCA, 0x0); 520 udelay(10); 521 522 rtl_write_word(rtlpriv, CMDR, 0x37FC); 523 udelay(10); 524 525 rtl_write_word(rtlpriv, CMDR, 0x77FC); 526 udelay(10); 527 528 rtl_write_word(rtlpriv, CMDR, 0x57FC); 529 530 /* we should chnge GPIO to input mode 531 * this will drop away current about 25mA*/ 532 rtl8192se_gpiobit3_cfg_inputmode(hw); 533 } 534 535 bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw, 536 enum rf_pwrstate rfpwr_state) 537 { 538 struct rtl_priv *rtlpriv = rtl_priv(hw); 539 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 540 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 541 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 542 bool bresult = true; 543 u8 i, queue_id; 544 struct rtl8192_tx_ring *ring = NULL; 545 546 if (rfpwr_state == ppsc->rfpwr_state) 547 return false; 548 549 switch (rfpwr_state) { 550 case ERFON:{ 551 if ((ppsc->rfpwr_state == ERFOFF) && 552 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 553 554 bool rtstatus; 555 u32 InitializeCount = 0; 556 do { 557 InitializeCount++; 558 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 559 "IPS Set eRf nic enable\n"); 560 rtstatus = rtl_ps_enable_nic(hw); 561 } while (!rtstatus && (InitializeCount < 10)); 562 563 RT_CLEAR_PS_LEVEL(ppsc, 564 RT_RF_OFF_LEVL_HALT_NIC); 565 } else { 566 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 567 "awake, sleeped:%d ms state_inap:%x\n", 568 jiffies_to_msecs(jiffies - 569 ppsc-> 570 last_sleep_jiffies), 571 rtlpriv->psc.state_inap); 572 ppsc->last_awake_jiffies = jiffies; 573 rtl_write_word(rtlpriv, CMDR, 0x37FC); 574 rtl_write_byte(rtlpriv, TXPAUSE, 0x00); 575 rtl_write_byte(rtlpriv, PHY_CCA, 0x3); 576 } 577 578 if (mac->link_state == MAC80211_LINKED) 579 rtlpriv->cfg->ops->led_control(hw, 580 LED_CTL_LINK); 581 else 582 rtlpriv->cfg->ops->led_control(hw, 583 LED_CTL_NO_LINK); 584 break; 585 } 586 case ERFOFF:{ 587 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 588 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 589 "IPS Set eRf nic disable\n"); 590 rtl_ps_disable_nic(hw); 591 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 592 } else { 593 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 594 rtlpriv->cfg->ops->led_control(hw, 595 LED_CTL_NO_LINK); 596 else 597 rtlpriv->cfg->ops->led_control(hw, 598 LED_CTL_POWER_OFF); 599 } 600 break; 601 } 602 case ERFSLEEP: 603 if (ppsc->rfpwr_state == ERFOFF) 604 return false; 605 606 for (queue_id = 0, i = 0; 607 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 608 ring = &pcipriv->dev.tx_ring[queue_id]; 609 if (skb_queue_len(&ring->queue) == 0 || 610 queue_id == BEACON_QUEUE) { 611 queue_id++; 612 continue; 613 } else { 614 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 615 "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n", 616 i + 1, queue_id, 617 skb_queue_len(&ring->queue)); 618 619 udelay(10); 620 i++; 621 } 622 623 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 624 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 625 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n", 626 MAX_DOZE_WAITING_TIMES_9x, 627 queue_id, 628 skb_queue_len(&ring->queue)); 629 break; 630 } 631 } 632 633 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 634 "Set ERFSLEEP awaked:%d ms\n", 635 jiffies_to_msecs(jiffies - 636 ppsc->last_awake_jiffies)); 637 638 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 639 "sleep awaked:%d ms state_inap:%x\n", 640 jiffies_to_msecs(jiffies - 641 ppsc->last_awake_jiffies), 642 rtlpriv->psc.state_inap); 643 ppsc->last_sleep_jiffies = jiffies; 644 _rtl92se_phy_set_rf_sleep(hw); 645 break; 646 default: 647 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 648 "switch case %#x not processed\n", rfpwr_state); 649 bresult = false; 650 break; 651 } 652 653 if (bresult) 654 ppsc->rfpwr_state = rfpwr_state; 655 656 return bresult; 657 } 658 659 static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw *hw, 660 enum radio_path rfpath) 661 { 662 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 663 bool rtstatus = true; 664 u32 tmpval = 0; 665 666 /* If inferiority IC, we have to increase the PA bias current */ 667 if (rtlhal->ic_class != IC_INFERIORITY_A) { 668 tmpval = rtl92s_phy_query_rf_reg(hw, rfpath, RF_IPA, 0xf); 669 rtl92s_phy_set_rf_reg(hw, rfpath, RF_IPA, 0xf, tmpval + 1); 670 } 671 672 return rtstatus; 673 } 674 675 static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, 676 u32 reg_addr, u32 bitmask, u32 data) 677 { 678 struct rtl_priv *rtlpriv = rtl_priv(hw); 679 struct rtl_phy *rtlphy = &(rtlpriv->phy); 680 int index; 681 682 if (reg_addr == RTXAGC_RATE18_06) 683 index = 0; 684 else if (reg_addr == RTXAGC_RATE54_24) 685 index = 1; 686 else if (reg_addr == RTXAGC_CCK_MCS32) 687 index = 6; 688 else if (reg_addr == RTXAGC_MCS03_MCS00) 689 index = 2; 690 else if (reg_addr == RTXAGC_MCS07_MCS04) 691 index = 3; 692 else if (reg_addr == RTXAGC_MCS11_MCS08) 693 index = 4; 694 else if (reg_addr == RTXAGC_MCS15_MCS12) 695 index = 5; 696 else 697 return; 698 699 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; 700 if (index == 5) 701 rtlphy->pwrgroup_cnt++; 702 } 703 704 static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw) 705 { 706 struct rtl_priv *rtlpriv = rtl_priv(hw); 707 struct rtl_phy *rtlphy = &(rtlpriv->phy); 708 709 /*RF Interface Sowrtware Control */ 710 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; 711 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; 712 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; 713 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; 714 715 /* RF Interface Readback Value */ 716 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; 717 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; 718 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; 719 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; 720 721 /* RF Interface Output (and Enable) */ 722 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; 723 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; 724 rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE; 725 rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE; 726 727 /* RF Interface (Output and) Enable */ 728 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; 729 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; 730 rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE; 731 rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE; 732 733 /* Addr of LSSI. Wirte RF register by driver */ 734 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = 735 RFPGA0_XA_LSSIPARAMETER; 736 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = 737 RFPGA0_XB_LSSIPARAMETER; 738 rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset = 739 RFPGA0_XC_LSSIPARAMETER; 740 rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset = 741 RFPGA0_XD_LSSIPARAMETER; 742 743 /* RF parameter */ 744 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; 745 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; 746 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; 747 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; 748 749 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ 750 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; 751 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; 752 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; 753 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; 754 755 /* Tranceiver A~D HSSI Parameter-1 */ 756 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; 757 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; 758 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1; 759 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1; 760 761 /* Tranceiver A~D HSSI Parameter-2 */ 762 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; 763 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; 764 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2; 765 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2; 766 767 /* RF switch Control */ 768 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 769 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 770 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 771 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 772 773 /* AGC control 1 */ 774 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; 775 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; 776 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; 777 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; 778 779 /* AGC control 2 */ 780 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; 781 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; 782 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; 783 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; 784 785 /* RX AFE control 1 */ 786 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; 787 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; 788 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE; 789 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; 790 791 /* RX AFE control 1 */ 792 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; 793 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; 794 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; 795 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; 796 797 /* Tx AFE control 1 */ 798 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; 799 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; 800 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; 801 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; 802 803 /* Tx AFE control 2 */ 804 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; 805 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; 806 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE; 807 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE; 808 809 /* Tranceiver LSSI Readback */ 810 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; 811 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; 812 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; 813 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; 814 815 /* Tranceiver LSSI Readback PI mode */ 816 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK; 817 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK; 818 } 819 820 821 static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype) 822 { 823 int i; 824 u32 *phy_reg_table; 825 u32 *agc_table; 826 u16 phy_reg_len, agc_len; 827 828 agc_len = AGCTAB_ARRAYLENGTH; 829 agc_table = rtl8192seagctab_array; 830 /* Default RF_type: 2T2R */ 831 phy_reg_len = PHY_REG_2T2RARRAYLENGTH; 832 phy_reg_table = rtl8192sephy_reg_2t2rarray; 833 834 if (configtype == BASEBAND_CONFIG_PHY_REG) { 835 for (i = 0; i < phy_reg_len; i = i + 2) { 836 rtl_addr_delay(phy_reg_table[i]); 837 838 /* Add delay for ECS T20 & LG malow platform, */ 839 udelay(1); 840 841 rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD, 842 phy_reg_table[i + 1]); 843 } 844 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 845 for (i = 0; i < agc_len; i = i + 2) { 846 rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD, 847 agc_table[i + 1]); 848 849 /* Add delay for ECS T20 & LG malow platform */ 850 udelay(1); 851 } 852 } 853 854 return true; 855 } 856 857 static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw, 858 u8 configtype) 859 { 860 struct rtl_priv *rtlpriv = rtl_priv(hw); 861 struct rtl_phy *rtlphy = &(rtlpriv->phy); 862 u32 *phy_regarray2xtxr_table; 863 u16 phy_regarray2xtxr_len; 864 int i; 865 866 if (rtlphy->rf_type == RF_1T1R) { 867 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t1rarray; 868 phy_regarray2xtxr_len = PHY_CHANGETO_1T1RARRAYLENGTH; 869 } else if (rtlphy->rf_type == RF_1T2R) { 870 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t2rarray; 871 phy_regarray2xtxr_len = PHY_CHANGETO_1T2RARRAYLENGTH; 872 } else { 873 return false; 874 } 875 876 if (configtype == BASEBAND_CONFIG_PHY_REG) { 877 for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) { 878 rtl_addr_delay(phy_regarray2xtxr_table[i]); 879 880 rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i], 881 phy_regarray2xtxr_table[i + 1], 882 phy_regarray2xtxr_table[i + 2]); 883 } 884 } 885 886 return true; 887 } 888 889 static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw, 890 u8 configtype) 891 { 892 int i; 893 u32 *phy_table_pg; 894 u16 phy_pg_len; 895 896 phy_pg_len = PHY_REG_ARRAY_PGLENGTH; 897 phy_table_pg = rtl8192sephy_reg_array_pg; 898 899 if (configtype == BASEBAND_CONFIG_PHY_REG) { 900 for (i = 0; i < phy_pg_len; i = i + 3) { 901 rtl_addr_delay(phy_table_pg[i]); 902 903 _rtl92s_store_pwrindex_diffrate_offset(hw, 904 phy_table_pg[i], 905 phy_table_pg[i + 1], 906 phy_table_pg[i + 2]); 907 rtl92s_phy_set_bb_reg(hw, phy_table_pg[i], 908 phy_table_pg[i + 1], 909 phy_table_pg[i + 2]); 910 } 911 } 912 913 return true; 914 } 915 916 static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw) 917 { 918 struct rtl_priv *rtlpriv = rtl_priv(hw); 919 struct rtl_phy *rtlphy = &(rtlpriv->phy); 920 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 921 bool rtstatus = true; 922 923 /* 1. Read PHY_REG.TXT BB INIT!! */ 924 /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */ 925 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R || 926 rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) { 927 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG); 928 929 if (rtlphy->rf_type != RF_2T2R && 930 rtlphy->rf_type != RF_2T2R_GREEN) 931 /* so we should reconfig BB reg with the right 932 * PHY parameters. */ 933 rtstatus = _rtl92s_phy_set_bb_to_diff_rf(hw, 934 BASEBAND_CONFIG_PHY_REG); 935 } else { 936 rtstatus = false; 937 } 938 939 if (!rtstatus) { 940 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, 941 "Write BB Reg Fail!!\n"); 942 goto phy_BB8190_Config_ParaFile_Fail; 943 } 944 945 /* 2. If EEPROM or EFUSE autoload OK, We must config by 946 * PHY_REG_PG.txt */ 947 if (rtlefuse->autoload_failflag == false) { 948 rtlphy->pwrgroup_cnt = 0; 949 950 rtstatus = _rtl92s_phy_config_bb_with_pg(hw, 951 BASEBAND_CONFIG_PHY_REG); 952 } 953 if (!rtstatus) { 954 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, 955 "_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n"); 956 goto phy_BB8190_Config_ParaFile_Fail; 957 } 958 959 /* 3. BB AGC table Initialization */ 960 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB); 961 962 if (!rtstatus) { 963 pr_err("%s(): AGC Table Fail\n", __func__); 964 goto phy_BB8190_Config_ParaFile_Fail; 965 } 966 967 /* Check if the CCK HighPower is turned ON. */ 968 /* This is used to calculate PWDB. */ 969 rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw, 970 RFPGA0_XA_HSSIPARAMETER2, 0x200)); 971 972 phy_BB8190_Config_ParaFile_Fail: 973 return rtstatus; 974 } 975 976 u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath) 977 { 978 struct rtl_priv *rtlpriv = rtl_priv(hw); 979 struct rtl_phy *rtlphy = &(rtlpriv->phy); 980 int i; 981 bool rtstatus = true; 982 u32 *radio_a_table; 983 u32 *radio_b_table; 984 u16 radio_a_tblen, radio_b_tblen; 985 986 radio_a_tblen = RADIOA_1T_ARRAYLENGTH; 987 radio_a_table = rtl8192seradioa_1t_array; 988 989 /* Using Green mode array table for RF_2T2R_GREEN */ 990 if (rtlphy->rf_type == RF_2T2R_GREEN) { 991 radio_b_table = rtl8192seradiob_gm_array; 992 radio_b_tblen = RADIOB_GM_ARRAYLENGTH; 993 } else { 994 radio_b_table = rtl8192seradiob_array; 995 radio_b_tblen = RADIOB_ARRAYLENGTH; 996 } 997 998 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath); 999 rtstatus = true; 1000 1001 switch (rfpath) { 1002 case RF90_PATH_A: 1003 for (i = 0; i < radio_a_tblen; i = i + 2) { 1004 rtl_rfreg_delay(hw, rfpath, radio_a_table[i], 1005 MASK20BITS, radio_a_table[i + 1]); 1006 1007 } 1008 1009 /* PA Bias current for inferiority IC */ 1010 _rtl92s_phy_config_rfpa_bias_current(hw, rfpath); 1011 break; 1012 case RF90_PATH_B: 1013 for (i = 0; i < radio_b_tblen; i = i + 2) { 1014 rtl_rfreg_delay(hw, rfpath, radio_b_table[i], 1015 MASK20BITS, radio_b_table[i + 1]); 1016 } 1017 break; 1018 case RF90_PATH_C: 1019 ; 1020 break; 1021 case RF90_PATH_D: 1022 ; 1023 break; 1024 default: 1025 break; 1026 } 1027 1028 return rtstatus; 1029 } 1030 1031 1032 bool rtl92s_phy_mac_config(struct ieee80211_hw *hw) 1033 { 1034 struct rtl_priv *rtlpriv = rtl_priv(hw); 1035 u32 i; 1036 u32 arraylength; 1037 u32 *ptraArray; 1038 1039 arraylength = MAC_2T_ARRAYLENGTH; 1040 ptraArray = rtl8192semac_2t_array; 1041 1042 for (i = 0; i < arraylength; i = i + 2) 1043 rtl_write_byte(rtlpriv, ptraArray[i], (u8)ptraArray[i + 1]); 1044 1045 return true; 1046 } 1047 1048 1049 bool rtl92s_phy_bb_config(struct ieee80211_hw *hw) 1050 { 1051 struct rtl_priv *rtlpriv = rtl_priv(hw); 1052 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1053 bool rtstatus = true; 1054 u8 pathmap, index, rf_num = 0; 1055 u8 path1, path2; 1056 1057 _rtl92s_phy_init_register_definition(hw); 1058 1059 /* Config BB and AGC */ 1060 rtstatus = _rtl92s_phy_bb_config_parafile(hw); 1061 1062 1063 /* Check BB/RF confiuration setting. */ 1064 /* We only need to configure RF which is turned on. */ 1065 path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf)); 1066 mdelay(10); 1067 path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf)); 1068 pathmap = path1 | path2; 1069 1070 rtlphy->rf_pathmap = pathmap; 1071 for (index = 0; index < 4; index++) { 1072 if ((pathmap >> index) & 0x1) 1073 rf_num++; 1074 } 1075 1076 if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) || 1077 (rtlphy->rf_type == RF_1T2R && rf_num != 2) || 1078 (rtlphy->rf_type == RF_2T2R && rf_num != 2) || 1079 (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) { 1080 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, 1081 "RF_Type(%x) does not match RF_Num(%x)!!\n", 1082 rtlphy->rf_type, rf_num); 1083 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, 1084 "path1 0x%x, path2 0x%x, pathmap 0x%x\n", 1085 path1, path2, pathmap); 1086 } 1087 1088 return rtstatus; 1089 } 1090 1091 bool rtl92s_phy_rf_config(struct ieee80211_hw *hw) 1092 { 1093 struct rtl_priv *rtlpriv = rtl_priv(hw); 1094 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1095 1096 /* Initialize general global value */ 1097 if (rtlphy->rf_type == RF_1T1R) 1098 rtlphy->num_total_rfpath = 1; 1099 else 1100 rtlphy->num_total_rfpath = 2; 1101 1102 /* Config BB and RF */ 1103 return rtl92s_phy_rf6052_config(hw); 1104 } 1105 1106 void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 1107 { 1108 struct rtl_priv *rtlpriv = rtl_priv(hw); 1109 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1110 1111 /* read rx initial gain */ 1112 rtlphy->default_initialgain[0] = rtl_get_bbreg(hw, 1113 ROFDM0_XAAGCCORE1, MASKBYTE0); 1114 rtlphy->default_initialgain[1] = rtl_get_bbreg(hw, 1115 ROFDM0_XBAGCCORE1, MASKBYTE0); 1116 rtlphy->default_initialgain[2] = rtl_get_bbreg(hw, 1117 ROFDM0_XCAGCCORE1, MASKBYTE0); 1118 rtlphy->default_initialgain[3] = rtl_get_bbreg(hw, 1119 ROFDM0_XDAGCCORE1, MASKBYTE0); 1120 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1121 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n", 1122 rtlphy->default_initialgain[0], 1123 rtlphy->default_initialgain[1], 1124 rtlphy->default_initialgain[2], 1125 rtlphy->default_initialgain[3]); 1126 1127 /* read framesync */ 1128 rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0); 1129 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, 1130 MASKDWORD); 1131 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1132 "Default framesync (0x%x) = 0x%x\n", 1133 ROFDM0_RXDETECTOR3, rtlphy->framesync); 1134 1135 } 1136 1137 static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel, 1138 u8 *cckpowerlevel, u8 *ofdmpowerLevel) 1139 { 1140 struct rtl_priv *rtlpriv = rtl_priv(hw); 1141 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1142 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1143 u8 index = (channel - 1); 1144 1145 /* 1. CCK */ 1146 /* RF-A */ 1147 cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index]; 1148 /* RF-B */ 1149 cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index]; 1150 1151 /* 2. OFDM for 1T or 2T */ 1152 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) { 1153 /* Read HT 40 OFDM TX power */ 1154 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index]; 1155 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index]; 1156 } else if (rtlphy->rf_type == RF_2T2R) { 1157 /* Read HT 40 OFDM TX power */ 1158 ofdmpowerLevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index]; 1159 ofdmpowerLevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index]; 1160 } else { 1161 ofdmpowerLevel[0] = 0; 1162 ofdmpowerLevel[1] = 0; 1163 } 1164 } 1165 1166 static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw, 1167 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel) 1168 { 1169 struct rtl_priv *rtlpriv = rtl_priv(hw); 1170 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1171 1172 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; 1173 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; 1174 } 1175 1176 void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel) 1177 { 1178 struct rtl_priv *rtlpriv = rtl_priv(hw); 1179 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1180 /* [0]:RF-A, [1]:RF-B */ 1181 u8 cckpowerlevel[2], ofdmpowerLevel[2]; 1182 1183 if (!rtlefuse->txpwr_fromeprom) 1184 return; 1185 1186 /* Mainly we use RF-A Tx Power to write the Tx Power registers, 1187 * but the RF-B Tx Power must be calculated by the antenna diff. 1188 * So we have to rewrite Antenna gain offset register here. 1189 * Please refer to BB register 0x80c 1190 * 1. For CCK. 1191 * 2. For OFDM 1T or 2T */ 1192 _rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0], 1193 &ofdmpowerLevel[0]); 1194 1195 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 1196 "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n", 1197 channel, cckpowerlevel[0], cckpowerlevel[1], 1198 ofdmpowerLevel[0], ofdmpowerLevel[1]); 1199 1200 _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0], 1201 &ofdmpowerLevel[0]); 1202 1203 rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]); 1204 rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerLevel[0], channel); 1205 1206 } 1207 1208 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw) 1209 { 1210 struct rtl_priv *rtlpriv = rtl_priv(hw); 1211 u16 pollingcnt = 10000; 1212 u32 tmpvalue; 1213 1214 /* Make sure that CMD IO has be accepted by FW. */ 1215 do { 1216 udelay(10); 1217 1218 tmpvalue = rtl_read_dword(rtlpriv, WFM5); 1219 if (tmpvalue == 0) 1220 break; 1221 } while (--pollingcnt); 1222 1223 if (pollingcnt == 0) 1224 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Set FW Cmd fail!!\n"); 1225 } 1226 1227 1228 static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw) 1229 { 1230 struct rtl_priv *rtlpriv = rtl_priv(hw); 1231 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1232 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1233 u32 input, current_aid = 0; 1234 1235 if (is_hal_stop(rtlhal)) 1236 return; 1237 1238 if (hal_get_firmwareversion(rtlpriv) < 0x34) 1239 goto skip; 1240 /* We re-map RA related CMD IO to combinational ones */ 1241 /* if FW version is v.52 or later. */ 1242 switch (rtlhal->current_fwcmd_io) { 1243 case FW_CMD_RA_REFRESH_N: 1244 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_N_COMB; 1245 break; 1246 case FW_CMD_RA_REFRESH_BG: 1247 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_BG_COMB; 1248 break; 1249 default: 1250 break; 1251 } 1252 1253 skip: 1254 switch (rtlhal->current_fwcmd_io) { 1255 case FW_CMD_RA_RESET: 1256 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n"); 1257 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET); 1258 rtl92s_phy_chk_fwcmd_iodone(hw); 1259 break; 1260 case FW_CMD_RA_ACTIVE: 1261 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n"); 1262 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE); 1263 rtl92s_phy_chk_fwcmd_iodone(hw); 1264 break; 1265 case FW_CMD_RA_REFRESH_N: 1266 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n"); 1267 input = FW_RA_REFRESH; 1268 rtl_write_dword(rtlpriv, WFM5, input); 1269 rtl92s_phy_chk_fwcmd_iodone(hw); 1270 rtl_write_dword(rtlpriv, WFM5, FW_RA_ENABLE_RSSI_MASK); 1271 rtl92s_phy_chk_fwcmd_iodone(hw); 1272 break; 1273 case FW_CMD_RA_REFRESH_BG: 1274 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, 1275 "FW_CMD_RA_REFRESH_BG\n"); 1276 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH); 1277 rtl92s_phy_chk_fwcmd_iodone(hw); 1278 rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK); 1279 rtl92s_phy_chk_fwcmd_iodone(hw); 1280 break; 1281 case FW_CMD_RA_REFRESH_N_COMB: 1282 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, 1283 "FW_CMD_RA_REFRESH_N_COMB\n"); 1284 input = FW_RA_IOT_N_COMB; 1285 rtl_write_dword(rtlpriv, WFM5, input); 1286 rtl92s_phy_chk_fwcmd_iodone(hw); 1287 break; 1288 case FW_CMD_RA_REFRESH_BG_COMB: 1289 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, 1290 "FW_CMD_RA_REFRESH_BG_COMB\n"); 1291 input = FW_RA_IOT_BG_COMB; 1292 rtl_write_dword(rtlpriv, WFM5, input); 1293 rtl92s_phy_chk_fwcmd_iodone(hw); 1294 break; 1295 case FW_CMD_IQK_ENABLE: 1296 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n"); 1297 rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE); 1298 rtl92s_phy_chk_fwcmd_iodone(hw); 1299 break; 1300 case FW_CMD_PAUSE_DM_BY_SCAN: 1301 /* Lower initial gain */ 1302 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17); 1303 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17); 1304 /* CCA threshold */ 1305 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40); 1306 break; 1307 case FW_CMD_RESUME_DM_BY_SCAN: 1308 /* CCA threshold */ 1309 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); 1310 rtl92s_phy_set_txpower(hw, rtlphy->current_channel); 1311 break; 1312 case FW_CMD_HIGH_PWR_DISABLE: 1313 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) 1314 break; 1315 1316 /* Lower initial gain */ 1317 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17); 1318 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17); 1319 /* CCA threshold */ 1320 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40); 1321 break; 1322 case FW_CMD_HIGH_PWR_ENABLE: 1323 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) || 1324 rtlpriv->dm.dynamic_txpower_enable) 1325 break; 1326 1327 /* CCA threshold */ 1328 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); 1329 break; 1330 case FW_CMD_LPS_ENTER: 1331 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n"); 1332 current_aid = rtlpriv->mac80211.assoc_id; 1333 rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER | 1334 ((current_aid | 0xc000) << 8))); 1335 rtl92s_phy_chk_fwcmd_iodone(hw); 1336 /* FW set TXOP disable here, so disable EDCA 1337 * turbo mode until driver leave LPS */ 1338 break; 1339 case FW_CMD_LPS_LEAVE: 1340 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n"); 1341 rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE); 1342 rtl92s_phy_chk_fwcmd_iodone(hw); 1343 break; 1344 case FW_CMD_ADD_A2_ENTRY: 1345 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n"); 1346 rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY); 1347 rtl92s_phy_chk_fwcmd_iodone(hw); 1348 break; 1349 case FW_CMD_CTRL_DM_BY_DRIVER: 1350 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 1351 "FW_CMD_CTRL_DM_BY_DRIVER\n"); 1352 rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER); 1353 rtl92s_phy_chk_fwcmd_iodone(hw); 1354 break; 1355 1356 default: 1357 break; 1358 } 1359 1360 rtl92s_phy_chk_fwcmd_iodone(hw); 1361 1362 /* Clear FW CMD operation flag. */ 1363 rtlhal->set_fwcmd_inprogress = false; 1364 } 1365 1366 bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio) 1367 { 1368 struct rtl_priv *rtlpriv = rtl_priv(hw); 1369 struct dig_t *digtable = &rtlpriv->dm_digtable; 1370 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1371 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1372 u32 fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv); 1373 u16 fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv); 1374 bool postprocessing = false; 1375 1376 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 1377 "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n", 1378 fw_cmdio, rtlhal->set_fwcmd_inprogress); 1379 1380 do { 1381 /* We re-map to combined FW CMD ones if firmware version */ 1382 /* is v.53 or later. */ 1383 if (hal_get_firmwareversion(rtlpriv) >= 0x35) { 1384 switch (fw_cmdio) { 1385 case FW_CMD_RA_REFRESH_N: 1386 fw_cmdio = FW_CMD_RA_REFRESH_N_COMB; 1387 break; 1388 case FW_CMD_RA_REFRESH_BG: 1389 fw_cmdio = FW_CMD_RA_REFRESH_BG_COMB; 1390 break; 1391 default: 1392 break; 1393 } 1394 } else { 1395 if ((fw_cmdio == FW_CMD_IQK_ENABLE) || 1396 (fw_cmdio == FW_CMD_RA_REFRESH_N) || 1397 (fw_cmdio == FW_CMD_RA_REFRESH_BG)) { 1398 postprocessing = true; 1399 break; 1400 } 1401 } 1402 1403 /* If firmware version is v.62 or later, 1404 * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */ 1405 if (hal_get_firmwareversion(rtlpriv) >= 0x3E) { 1406 if (fw_cmdio == FW_CMD_CTRL_DM_BY_DRIVER) 1407 fw_cmdio = FW_CMD_CTRL_DM_BY_DRIVER_NEW; 1408 } 1409 1410 1411 /* We shall revise all FW Cmd IO into Reg0x364 1412 * DM map table in the future. */ 1413 switch (fw_cmdio) { 1414 case FW_CMD_RA_INIT: 1415 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n"); 1416 fw_cmdmap |= FW_RA_INIT_CTL; 1417 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1418 /* Clear control flag to sync with FW. */ 1419 FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL); 1420 break; 1421 case FW_CMD_DIG_DISABLE: 1422 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 1423 "Set DIG disable!!\n"); 1424 fw_cmdmap &= ~FW_DIG_ENABLE_CTL; 1425 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1426 break; 1427 case FW_CMD_DIG_ENABLE: 1428 case FW_CMD_DIG_RESUME: 1429 if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) { 1430 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 1431 "Set DIG enable or resume!!\n"); 1432 fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL); 1433 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1434 } 1435 break; 1436 case FW_CMD_DIG_HALT: 1437 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 1438 "Set DIG halt!!\n"); 1439 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL); 1440 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1441 break; 1442 case FW_CMD_TXPWR_TRACK_THERMAL: { 1443 u8 thermalval = 0; 1444 fw_cmdmap |= FW_PWR_TRK_CTL; 1445 1446 /* Clear FW parameter in terms of thermal parts. */ 1447 fw_param &= FW_PWR_TRK_PARAM_CLR; 1448 1449 thermalval = rtlpriv->dm.thermalvalue; 1450 fw_param |= ((thermalval << 24) | 1451 (rtlefuse->thermalmeter[0] << 16)); 1452 1453 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 1454 "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n", 1455 fw_cmdmap, fw_param); 1456 1457 FW_CMD_PARA_SET(rtlpriv, fw_param); 1458 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1459 1460 /* Clear control flag to sync with FW. */ 1461 FW_CMD_IO_CLR(rtlpriv, FW_PWR_TRK_CTL); 1462 } 1463 break; 1464 /* The following FW CMDs are only compatible to 1465 * v.53 or later. */ 1466 case FW_CMD_RA_REFRESH_N_COMB: 1467 fw_cmdmap |= FW_RA_N_CTL; 1468 1469 /* Clear RA BG mode control. */ 1470 fw_cmdmap &= ~(FW_RA_BG_CTL | FW_RA_INIT_CTL); 1471 1472 /* Clear FW parameter in terms of RA parts. */ 1473 fw_param &= FW_RA_PARAM_CLR; 1474 1475 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 1476 "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n", 1477 fw_cmdmap, fw_param); 1478 1479 FW_CMD_PARA_SET(rtlpriv, fw_param); 1480 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1481 1482 /* Clear control flag to sync with FW. */ 1483 FW_CMD_IO_CLR(rtlpriv, FW_RA_N_CTL); 1484 break; 1485 case FW_CMD_RA_REFRESH_BG_COMB: 1486 fw_cmdmap |= FW_RA_BG_CTL; 1487 1488 /* Clear RA n-mode control. */ 1489 fw_cmdmap &= ~(FW_RA_N_CTL | FW_RA_INIT_CTL); 1490 /* Clear FW parameter in terms of RA parts. */ 1491 fw_param &= FW_RA_PARAM_CLR; 1492 1493 FW_CMD_PARA_SET(rtlpriv, fw_param); 1494 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1495 1496 /* Clear control flag to sync with FW. */ 1497 FW_CMD_IO_CLR(rtlpriv, FW_RA_BG_CTL); 1498 break; 1499 case FW_CMD_IQK_ENABLE: 1500 fw_cmdmap |= FW_IQK_CTL; 1501 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1502 /* Clear control flag to sync with FW. */ 1503 FW_CMD_IO_CLR(rtlpriv, FW_IQK_CTL); 1504 break; 1505 /* The following FW CMD is compatible to v.62 or later. */ 1506 case FW_CMD_CTRL_DM_BY_DRIVER_NEW: 1507 fw_cmdmap |= FW_DRIVER_CTRL_DM_CTL; 1508 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1509 break; 1510 /* The followed FW Cmds needs post-processing later. */ 1511 case FW_CMD_RESUME_DM_BY_SCAN: 1512 fw_cmdmap |= (FW_DIG_ENABLE_CTL | 1513 FW_HIGH_PWR_ENABLE_CTL | 1514 FW_SS_CTL); 1515 1516 if (rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE || 1517 !digtable->dig_enable_flag) 1518 fw_cmdmap &= ~FW_DIG_ENABLE_CTL; 1519 1520 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) || 1521 rtlpriv->dm.dynamic_txpower_enable) 1522 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL; 1523 1524 if ((digtable->dig_ext_port_stage == 1525 DIG_EXT_PORT_STAGE_0) || 1526 (digtable->dig_ext_port_stage == 1527 DIG_EXT_PORT_STAGE_1)) 1528 fw_cmdmap &= ~FW_DIG_ENABLE_CTL; 1529 1530 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1531 postprocessing = true; 1532 break; 1533 case FW_CMD_PAUSE_DM_BY_SCAN: 1534 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | 1535 FW_HIGH_PWR_ENABLE_CTL | 1536 FW_SS_CTL); 1537 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1538 postprocessing = true; 1539 break; 1540 case FW_CMD_HIGH_PWR_DISABLE: 1541 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL; 1542 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1543 postprocessing = true; 1544 break; 1545 case FW_CMD_HIGH_PWR_ENABLE: 1546 if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) && 1547 !rtlpriv->dm.dynamic_txpower_enable) { 1548 fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL | 1549 FW_SS_CTL); 1550 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1551 postprocessing = true; 1552 } 1553 break; 1554 case FW_CMD_DIG_MODE_FA: 1555 fw_cmdmap |= FW_FA_CTL; 1556 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1557 break; 1558 case FW_CMD_DIG_MODE_SS: 1559 fw_cmdmap &= ~FW_FA_CTL; 1560 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1561 break; 1562 case FW_CMD_PAPE_CONTROL: 1563 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 1564 "[FW CMD] Set PAPE Control\n"); 1565 fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW; 1566 1567 FW_CMD_IO_SET(rtlpriv, fw_cmdmap); 1568 break; 1569 default: 1570 /* Pass to original FW CMD processing callback 1571 * routine. */ 1572 postprocessing = true; 1573 break; 1574 } 1575 } while (false); 1576 1577 /* We shall post processing these FW CMD if 1578 * variable postprocessing is set. 1579 */ 1580 if (postprocessing && !rtlhal->set_fwcmd_inprogress) { 1581 rtlhal->set_fwcmd_inprogress = true; 1582 /* Update current FW Cmd for callback use. */ 1583 rtlhal->current_fwcmd_io = fw_cmdio; 1584 } else { 1585 return false; 1586 } 1587 1588 _rtl92s_phy_set_fwcmd_io(hw); 1589 return true; 1590 } 1591 1592 static void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw *hw) 1593 { 1594 struct rtl_priv *rtlpriv = rtl_priv(hw); 1595 u32 delay = 100; 1596 u8 regu1; 1597 1598 regu1 = rtl_read_byte(rtlpriv, 0x554); 1599 while ((regu1 & BIT(5)) && (delay > 0)) { 1600 regu1 = rtl_read_byte(rtlpriv, 0x554); 1601 delay--; 1602 /* We delay only 50us to prevent 1603 * being scheduled out. */ 1604 udelay(50); 1605 } 1606 } 1607 1608 void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw) 1609 { 1610 struct rtl_priv *rtlpriv = rtl_priv(hw); 1611 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1612 1613 /* The way to be capable to switch clock request 1614 * when the PG setting does not support clock request. 1615 * This is the backdoor solution to switch clock 1616 * request before ASPM or D3. */ 1617 rtl_write_dword(rtlpriv, 0x540, 0x73c11); 1618 rtl_write_dword(rtlpriv, 0x548, 0x2407c); 1619 1620 /* Switch EPHY parameter!!!! */ 1621 rtl_write_word(rtlpriv, 0x550, 0x1000); 1622 rtl_write_byte(rtlpriv, 0x554, 0x20); 1623 _rtl92s_phy_check_ephy_switchready(hw); 1624 1625 rtl_write_word(rtlpriv, 0x550, 0xa0eb); 1626 rtl_write_byte(rtlpriv, 0x554, 0x3e); 1627 _rtl92s_phy_check_ephy_switchready(hw); 1628 1629 rtl_write_word(rtlpriv, 0x550, 0xff80); 1630 rtl_write_byte(rtlpriv, 0x554, 0x39); 1631 _rtl92s_phy_check_ephy_switchready(hw); 1632 1633 /* Delay L1 enter time */ 1634 if (ppsc->support_aspm && !ppsc->support_backdoor) 1635 rtl_write_byte(rtlpriv, 0x560, 0x40); 1636 else 1637 rtl_write_byte(rtlpriv, 0x560, 0x00); 1638 1639 } 1640 1641 void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval) 1642 { 1643 struct rtl_priv *rtlpriv = rtl_priv(hw); 1644 u32 new_bcn_num = 0; 1645 1646 if (hal_get_firmwareversion(rtlpriv) >= 0x33) { 1647 /* Fw v.51 and later. */ 1648 rtl_write_dword(rtlpriv, WFM5, 0xF1000000 | 1649 (beaconinterval << 8)); 1650 } else { 1651 new_bcn_num = beaconinterval * 32 - 64; 1652 rtl_write_dword(rtlpriv, WFM3 + 4, new_bcn_num); 1653 rtl_write_dword(rtlpriv, WFM3, 0xB026007C); 1654 } 1655 } 1656