1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../regd.h" 30 #include "../cam.h" 31 #include "../ps.h" 32 #include "../pci.h" 33 #include "reg.h" 34 #include "def.h" 35 #include "phy.h" 36 #include "dm.h" 37 #include "fw.h" 38 #include "led.h" 39 #include "hw.h" 40 41 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 42 { 43 struct rtl_priv *rtlpriv = rtl_priv(hw); 44 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 45 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 46 47 switch (variable) { 48 case HW_VAR_RCR: { 49 *((u32 *) (val)) = rtlpci->receive_config; 50 break; 51 } 52 case HW_VAR_RF_STATE: { 53 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 54 break; 55 } 56 case HW_VAR_FW_PSMODE_STATUS: { 57 *((bool *) (val)) = ppsc->fw_current_inpsmode; 58 break; 59 } 60 case HW_VAR_CORRECT_TSF: { 61 u64 tsf; 62 u32 *ptsf_low = (u32 *)&tsf; 63 u32 *ptsf_high = ((u32 *)&tsf) + 1; 64 65 *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4)); 66 *ptsf_low = rtl_read_dword(rtlpriv, TSFR); 67 68 *((u64 *) (val)) = tsf; 69 70 break; 71 } 72 case HW_VAR_MRC: { 73 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch; 74 break; 75 } 76 case HAL_DEF_WOWLAN: 77 break; 78 default: 79 pr_err("switch case %#x not processed\n", variable); 80 break; 81 } 82 } 83 84 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 85 { 86 struct rtl_priv *rtlpriv = rtl_priv(hw); 87 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 88 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 89 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 90 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 91 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 92 93 switch (variable) { 94 case HW_VAR_ETHER_ADDR:{ 95 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]); 96 rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]); 97 break; 98 } 99 case HW_VAR_BASIC_RATE:{ 100 u16 rate_cfg = ((u16 *) val)[0]; 101 u8 rate_index = 0; 102 103 if (rtlhal->version == VERSION_8192S_ACUT) 104 rate_cfg = rate_cfg & 0x150; 105 else 106 rate_cfg = rate_cfg & 0x15f; 107 108 rate_cfg |= 0x01; 109 110 rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff); 111 rtl_write_byte(rtlpriv, RRSR + 1, 112 (rate_cfg >> 8) & 0xff); 113 114 while (rate_cfg > 0x1) { 115 rate_cfg = (rate_cfg >> 1); 116 rate_index++; 117 } 118 rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index); 119 120 break; 121 } 122 case HW_VAR_BSSID:{ 123 rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]); 124 rtl_write_word(rtlpriv, BSSIDR + 4, 125 ((u16 *)(val + 4))[0]); 126 break; 127 } 128 case HW_VAR_SIFS:{ 129 rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]); 130 rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]); 131 break; 132 } 133 case HW_VAR_SLOT_TIME:{ 134 u8 e_aci; 135 136 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 137 "HW_VAR_SLOT_TIME %x\n", val[0]); 138 139 rtl_write_byte(rtlpriv, SLOT_TIME, val[0]); 140 141 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 142 rtlpriv->cfg->ops->set_hw_reg(hw, 143 HW_VAR_AC_PARAM, 144 (&e_aci)); 145 } 146 break; 147 } 148 case HW_VAR_ACK_PREAMBLE:{ 149 u8 reg_tmp; 150 u8 short_preamble = (bool) (*val); 151 reg_tmp = (mac->cur_40_prime_sc) << 5; 152 if (short_preamble) 153 reg_tmp |= 0x80; 154 155 rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp); 156 break; 157 } 158 case HW_VAR_AMPDU_MIN_SPACE:{ 159 u8 min_spacing_to_set; 160 u8 sec_min_space; 161 162 min_spacing_to_set = *val; 163 if (min_spacing_to_set <= 7) { 164 if (rtlpriv->sec.pairwise_enc_algorithm == 165 NO_ENCRYPTION) 166 sec_min_space = 0; 167 else 168 sec_min_space = 1; 169 170 if (min_spacing_to_set < sec_min_space) 171 min_spacing_to_set = sec_min_space; 172 if (min_spacing_to_set > 5) 173 min_spacing_to_set = 5; 174 175 mac->min_space_cfg = 176 ((mac->min_space_cfg & 0xf8) | 177 min_spacing_to_set); 178 179 *val = min_spacing_to_set; 180 181 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 182 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 183 mac->min_space_cfg); 184 185 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 186 mac->min_space_cfg); 187 } 188 break; 189 } 190 case HW_VAR_SHORTGI_DENSITY:{ 191 u8 density_to_set; 192 193 density_to_set = *val; 194 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg; 195 mac->min_space_cfg |= (density_to_set << 3); 196 197 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 198 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 199 mac->min_space_cfg); 200 201 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 202 mac->min_space_cfg); 203 204 break; 205 } 206 case HW_VAR_AMPDU_FACTOR:{ 207 u8 factor_toset; 208 u8 regtoset; 209 u8 factorlevel[18] = { 210 2, 4, 4, 7, 7, 13, 13, 211 13, 2, 7, 7, 13, 13, 212 15, 15, 15, 15, 0}; 213 u8 index = 0; 214 215 factor_toset = *val; 216 if (factor_toset <= 3) { 217 factor_toset = (1 << (factor_toset + 2)); 218 if (factor_toset > 0xf) 219 factor_toset = 0xf; 220 221 for (index = 0; index < 17; index++) { 222 if (factorlevel[index] > factor_toset) 223 factorlevel[index] = 224 factor_toset; 225 } 226 227 for (index = 0; index < 8; index++) { 228 regtoset = ((factorlevel[index * 2]) | 229 (factorlevel[index * 230 2 + 1] << 4)); 231 rtl_write_byte(rtlpriv, 232 AGGLEN_LMT_L + index, 233 regtoset); 234 } 235 236 regtoset = ((factorlevel[16]) | 237 (factorlevel[17] << 4)); 238 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset); 239 240 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 241 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 242 factor_toset); 243 } 244 break; 245 } 246 case HW_VAR_AC_PARAM:{ 247 u8 e_aci = *val; 248 rtl92s_dm_init_edca_turbo(hw); 249 250 if (rtlpci->acm_method != EACMWAY2_SW) 251 rtlpriv->cfg->ops->set_hw_reg(hw, 252 HW_VAR_ACM_CTRL, 253 &e_aci); 254 break; 255 } 256 case HW_VAR_ACM_CTRL:{ 257 u8 e_aci = *val; 258 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&( 259 mac->ac[0].aifs)); 260 u8 acm = p_aci_aifsn->f.acm; 261 u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl); 262 263 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 264 0x0 : 0x1); 265 266 if (acm) { 267 switch (e_aci) { 268 case AC0_BE: 269 acm_ctrl |= AcmHw_BeqEn; 270 break; 271 case AC2_VI: 272 acm_ctrl |= AcmHw_ViqEn; 273 break; 274 case AC3_VO: 275 acm_ctrl |= AcmHw_VoqEn; 276 break; 277 default: 278 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 279 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 280 acm); 281 break; 282 } 283 } else { 284 switch (e_aci) { 285 case AC0_BE: 286 acm_ctrl &= (~AcmHw_BeqEn); 287 break; 288 case AC2_VI: 289 acm_ctrl &= (~AcmHw_ViqEn); 290 break; 291 case AC3_VO: 292 acm_ctrl &= (~AcmHw_VoqEn); 293 break; 294 default: 295 pr_err("switch case %#x not processed\n", 296 e_aci); 297 break; 298 } 299 } 300 301 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 302 "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl); 303 rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl); 304 break; 305 } 306 case HW_VAR_RCR:{ 307 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]); 308 rtlpci->receive_config = ((u32 *) (val))[0]; 309 break; 310 } 311 case HW_VAR_RETRY_LIMIT:{ 312 u8 retry_limit = val[0]; 313 314 rtl_write_word(rtlpriv, RETRY_LIMIT, 315 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 316 retry_limit << RETRY_LIMIT_LONG_SHIFT); 317 break; 318 } 319 case HW_VAR_DUAL_TSF_RST: { 320 break; 321 } 322 case HW_VAR_EFUSE_BYTES: { 323 rtlefuse->efuse_usedbytes = *((u16 *) val); 324 break; 325 } 326 case HW_VAR_EFUSE_USAGE: { 327 rtlefuse->efuse_usedpercentage = *val; 328 break; 329 } 330 case HW_VAR_IO_CMD: { 331 break; 332 } 333 case HW_VAR_WPA_CONFIG: { 334 rtl_write_byte(rtlpriv, REG_SECR, *val); 335 break; 336 } 337 case HW_VAR_SET_RPWM:{ 338 break; 339 } 340 case HW_VAR_H2C_FW_PWRMODE:{ 341 break; 342 } 343 case HW_VAR_FW_PSMODE_STATUS: { 344 ppsc->fw_current_inpsmode = *((bool *) val); 345 break; 346 } 347 case HW_VAR_H2C_FW_JOINBSSRPT:{ 348 break; 349 } 350 case HW_VAR_AID:{ 351 break; 352 } 353 case HW_VAR_CORRECT_TSF:{ 354 break; 355 } 356 case HW_VAR_MRC: { 357 bool bmrc_toset = *((bool *)val); 358 u8 u1bdata = 0; 359 360 if (bmrc_toset) { 361 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, 362 MASKBYTE0, 0x33); 363 u1bdata = (u8)rtl_get_bbreg(hw, 364 ROFDM1_TRXPATHENABLE, 365 MASKBYTE0); 366 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, 367 MASKBYTE0, 368 ((u1bdata & 0xf0) | 0x03)); 369 u1bdata = (u8)rtl_get_bbreg(hw, 370 ROFDM0_TRXPATHENABLE, 371 MASKBYTE1); 372 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, 373 MASKBYTE1, 374 (u1bdata | 0x04)); 375 376 /* Update current settings. */ 377 rtlpriv->dm.current_mrc_switch = bmrc_toset; 378 } else { 379 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, 380 MASKBYTE0, 0x13); 381 u1bdata = (u8)rtl_get_bbreg(hw, 382 ROFDM1_TRXPATHENABLE, 383 MASKBYTE0); 384 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, 385 MASKBYTE0, 386 ((u1bdata & 0xf0) | 0x01)); 387 u1bdata = (u8)rtl_get_bbreg(hw, 388 ROFDM0_TRXPATHENABLE, 389 MASKBYTE1); 390 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, 391 MASKBYTE1, (u1bdata & 0xfb)); 392 393 /* Update current settings. */ 394 rtlpriv->dm.current_mrc_switch = bmrc_toset; 395 } 396 397 break; 398 } 399 case HW_VAR_FW_LPS_ACTION: { 400 bool enter_fwlps = *((bool *)val); 401 u8 rpwm_val, fw_pwrmode; 402 bool fw_current_inps; 403 404 if (enter_fwlps) { 405 rpwm_val = 0x02; /* RF off */ 406 fw_current_inps = true; 407 rtlpriv->cfg->ops->set_hw_reg(hw, 408 HW_VAR_FW_PSMODE_STATUS, 409 (u8 *)(&fw_current_inps)); 410 rtlpriv->cfg->ops->set_hw_reg(hw, 411 HW_VAR_H2C_FW_PWRMODE, 412 &ppsc->fwctrl_psmode); 413 414 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 415 &rpwm_val); 416 } else { 417 rpwm_val = 0x0C; /* RF on */ 418 fw_pwrmode = FW_PS_ACTIVE_MODE; 419 fw_current_inps = false; 420 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 421 &rpwm_val); 422 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 423 &fw_pwrmode); 424 425 rtlpriv->cfg->ops->set_hw_reg(hw, 426 HW_VAR_FW_PSMODE_STATUS, 427 (u8 *)(&fw_current_inps)); 428 } 429 break; } 430 default: 431 pr_err("switch case %#x not processed\n", variable); 432 break; 433 } 434 435 } 436 437 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw) 438 { 439 struct rtl_priv *rtlpriv = rtl_priv(hw); 440 u8 sec_reg_value = 0x0; 441 442 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 443 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 444 rtlpriv->sec.pairwise_enc_algorithm, 445 rtlpriv->sec.group_enc_algorithm); 446 447 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 448 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 449 "not open hw encryption\n"); 450 return; 451 } 452 453 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE; 454 455 if (rtlpriv->sec.use_defaultkey) { 456 sec_reg_value |= SCR_TXUSEDK; 457 sec_reg_value |= SCR_RXUSEDK; 458 } 459 460 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n", 461 sec_reg_value); 462 463 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 464 465 } 466 467 static u8 _rtl92se_halset_sysclk(struct ieee80211_hw *hw, u8 data) 468 { 469 struct rtl_priv *rtlpriv = rtl_priv(hw); 470 u8 waitcount = 100; 471 bool bresult = false; 472 u8 tmpvalue; 473 474 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data); 475 476 /* Wait the MAC synchronized. */ 477 udelay(400); 478 479 /* Check if it is set ready. */ 480 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1); 481 bresult = ((tmpvalue & BIT(7)) == (data & BIT(7))); 482 483 if ((data & (BIT(6) | BIT(7))) == false) { 484 waitcount = 100; 485 tmpvalue = 0; 486 487 while (1) { 488 waitcount--; 489 490 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1); 491 if ((tmpvalue & BIT(6))) 492 break; 493 494 pr_err("wait for BIT(6) return value %x\n", tmpvalue); 495 if (waitcount == 0) 496 break; 497 498 udelay(10); 499 } 500 501 if (waitcount == 0) 502 bresult = false; 503 else 504 bresult = true; 505 } 506 507 return bresult; 508 } 509 510 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw) 511 { 512 struct rtl_priv *rtlpriv = rtl_priv(hw); 513 u8 u1tmp; 514 515 /* The following config GPIO function */ 516 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO)); 517 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL); 518 519 /* config GPIO3 to input */ 520 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK; 521 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp); 522 523 } 524 525 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw) 526 { 527 struct rtl_priv *rtlpriv = rtl_priv(hw); 528 u8 u1tmp; 529 u8 retval = ERFON; 530 531 /* The following config GPIO function */ 532 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO)); 533 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL); 534 535 /* config GPIO3 to input */ 536 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK; 537 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp); 538 539 /* On some of the platform, driver cannot read correct 540 * value without delay between Write_GPIO_SEL and Read_GPIO_IN */ 541 mdelay(10); 542 543 /* check GPIO3 */ 544 u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE); 545 retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF; 546 547 return retval; 548 } 549 550 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw) 551 { 552 struct rtl_priv *rtlpriv = rtl_priv(hw); 553 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 554 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 555 556 u8 i; 557 u8 tmpu1b; 558 u16 tmpu2b; 559 u8 pollingcnt = 20; 560 561 if (rtlpci->first_init) { 562 /* Reset PCIE Digital */ 563 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 564 tmpu1b &= 0xFE; 565 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b); 566 udelay(1); 567 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0)); 568 } 569 570 /* Switch to SW IO control */ 571 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 572 if (tmpu1b & BIT(7)) { 573 tmpu1b &= ~(BIT(6) | BIT(7)); 574 575 /* Set failed, return to prevent hang. */ 576 if (!_rtl92se_halset_sysclk(hw, tmpu1b)) 577 return; 578 } 579 580 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0); 581 udelay(50); 582 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34); 583 udelay(50); 584 585 /* Clear FW RPWM for FW control LPS.*/ 586 rtl_write_byte(rtlpriv, RPWM, 0x0); 587 588 /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */ 589 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 590 tmpu1b &= 0x73; 591 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b); 592 /* wait for BIT 10/11/15 to pull high automatically!! */ 593 mdelay(1); 594 595 rtl_write_byte(rtlpriv, CMDR, 0); 596 rtl_write_byte(rtlpriv, TCR, 0); 597 598 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */ 599 tmpu1b = rtl_read_byte(rtlpriv, 0x562); 600 tmpu1b |= 0x08; 601 rtl_write_byte(rtlpriv, 0x562, tmpu1b); 602 tmpu1b &= ~(BIT(3)); 603 rtl_write_byte(rtlpriv, 0x562, tmpu1b); 604 605 /* Enable AFE clock source */ 606 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL); 607 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01)); 608 /* Delay 1.5ms */ 609 mdelay(2); 610 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1); 611 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb)); 612 613 /* Enable AFE Macro Block's Bandgap */ 614 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC); 615 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0))); 616 mdelay(1); 617 618 /* Enable AFE Mbias */ 619 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC); 620 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02)); 621 mdelay(1); 622 623 /* Enable LDOA15 block */ 624 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL); 625 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0))); 626 627 /* Set Digital Vdd to Retention isolation Path. */ 628 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); 629 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11))); 630 631 /* For warm reboot NIC disappera bug. */ 632 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 633 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13))); 634 635 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68); 636 637 /* Enable AFE PLL Macro Block */ 638 /* We need to delay 100u before enabling PLL. */ 639 udelay(200); 640 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL); 641 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); 642 643 /* for divider reset */ 644 udelay(100); 645 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | 646 BIT(4) | BIT(6))); 647 udelay(10); 648 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); 649 udelay(10); 650 651 /* Enable MAC 80MHZ clock */ 652 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1); 653 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0))); 654 mdelay(1); 655 656 /* Release isolation AFE PLL & MD */ 657 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6); 658 659 /* Enable MAC clock */ 660 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR); 661 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11))); 662 663 /* Enable Core digital and enable IOREG R/W */ 664 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 665 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11))); 666 667 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 668 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7))); 669 670 /* enable REG_EN */ 671 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15))); 672 673 /* Switch the control path. */ 674 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR); 675 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2)))); 676 677 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 678 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6))); 679 if (!_rtl92se_halset_sysclk(hw, tmpu1b)) 680 return; /* Set failed, return to prevent hang. */ 681 682 rtl_write_word(rtlpriv, CMDR, 0x07FC); 683 684 /* MH We must enable the section of code to prevent load IMEM fail. */ 685 /* Load MAC register from WMAc temporarily We simulate macreg. */ 686 /* txt HW will provide MAC txt later */ 687 rtl_write_byte(rtlpriv, 0x6, 0x30); 688 rtl_write_byte(rtlpriv, 0x49, 0xf0); 689 690 rtl_write_byte(rtlpriv, 0x4b, 0x81); 691 692 rtl_write_byte(rtlpriv, 0xb5, 0x21); 693 694 rtl_write_byte(rtlpriv, 0xdc, 0xff); 695 rtl_write_byte(rtlpriv, 0xdd, 0xff); 696 rtl_write_byte(rtlpriv, 0xde, 0xff); 697 rtl_write_byte(rtlpriv, 0xdf, 0xff); 698 699 rtl_write_byte(rtlpriv, 0x11a, 0x00); 700 rtl_write_byte(rtlpriv, 0x11b, 0x00); 701 702 for (i = 0; i < 32; i++) 703 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b); 704 705 rtl_write_byte(rtlpriv, 0x236, 0xff); 706 707 rtl_write_byte(rtlpriv, 0x503, 0x22); 708 709 if (ppsc->support_aspm && !ppsc->support_backdoor) 710 rtl_write_byte(rtlpriv, 0x560, 0x40); 711 else 712 rtl_write_byte(rtlpriv, 0x560, 0x00); 713 714 rtl_write_byte(rtlpriv, DBG_PORT, 0x91); 715 716 /* Set RX Desc Address */ 717 rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma); 718 rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma); 719 720 /* Set TX Desc Address */ 721 rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma); 722 rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma); 723 rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma); 724 rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma); 725 rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma); 726 rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma); 727 rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma); 728 rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma); 729 rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma); 730 731 rtl_write_word(rtlpriv, CMDR, 0x37FC); 732 733 /* To make sure that TxDMA can ready to download FW. */ 734 /* We should reset TxDMA if IMEM RPT was not ready. */ 735 do { 736 tmpu1b = rtl_read_byte(rtlpriv, TCR); 737 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE) 738 break; 739 740 udelay(5); 741 } while (pollingcnt--); 742 743 if (pollingcnt <= 0) { 744 pr_err("Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n", 745 tmpu1b); 746 tmpu1b = rtl_read_byte(rtlpriv, CMDR); 747 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN)); 748 udelay(2); 749 /* Reset TxDMA */ 750 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN); 751 } 752 753 /* After MACIO reset,we must refresh LED state. */ 754 if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) || 755 (ppsc->rfoff_reason == 0)) { 756 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 757 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0); 758 enum rf_pwrstate rfpwr_state_toset; 759 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw); 760 761 if (rfpwr_state_toset == ERFON) 762 rtl92se_sw_led_on(hw, pLed0); 763 } 764 } 765 766 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw) 767 { 768 struct rtl_priv *rtlpriv = rtl_priv(hw); 769 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 770 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 771 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 772 u8 i; 773 u16 tmpu2b; 774 775 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */ 776 777 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */ 778 /* Turn on 0x40 Command register */ 779 rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN | 780 SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN | 781 RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN)); 782 783 /* Set TCR TX DMA pre 2 FULL enable bit */ 784 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) | 785 TXDMAPRE2FULL); 786 787 /* Set RCR */ 788 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config); 789 790 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */ 791 792 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */ 793 /* Set CCK/OFDM SIFS */ 794 /* CCK SIFS shall always be 10us. */ 795 rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a); 796 rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010); 797 798 /* Set AckTimeout */ 799 rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40); 800 801 /* Beacon related */ 802 rtl_write_word(rtlpriv, BCN_INTERVAL, 100); 803 rtl_write_word(rtlpriv, ATIMWND, 2); 804 805 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */ 806 /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */ 807 /* Firmware allocate now, associate with FW internal setting.!!! */ 808 809 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */ 810 /* 5.3 Set driver info, we only accept PHY status now. */ 811 /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO */ 812 rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6)); 813 814 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */ 815 /* Set RRSR to all legacy rate and HT rate 816 * CCK rate is supported by default. 817 * CCK rate will be filtered out only when associated 818 * AP does not support it. 819 * Only enable ACK rate to OFDM 24M 820 * Disable RRSR for CCK rate in A-Cut */ 821 822 if (rtlhal->version == VERSION_8192S_ACUT) 823 rtl_write_byte(rtlpriv, RRSR, 0xf0); 824 else if (rtlhal->version == VERSION_8192S_BCUT) 825 rtl_write_byte(rtlpriv, RRSR, 0xff); 826 rtl_write_byte(rtlpriv, RRSR + 1, 0x01); 827 rtl_write_byte(rtlpriv, RRSR + 2, 0x00); 828 829 /* A-Cut IC do not support CCK rate. We forbid ARFR to */ 830 /* fallback to CCK rate */ 831 for (i = 0; i < 8; i++) { 832 /*Disable RRSR for CCK rate in A-Cut */ 833 if (rtlhal->version == VERSION_8192S_ACUT) 834 rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0); 835 } 836 837 /* Different rate use different AMPDU size */ 838 /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */ 839 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f); 840 /* MCS0/1/2/3 use max AMPDU size 4*2=8K */ 841 rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442); 842 /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */ 843 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7); 844 /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */ 845 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772); 846 /* MCS12/13/14/15 use max AMPDU size 15*2=30K */ 847 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd); 848 849 /* Set Data / Response auto rate fallack retry count */ 850 rtl_write_dword(rtlpriv, DARFRC, 0x04010000); 851 rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605); 852 rtl_write_dword(rtlpriv, RARFRC, 0x04010000); 853 rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605); 854 855 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */ 856 /* Set all rate to support SG */ 857 rtl_write_word(rtlpriv, SG_RATE, 0xFFFF); 858 859 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */ 860 /* Set NAV protection length */ 861 rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080); 862 /* CF-END Threshold */ 863 rtl_write_byte(rtlpriv, CFEND_TH, 0xFF); 864 /* Set AMPDU minimum space */ 865 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07); 866 /* Set TXOP stall control for several queue/HI/BCN/MGT/ */ 867 rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00); 868 869 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */ 870 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */ 871 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */ 872 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */ 873 /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */ 874 875 /* 14. Set driver info, we only accept PHY status now. */ 876 rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4); 877 878 /* 15. For EEPROM R/W Workaround */ 879 /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */ 880 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 881 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13)); 882 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL); 883 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8))); 884 885 /* 17. For EFUSE */ 886 /* We may R/W EFUSE in EEPROM mode */ 887 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) { 888 u8 tempval; 889 890 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1); 891 tempval &= 0xFE; 892 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval); 893 894 /* Change Program timing */ 895 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72); 896 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n"); 897 } 898 899 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n"); 900 901 } 902 903 static void _rtl92se_hw_configure(struct ieee80211_hw *hw) 904 { 905 struct rtl_priv *rtlpriv = rtl_priv(hw); 906 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 907 struct rtl_phy *rtlphy = &(rtlpriv->phy); 908 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 909 910 u8 reg_bw_opmode = 0; 911 u32 reg_rrsr = 0; 912 u8 regtmp = 0; 913 914 reg_bw_opmode = BW_OPMODE_20MHZ; 915 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 916 917 regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL); 918 reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp; 919 rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr); 920 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode); 921 922 /* Set Retry Limit here */ 923 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, 924 (u8 *)(&rtlpci->shortretry_limit)); 925 926 rtl_write_byte(rtlpriv, MLT, 0x8f); 927 928 /* For Min Spacing configuration. */ 929 switch (rtlphy->rf_type) { 930 case RF_1T2R: 931 case RF_1T1R: 932 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3); 933 break; 934 case RF_2T2R: 935 case RF_2T2R_GREEN: 936 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3); 937 break; 938 } 939 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg); 940 } 941 942 int rtl92se_hw_init(struct ieee80211_hw *hw) 943 { 944 struct rtl_priv *rtlpriv = rtl_priv(hw); 945 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 946 struct rtl_phy *rtlphy = &(rtlpriv->phy); 947 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 948 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 949 u8 tmp_byte = 0; 950 unsigned long flags; 951 bool rtstatus = true; 952 u8 tmp_u1b; 953 int err = false; 954 u8 i; 955 int wdcapra_add[] = { 956 EDCAPARA_BE, EDCAPARA_BK, 957 EDCAPARA_VI, EDCAPARA_VO}; 958 u8 secr_value = 0x0; 959 960 rtlpci->being_init_adapter = true; 961 962 /* As this function can take a very long time (up to 350 ms) 963 * and can be called with irqs disabled, reenable the irqs 964 * to let the other devices continue being serviced. 965 * 966 * It is safe doing so since our own interrupts will only be enabled 967 * in a subsequent step. 968 */ 969 local_save_flags(flags); 970 local_irq_enable(); 971 972 rtlpriv->intf_ops->disable_aspm(hw); 973 974 /* 1. MAC Initialize */ 975 /* Before FW download, we have to set some MAC register */ 976 _rtl92se_macconfig_before_fwdownload(hw); 977 978 rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv, 979 PMC_FSM) >> 16) & 0xF); 980 981 rtl8192se_gpiobit3_cfg_inputmode(hw); 982 983 /* 2. download firmware */ 984 rtstatus = rtl92s_download_fw(hw); 985 if (!rtstatus) { 986 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 987 "Failed to download FW. Init HW without FW now... " 988 "Please copy FW into /lib/firmware/rtlwifi\n"); 989 err = 1; 990 goto exit; 991 } 992 993 /* After FW download, we have to reset MAC register */ 994 _rtl92se_macconfig_after_fwdownload(hw); 995 996 /*Retrieve default FW Cmd IO map. */ 997 rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, LBUS_MON_ADDR); 998 rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK); 999 1000 /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */ 1001 if (!rtl92s_phy_mac_config(hw)) { 1002 pr_err("MAC Config failed\n"); 1003 err = rtstatus; 1004 goto exit; 1005 } 1006 1007 /* because last function modify RCR, so we update 1008 * rcr var here, or TP will unstable for receive_config 1009 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 1010 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 1011 */ 1012 rtlpci->receive_config = rtl_read_dword(rtlpriv, RCR); 1013 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 1014 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config); 1015 1016 /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */ 1017 /* We must set flag avoid BB/RF config period later!! */ 1018 rtl_write_dword(rtlpriv, CMDR, 0x37FC); 1019 1020 /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */ 1021 if (!rtl92s_phy_bb_config(hw)) { 1022 pr_err("BB Config failed\n"); 1023 err = rtstatus; 1024 goto exit; 1025 } 1026 1027 /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */ 1028 /* Before initalizing RF. We can not use FW to do RF-R/W. */ 1029 1030 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 1031 1032 /* Before RF-R/W we must execute the IO from Scott's suggestion. */ 1033 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB); 1034 if (rtlhal->version == VERSION_8192S_ACUT) 1035 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07); 1036 else 1037 rtl_write_byte(rtlpriv, RF_CTRL, 0x07); 1038 1039 if (!rtl92s_phy_rf_config(hw)) { 1040 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n"); 1041 err = rtstatus; 1042 goto exit; 1043 } 1044 1045 /* After read predefined TXT, we must set BB/MAC/RF 1046 * register as our requirement */ 1047 1048 rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw, 1049 (enum radio_path)0, 1050 RF_CHNLBW, 1051 RFREG_OFFSET_MASK); 1052 rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw, 1053 (enum radio_path)1, 1054 RF_CHNLBW, 1055 RFREG_OFFSET_MASK); 1056 1057 /*---- Set CCK and OFDM Block "ON"----*/ 1058 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1059 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1060 1061 /*3 Set Hardware(Do nothing now) */ 1062 _rtl92se_hw_configure(hw); 1063 1064 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */ 1065 /* TX power index for different rate set. */ 1066 /* Get original hw reg values */ 1067 rtl92s_phy_get_hw_reg_originalvalue(hw); 1068 /* Write correct tx power index */ 1069 rtl92s_phy_set_txpower(hw, rtlphy->current_channel); 1070 1071 /* We must set MAC address after firmware download. */ 1072 for (i = 0; i < 6; i++) 1073 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]); 1074 1075 /* EEPROM R/W workaround */ 1076 tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG); 1077 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3))); 1078 1079 rtl_write_byte(rtlpriv, 0x4d, 0x0); 1080 1081 if (hal_get_firmwareversion(rtlpriv) >= 0x49) { 1082 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4)); 1083 tmp_byte = tmp_byte | BIT(5); 1084 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte); 1085 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF); 1086 } 1087 1088 /* We enable high power and RA related mechanism after NIC 1089 * initialized. */ 1090 if (hal_get_firmwareversion(rtlpriv) >= 0x35) { 1091 /* Fw v.53 and later. */ 1092 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT); 1093 } else if (hal_get_firmwareversion(rtlpriv) == 0x34) { 1094 /* Fw v.52. */ 1095 rtl_write_dword(rtlpriv, WFM5, FW_RA_INIT); 1096 rtl92s_phy_chk_fwcmd_iodone(hw); 1097 } else { 1098 /* Compatible earlier FW version. */ 1099 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET); 1100 rtl92s_phy_chk_fwcmd_iodone(hw); 1101 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE); 1102 rtl92s_phy_chk_fwcmd_iodone(hw); 1103 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH); 1104 rtl92s_phy_chk_fwcmd_iodone(hw); 1105 } 1106 1107 /* Add to prevent ASPM bug. */ 1108 /* Always enable hst and NIC clock request. */ 1109 rtl92s_phy_switch_ephy_parameter(hw); 1110 1111 /* Security related 1112 * 1. Clear all H/W keys. 1113 * 2. Enable H/W encryption/decryption. */ 1114 rtl_cam_reset_all_entry(hw); 1115 secr_value |= SCR_TXENCENABLE; 1116 secr_value |= SCR_RXENCENABLE; 1117 secr_value |= SCR_NOSKMC; 1118 rtl_write_byte(rtlpriv, REG_SECR, secr_value); 1119 1120 for (i = 0; i < 4; i++) 1121 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322); 1122 1123 if (rtlphy->rf_type == RF_1T2R) { 1124 bool mrc2set = true; 1125 /* Turn on B-Path */ 1126 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set); 1127 } 1128 1129 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON); 1130 rtl92s_dm_init(hw); 1131 exit: 1132 local_irq_restore(flags); 1133 rtlpci->being_init_adapter = false; 1134 return err; 1135 } 1136 1137 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 *addr) 1138 { 1139 /* This is a stub. */ 1140 } 1141 1142 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1143 { 1144 struct rtl_priv *rtlpriv = rtl_priv(hw); 1145 u32 reg_rcr; 1146 1147 if (rtlpriv->psc.rfpwr_state != ERFON) 1148 return; 1149 1150 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1151 1152 if (check_bssid) { 1153 reg_rcr |= (RCR_CBSSID); 1154 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1155 } else if (!check_bssid) { 1156 reg_rcr &= (~RCR_CBSSID); 1157 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1158 } 1159 1160 } 1161 1162 static int _rtl92se_set_media_status(struct ieee80211_hw *hw, 1163 enum nl80211_iftype type) 1164 { 1165 struct rtl_priv *rtlpriv = rtl_priv(hw); 1166 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1167 u32 temp; 1168 bt_msr &= ~MSR_LINK_MASK; 1169 1170 switch (type) { 1171 case NL80211_IFTYPE_UNSPECIFIED: 1172 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); 1173 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1174 "Set Network type to NO LINK!\n"); 1175 break; 1176 case NL80211_IFTYPE_ADHOC: 1177 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT); 1178 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1179 "Set Network type to Ad Hoc!\n"); 1180 break; 1181 case NL80211_IFTYPE_STATION: 1182 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT); 1183 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1184 "Set Network type to STA!\n"); 1185 break; 1186 case NL80211_IFTYPE_AP: 1187 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT); 1188 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1189 "Set Network type to AP!\n"); 1190 break; 1191 default: 1192 pr_err("Network type %d not supported!\n", type); 1193 return 1; 1194 1195 } 1196 1197 if (type != NL80211_IFTYPE_AP && 1198 rtlpriv->mac80211.link_state < MAC80211_LINKED) 1199 bt_msr = rtl_read_byte(rtlpriv, MSR) & ~MSR_LINK_MASK; 1200 rtl_write_byte(rtlpriv, MSR, bt_msr); 1201 1202 temp = rtl_read_dword(rtlpriv, TCR); 1203 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8))); 1204 rtl_write_dword(rtlpriv, TCR, temp | BIT(8)); 1205 1206 1207 return 0; 1208 } 1209 1210 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */ 1211 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1212 { 1213 struct rtl_priv *rtlpriv = rtl_priv(hw); 1214 1215 if (_rtl92se_set_media_status(hw, type)) 1216 return -EOPNOTSUPP; 1217 1218 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1219 if (type != NL80211_IFTYPE_AP) 1220 rtl92se_set_check_bssid(hw, true); 1221 } else { 1222 rtl92se_set_check_bssid(hw, false); 1223 } 1224 1225 return 0; 1226 } 1227 1228 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ 1229 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci) 1230 { 1231 struct rtl_priv *rtlpriv = rtl_priv(hw); 1232 rtl92s_dm_init_edca_turbo(hw); 1233 1234 switch (aci) { 1235 case AC1_BK: 1236 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f); 1237 break; 1238 case AC0_BE: 1239 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */ 1240 break; 1241 case AC2_VI: 1242 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322); 1243 break; 1244 case AC3_VO: 1245 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222); 1246 break; 1247 default: 1248 WARN_ONCE(true, "rtl8192se: invalid aci: %d !\n", aci); 1249 break; 1250 } 1251 } 1252 1253 void rtl92se_enable_interrupt(struct ieee80211_hw *hw) 1254 { 1255 struct rtl_priv *rtlpriv = rtl_priv(hw); 1256 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1257 1258 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]); 1259 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */ 1260 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F); 1261 rtlpci->irq_enabled = true; 1262 } 1263 1264 void rtl92se_disable_interrupt(struct ieee80211_hw *hw) 1265 { 1266 struct rtl_priv *rtlpriv; 1267 struct rtl_pci *rtlpci; 1268 1269 rtlpriv = rtl_priv(hw); 1270 /* if firmware not available, no interrupts */ 1271 if (!rtlpriv || !rtlpriv->max_fw_size) 1272 return; 1273 rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1274 rtl_write_dword(rtlpriv, INTA_MASK, 0); 1275 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0); 1276 rtlpci->irq_enabled = false; 1277 } 1278 1279 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data) 1280 { 1281 struct rtl_priv *rtlpriv = rtl_priv(hw); 1282 u8 waitcnt = 100; 1283 bool result = false; 1284 u8 tmp; 1285 1286 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data); 1287 1288 /* Wait the MAC synchronized. */ 1289 udelay(400); 1290 1291 /* Check if it is set ready. */ 1292 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1); 1293 result = ((tmp & BIT(7)) == (data & BIT(7))); 1294 1295 if ((data & (BIT(6) | BIT(7))) == false) { 1296 waitcnt = 100; 1297 tmp = 0; 1298 1299 while (1) { 1300 waitcnt--; 1301 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1); 1302 1303 if ((tmp & BIT(6))) 1304 break; 1305 1306 pr_err("wait for BIT(6) return value %x\n", tmp); 1307 1308 if (waitcnt == 0) 1309 break; 1310 udelay(10); 1311 } 1312 1313 if (waitcnt == 0) 1314 result = false; 1315 else 1316 result = true; 1317 } 1318 1319 return result; 1320 } 1321 1322 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw) 1323 { 1324 struct rtl_priv *rtlpriv = rtl_priv(hw); 1325 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1326 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1327 u8 u1btmp; 1328 1329 if (rtlhal->driver_going2unload) 1330 rtl_write_byte(rtlpriv, 0x560, 0x0); 1331 1332 /* Power save for BB/RF */ 1333 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL); 1334 u1btmp |= BIT(0); 1335 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp); 1336 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0); 1337 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF); 1338 rtl_write_word(rtlpriv, CMDR, 0x57FC); 1339 udelay(100); 1340 rtl_write_word(rtlpriv, CMDR, 0x77FC); 1341 rtl_write_byte(rtlpriv, PHY_CCA, 0x0); 1342 udelay(10); 1343 rtl_write_word(rtlpriv, CMDR, 0x37FC); 1344 udelay(10); 1345 rtl_write_word(rtlpriv, CMDR, 0x77FC); 1346 udelay(10); 1347 rtl_write_word(rtlpriv, CMDR, 0x57FC); 1348 rtl_write_word(rtlpriv, CMDR, 0x0000); 1349 1350 if (rtlhal->driver_going2unload) { 1351 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1)); 1352 u1btmp &= ~(BIT(0)); 1353 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp); 1354 } 1355 1356 u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 1357 1358 /* Add description. After switch control path. register 1359 * after page1 will be invisible. We can not do any IO 1360 * for register>0x40. After resume&MACIO reset, we need 1361 * to remember previous reg content. */ 1362 if (u1btmp & BIT(7)) { 1363 u1btmp &= ~(BIT(6) | BIT(7)); 1364 if (!_rtl92s_set_sysclk(hw, u1btmp)) { 1365 pr_err("Switch ctrl path fail\n"); 1366 return; 1367 } 1368 } 1369 1370 /* Power save for MAC */ 1371 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS && 1372 !rtlhal->driver_going2unload) { 1373 /* enable LED function */ 1374 rtl_write_byte(rtlpriv, 0x03, 0xF9); 1375 /* SW/HW radio off or halt adapter!! For example S3/S4 */ 1376 } else { 1377 /* LED function disable. Power range is about 8mA now. */ 1378 /* if write 0xF1 disconnet_pci power 1379 * ifconfig wlan0 down power are both high 35:70 */ 1380 /* if write oxF9 disconnet_pci power 1381 * ifconfig wlan0 down power are both low 12:45*/ 1382 rtl_write_byte(rtlpriv, 0x03, 0xF9); 1383 } 1384 1385 rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70); 1386 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68); 1387 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x00); 1388 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34); 1389 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E); 1390 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1391 1392 } 1393 1394 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw) 1395 { 1396 struct rtl_priv *rtlpriv = rtl_priv(hw); 1397 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1398 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1399 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0); 1400 1401 if (rtlpci->up_first_time == 1) 1402 return; 1403 1404 if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS) 1405 rtl92se_sw_led_on(hw, pLed0); 1406 else 1407 rtl92se_sw_led_off(hw, pLed0); 1408 } 1409 1410 1411 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw) 1412 { 1413 struct rtl_priv *rtlpriv = rtl_priv(hw); 1414 u16 tmpu2b; 1415 u8 tmpu1b; 1416 1417 rtlpriv->psc.pwrdomain_protect = true; 1418 1419 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 1420 if (tmpu1b & BIT(7)) { 1421 tmpu1b &= ~(BIT(6) | BIT(7)); 1422 if (!_rtl92s_set_sysclk(hw, tmpu1b)) { 1423 rtlpriv->psc.pwrdomain_protect = false; 1424 return; 1425 } 1426 } 1427 1428 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0); 1429 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34); 1430 1431 /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */ 1432 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1433 1434 /* If IPS we need to turn LED on. So we not 1435 * not disable BIT 3/7 of reg3. */ 1436 if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW)) 1437 tmpu1b &= 0xFB; 1438 else 1439 tmpu1b &= 0x73; 1440 1441 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b); 1442 /* wait for BIT 10/11/15 to pull high automatically!! */ 1443 mdelay(1); 1444 1445 rtl_write_byte(rtlpriv, CMDR, 0); 1446 rtl_write_byte(rtlpriv, TCR, 0); 1447 1448 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */ 1449 tmpu1b = rtl_read_byte(rtlpriv, 0x562); 1450 tmpu1b |= 0x08; 1451 rtl_write_byte(rtlpriv, 0x562, tmpu1b); 1452 tmpu1b &= ~(BIT(3)); 1453 rtl_write_byte(rtlpriv, 0x562, tmpu1b); 1454 1455 /* Enable AFE clock source */ 1456 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL); 1457 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01)); 1458 /* Delay 1.5ms */ 1459 udelay(1500); 1460 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1); 1461 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb)); 1462 1463 /* Enable AFE Macro Block's Bandgap */ 1464 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC); 1465 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0))); 1466 mdelay(1); 1467 1468 /* Enable AFE Mbias */ 1469 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC); 1470 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02)); 1471 mdelay(1); 1472 1473 /* Enable LDOA15 block */ 1474 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL); 1475 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0))); 1476 1477 /* Set Digital Vdd to Retention isolation Path. */ 1478 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); 1479 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11))); 1480 1481 1482 /* For warm reboot NIC disappera bug. */ 1483 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1484 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13))); 1485 1486 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68); 1487 1488 /* Enable AFE PLL Macro Block */ 1489 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL); 1490 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); 1491 /* Enable MAC 80MHZ clock */ 1492 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1); 1493 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0))); 1494 mdelay(1); 1495 1496 /* Release isolation AFE PLL & MD */ 1497 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6); 1498 1499 /* Enable MAC clock */ 1500 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR); 1501 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11))); 1502 1503 /* Enable Core digital and enable IOREG R/W */ 1504 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1505 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11))); 1506 /* enable REG_EN */ 1507 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15))); 1508 1509 /* Switch the control path. */ 1510 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR); 1511 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2)))); 1512 1513 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 1514 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6))); 1515 if (!_rtl92s_set_sysclk(hw, tmpu1b)) { 1516 rtlpriv->psc.pwrdomain_protect = false; 1517 return; 1518 } 1519 1520 rtl_write_word(rtlpriv, CMDR, 0x37FC); 1521 1522 /* After MACIO reset,we must refresh LED state. */ 1523 _rtl92se_gen_refreshledstate(hw); 1524 1525 rtlpriv->psc.pwrdomain_protect = false; 1526 } 1527 1528 void rtl92se_card_disable(struct ieee80211_hw *hw) 1529 { 1530 struct rtl_priv *rtlpriv = rtl_priv(hw); 1531 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1532 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1533 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1534 enum nl80211_iftype opmode; 1535 u8 wait = 30; 1536 1537 rtlpriv->intf_ops->enable_aspm(hw); 1538 1539 if (rtlpci->driver_is_goingto_unload || 1540 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1541 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1542 1543 /* we should chnge GPIO to input mode 1544 * this will drop away current about 25mA*/ 1545 rtl8192se_gpiobit3_cfg_inputmode(hw); 1546 1547 /* this is very important for ips power save */ 1548 while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) { 1549 if (rtlpriv->psc.pwrdomain_protect) 1550 mdelay(20); 1551 else 1552 break; 1553 } 1554 1555 mac->link_state = MAC80211_NOLINK; 1556 opmode = NL80211_IFTYPE_UNSPECIFIED; 1557 _rtl92se_set_media_status(hw, opmode); 1558 1559 _rtl92s_phy_set_rfhalt(hw); 1560 udelay(100); 1561 } 1562 1563 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta, 1564 u32 *p_intb) 1565 { 1566 struct rtl_priv *rtlpriv = rtl_priv(hw); 1567 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1568 1569 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 1570 rtl_write_dword(rtlpriv, ISR, *p_inta); 1571 1572 *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1]; 1573 rtl_write_dword(rtlpriv, ISR + 4, *p_intb); 1574 } 1575 1576 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw) 1577 { 1578 struct rtl_priv *rtlpriv = rtl_priv(hw); 1579 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1580 u16 bcntime_cfg = 0; 1581 u16 bcn_cw = 6, bcn_ifs = 0xf; 1582 u16 atim_window = 2; 1583 1584 /* ATIM Window (in unit of TU). */ 1585 rtl_write_word(rtlpriv, ATIMWND, atim_window); 1586 1587 /* Beacon interval (in unit of TU). */ 1588 rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval); 1589 1590 /* DrvErlyInt (in unit of TU). (Time to send 1591 * interrupt to notify driver to change 1592 * beacon content) */ 1593 rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4); 1594 1595 /* BcnDMATIM(in unit of us). Indicates the 1596 * time before TBTT to perform beacon queue DMA */ 1597 rtl_write_word(rtlpriv, BCN_DMATIME, 256); 1598 1599 /* Force beacon frame transmission even 1600 * after receiving beacon frame from 1601 * other ad hoc STA */ 1602 rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100); 1603 1604 /* Beacon Time Configuration */ 1605 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1606 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT); 1607 1608 /* TODO: bcn_ifs may required to be changed on ASIC */ 1609 bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS; 1610 1611 /*for beacon changed */ 1612 rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval); 1613 } 1614 1615 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw) 1616 { 1617 struct rtl_priv *rtlpriv = rtl_priv(hw); 1618 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1619 u16 bcn_interval = mac->beacon_interval; 1620 1621 /* Beacon interval (in unit of TU). */ 1622 rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval); 1623 /* 2008.10.24 added by tynli for beacon changed. */ 1624 rtl92s_phy_set_beacon_hwreg(hw, bcn_interval); 1625 } 1626 1627 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw, 1628 u32 add_msr, u32 rm_msr) 1629 { 1630 struct rtl_priv *rtlpriv = rtl_priv(hw); 1631 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1632 1633 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n", 1634 add_msr, rm_msr); 1635 1636 if (add_msr) 1637 rtlpci->irq_mask[0] |= add_msr; 1638 1639 if (rm_msr) 1640 rtlpci->irq_mask[0] &= (~rm_msr); 1641 1642 rtl92se_disable_interrupt(hw); 1643 rtl92se_enable_interrupt(hw); 1644 } 1645 1646 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw) 1647 { 1648 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1649 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1650 u8 efuse_id; 1651 1652 rtlhal->ic_class = IC_INFERIORITY_A; 1653 1654 /* Only retrieving while using EFUSE. */ 1655 if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) && 1656 !rtlefuse->autoload_failflag) { 1657 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET); 1658 1659 if (efuse_id == 0xfe) 1660 rtlhal->ic_class = IC_INFERIORITY_B; 1661 } 1662 } 1663 1664 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw) 1665 { 1666 struct rtl_priv *rtlpriv = rtl_priv(hw); 1667 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1668 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1669 struct device *dev = &rtl_pcipriv(hw)->dev.pdev->dev; 1670 u16 i, usvalue; 1671 u16 eeprom_id; 1672 u8 tempval; 1673 u8 hwinfo[HWSET_MAX_SIZE_92S]; 1674 u8 rf_path, index; 1675 1676 switch (rtlefuse->epromtype) { 1677 case EEPROM_BOOT_EFUSE: 1678 rtl_efuse_shadow_map_update(hw); 1679 break; 1680 1681 case EEPROM_93C46: 1682 pr_err("RTL819X Not boot from eeprom, check it !!\n"); 1683 return; 1684 1685 default: 1686 dev_warn(dev, "no efuse data\n"); 1687 return; 1688 } 1689 1690 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0], 1691 HWSET_MAX_SIZE_92S); 1692 1693 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP", 1694 hwinfo, HWSET_MAX_SIZE_92S); 1695 1696 eeprom_id = *((u16 *)&hwinfo[0]); 1697 if (eeprom_id != RTL8190_EEPROM_ID) { 1698 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1699 "EEPROM ID(%#x) is invalid!!\n", eeprom_id); 1700 rtlefuse->autoload_failflag = true; 1701 } else { 1702 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1703 rtlefuse->autoload_failflag = false; 1704 } 1705 1706 if (rtlefuse->autoload_failflag) 1707 return; 1708 1709 _rtl8192se_get_IC_Inferiority(hw); 1710 1711 /* Read IC Version && Channel Plan */ 1712 /* VID, DID SE 0xA-D */ 1713 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID]; 1714 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID]; 1715 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID]; 1716 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID]; 1717 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION]; 1718 1719 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1720 "EEPROMId = 0x%4x\n", eeprom_id); 1721 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1722 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid); 1723 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1724 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did); 1725 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1726 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid); 1727 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1728 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid); 1729 1730 for (i = 0; i < 6; i += 2) { 1731 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i]; 1732 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; 1733 } 1734 1735 for (i = 0; i < 6; i++) 1736 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]); 1737 1738 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); 1739 1740 /* Get Tx Power Level by Channel */ 1741 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */ 1742 /* 92S suupport RF A & B */ 1743 for (rf_path = 0; rf_path < 2; rf_path++) { 1744 for (i = 0; i < 3; i++) { 1745 /* Read CCK RF A & B Tx power */ 1746 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] = 1747 hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i]; 1748 1749 /* Read OFDM RF A & B Tx power for 1T */ 1750 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1751 hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i]; 1752 1753 /* Read OFDM RF A & B Tx power for 2T */ 1754 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][i] 1755 = hwinfo[EEPROM_TXPOWERBASE + 12 + 1756 rf_path * 3 + i]; 1757 } 1758 } 1759 1760 for (rf_path = 0; rf_path < 2; rf_path++) 1761 for (i = 0; i < 3; i++) 1762 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1763 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", 1764 rf_path, i, 1765 rtlefuse->eeprom_chnlarea_txpwr_cck 1766 [rf_path][i]); 1767 for (rf_path = 0; rf_path < 2; rf_path++) 1768 for (i = 0; i < 3; i++) 1769 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1770 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 1771 rf_path, i, 1772 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1773 [rf_path][i]); 1774 for (rf_path = 0; rf_path < 2; rf_path++) 1775 for (i = 0; i < 3; i++) 1776 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1777 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 1778 rf_path, i, 1779 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1780 [rf_path][i]); 1781 1782 for (rf_path = 0; rf_path < 2; rf_path++) { 1783 1784 /* Assign dedicated channel tx power */ 1785 for (i = 0; i < 14; i++) { 1786 /* channel 1~3 use the same Tx Power Level. */ 1787 if (i < 3) 1788 index = 0; 1789 /* Channel 4-8 */ 1790 else if (i < 8) 1791 index = 1; 1792 /* Channel 9-14 */ 1793 else 1794 index = 2; 1795 1796 /* Record A & B CCK /OFDM - 1T/2T Channel area 1797 * tx power */ 1798 rtlefuse->txpwrlevel_cck[rf_path][i] = 1799 rtlefuse->eeprom_chnlarea_txpwr_cck 1800 [rf_path][index]; 1801 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 1802 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1803 [rf_path][index]; 1804 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 1805 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1806 [rf_path][index]; 1807 } 1808 1809 for (i = 0; i < 14; i++) { 1810 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1811 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", 1812 rf_path, i, 1813 rtlefuse->txpwrlevel_cck[rf_path][i], 1814 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 1815 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 1816 } 1817 } 1818 1819 for (rf_path = 0; rf_path < 2; rf_path++) { 1820 for (i = 0; i < 3; i++) { 1821 /* Read Power diff limit. */ 1822 rtlefuse->eeprom_pwrgroup[rf_path][i] = 1823 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i]; 1824 } 1825 } 1826 1827 for (rf_path = 0; rf_path < 2; rf_path++) { 1828 /* Fill Pwr group */ 1829 for (i = 0; i < 14; i++) { 1830 /* Chanel 1-3 */ 1831 if (i < 3) 1832 index = 0; 1833 /* Channel 4-8 */ 1834 else if (i < 8) 1835 index = 1; 1836 /* Channel 9-13 */ 1837 else 1838 index = 2; 1839 1840 rtlefuse->pwrgroup_ht20[rf_path][i] = 1841 (rtlefuse->eeprom_pwrgroup[rf_path][index] & 1842 0xf); 1843 rtlefuse->pwrgroup_ht40[rf_path][i] = 1844 ((rtlefuse->eeprom_pwrgroup[rf_path][index] & 1845 0xf0) >> 4); 1846 1847 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1848 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", 1849 rf_path, i, 1850 rtlefuse->pwrgroup_ht20[rf_path][i]); 1851 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1852 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", 1853 rf_path, i, 1854 rtlefuse->pwrgroup_ht40[rf_path][i]); 1855 } 1856 } 1857 1858 for (i = 0; i < 14; i++) { 1859 /* Read tx power difference between HT OFDM 20/40 MHZ */ 1860 /* channel 1-3 */ 1861 if (i < 3) 1862 index = 0; 1863 /* Channel 4-8 */ 1864 else if (i < 8) 1865 index = 1; 1866 /* Channel 9-14 */ 1867 else 1868 index = 2; 1869 1870 tempval = hwinfo[EEPROM_TX_PWR_HT20_DIFF + index] & 0xff; 1871 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 1872 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 1873 ((tempval >> 4) & 0xF); 1874 1875 /* Read OFDM<->HT tx power diff */ 1876 /* Channel 1-3 */ 1877 if (i < 3) 1878 index = 0; 1879 /* Channel 4-8 */ 1880 else if (i < 8) 1881 index = 0x11; 1882 /* Channel 9-14 */ 1883 else 1884 index = 1; 1885 1886 tempval = hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index] & 0xff; 1887 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = 1888 (tempval & 0xF); 1889 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 1890 ((tempval >> 4) & 0xF); 1891 1892 tempval = hwinfo[TX_PWR_SAFETY_CHK]; 1893 rtlefuse->txpwr_safetyflag = (tempval & 0x01); 1894 } 1895 1896 rtlefuse->eeprom_regulatory = 0; 1897 if (rtlefuse->eeprom_version >= 2) { 1898 /* BIT(0)~2 */ 1899 if (rtlefuse->eeprom_version >= 4) 1900 rtlefuse->eeprom_regulatory = 1901 (hwinfo[EEPROM_REGULATORY] & 0x7); 1902 else /* BIT(0) */ 1903 rtlefuse->eeprom_regulatory = 1904 (hwinfo[EEPROM_REGULATORY] & 0x1); 1905 } 1906 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1907 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 1908 1909 for (i = 0; i < 14; i++) 1910 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1911 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", 1912 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 1913 for (i = 0; i < 14; i++) 1914 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1915 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", 1916 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 1917 for (i = 0; i < 14; i++) 1918 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1919 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", 1920 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 1921 for (i = 0; i < 14; i++) 1922 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1923 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", 1924 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 1925 1926 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1927 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag); 1928 1929 /* Read RF-indication and Tx Power gain 1930 * index diff of legacy to HT OFDM rate. */ 1931 tempval = hwinfo[EEPROM_RFIND_POWERDIFF] & 0xff; 1932 rtlefuse->eeprom_txpowerdiff = tempval; 1933 rtlefuse->legacy_httxpowerdiff = 1934 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0]; 1935 1936 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1937 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff); 1938 1939 /* Get TSSI value for each path. */ 1940 usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A]; 1941 rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8); 1942 usvalue = hwinfo[EEPROM_TSSI_B]; 1943 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff); 1944 1945 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 1946 rtlefuse->eeprom_tssi[RF90_PATH_A], 1947 rtlefuse->eeprom_tssi[RF90_PATH_B]); 1948 1949 /* Read antenna tx power offset of B/C/D to A from EEPROM */ 1950 /* and read ThermalMeter from EEPROM */ 1951 tempval = hwinfo[EEPROM_THERMALMETER]; 1952 rtlefuse->eeprom_thermalmeter = tempval; 1953 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1954 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1955 1956 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */ 1957 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f); 1958 rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100; 1959 1960 /* Read CrystalCap from EEPROM */ 1961 tempval = hwinfo[EEPROM_CRYSTALCAP] >> 4; 1962 rtlefuse->eeprom_crystalcap = tempval; 1963 /* CrystalCap, BIT(12)~15 */ 1964 rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap; 1965 1966 /* Read IC Version && Channel Plan */ 1967 /* Version ID, Channel plan */ 1968 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN]; 1969 rtlefuse->txpwr_fromeprom = true; 1970 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1971 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan); 1972 1973 /* Read Customer ID or Board Type!!! */ 1974 tempval = hwinfo[EEPROM_BOARDTYPE]; 1975 /* Change RF type definition */ 1976 if (tempval == 0) 1977 rtlphy->rf_type = RF_2T2R; 1978 else if (tempval == 1) 1979 rtlphy->rf_type = RF_1T2R; 1980 else if (tempval == 2) 1981 rtlphy->rf_type = RF_1T2R; 1982 else if (tempval == 3) 1983 rtlphy->rf_type = RF_1T1R; 1984 1985 /* 1T2R but 1SS (1x1 receive combining) */ 1986 rtlefuse->b1x1_recvcombine = false; 1987 if (rtlphy->rf_type == RF_1T2R) { 1988 tempval = rtl_read_byte(rtlpriv, 0x07); 1989 if (!(tempval & BIT(0))) { 1990 rtlefuse->b1x1_recvcombine = true; 1991 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1992 "RF_TYPE=1T2R but only 1SS\n"); 1993 } 1994 } 1995 rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine; 1996 rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMID]; 1997 1998 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n", 1999 rtlefuse->eeprom_oemid); 2000 2001 /* set channel paln to world wide 13 */ 2002 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13; 2003 } 2004 2005 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw) 2006 { 2007 struct rtl_priv *rtlpriv = rtl_priv(hw); 2008 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2009 u8 tmp_u1b = 0; 2010 2011 tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD); 2012 2013 if (tmp_u1b & BIT(4)) { 2014 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 2015 rtlefuse->epromtype = EEPROM_93C46; 2016 } else { 2017 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 2018 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 2019 } 2020 2021 if (tmp_u1b & BIT(5)) { 2022 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 2023 rtlefuse->autoload_failflag = false; 2024 _rtl92se_read_adapter_info(hw); 2025 } else { 2026 pr_err("Autoload ERR!!\n"); 2027 rtlefuse->autoload_failflag = true; 2028 } 2029 } 2030 2031 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw, 2032 struct ieee80211_sta *sta) 2033 { 2034 struct rtl_priv *rtlpriv = rtl_priv(hw); 2035 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2036 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2037 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2038 u32 ratr_value; 2039 u8 ratr_index = 0; 2040 u8 nmode = mac->ht_enable; 2041 u8 mimo_ps = IEEE80211_SMPS_OFF; 2042 u16 shortgi_rate = 0; 2043 u32 tmp_ratr_value = 0; 2044 u8 curtxbw_40mhz = mac->bw_40; 2045 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2046 1 : 0; 2047 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2048 1 : 0; 2049 enum wireless_mode wirelessmode = mac->mode; 2050 2051 if (rtlhal->current_bandtype == BAND_ON_5G) 2052 ratr_value = sta->supp_rates[1] << 4; 2053 else 2054 ratr_value = sta->supp_rates[0]; 2055 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2056 ratr_value = 0xfff; 2057 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 2058 sta->ht_cap.mcs.rx_mask[0] << 12); 2059 switch (wirelessmode) { 2060 case WIRELESS_MODE_B: 2061 ratr_value &= 0x0000000D; 2062 break; 2063 case WIRELESS_MODE_G: 2064 ratr_value &= 0x00000FF5; 2065 break; 2066 case WIRELESS_MODE_N_24G: 2067 case WIRELESS_MODE_N_5G: 2068 nmode = 1; 2069 if (mimo_ps == IEEE80211_SMPS_STATIC) { 2070 ratr_value &= 0x0007F005; 2071 } else { 2072 u32 ratr_mask; 2073 2074 if (get_rf_type(rtlphy) == RF_1T2R || 2075 get_rf_type(rtlphy) == RF_1T1R) { 2076 if (curtxbw_40mhz) 2077 ratr_mask = 0x000ff015; 2078 else 2079 ratr_mask = 0x000ff005; 2080 } else { 2081 if (curtxbw_40mhz) 2082 ratr_mask = 0x0f0ff015; 2083 else 2084 ratr_mask = 0x0f0ff005; 2085 } 2086 2087 ratr_value &= ratr_mask; 2088 } 2089 break; 2090 default: 2091 if (rtlphy->rf_type == RF_1T2R) 2092 ratr_value &= 0x000ff0ff; 2093 else 2094 ratr_value &= 0x0f0ff0ff; 2095 2096 break; 2097 } 2098 2099 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT) 2100 ratr_value &= 0x0FFFFFFF; 2101 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT) 2102 ratr_value &= 0x0FFFFFF0; 2103 2104 if (nmode && ((curtxbw_40mhz && 2105 curshortgi_40mhz) || (!curtxbw_40mhz && 2106 curshortgi_20mhz))) { 2107 2108 ratr_value |= 0x10000000; 2109 tmp_ratr_value = (ratr_value >> 12); 2110 2111 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 2112 if ((1 << shortgi_rate) & tmp_ratr_value) 2113 break; 2114 } 2115 2116 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 2117 (shortgi_rate << 4) | (shortgi_rate); 2118 2119 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate); 2120 } 2121 2122 rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value); 2123 if (ratr_value & 0xfffff000) 2124 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N); 2125 else 2126 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG); 2127 2128 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", 2129 rtl_read_dword(rtlpriv, ARFR0)); 2130 } 2131 2132 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw, 2133 struct ieee80211_sta *sta, 2134 u8 rssi_level) 2135 { 2136 struct rtl_priv *rtlpriv = rtl_priv(hw); 2137 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2138 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2139 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2140 struct rtl_sta_info *sta_entry = NULL; 2141 u32 ratr_bitmap; 2142 u8 ratr_index = 0; 2143 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; 2144 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2145 1 : 0; 2146 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2147 1 : 0; 2148 enum wireless_mode wirelessmode = 0; 2149 bool shortgi = false; 2150 u32 ratr_value = 0; 2151 u8 shortgi_rate = 0; 2152 u32 mask = 0; 2153 u32 band = 0; 2154 bool bmulticast = false; 2155 u8 macid = 0; 2156 u8 mimo_ps = IEEE80211_SMPS_OFF; 2157 2158 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 2159 wirelessmode = sta_entry->wireless_mode; 2160 if (mac->opmode == NL80211_IFTYPE_STATION) 2161 curtxbw_40mhz = mac->bw_40; 2162 else if (mac->opmode == NL80211_IFTYPE_AP || 2163 mac->opmode == NL80211_IFTYPE_ADHOC) 2164 macid = sta->aid + 1; 2165 2166 if (rtlhal->current_bandtype == BAND_ON_5G) 2167 ratr_bitmap = sta->supp_rates[1] << 4; 2168 else 2169 ratr_bitmap = sta->supp_rates[0]; 2170 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2171 ratr_bitmap = 0xfff; 2172 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 2173 sta->ht_cap.mcs.rx_mask[0] << 12); 2174 switch (wirelessmode) { 2175 case WIRELESS_MODE_B: 2176 band |= WIRELESS_11B; 2177 ratr_index = RATR_INX_WIRELESS_B; 2178 if (ratr_bitmap & 0x0000000c) 2179 ratr_bitmap &= 0x0000000d; 2180 else 2181 ratr_bitmap &= 0x0000000f; 2182 break; 2183 case WIRELESS_MODE_G: 2184 band |= (WIRELESS_11G | WIRELESS_11B); 2185 ratr_index = RATR_INX_WIRELESS_GB; 2186 2187 if (rssi_level == 1) 2188 ratr_bitmap &= 0x00000f00; 2189 else if (rssi_level == 2) 2190 ratr_bitmap &= 0x00000ff0; 2191 else 2192 ratr_bitmap &= 0x00000ff5; 2193 break; 2194 case WIRELESS_MODE_A: 2195 band |= WIRELESS_11A; 2196 ratr_index = RATR_INX_WIRELESS_A; 2197 ratr_bitmap &= 0x00000ff0; 2198 break; 2199 case WIRELESS_MODE_N_24G: 2200 case WIRELESS_MODE_N_5G: 2201 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B); 2202 ratr_index = RATR_INX_WIRELESS_NGB; 2203 2204 if (mimo_ps == IEEE80211_SMPS_STATIC) { 2205 if (rssi_level == 1) 2206 ratr_bitmap &= 0x00070000; 2207 else if (rssi_level == 2) 2208 ratr_bitmap &= 0x0007f000; 2209 else 2210 ratr_bitmap &= 0x0007f005; 2211 } else { 2212 if (rtlphy->rf_type == RF_1T2R || 2213 rtlphy->rf_type == RF_1T1R) { 2214 if (rssi_level == 1) { 2215 ratr_bitmap &= 0x000f0000; 2216 } else if (rssi_level == 3) { 2217 ratr_bitmap &= 0x000fc000; 2218 } else if (rssi_level == 5) { 2219 ratr_bitmap &= 0x000ff000; 2220 } else { 2221 if (curtxbw_40mhz) 2222 ratr_bitmap &= 0x000ff015; 2223 else 2224 ratr_bitmap &= 0x000ff005; 2225 } 2226 } else { 2227 if (rssi_level == 1) { 2228 ratr_bitmap &= 0x0f8f0000; 2229 } else if (rssi_level == 3) { 2230 ratr_bitmap &= 0x0f8fc000; 2231 } else if (rssi_level == 5) { 2232 ratr_bitmap &= 0x0f8ff000; 2233 } else { 2234 if (curtxbw_40mhz) 2235 ratr_bitmap &= 0x0f8ff015; 2236 else 2237 ratr_bitmap &= 0x0f8ff005; 2238 } 2239 } 2240 } 2241 2242 if ((curtxbw_40mhz && curshortgi_40mhz) || 2243 (!curtxbw_40mhz && curshortgi_20mhz)) { 2244 if (macid == 0) 2245 shortgi = true; 2246 else if (macid == 1) 2247 shortgi = false; 2248 } 2249 break; 2250 default: 2251 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B); 2252 ratr_index = RATR_INX_WIRELESS_NGB; 2253 2254 if (rtlphy->rf_type == RF_1T2R) 2255 ratr_bitmap &= 0x000ff0ff; 2256 else 2257 ratr_bitmap &= 0x0f8ff0ff; 2258 break; 2259 } 2260 sta_entry->ratr_index = ratr_index; 2261 2262 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT) 2263 ratr_bitmap &= 0x0FFFFFFF; 2264 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT) 2265 ratr_bitmap &= 0x0FFFFFF0; 2266 2267 if (shortgi) { 2268 ratr_bitmap |= 0x10000000; 2269 /* Get MAX MCS available. */ 2270 ratr_value = (ratr_bitmap >> 12); 2271 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 2272 if ((1 << shortgi_rate) & ratr_value) 2273 break; 2274 } 2275 2276 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 2277 (shortgi_rate << 4) | (shortgi_rate); 2278 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate); 2279 } 2280 2281 mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf); 2282 2283 RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n", 2284 mask, ratr_bitmap); 2285 rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap); 2286 rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8))); 2287 2288 if (macid != 0) 2289 sta_entry->ratr_index = ratr_index; 2290 } 2291 2292 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw, 2293 struct ieee80211_sta *sta, u8 rssi_level) 2294 { 2295 struct rtl_priv *rtlpriv = rtl_priv(hw); 2296 2297 if (rtlpriv->dm.useramask) 2298 rtl92se_update_hal_rate_mask(hw, sta, rssi_level); 2299 else 2300 rtl92se_update_hal_rate_table(hw, sta); 2301 } 2302 2303 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw) 2304 { 2305 struct rtl_priv *rtlpriv = rtl_priv(hw); 2306 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2307 u16 sifs_timer; 2308 2309 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2310 &mac->slot_time); 2311 sifs_timer = 0x0e0e; 2312 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2313 2314 } 2315 2316 /* this ifunction is for RFKILL, it's different with windows, 2317 * because UI will disable wireless when GPIO Radio Off. 2318 * And here we not check or Disable/Enable ASPM like windows*/ 2319 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2320 { 2321 struct rtl_priv *rtlpriv = rtl_priv(hw); 2322 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2323 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2324 enum rf_pwrstate rfpwr_toset /*, cur_rfstate */; 2325 unsigned long flag = 0; 2326 bool actuallyset = false; 2327 bool turnonbypowerdomain = false; 2328 2329 /* just 8191se can check gpio before firstup, 92c/92d have fixed it */ 2330 if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter)) 2331 return false; 2332 2333 if (ppsc->swrf_processing) 2334 return false; 2335 2336 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2337 if (ppsc->rfchange_inprogress) { 2338 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2339 return false; 2340 } else { 2341 ppsc->rfchange_inprogress = true; 2342 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2343 } 2344 2345 /* cur_rfstate = ppsc->rfpwr_state;*/ 2346 2347 /* because after _rtl92s_phy_set_rfhalt, all power 2348 * closed, so we must open some power for GPIO check, 2349 * or we will always check GPIO RFOFF here, 2350 * And we should close power after GPIO check */ 2351 if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 2352 _rtl92se_power_domain_init(hw); 2353 turnonbypowerdomain = true; 2354 } 2355 2356 rfpwr_toset = _rtl92se_rf_onoff_detect(hw); 2357 2358 if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) { 2359 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2360 "RFKILL-HW Radio ON, RF ON\n"); 2361 2362 rfpwr_toset = ERFON; 2363 ppsc->hwradiooff = false; 2364 actuallyset = true; 2365 } else if ((!ppsc->hwradiooff) && (rfpwr_toset == ERFOFF)) { 2366 RT_TRACE(rtlpriv, COMP_RF, 2367 DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n"); 2368 2369 rfpwr_toset = ERFOFF; 2370 ppsc->hwradiooff = true; 2371 actuallyset = true; 2372 } 2373 2374 if (actuallyset) { 2375 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2376 ppsc->rfchange_inprogress = false; 2377 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2378 2379 /* this not include ifconfig wlan0 down case */ 2380 /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */ 2381 } else { 2382 /* because power_domain_init may be happen when 2383 * _rtl92s_phy_set_rfhalt, this will open some powers 2384 * and cause current increasing about 40 mA for ips, 2385 * rfoff and ifconfig down, so we set 2386 * _rtl92s_phy_set_rfhalt again here */ 2387 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC && 2388 turnonbypowerdomain) { 2389 _rtl92s_phy_set_rfhalt(hw); 2390 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2391 } 2392 2393 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2394 ppsc->rfchange_inprogress = false; 2395 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2396 } 2397 2398 *valid = 1; 2399 return !ppsc->hwradiooff; 2400 2401 } 2402 2403 /* Is_wepkey just used for WEP used as group & pairwise key 2404 * if pairwise is AES ang group is WEP Is_wepkey == false.*/ 2405 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr, 2406 bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all) 2407 { 2408 struct rtl_priv *rtlpriv = rtl_priv(hw); 2409 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2410 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2411 u8 *macaddr = p_macaddr; 2412 2413 u32 entry_id = 0; 2414 bool is_pairwise = false; 2415 2416 static u8 cam_const_addr[4][6] = { 2417 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2418 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2419 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2420 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2421 }; 2422 static u8 cam_const_broad[] = { 2423 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2424 }; 2425 2426 if (clear_all) { 2427 u8 idx = 0; 2428 u8 cam_offset = 0; 2429 u8 clear_number = 5; 2430 2431 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2432 2433 for (idx = 0; idx < clear_number; idx++) { 2434 rtl_cam_mark_invalid(hw, cam_offset + idx); 2435 rtl_cam_empty_entry(hw, cam_offset + idx); 2436 2437 if (idx < 5) { 2438 memset(rtlpriv->sec.key_buf[idx], 0, 2439 MAX_KEY_LEN); 2440 rtlpriv->sec.key_len[idx] = 0; 2441 } 2442 } 2443 2444 } else { 2445 switch (enc_algo) { 2446 case WEP40_ENCRYPTION: 2447 enc_algo = CAM_WEP40; 2448 break; 2449 case WEP104_ENCRYPTION: 2450 enc_algo = CAM_WEP104; 2451 break; 2452 case TKIP_ENCRYPTION: 2453 enc_algo = CAM_TKIP; 2454 break; 2455 case AESCCMP_ENCRYPTION: 2456 enc_algo = CAM_AES; 2457 break; 2458 default: 2459 pr_err("switch case %#x not processed\n", 2460 enc_algo); 2461 enc_algo = CAM_TKIP; 2462 break; 2463 } 2464 2465 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2466 macaddr = cam_const_addr[key_index]; 2467 entry_id = key_index; 2468 } else { 2469 if (is_group) { 2470 macaddr = cam_const_broad; 2471 entry_id = key_index; 2472 } else { 2473 if (mac->opmode == NL80211_IFTYPE_AP) { 2474 entry_id = rtl_cam_get_free_entry(hw, 2475 p_macaddr); 2476 if (entry_id >= TOTAL_CAM_ENTRY) { 2477 pr_err("Can not find free hw security cam entry\n"); 2478 return; 2479 } 2480 } else { 2481 entry_id = CAM_PAIRWISE_KEY_POSITION; 2482 } 2483 2484 key_index = PAIRWISE_KEYIDX; 2485 is_pairwise = true; 2486 } 2487 } 2488 2489 if (rtlpriv->sec.key_len[key_index] == 0) { 2490 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2491 "delete one entry, entry_id is %d\n", 2492 entry_id); 2493 if (mac->opmode == NL80211_IFTYPE_AP) 2494 rtl_cam_del_entry(hw, p_macaddr); 2495 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2496 } else { 2497 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2498 "add one entry\n"); 2499 if (is_pairwise) { 2500 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2501 "set Pairwise key\n"); 2502 2503 rtl_cam_add_one_entry(hw, macaddr, key_index, 2504 entry_id, enc_algo, 2505 CAM_CONFIG_NO_USEDK, 2506 rtlpriv->sec.key_buf[key_index]); 2507 } else { 2508 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2509 "set group key\n"); 2510 2511 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2512 rtl_cam_add_one_entry(hw, 2513 rtlefuse->dev_addr, 2514 PAIRWISE_KEYIDX, 2515 CAM_PAIRWISE_KEY_POSITION, 2516 enc_algo, CAM_CONFIG_NO_USEDK, 2517 rtlpriv->sec.key_buf[entry_id]); 2518 } 2519 2520 rtl_cam_add_one_entry(hw, macaddr, key_index, 2521 entry_id, enc_algo, 2522 CAM_CONFIG_NO_USEDK, 2523 rtlpriv->sec.key_buf[entry_id]); 2524 } 2525 2526 } 2527 } 2528 } 2529 2530 void rtl92se_suspend(struct ieee80211_hw *hw) 2531 { 2532 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2533 2534 rtlpci->up_first_time = true; 2535 } 2536 2537 void rtl92se_resume(struct ieee80211_hw *hw) 2538 { 2539 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2540 u32 val; 2541 2542 pci_read_config_dword(rtlpci->pdev, 0x40, &val); 2543 if ((val & 0x0000ff00) != 0) 2544 pci_write_config_dword(rtlpci->pdev, 0x40, 2545 val & 0xffff00ff); 2546 } 2547