1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../regd.h" 30 #include "../cam.h" 31 #include "../ps.h" 32 #include "../pci.h" 33 #include "reg.h" 34 #include "def.h" 35 #include "phy.h" 36 #include "dm.h" 37 #include "fw.h" 38 #include "led.h" 39 #include "hw.h" 40 41 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 42 { 43 struct rtl_priv *rtlpriv = rtl_priv(hw); 44 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 45 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 46 47 switch (variable) { 48 case HW_VAR_RCR: { 49 *((u32 *) (val)) = rtlpci->receive_config; 50 break; 51 } 52 case HW_VAR_RF_STATE: { 53 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 54 break; 55 } 56 case HW_VAR_FW_PSMODE_STATUS: { 57 *((bool *) (val)) = ppsc->fw_current_inpsmode; 58 break; 59 } 60 case HW_VAR_CORRECT_TSF: { 61 u64 tsf; 62 u32 *ptsf_low = (u32 *)&tsf; 63 u32 *ptsf_high = ((u32 *)&tsf) + 1; 64 65 *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4)); 66 *ptsf_low = rtl_read_dword(rtlpriv, TSFR); 67 68 *((u64 *) (val)) = tsf; 69 70 break; 71 } 72 case HW_VAR_MRC: { 73 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch; 74 break; 75 } 76 case HAL_DEF_WOWLAN: 77 break; 78 default: 79 pr_err("switch case %#x not processed\n", variable); 80 break; 81 } 82 } 83 84 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 85 { 86 struct rtl_priv *rtlpriv = rtl_priv(hw); 87 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 88 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 89 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 90 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 91 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 92 93 switch (variable) { 94 case HW_VAR_ETHER_ADDR:{ 95 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]); 96 rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]); 97 break; 98 } 99 case HW_VAR_BASIC_RATE:{ 100 u16 rate_cfg = ((u16 *) val)[0]; 101 u8 rate_index = 0; 102 103 if (rtlhal->version == VERSION_8192S_ACUT) 104 rate_cfg = rate_cfg & 0x150; 105 else 106 rate_cfg = rate_cfg & 0x15f; 107 108 rate_cfg |= 0x01; 109 110 rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff); 111 rtl_write_byte(rtlpriv, RRSR + 1, 112 (rate_cfg >> 8) & 0xff); 113 114 while (rate_cfg > 0x1) { 115 rate_cfg = (rate_cfg >> 1); 116 rate_index++; 117 } 118 rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index); 119 120 break; 121 } 122 case HW_VAR_BSSID:{ 123 rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]); 124 rtl_write_word(rtlpriv, BSSIDR + 4, 125 ((u16 *)(val + 4))[0]); 126 break; 127 } 128 case HW_VAR_SIFS:{ 129 rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]); 130 rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]); 131 break; 132 } 133 case HW_VAR_SLOT_TIME:{ 134 u8 e_aci; 135 136 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 137 "HW_VAR_SLOT_TIME %x\n", val[0]); 138 139 rtl_write_byte(rtlpriv, SLOT_TIME, val[0]); 140 141 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 142 rtlpriv->cfg->ops->set_hw_reg(hw, 143 HW_VAR_AC_PARAM, 144 (&e_aci)); 145 } 146 break; 147 } 148 case HW_VAR_ACK_PREAMBLE:{ 149 u8 reg_tmp; 150 u8 short_preamble = (bool) (*val); 151 reg_tmp = (mac->cur_40_prime_sc) << 5; 152 if (short_preamble) 153 reg_tmp |= 0x80; 154 155 rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp); 156 break; 157 } 158 case HW_VAR_AMPDU_MIN_SPACE:{ 159 u8 min_spacing_to_set; 160 u8 sec_min_space; 161 162 min_spacing_to_set = *val; 163 if (min_spacing_to_set <= 7) { 164 if (rtlpriv->sec.pairwise_enc_algorithm == 165 NO_ENCRYPTION) 166 sec_min_space = 0; 167 else 168 sec_min_space = 1; 169 170 if (min_spacing_to_set < sec_min_space) 171 min_spacing_to_set = sec_min_space; 172 if (min_spacing_to_set > 5) 173 min_spacing_to_set = 5; 174 175 mac->min_space_cfg = 176 ((mac->min_space_cfg & 0xf8) | 177 min_spacing_to_set); 178 179 *val = min_spacing_to_set; 180 181 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 182 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 183 mac->min_space_cfg); 184 185 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 186 mac->min_space_cfg); 187 } 188 break; 189 } 190 case HW_VAR_SHORTGI_DENSITY:{ 191 u8 density_to_set; 192 193 density_to_set = *val; 194 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg; 195 mac->min_space_cfg |= (density_to_set << 3); 196 197 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 198 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 199 mac->min_space_cfg); 200 201 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 202 mac->min_space_cfg); 203 204 break; 205 } 206 case HW_VAR_AMPDU_FACTOR:{ 207 u8 factor_toset; 208 u8 regtoset; 209 u8 factorlevel[18] = { 210 2, 4, 4, 7, 7, 13, 13, 211 13, 2, 7, 7, 13, 13, 212 15, 15, 15, 15, 0}; 213 u8 index = 0; 214 215 factor_toset = *val; 216 if (factor_toset <= 3) { 217 factor_toset = (1 << (factor_toset + 2)); 218 if (factor_toset > 0xf) 219 factor_toset = 0xf; 220 221 for (index = 0; index < 17; index++) { 222 if (factorlevel[index] > factor_toset) 223 factorlevel[index] = 224 factor_toset; 225 } 226 227 for (index = 0; index < 8; index++) { 228 regtoset = ((factorlevel[index * 2]) | 229 (factorlevel[index * 230 2 + 1] << 4)); 231 rtl_write_byte(rtlpriv, 232 AGGLEN_LMT_L + index, 233 regtoset); 234 } 235 236 regtoset = ((factorlevel[16]) | 237 (factorlevel[17] << 4)); 238 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset); 239 240 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 241 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 242 factor_toset); 243 } 244 break; 245 } 246 case HW_VAR_AC_PARAM:{ 247 u8 e_aci = *val; 248 rtl92s_dm_init_edca_turbo(hw); 249 250 if (rtlpci->acm_method != EACMWAY2_SW) 251 rtlpriv->cfg->ops->set_hw_reg(hw, 252 HW_VAR_ACM_CTRL, 253 &e_aci); 254 break; 255 } 256 case HW_VAR_ACM_CTRL:{ 257 u8 e_aci = *val; 258 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&( 259 mac->ac[0].aifs)); 260 u8 acm = p_aci_aifsn->f.acm; 261 u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl); 262 263 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 264 0x0 : 0x1); 265 266 if (acm) { 267 switch (e_aci) { 268 case AC0_BE: 269 acm_ctrl |= AcmHw_BeqEn; 270 break; 271 case AC2_VI: 272 acm_ctrl |= AcmHw_ViqEn; 273 break; 274 case AC3_VO: 275 acm_ctrl |= AcmHw_VoqEn; 276 break; 277 default: 278 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 279 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 280 acm); 281 break; 282 } 283 } else { 284 switch (e_aci) { 285 case AC0_BE: 286 acm_ctrl &= (~AcmHw_BeqEn); 287 break; 288 case AC2_VI: 289 acm_ctrl &= (~AcmHw_ViqEn); 290 break; 291 case AC3_VO: 292 acm_ctrl &= (~AcmHw_VoqEn); 293 break; 294 default: 295 pr_err("switch case %#x not processed\n", 296 e_aci); 297 break; 298 } 299 } 300 301 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 302 "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl); 303 rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl); 304 break; 305 } 306 case HW_VAR_RCR:{ 307 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]); 308 rtlpci->receive_config = ((u32 *) (val))[0]; 309 break; 310 } 311 case HW_VAR_RETRY_LIMIT:{ 312 u8 retry_limit = val[0]; 313 314 rtl_write_word(rtlpriv, RETRY_LIMIT, 315 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 316 retry_limit << RETRY_LIMIT_LONG_SHIFT); 317 break; 318 } 319 case HW_VAR_DUAL_TSF_RST: { 320 break; 321 } 322 case HW_VAR_EFUSE_BYTES: { 323 rtlefuse->efuse_usedbytes = *((u16 *) val); 324 break; 325 } 326 case HW_VAR_EFUSE_USAGE: { 327 rtlefuse->efuse_usedpercentage = *val; 328 break; 329 } 330 case HW_VAR_IO_CMD: { 331 break; 332 } 333 case HW_VAR_WPA_CONFIG: { 334 rtl_write_byte(rtlpriv, REG_SECR, *val); 335 break; 336 } 337 case HW_VAR_SET_RPWM:{ 338 break; 339 } 340 case HW_VAR_H2C_FW_PWRMODE:{ 341 break; 342 } 343 case HW_VAR_FW_PSMODE_STATUS: { 344 ppsc->fw_current_inpsmode = *((bool *) val); 345 break; 346 } 347 case HW_VAR_H2C_FW_JOINBSSRPT:{ 348 break; 349 } 350 case HW_VAR_AID:{ 351 break; 352 } 353 case HW_VAR_CORRECT_TSF:{ 354 break; 355 } 356 case HW_VAR_MRC: { 357 bool bmrc_toset = *((bool *)val); 358 u8 u1bdata = 0; 359 360 if (bmrc_toset) { 361 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, 362 MASKBYTE0, 0x33); 363 u1bdata = (u8)rtl_get_bbreg(hw, 364 ROFDM1_TRXPATHENABLE, 365 MASKBYTE0); 366 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, 367 MASKBYTE0, 368 ((u1bdata & 0xf0) | 0x03)); 369 u1bdata = (u8)rtl_get_bbreg(hw, 370 ROFDM0_TRXPATHENABLE, 371 MASKBYTE1); 372 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, 373 MASKBYTE1, 374 (u1bdata | 0x04)); 375 376 /* Update current settings. */ 377 rtlpriv->dm.current_mrc_switch = bmrc_toset; 378 } else { 379 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, 380 MASKBYTE0, 0x13); 381 u1bdata = (u8)rtl_get_bbreg(hw, 382 ROFDM1_TRXPATHENABLE, 383 MASKBYTE0); 384 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, 385 MASKBYTE0, 386 ((u1bdata & 0xf0) | 0x01)); 387 u1bdata = (u8)rtl_get_bbreg(hw, 388 ROFDM0_TRXPATHENABLE, 389 MASKBYTE1); 390 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, 391 MASKBYTE1, (u1bdata & 0xfb)); 392 393 /* Update current settings. */ 394 rtlpriv->dm.current_mrc_switch = bmrc_toset; 395 } 396 397 break; 398 } 399 case HW_VAR_FW_LPS_ACTION: { 400 bool enter_fwlps = *((bool *)val); 401 u8 rpwm_val, fw_pwrmode; 402 bool fw_current_inps; 403 404 if (enter_fwlps) { 405 rpwm_val = 0x02; /* RF off */ 406 fw_current_inps = true; 407 rtlpriv->cfg->ops->set_hw_reg(hw, 408 HW_VAR_FW_PSMODE_STATUS, 409 (u8 *)(&fw_current_inps)); 410 rtlpriv->cfg->ops->set_hw_reg(hw, 411 HW_VAR_H2C_FW_PWRMODE, 412 &ppsc->fwctrl_psmode); 413 414 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 415 &rpwm_val); 416 } else { 417 rpwm_val = 0x0C; /* RF on */ 418 fw_pwrmode = FW_PS_ACTIVE_MODE; 419 fw_current_inps = false; 420 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 421 &rpwm_val); 422 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 423 &fw_pwrmode); 424 425 rtlpriv->cfg->ops->set_hw_reg(hw, 426 HW_VAR_FW_PSMODE_STATUS, 427 (u8 *)(&fw_current_inps)); 428 } 429 break; } 430 default: 431 pr_err("switch case %#x not processed\n", variable); 432 break; 433 } 434 435 } 436 437 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw) 438 { 439 struct rtl_priv *rtlpriv = rtl_priv(hw); 440 u8 sec_reg_value = 0x0; 441 442 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 443 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 444 rtlpriv->sec.pairwise_enc_algorithm, 445 rtlpriv->sec.group_enc_algorithm); 446 447 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 448 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 449 "not open hw encryption\n"); 450 return; 451 } 452 453 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE; 454 455 if (rtlpriv->sec.use_defaultkey) { 456 sec_reg_value |= SCR_TXUSEDK; 457 sec_reg_value |= SCR_RXUSEDK; 458 } 459 460 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n", 461 sec_reg_value); 462 463 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 464 465 } 466 467 static u8 _rtl92se_halset_sysclk(struct ieee80211_hw *hw, u8 data) 468 { 469 struct rtl_priv *rtlpriv = rtl_priv(hw); 470 u8 waitcount = 100; 471 bool bresult = false; 472 u8 tmpvalue; 473 474 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data); 475 476 /* Wait the MAC synchronized. */ 477 udelay(400); 478 479 /* Check if it is set ready. */ 480 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1); 481 bresult = ((tmpvalue & BIT(7)) == (data & BIT(7))); 482 483 if ((data & (BIT(6) | BIT(7))) == false) { 484 waitcount = 100; 485 tmpvalue = 0; 486 487 while (1) { 488 waitcount--; 489 490 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1); 491 if ((tmpvalue & BIT(6))) 492 break; 493 494 pr_err("wait for BIT(6) return value %x\n", tmpvalue); 495 if (waitcount == 0) 496 break; 497 498 udelay(10); 499 } 500 501 if (waitcount == 0) 502 bresult = false; 503 else 504 bresult = true; 505 } 506 507 return bresult; 508 } 509 510 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw) 511 { 512 struct rtl_priv *rtlpriv = rtl_priv(hw); 513 u8 u1tmp; 514 515 /* The following config GPIO function */ 516 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO)); 517 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL); 518 519 /* config GPIO3 to input */ 520 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK; 521 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp); 522 523 } 524 525 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw) 526 { 527 struct rtl_priv *rtlpriv = rtl_priv(hw); 528 u8 u1tmp; 529 u8 retval = ERFON; 530 531 /* The following config GPIO function */ 532 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO)); 533 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL); 534 535 /* config GPIO3 to input */ 536 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK; 537 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp); 538 539 /* On some of the platform, driver cannot read correct 540 * value without delay between Write_GPIO_SEL and Read_GPIO_IN */ 541 mdelay(10); 542 543 /* check GPIO3 */ 544 u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE); 545 retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF; 546 547 return retval; 548 } 549 550 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw) 551 { 552 struct rtl_priv *rtlpriv = rtl_priv(hw); 553 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 554 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 555 556 u8 i; 557 u8 tmpu1b; 558 u16 tmpu2b; 559 u8 pollingcnt = 20; 560 561 if (rtlpci->first_init) { 562 /* Reset PCIE Digital */ 563 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 564 tmpu1b &= 0xFE; 565 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b); 566 udelay(1); 567 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0)); 568 } 569 570 /* Switch to SW IO control */ 571 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 572 if (tmpu1b & BIT(7)) { 573 tmpu1b &= ~(BIT(6) | BIT(7)); 574 575 /* Set failed, return to prevent hang. */ 576 if (!_rtl92se_halset_sysclk(hw, tmpu1b)) 577 return; 578 } 579 580 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0); 581 udelay(50); 582 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34); 583 udelay(50); 584 585 /* Clear FW RPWM for FW control LPS.*/ 586 rtl_write_byte(rtlpriv, RPWM, 0x0); 587 588 /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */ 589 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 590 tmpu1b &= 0x73; 591 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b); 592 /* wait for BIT 10/11/15 to pull high automatically!! */ 593 mdelay(1); 594 595 rtl_write_byte(rtlpriv, CMDR, 0); 596 rtl_write_byte(rtlpriv, TCR, 0); 597 598 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */ 599 tmpu1b = rtl_read_byte(rtlpriv, 0x562); 600 tmpu1b |= 0x08; 601 rtl_write_byte(rtlpriv, 0x562, tmpu1b); 602 tmpu1b &= ~(BIT(3)); 603 rtl_write_byte(rtlpriv, 0x562, tmpu1b); 604 605 /* Enable AFE clock source */ 606 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL); 607 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01)); 608 /* Delay 1.5ms */ 609 mdelay(2); 610 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1); 611 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb)); 612 613 /* Enable AFE Macro Block's Bandgap */ 614 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC); 615 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0))); 616 mdelay(1); 617 618 /* Enable AFE Mbias */ 619 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC); 620 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02)); 621 mdelay(1); 622 623 /* Enable LDOA15 block */ 624 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL); 625 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0))); 626 627 /* Set Digital Vdd to Retention isolation Path. */ 628 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); 629 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11))); 630 631 /* For warm reboot NIC disappera bug. */ 632 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 633 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13))); 634 635 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68); 636 637 /* Enable AFE PLL Macro Block */ 638 /* We need to delay 100u before enabling PLL. */ 639 udelay(200); 640 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL); 641 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); 642 643 /* for divider reset */ 644 udelay(100); 645 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | 646 BIT(4) | BIT(6))); 647 udelay(10); 648 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); 649 udelay(10); 650 651 /* Enable MAC 80MHZ clock */ 652 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1); 653 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0))); 654 mdelay(1); 655 656 /* Release isolation AFE PLL & MD */ 657 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6); 658 659 /* Enable MAC clock */ 660 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR); 661 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11))); 662 663 /* Enable Core digital and enable IOREG R/W */ 664 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 665 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11))); 666 667 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 668 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7))); 669 670 /* enable REG_EN */ 671 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15))); 672 673 /* Switch the control path. */ 674 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR); 675 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2)))); 676 677 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 678 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6))); 679 if (!_rtl92se_halset_sysclk(hw, tmpu1b)) 680 return; /* Set failed, return to prevent hang. */ 681 682 rtl_write_word(rtlpriv, CMDR, 0x07FC); 683 684 /* MH We must enable the section of code to prevent load IMEM fail. */ 685 /* Load MAC register from WMAc temporarily We simulate macreg. */ 686 /* txt HW will provide MAC txt later */ 687 rtl_write_byte(rtlpriv, 0x6, 0x30); 688 rtl_write_byte(rtlpriv, 0x49, 0xf0); 689 690 rtl_write_byte(rtlpriv, 0x4b, 0x81); 691 692 rtl_write_byte(rtlpriv, 0xb5, 0x21); 693 694 rtl_write_byte(rtlpriv, 0xdc, 0xff); 695 rtl_write_byte(rtlpriv, 0xdd, 0xff); 696 rtl_write_byte(rtlpriv, 0xde, 0xff); 697 rtl_write_byte(rtlpriv, 0xdf, 0xff); 698 699 rtl_write_byte(rtlpriv, 0x11a, 0x00); 700 rtl_write_byte(rtlpriv, 0x11b, 0x00); 701 702 for (i = 0; i < 32; i++) 703 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b); 704 705 rtl_write_byte(rtlpriv, 0x236, 0xff); 706 707 rtl_write_byte(rtlpriv, 0x503, 0x22); 708 709 if (ppsc->support_aspm && !ppsc->support_backdoor) 710 rtl_write_byte(rtlpriv, 0x560, 0x40); 711 else 712 rtl_write_byte(rtlpriv, 0x560, 0x00); 713 714 rtl_write_byte(rtlpriv, DBG_PORT, 0x91); 715 716 /* Set RX Desc Address */ 717 rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma); 718 rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma); 719 720 /* Set TX Desc Address */ 721 rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma); 722 rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma); 723 rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma); 724 rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma); 725 rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma); 726 rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma); 727 rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma); 728 rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma); 729 rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma); 730 731 rtl_write_word(rtlpriv, CMDR, 0x37FC); 732 733 /* To make sure that TxDMA can ready to download FW. */ 734 /* We should reset TxDMA if IMEM RPT was not ready. */ 735 do { 736 tmpu1b = rtl_read_byte(rtlpriv, TCR); 737 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE) 738 break; 739 740 udelay(5); 741 } while (pollingcnt--); 742 743 if (pollingcnt <= 0) { 744 pr_err("Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n", 745 tmpu1b); 746 tmpu1b = rtl_read_byte(rtlpriv, CMDR); 747 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN)); 748 udelay(2); 749 /* Reset TxDMA */ 750 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN); 751 } 752 753 /* After MACIO reset,we must refresh LED state. */ 754 if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) || 755 (ppsc->rfoff_reason == 0)) { 756 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0; 757 enum rf_pwrstate rfpwr_state_toset; 758 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw); 759 760 if (rfpwr_state_toset == ERFON) 761 rtl92se_sw_led_on(hw, pled0); 762 } 763 } 764 765 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw) 766 { 767 struct rtl_priv *rtlpriv = rtl_priv(hw); 768 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 769 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 770 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 771 u8 i; 772 u16 tmpu2b; 773 774 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */ 775 776 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */ 777 /* Turn on 0x40 Command register */ 778 rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN | 779 SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN | 780 RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN)); 781 782 /* Set TCR TX DMA pre 2 FULL enable bit */ 783 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) | 784 TXDMAPRE2FULL); 785 786 /* Set RCR */ 787 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config); 788 789 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */ 790 791 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */ 792 /* Set CCK/OFDM SIFS */ 793 /* CCK SIFS shall always be 10us. */ 794 rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a); 795 rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010); 796 797 /* Set AckTimeout */ 798 rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40); 799 800 /* Beacon related */ 801 rtl_write_word(rtlpriv, BCN_INTERVAL, 100); 802 rtl_write_word(rtlpriv, ATIMWND, 2); 803 804 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */ 805 /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */ 806 /* Firmware allocate now, associate with FW internal setting.!!! */ 807 808 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */ 809 /* 5.3 Set driver info, we only accept PHY status now. */ 810 /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO */ 811 rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6)); 812 813 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */ 814 /* Set RRSR to all legacy rate and HT rate 815 * CCK rate is supported by default. 816 * CCK rate will be filtered out only when associated 817 * AP does not support it. 818 * Only enable ACK rate to OFDM 24M 819 * Disable RRSR for CCK rate in A-Cut */ 820 821 if (rtlhal->version == VERSION_8192S_ACUT) 822 rtl_write_byte(rtlpriv, RRSR, 0xf0); 823 else if (rtlhal->version == VERSION_8192S_BCUT) 824 rtl_write_byte(rtlpriv, RRSR, 0xff); 825 rtl_write_byte(rtlpriv, RRSR + 1, 0x01); 826 rtl_write_byte(rtlpriv, RRSR + 2, 0x00); 827 828 /* A-Cut IC do not support CCK rate. We forbid ARFR to */ 829 /* fallback to CCK rate */ 830 for (i = 0; i < 8; i++) { 831 /*Disable RRSR for CCK rate in A-Cut */ 832 if (rtlhal->version == VERSION_8192S_ACUT) 833 rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0); 834 } 835 836 /* Different rate use different AMPDU size */ 837 /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */ 838 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f); 839 /* MCS0/1/2/3 use max AMPDU size 4*2=8K */ 840 rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442); 841 /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */ 842 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7); 843 /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */ 844 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772); 845 /* MCS12/13/14/15 use max AMPDU size 15*2=30K */ 846 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd); 847 848 /* Set Data / Response auto rate fallack retry count */ 849 rtl_write_dword(rtlpriv, DARFRC, 0x04010000); 850 rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605); 851 rtl_write_dword(rtlpriv, RARFRC, 0x04010000); 852 rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605); 853 854 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */ 855 /* Set all rate to support SG */ 856 rtl_write_word(rtlpriv, SG_RATE, 0xFFFF); 857 858 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */ 859 /* Set NAV protection length */ 860 rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080); 861 /* CF-END Threshold */ 862 rtl_write_byte(rtlpriv, CFEND_TH, 0xFF); 863 /* Set AMPDU minimum space */ 864 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07); 865 /* Set TXOP stall control for several queue/HI/BCN/MGT/ */ 866 rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00); 867 868 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */ 869 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */ 870 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */ 871 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */ 872 /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */ 873 874 /* 14. Set driver info, we only accept PHY status now. */ 875 rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4); 876 877 /* 15. For EEPROM R/W Workaround */ 878 /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */ 879 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 880 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13)); 881 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL); 882 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8))); 883 884 /* 17. For EFUSE */ 885 /* We may R/W EFUSE in EEPROM mode */ 886 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) { 887 u8 tempval; 888 889 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1); 890 tempval &= 0xFE; 891 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval); 892 893 /* Change Program timing */ 894 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72); 895 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n"); 896 } 897 898 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n"); 899 900 } 901 902 static void _rtl92se_hw_configure(struct ieee80211_hw *hw) 903 { 904 struct rtl_priv *rtlpriv = rtl_priv(hw); 905 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 906 struct rtl_phy *rtlphy = &(rtlpriv->phy); 907 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 908 909 u8 reg_bw_opmode = 0; 910 u32 reg_rrsr = 0; 911 u8 regtmp = 0; 912 913 reg_bw_opmode = BW_OPMODE_20MHZ; 914 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 915 916 regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL); 917 reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp; 918 rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr); 919 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode); 920 921 /* Set Retry Limit here */ 922 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, 923 (u8 *)(&rtlpci->shortretry_limit)); 924 925 rtl_write_byte(rtlpriv, MLT, 0x8f); 926 927 /* For Min Spacing configuration. */ 928 switch (rtlphy->rf_type) { 929 case RF_1T2R: 930 case RF_1T1R: 931 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3); 932 break; 933 case RF_2T2R: 934 case RF_2T2R_GREEN: 935 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3); 936 break; 937 } 938 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg); 939 } 940 941 int rtl92se_hw_init(struct ieee80211_hw *hw) 942 { 943 struct rtl_priv *rtlpriv = rtl_priv(hw); 944 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 945 struct rtl_phy *rtlphy = &(rtlpriv->phy); 946 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 947 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 948 u8 tmp_byte = 0; 949 unsigned long flags; 950 bool rtstatus = true; 951 u8 tmp_u1b; 952 int err = false; 953 u8 i; 954 int wdcapra_add[] = { 955 EDCAPARA_BE, EDCAPARA_BK, 956 EDCAPARA_VI, EDCAPARA_VO}; 957 u8 secr_value = 0x0; 958 959 rtlpci->being_init_adapter = true; 960 961 /* As this function can take a very long time (up to 350 ms) 962 * and can be called with irqs disabled, reenable the irqs 963 * to let the other devices continue being serviced. 964 * 965 * It is safe doing so since our own interrupts will only be enabled 966 * in a subsequent step. 967 */ 968 local_save_flags(flags); 969 local_irq_enable(); 970 971 rtlpriv->intf_ops->disable_aspm(hw); 972 973 /* 1. MAC Initialize */ 974 /* Before FW download, we have to set some MAC register */ 975 _rtl92se_macconfig_before_fwdownload(hw); 976 977 rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv, 978 PMC_FSM) >> 16) & 0xF); 979 980 rtl8192se_gpiobit3_cfg_inputmode(hw); 981 982 /* 2. download firmware */ 983 rtstatus = rtl92s_download_fw(hw); 984 if (!rtstatus) { 985 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 986 "Failed to download FW. Init HW without FW now... " 987 "Please copy FW into /lib/firmware/rtlwifi\n"); 988 err = 1; 989 goto exit; 990 } 991 992 /* After FW download, we have to reset MAC register */ 993 _rtl92se_macconfig_after_fwdownload(hw); 994 995 /*Retrieve default FW Cmd IO map. */ 996 rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, LBUS_MON_ADDR); 997 rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK); 998 999 /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */ 1000 if (!rtl92s_phy_mac_config(hw)) { 1001 pr_err("MAC Config failed\n"); 1002 err = rtstatus; 1003 goto exit; 1004 } 1005 1006 /* because last function modify RCR, so we update 1007 * rcr var here, or TP will unstable for receive_config 1008 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 1009 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 1010 */ 1011 rtlpci->receive_config = rtl_read_dword(rtlpriv, RCR); 1012 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 1013 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config); 1014 1015 /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */ 1016 /* We must set flag avoid BB/RF config period later!! */ 1017 rtl_write_dword(rtlpriv, CMDR, 0x37FC); 1018 1019 /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */ 1020 if (!rtl92s_phy_bb_config(hw)) { 1021 pr_err("BB Config failed\n"); 1022 err = rtstatus; 1023 goto exit; 1024 } 1025 1026 /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */ 1027 /* Before initalizing RF. We can not use FW to do RF-R/W. */ 1028 1029 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 1030 1031 /* Before RF-R/W we must execute the IO from Scott's suggestion. */ 1032 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB); 1033 if (rtlhal->version == VERSION_8192S_ACUT) 1034 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07); 1035 else 1036 rtl_write_byte(rtlpriv, RF_CTRL, 0x07); 1037 1038 if (!rtl92s_phy_rf_config(hw)) { 1039 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n"); 1040 err = rtstatus; 1041 goto exit; 1042 } 1043 1044 /* After read predefined TXT, we must set BB/MAC/RF 1045 * register as our requirement */ 1046 1047 rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw, 1048 (enum radio_path)0, 1049 RF_CHNLBW, 1050 RFREG_OFFSET_MASK); 1051 rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw, 1052 (enum radio_path)1, 1053 RF_CHNLBW, 1054 RFREG_OFFSET_MASK); 1055 1056 /*---- Set CCK and OFDM Block "ON"----*/ 1057 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1058 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1059 1060 /*3 Set Hardware(Do nothing now) */ 1061 _rtl92se_hw_configure(hw); 1062 1063 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */ 1064 /* TX power index for different rate set. */ 1065 /* Get original hw reg values */ 1066 rtl92s_phy_get_hw_reg_originalvalue(hw); 1067 /* Write correct tx power index */ 1068 rtl92s_phy_set_txpower(hw, rtlphy->current_channel); 1069 1070 /* We must set MAC address after firmware download. */ 1071 for (i = 0; i < 6; i++) 1072 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]); 1073 1074 /* EEPROM R/W workaround */ 1075 tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG); 1076 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3))); 1077 1078 rtl_write_byte(rtlpriv, 0x4d, 0x0); 1079 1080 if (hal_get_firmwareversion(rtlpriv) >= 0x49) { 1081 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4)); 1082 tmp_byte = tmp_byte | BIT(5); 1083 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte); 1084 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF); 1085 } 1086 1087 /* We enable high power and RA related mechanism after NIC 1088 * initialized. */ 1089 if (hal_get_firmwareversion(rtlpriv) >= 0x35) { 1090 /* Fw v.53 and later. */ 1091 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT); 1092 } else if (hal_get_firmwareversion(rtlpriv) == 0x34) { 1093 /* Fw v.52. */ 1094 rtl_write_dword(rtlpriv, WFM5, FW_RA_INIT); 1095 rtl92s_phy_chk_fwcmd_iodone(hw); 1096 } else { 1097 /* Compatible earlier FW version. */ 1098 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET); 1099 rtl92s_phy_chk_fwcmd_iodone(hw); 1100 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE); 1101 rtl92s_phy_chk_fwcmd_iodone(hw); 1102 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH); 1103 rtl92s_phy_chk_fwcmd_iodone(hw); 1104 } 1105 1106 /* Add to prevent ASPM bug. */ 1107 /* Always enable hst and NIC clock request. */ 1108 rtl92s_phy_switch_ephy_parameter(hw); 1109 1110 /* Security related 1111 * 1. Clear all H/W keys. 1112 * 2. Enable H/W encryption/decryption. */ 1113 rtl_cam_reset_all_entry(hw); 1114 secr_value |= SCR_TXENCENABLE; 1115 secr_value |= SCR_RXENCENABLE; 1116 secr_value |= SCR_NOSKMC; 1117 rtl_write_byte(rtlpriv, REG_SECR, secr_value); 1118 1119 for (i = 0; i < 4; i++) 1120 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322); 1121 1122 if (rtlphy->rf_type == RF_1T2R) { 1123 bool mrc2set = true; 1124 /* Turn on B-Path */ 1125 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set); 1126 } 1127 1128 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON); 1129 rtl92s_dm_init(hw); 1130 exit: 1131 local_irq_restore(flags); 1132 rtlpci->being_init_adapter = false; 1133 return err; 1134 } 1135 1136 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 *addr) 1137 { 1138 /* This is a stub. */ 1139 } 1140 1141 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1142 { 1143 struct rtl_priv *rtlpriv = rtl_priv(hw); 1144 u32 reg_rcr; 1145 1146 if (rtlpriv->psc.rfpwr_state != ERFON) 1147 return; 1148 1149 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1150 1151 if (check_bssid) { 1152 reg_rcr |= (RCR_CBSSID); 1153 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1154 } else if (!check_bssid) { 1155 reg_rcr &= (~RCR_CBSSID); 1156 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1157 } 1158 1159 } 1160 1161 static int _rtl92se_set_media_status(struct ieee80211_hw *hw, 1162 enum nl80211_iftype type) 1163 { 1164 struct rtl_priv *rtlpriv = rtl_priv(hw); 1165 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1166 u32 temp; 1167 bt_msr &= ~MSR_LINK_MASK; 1168 1169 switch (type) { 1170 case NL80211_IFTYPE_UNSPECIFIED: 1171 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); 1172 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1173 "Set Network type to NO LINK!\n"); 1174 break; 1175 case NL80211_IFTYPE_ADHOC: 1176 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT); 1177 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1178 "Set Network type to Ad Hoc!\n"); 1179 break; 1180 case NL80211_IFTYPE_STATION: 1181 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT); 1182 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1183 "Set Network type to STA!\n"); 1184 break; 1185 case NL80211_IFTYPE_AP: 1186 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT); 1187 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1188 "Set Network type to AP!\n"); 1189 break; 1190 default: 1191 pr_err("Network type %d not supported!\n", type); 1192 return 1; 1193 1194 } 1195 1196 if (type != NL80211_IFTYPE_AP && 1197 rtlpriv->mac80211.link_state < MAC80211_LINKED) 1198 bt_msr = rtl_read_byte(rtlpriv, MSR) & ~MSR_LINK_MASK; 1199 rtl_write_byte(rtlpriv, MSR, bt_msr); 1200 1201 temp = rtl_read_dword(rtlpriv, TCR); 1202 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8))); 1203 rtl_write_dword(rtlpriv, TCR, temp | BIT(8)); 1204 1205 1206 return 0; 1207 } 1208 1209 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */ 1210 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1211 { 1212 struct rtl_priv *rtlpriv = rtl_priv(hw); 1213 1214 if (_rtl92se_set_media_status(hw, type)) 1215 return -EOPNOTSUPP; 1216 1217 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1218 if (type != NL80211_IFTYPE_AP) 1219 rtl92se_set_check_bssid(hw, true); 1220 } else { 1221 rtl92se_set_check_bssid(hw, false); 1222 } 1223 1224 return 0; 1225 } 1226 1227 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ 1228 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci) 1229 { 1230 struct rtl_priv *rtlpriv = rtl_priv(hw); 1231 rtl92s_dm_init_edca_turbo(hw); 1232 1233 switch (aci) { 1234 case AC1_BK: 1235 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f); 1236 break; 1237 case AC0_BE: 1238 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */ 1239 break; 1240 case AC2_VI: 1241 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322); 1242 break; 1243 case AC3_VO: 1244 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222); 1245 break; 1246 default: 1247 WARN_ONCE(true, "rtl8192se: invalid aci: %d !\n", aci); 1248 break; 1249 } 1250 } 1251 1252 void rtl92se_enable_interrupt(struct ieee80211_hw *hw) 1253 { 1254 struct rtl_priv *rtlpriv = rtl_priv(hw); 1255 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1256 1257 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]); 1258 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */ 1259 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F); 1260 rtlpci->irq_enabled = true; 1261 } 1262 1263 void rtl92se_disable_interrupt(struct ieee80211_hw *hw) 1264 { 1265 struct rtl_priv *rtlpriv; 1266 struct rtl_pci *rtlpci; 1267 1268 rtlpriv = rtl_priv(hw); 1269 /* if firmware not available, no interrupts */ 1270 if (!rtlpriv || !rtlpriv->max_fw_size) 1271 return; 1272 rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1273 rtl_write_dword(rtlpriv, INTA_MASK, 0); 1274 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0); 1275 rtlpci->irq_enabled = false; 1276 } 1277 1278 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data) 1279 { 1280 struct rtl_priv *rtlpriv = rtl_priv(hw); 1281 u8 waitcnt = 100; 1282 bool result = false; 1283 u8 tmp; 1284 1285 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data); 1286 1287 /* Wait the MAC synchronized. */ 1288 udelay(400); 1289 1290 /* Check if it is set ready. */ 1291 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1); 1292 result = ((tmp & BIT(7)) == (data & BIT(7))); 1293 1294 if ((data & (BIT(6) | BIT(7))) == false) { 1295 waitcnt = 100; 1296 tmp = 0; 1297 1298 while (1) { 1299 waitcnt--; 1300 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1); 1301 1302 if ((tmp & BIT(6))) 1303 break; 1304 1305 pr_err("wait for BIT(6) return value %x\n", tmp); 1306 1307 if (waitcnt == 0) 1308 break; 1309 udelay(10); 1310 } 1311 1312 if (waitcnt == 0) 1313 result = false; 1314 else 1315 result = true; 1316 } 1317 1318 return result; 1319 } 1320 1321 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw) 1322 { 1323 struct rtl_priv *rtlpriv = rtl_priv(hw); 1324 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1325 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1326 u8 u1btmp; 1327 1328 if (rtlhal->driver_going2unload) 1329 rtl_write_byte(rtlpriv, 0x560, 0x0); 1330 1331 /* Power save for BB/RF */ 1332 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL); 1333 u1btmp |= BIT(0); 1334 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp); 1335 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0); 1336 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF); 1337 rtl_write_word(rtlpriv, CMDR, 0x57FC); 1338 udelay(100); 1339 rtl_write_word(rtlpriv, CMDR, 0x77FC); 1340 rtl_write_byte(rtlpriv, PHY_CCA, 0x0); 1341 udelay(10); 1342 rtl_write_word(rtlpriv, CMDR, 0x37FC); 1343 udelay(10); 1344 rtl_write_word(rtlpriv, CMDR, 0x77FC); 1345 udelay(10); 1346 rtl_write_word(rtlpriv, CMDR, 0x57FC); 1347 rtl_write_word(rtlpriv, CMDR, 0x0000); 1348 1349 if (rtlhal->driver_going2unload) { 1350 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1)); 1351 u1btmp &= ~(BIT(0)); 1352 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp); 1353 } 1354 1355 u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 1356 1357 /* Add description. After switch control path. register 1358 * after page1 will be invisible. We can not do any IO 1359 * for register>0x40. After resume&MACIO reset, we need 1360 * to remember previous reg content. */ 1361 if (u1btmp & BIT(7)) { 1362 u1btmp &= ~(BIT(6) | BIT(7)); 1363 if (!_rtl92s_set_sysclk(hw, u1btmp)) { 1364 pr_err("Switch ctrl path fail\n"); 1365 return; 1366 } 1367 } 1368 1369 /* Power save for MAC */ 1370 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS && 1371 !rtlhal->driver_going2unload) { 1372 /* enable LED function */ 1373 rtl_write_byte(rtlpriv, 0x03, 0xF9); 1374 /* SW/HW radio off or halt adapter!! For example S3/S4 */ 1375 } else { 1376 /* LED function disable. Power range is about 8mA now. */ 1377 /* if write 0xF1 disconnet_pci power 1378 * ifconfig wlan0 down power are both high 35:70 */ 1379 /* if write oxF9 disconnet_pci power 1380 * ifconfig wlan0 down power are both low 12:45*/ 1381 rtl_write_byte(rtlpriv, 0x03, 0xF9); 1382 } 1383 1384 rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70); 1385 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68); 1386 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x00); 1387 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34); 1388 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E); 1389 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1390 1391 } 1392 1393 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw) 1394 { 1395 struct rtl_priv *rtlpriv = rtl_priv(hw); 1396 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1397 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0; 1398 1399 if (rtlpci->up_first_time == 1) 1400 return; 1401 1402 if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS) 1403 rtl92se_sw_led_on(hw, pled0); 1404 else 1405 rtl92se_sw_led_off(hw, pled0); 1406 } 1407 1408 1409 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw) 1410 { 1411 struct rtl_priv *rtlpriv = rtl_priv(hw); 1412 u16 tmpu2b; 1413 u8 tmpu1b; 1414 1415 rtlpriv->psc.pwrdomain_protect = true; 1416 1417 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 1418 if (tmpu1b & BIT(7)) { 1419 tmpu1b &= ~(BIT(6) | BIT(7)); 1420 if (!_rtl92s_set_sysclk(hw, tmpu1b)) { 1421 rtlpriv->psc.pwrdomain_protect = false; 1422 return; 1423 } 1424 } 1425 1426 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0); 1427 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34); 1428 1429 /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */ 1430 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1431 1432 /* If IPS we need to turn LED on. So we not 1433 * not disable BIT 3/7 of reg3. */ 1434 if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW)) 1435 tmpu1b &= 0xFB; 1436 else 1437 tmpu1b &= 0x73; 1438 1439 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b); 1440 /* wait for BIT 10/11/15 to pull high automatically!! */ 1441 mdelay(1); 1442 1443 rtl_write_byte(rtlpriv, CMDR, 0); 1444 rtl_write_byte(rtlpriv, TCR, 0); 1445 1446 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */ 1447 tmpu1b = rtl_read_byte(rtlpriv, 0x562); 1448 tmpu1b |= 0x08; 1449 rtl_write_byte(rtlpriv, 0x562, tmpu1b); 1450 tmpu1b &= ~(BIT(3)); 1451 rtl_write_byte(rtlpriv, 0x562, tmpu1b); 1452 1453 /* Enable AFE clock source */ 1454 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL); 1455 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01)); 1456 /* Delay 1.5ms */ 1457 udelay(1500); 1458 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1); 1459 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb)); 1460 1461 /* Enable AFE Macro Block's Bandgap */ 1462 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC); 1463 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0))); 1464 mdelay(1); 1465 1466 /* Enable AFE Mbias */ 1467 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC); 1468 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02)); 1469 mdelay(1); 1470 1471 /* Enable LDOA15 block */ 1472 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL); 1473 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0))); 1474 1475 /* Set Digital Vdd to Retention isolation Path. */ 1476 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); 1477 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11))); 1478 1479 1480 /* For warm reboot NIC disappera bug. */ 1481 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1482 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13))); 1483 1484 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68); 1485 1486 /* Enable AFE PLL Macro Block */ 1487 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL); 1488 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); 1489 /* Enable MAC 80MHZ clock */ 1490 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1); 1491 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0))); 1492 mdelay(1); 1493 1494 /* Release isolation AFE PLL & MD */ 1495 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6); 1496 1497 /* Enable MAC clock */ 1498 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR); 1499 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11))); 1500 1501 /* Enable Core digital and enable IOREG R/W */ 1502 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1503 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11))); 1504 /* enable REG_EN */ 1505 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15))); 1506 1507 /* Switch the control path. */ 1508 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR); 1509 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2)))); 1510 1511 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 1512 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6))); 1513 if (!_rtl92s_set_sysclk(hw, tmpu1b)) { 1514 rtlpriv->psc.pwrdomain_protect = false; 1515 return; 1516 } 1517 1518 rtl_write_word(rtlpriv, CMDR, 0x37FC); 1519 1520 /* After MACIO reset,we must refresh LED state. */ 1521 _rtl92se_gen_refreshledstate(hw); 1522 1523 rtlpriv->psc.pwrdomain_protect = false; 1524 } 1525 1526 void rtl92se_card_disable(struct ieee80211_hw *hw) 1527 { 1528 struct rtl_priv *rtlpriv = rtl_priv(hw); 1529 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1530 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1531 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1532 enum nl80211_iftype opmode; 1533 u8 wait = 30; 1534 1535 rtlpriv->intf_ops->enable_aspm(hw); 1536 1537 if (rtlpci->driver_is_goingto_unload || 1538 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1539 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1540 1541 /* we should chnge GPIO to input mode 1542 * this will drop away current about 25mA*/ 1543 rtl8192se_gpiobit3_cfg_inputmode(hw); 1544 1545 /* this is very important for ips power save */ 1546 while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) { 1547 if (rtlpriv->psc.pwrdomain_protect) 1548 mdelay(20); 1549 else 1550 break; 1551 } 1552 1553 mac->link_state = MAC80211_NOLINK; 1554 opmode = NL80211_IFTYPE_UNSPECIFIED; 1555 _rtl92se_set_media_status(hw, opmode); 1556 1557 _rtl92s_phy_set_rfhalt(hw); 1558 udelay(100); 1559 } 1560 1561 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, 1562 struct rtl_int *intvec) 1563 { 1564 struct rtl_priv *rtlpriv = rtl_priv(hw); 1565 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1566 1567 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 1568 rtl_write_dword(rtlpriv, ISR, intvec->inta); 1569 1570 intvec->intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1]; 1571 rtl_write_dword(rtlpriv, ISR + 4, intvec->intb); 1572 } 1573 1574 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw) 1575 { 1576 struct rtl_priv *rtlpriv = rtl_priv(hw); 1577 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1578 u16 bcntime_cfg = 0; 1579 u16 bcn_cw = 6, bcn_ifs = 0xf; 1580 u16 atim_window = 2; 1581 1582 /* ATIM Window (in unit of TU). */ 1583 rtl_write_word(rtlpriv, ATIMWND, atim_window); 1584 1585 /* Beacon interval (in unit of TU). */ 1586 rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval); 1587 1588 /* DrvErlyInt (in unit of TU). (Time to send 1589 * interrupt to notify driver to change 1590 * beacon content) */ 1591 rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4); 1592 1593 /* BcnDMATIM(in unit of us). Indicates the 1594 * time before TBTT to perform beacon queue DMA */ 1595 rtl_write_word(rtlpriv, BCN_DMATIME, 256); 1596 1597 /* Force beacon frame transmission even 1598 * after receiving beacon frame from 1599 * other ad hoc STA */ 1600 rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100); 1601 1602 /* Beacon Time Configuration */ 1603 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1604 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT); 1605 1606 /* TODO: bcn_ifs may required to be changed on ASIC */ 1607 bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS; 1608 1609 /*for beacon changed */ 1610 rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval); 1611 } 1612 1613 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw) 1614 { 1615 struct rtl_priv *rtlpriv = rtl_priv(hw); 1616 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1617 u16 bcn_interval = mac->beacon_interval; 1618 1619 /* Beacon interval (in unit of TU). */ 1620 rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval); 1621 /* 2008.10.24 added by tynli for beacon changed. */ 1622 rtl92s_phy_set_beacon_hwreg(hw, bcn_interval); 1623 } 1624 1625 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw, 1626 u32 add_msr, u32 rm_msr) 1627 { 1628 struct rtl_priv *rtlpriv = rtl_priv(hw); 1629 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1630 1631 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n", 1632 add_msr, rm_msr); 1633 1634 if (add_msr) 1635 rtlpci->irq_mask[0] |= add_msr; 1636 1637 if (rm_msr) 1638 rtlpci->irq_mask[0] &= (~rm_msr); 1639 1640 rtl92se_disable_interrupt(hw); 1641 rtl92se_enable_interrupt(hw); 1642 } 1643 1644 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw) 1645 { 1646 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1647 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1648 u8 efuse_id; 1649 1650 rtlhal->ic_class = IC_INFERIORITY_A; 1651 1652 /* Only retrieving while using EFUSE. */ 1653 if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) && 1654 !rtlefuse->autoload_failflag) { 1655 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET); 1656 1657 if (efuse_id == 0xfe) 1658 rtlhal->ic_class = IC_INFERIORITY_B; 1659 } 1660 } 1661 1662 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw) 1663 { 1664 struct rtl_priv *rtlpriv = rtl_priv(hw); 1665 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1666 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1667 struct device *dev = &rtl_pcipriv(hw)->dev.pdev->dev; 1668 u16 i, usvalue; 1669 u16 eeprom_id; 1670 u8 tempval; 1671 u8 hwinfo[HWSET_MAX_SIZE_92S]; 1672 u8 rf_path, index; 1673 1674 switch (rtlefuse->epromtype) { 1675 case EEPROM_BOOT_EFUSE: 1676 rtl_efuse_shadow_map_update(hw); 1677 break; 1678 1679 case EEPROM_93C46: 1680 pr_err("RTL819X Not boot from eeprom, check it !!\n"); 1681 return; 1682 1683 default: 1684 dev_warn(dev, "no efuse data\n"); 1685 return; 1686 } 1687 1688 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0], 1689 HWSET_MAX_SIZE_92S); 1690 1691 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP", 1692 hwinfo, HWSET_MAX_SIZE_92S); 1693 1694 eeprom_id = *((u16 *)&hwinfo[0]); 1695 if (eeprom_id != RTL8190_EEPROM_ID) { 1696 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1697 "EEPROM ID(%#x) is invalid!!\n", eeprom_id); 1698 rtlefuse->autoload_failflag = true; 1699 } else { 1700 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1701 rtlefuse->autoload_failflag = false; 1702 } 1703 1704 if (rtlefuse->autoload_failflag) 1705 return; 1706 1707 _rtl8192se_get_IC_Inferiority(hw); 1708 1709 /* Read IC Version && Channel Plan */ 1710 /* VID, DID SE 0xA-D */ 1711 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID]; 1712 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID]; 1713 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID]; 1714 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID]; 1715 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION]; 1716 1717 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1718 "EEPROMId = 0x%4x\n", eeprom_id); 1719 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1720 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid); 1721 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1722 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did); 1723 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1724 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid); 1725 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1726 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid); 1727 1728 for (i = 0; i < 6; i += 2) { 1729 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i]; 1730 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; 1731 } 1732 1733 for (i = 0; i < 6; i++) 1734 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]); 1735 1736 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); 1737 1738 /* Get Tx Power Level by Channel */ 1739 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */ 1740 /* 92S suupport RF A & B */ 1741 for (rf_path = 0; rf_path < 2; rf_path++) { 1742 for (i = 0; i < 3; i++) { 1743 /* Read CCK RF A & B Tx power */ 1744 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] = 1745 hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i]; 1746 1747 /* Read OFDM RF A & B Tx power for 1T */ 1748 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1749 hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i]; 1750 1751 /* Read OFDM RF A & B Tx power for 2T */ 1752 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][i] 1753 = hwinfo[EEPROM_TXPOWERBASE + 12 + 1754 rf_path * 3 + i]; 1755 } 1756 } 1757 1758 for (rf_path = 0; rf_path < 2; rf_path++) 1759 for (i = 0; i < 3; i++) 1760 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1761 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", 1762 rf_path, i, 1763 rtlefuse->eeprom_chnlarea_txpwr_cck 1764 [rf_path][i]); 1765 for (rf_path = 0; rf_path < 2; rf_path++) 1766 for (i = 0; i < 3; i++) 1767 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1768 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 1769 rf_path, i, 1770 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1771 [rf_path][i]); 1772 for (rf_path = 0; rf_path < 2; rf_path++) 1773 for (i = 0; i < 3; i++) 1774 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1775 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 1776 rf_path, i, 1777 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1778 [rf_path][i]); 1779 1780 for (rf_path = 0; rf_path < 2; rf_path++) { 1781 1782 /* Assign dedicated channel tx power */ 1783 for (i = 0; i < 14; i++) { 1784 /* channel 1~3 use the same Tx Power Level. */ 1785 if (i < 3) 1786 index = 0; 1787 /* Channel 4-8 */ 1788 else if (i < 8) 1789 index = 1; 1790 /* Channel 9-14 */ 1791 else 1792 index = 2; 1793 1794 /* Record A & B CCK /OFDM - 1T/2T Channel area 1795 * tx power */ 1796 rtlefuse->txpwrlevel_cck[rf_path][i] = 1797 rtlefuse->eeprom_chnlarea_txpwr_cck 1798 [rf_path][index]; 1799 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 1800 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1801 [rf_path][index]; 1802 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 1803 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1804 [rf_path][index]; 1805 } 1806 1807 for (i = 0; i < 14; i++) { 1808 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1809 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", 1810 rf_path, i, 1811 rtlefuse->txpwrlevel_cck[rf_path][i], 1812 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 1813 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 1814 } 1815 } 1816 1817 for (rf_path = 0; rf_path < 2; rf_path++) { 1818 for (i = 0; i < 3; i++) { 1819 /* Read Power diff limit. */ 1820 rtlefuse->eeprom_pwrgroup[rf_path][i] = 1821 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i]; 1822 } 1823 } 1824 1825 for (rf_path = 0; rf_path < 2; rf_path++) { 1826 /* Fill Pwr group */ 1827 for (i = 0; i < 14; i++) { 1828 /* Chanel 1-3 */ 1829 if (i < 3) 1830 index = 0; 1831 /* Channel 4-8 */ 1832 else if (i < 8) 1833 index = 1; 1834 /* Channel 9-13 */ 1835 else 1836 index = 2; 1837 1838 rtlefuse->pwrgroup_ht20[rf_path][i] = 1839 (rtlefuse->eeprom_pwrgroup[rf_path][index] & 1840 0xf); 1841 rtlefuse->pwrgroup_ht40[rf_path][i] = 1842 ((rtlefuse->eeprom_pwrgroup[rf_path][index] & 1843 0xf0) >> 4); 1844 1845 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1846 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", 1847 rf_path, i, 1848 rtlefuse->pwrgroup_ht20[rf_path][i]); 1849 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1850 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", 1851 rf_path, i, 1852 rtlefuse->pwrgroup_ht40[rf_path][i]); 1853 } 1854 } 1855 1856 for (i = 0; i < 14; i++) { 1857 /* Read tx power difference between HT OFDM 20/40 MHZ */ 1858 /* channel 1-3 */ 1859 if (i < 3) 1860 index = 0; 1861 /* Channel 4-8 */ 1862 else if (i < 8) 1863 index = 1; 1864 /* Channel 9-14 */ 1865 else 1866 index = 2; 1867 1868 tempval = hwinfo[EEPROM_TX_PWR_HT20_DIFF + index] & 0xff; 1869 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 1870 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 1871 ((tempval >> 4) & 0xF); 1872 1873 /* Read OFDM<->HT tx power diff */ 1874 /* Channel 1-3 */ 1875 if (i < 3) 1876 index = 0; 1877 /* Channel 4-8 */ 1878 else if (i < 8) 1879 index = 0x11; 1880 /* Channel 9-14 */ 1881 else 1882 index = 1; 1883 1884 tempval = hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index] & 0xff; 1885 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = 1886 (tempval & 0xF); 1887 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 1888 ((tempval >> 4) & 0xF); 1889 1890 tempval = hwinfo[TX_PWR_SAFETY_CHK]; 1891 rtlefuse->txpwr_safetyflag = (tempval & 0x01); 1892 } 1893 1894 rtlefuse->eeprom_regulatory = 0; 1895 if (rtlefuse->eeprom_version >= 2) { 1896 /* BIT(0)~2 */ 1897 if (rtlefuse->eeprom_version >= 4) 1898 rtlefuse->eeprom_regulatory = 1899 (hwinfo[EEPROM_REGULATORY] & 0x7); 1900 else /* BIT(0) */ 1901 rtlefuse->eeprom_regulatory = 1902 (hwinfo[EEPROM_REGULATORY] & 0x1); 1903 } 1904 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1905 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 1906 1907 for (i = 0; i < 14; i++) 1908 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1909 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", 1910 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 1911 for (i = 0; i < 14; i++) 1912 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1913 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", 1914 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 1915 for (i = 0; i < 14; i++) 1916 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1917 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", 1918 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 1919 for (i = 0; i < 14; i++) 1920 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1921 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", 1922 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 1923 1924 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1925 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag); 1926 1927 /* Read RF-indication and Tx Power gain 1928 * index diff of legacy to HT OFDM rate. */ 1929 tempval = hwinfo[EEPROM_RFIND_POWERDIFF] & 0xff; 1930 rtlefuse->eeprom_txpowerdiff = tempval; 1931 rtlefuse->legacy_httxpowerdiff = 1932 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0]; 1933 1934 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1935 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff); 1936 1937 /* Get TSSI value for each path. */ 1938 usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A]; 1939 rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8); 1940 usvalue = hwinfo[EEPROM_TSSI_B]; 1941 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff); 1942 1943 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 1944 rtlefuse->eeprom_tssi[RF90_PATH_A], 1945 rtlefuse->eeprom_tssi[RF90_PATH_B]); 1946 1947 /* Read antenna tx power offset of B/C/D to A from EEPROM */ 1948 /* and read ThermalMeter from EEPROM */ 1949 tempval = hwinfo[EEPROM_THERMALMETER]; 1950 rtlefuse->eeprom_thermalmeter = tempval; 1951 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1952 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1953 1954 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */ 1955 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f); 1956 rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100; 1957 1958 /* Read CrystalCap from EEPROM */ 1959 tempval = hwinfo[EEPROM_CRYSTALCAP] >> 4; 1960 rtlefuse->eeprom_crystalcap = tempval; 1961 /* CrystalCap, BIT(12)~15 */ 1962 rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap; 1963 1964 /* Read IC Version && Channel Plan */ 1965 /* Version ID, Channel plan */ 1966 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN]; 1967 rtlefuse->txpwr_fromeprom = true; 1968 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1969 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan); 1970 1971 /* Read Customer ID or Board Type!!! */ 1972 tempval = hwinfo[EEPROM_BOARDTYPE]; 1973 /* Change RF type definition */ 1974 if (tempval == 0) 1975 rtlphy->rf_type = RF_2T2R; 1976 else if (tempval == 1) 1977 rtlphy->rf_type = RF_1T2R; 1978 else if (tempval == 2) 1979 rtlphy->rf_type = RF_1T2R; 1980 else if (tempval == 3) 1981 rtlphy->rf_type = RF_1T1R; 1982 1983 /* 1T2R but 1SS (1x1 receive combining) */ 1984 rtlefuse->b1x1_recvcombine = false; 1985 if (rtlphy->rf_type == RF_1T2R) { 1986 tempval = rtl_read_byte(rtlpriv, 0x07); 1987 if (!(tempval & BIT(0))) { 1988 rtlefuse->b1x1_recvcombine = true; 1989 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1990 "RF_TYPE=1T2R but only 1SS\n"); 1991 } 1992 } 1993 rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine; 1994 rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMID]; 1995 1996 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n", 1997 rtlefuse->eeprom_oemid); 1998 1999 /* set channel paln to world wide 13 */ 2000 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13; 2001 } 2002 2003 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw) 2004 { 2005 struct rtl_priv *rtlpriv = rtl_priv(hw); 2006 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2007 u8 tmp_u1b = 0; 2008 2009 tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD); 2010 2011 if (tmp_u1b & BIT(4)) { 2012 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 2013 rtlefuse->epromtype = EEPROM_93C46; 2014 } else { 2015 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 2016 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 2017 } 2018 2019 if (tmp_u1b & BIT(5)) { 2020 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 2021 rtlefuse->autoload_failflag = false; 2022 _rtl92se_read_adapter_info(hw); 2023 } else { 2024 pr_err("Autoload ERR!!\n"); 2025 rtlefuse->autoload_failflag = true; 2026 } 2027 } 2028 2029 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw, 2030 struct ieee80211_sta *sta) 2031 { 2032 struct rtl_priv *rtlpriv = rtl_priv(hw); 2033 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2034 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2035 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2036 u32 ratr_value; 2037 u8 ratr_index = 0; 2038 u8 nmode = mac->ht_enable; 2039 u8 mimo_ps = IEEE80211_SMPS_OFF; 2040 u16 shortgi_rate = 0; 2041 u32 tmp_ratr_value = 0; 2042 u8 curtxbw_40mhz = mac->bw_40; 2043 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2044 1 : 0; 2045 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2046 1 : 0; 2047 enum wireless_mode wirelessmode = mac->mode; 2048 2049 if (rtlhal->current_bandtype == BAND_ON_5G) 2050 ratr_value = sta->supp_rates[1] << 4; 2051 else 2052 ratr_value = sta->supp_rates[0]; 2053 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2054 ratr_value = 0xfff; 2055 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 2056 sta->ht_cap.mcs.rx_mask[0] << 12); 2057 switch (wirelessmode) { 2058 case WIRELESS_MODE_B: 2059 ratr_value &= 0x0000000D; 2060 break; 2061 case WIRELESS_MODE_G: 2062 ratr_value &= 0x00000FF5; 2063 break; 2064 case WIRELESS_MODE_N_24G: 2065 case WIRELESS_MODE_N_5G: 2066 nmode = 1; 2067 if (mimo_ps == IEEE80211_SMPS_STATIC) { 2068 ratr_value &= 0x0007F005; 2069 } else { 2070 u32 ratr_mask; 2071 2072 if (get_rf_type(rtlphy) == RF_1T2R || 2073 get_rf_type(rtlphy) == RF_1T1R) { 2074 if (curtxbw_40mhz) 2075 ratr_mask = 0x000ff015; 2076 else 2077 ratr_mask = 0x000ff005; 2078 } else { 2079 if (curtxbw_40mhz) 2080 ratr_mask = 0x0f0ff015; 2081 else 2082 ratr_mask = 0x0f0ff005; 2083 } 2084 2085 ratr_value &= ratr_mask; 2086 } 2087 break; 2088 default: 2089 if (rtlphy->rf_type == RF_1T2R) 2090 ratr_value &= 0x000ff0ff; 2091 else 2092 ratr_value &= 0x0f0ff0ff; 2093 2094 break; 2095 } 2096 2097 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT) 2098 ratr_value &= 0x0FFFFFFF; 2099 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT) 2100 ratr_value &= 0x0FFFFFF0; 2101 2102 if (nmode && ((curtxbw_40mhz && 2103 curshortgi_40mhz) || (!curtxbw_40mhz && 2104 curshortgi_20mhz))) { 2105 2106 ratr_value |= 0x10000000; 2107 tmp_ratr_value = (ratr_value >> 12); 2108 2109 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 2110 if ((1 << shortgi_rate) & tmp_ratr_value) 2111 break; 2112 } 2113 2114 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 2115 (shortgi_rate << 4) | (shortgi_rate); 2116 2117 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate); 2118 } 2119 2120 rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value); 2121 if (ratr_value & 0xfffff000) 2122 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N); 2123 else 2124 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG); 2125 2126 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", 2127 rtl_read_dword(rtlpriv, ARFR0)); 2128 } 2129 2130 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw, 2131 struct ieee80211_sta *sta, 2132 u8 rssi_level, bool update_bw) 2133 { 2134 struct rtl_priv *rtlpriv = rtl_priv(hw); 2135 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2136 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2137 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2138 struct rtl_sta_info *sta_entry = NULL; 2139 u32 ratr_bitmap; 2140 u8 ratr_index = 0; 2141 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; 2142 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2143 1 : 0; 2144 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2145 1 : 0; 2146 enum wireless_mode wirelessmode = 0; 2147 bool shortgi = false; 2148 u32 ratr_value = 0; 2149 u8 shortgi_rate = 0; 2150 u32 mask = 0; 2151 u32 band = 0; 2152 bool bmulticast = false; 2153 u8 macid = 0; 2154 u8 mimo_ps = IEEE80211_SMPS_OFF; 2155 2156 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 2157 wirelessmode = sta_entry->wireless_mode; 2158 if (mac->opmode == NL80211_IFTYPE_STATION) 2159 curtxbw_40mhz = mac->bw_40; 2160 else if (mac->opmode == NL80211_IFTYPE_AP || 2161 mac->opmode == NL80211_IFTYPE_ADHOC) 2162 macid = sta->aid + 1; 2163 2164 if (rtlhal->current_bandtype == BAND_ON_5G) 2165 ratr_bitmap = sta->supp_rates[1] << 4; 2166 else 2167 ratr_bitmap = sta->supp_rates[0]; 2168 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2169 ratr_bitmap = 0xfff; 2170 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 2171 sta->ht_cap.mcs.rx_mask[0] << 12); 2172 switch (wirelessmode) { 2173 case WIRELESS_MODE_B: 2174 band |= WIRELESS_11B; 2175 ratr_index = RATR_INX_WIRELESS_B; 2176 if (ratr_bitmap & 0x0000000c) 2177 ratr_bitmap &= 0x0000000d; 2178 else 2179 ratr_bitmap &= 0x0000000f; 2180 break; 2181 case WIRELESS_MODE_G: 2182 band |= (WIRELESS_11G | WIRELESS_11B); 2183 ratr_index = RATR_INX_WIRELESS_GB; 2184 2185 if (rssi_level == 1) 2186 ratr_bitmap &= 0x00000f00; 2187 else if (rssi_level == 2) 2188 ratr_bitmap &= 0x00000ff0; 2189 else 2190 ratr_bitmap &= 0x00000ff5; 2191 break; 2192 case WIRELESS_MODE_A: 2193 band |= WIRELESS_11A; 2194 ratr_index = RATR_INX_WIRELESS_A; 2195 ratr_bitmap &= 0x00000ff0; 2196 break; 2197 case WIRELESS_MODE_N_24G: 2198 case WIRELESS_MODE_N_5G: 2199 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B); 2200 ratr_index = RATR_INX_WIRELESS_NGB; 2201 2202 if (mimo_ps == IEEE80211_SMPS_STATIC) { 2203 if (rssi_level == 1) 2204 ratr_bitmap &= 0x00070000; 2205 else if (rssi_level == 2) 2206 ratr_bitmap &= 0x0007f000; 2207 else 2208 ratr_bitmap &= 0x0007f005; 2209 } else { 2210 if (rtlphy->rf_type == RF_1T2R || 2211 rtlphy->rf_type == RF_1T1R) { 2212 if (rssi_level == 1) { 2213 ratr_bitmap &= 0x000f0000; 2214 } else if (rssi_level == 3) { 2215 ratr_bitmap &= 0x000fc000; 2216 } else if (rssi_level == 5) { 2217 ratr_bitmap &= 0x000ff000; 2218 } else { 2219 if (curtxbw_40mhz) 2220 ratr_bitmap &= 0x000ff015; 2221 else 2222 ratr_bitmap &= 0x000ff005; 2223 } 2224 } else { 2225 if (rssi_level == 1) { 2226 ratr_bitmap &= 0x0f8f0000; 2227 } else if (rssi_level == 3) { 2228 ratr_bitmap &= 0x0f8fc000; 2229 } else if (rssi_level == 5) { 2230 ratr_bitmap &= 0x0f8ff000; 2231 } else { 2232 if (curtxbw_40mhz) 2233 ratr_bitmap &= 0x0f8ff015; 2234 else 2235 ratr_bitmap &= 0x0f8ff005; 2236 } 2237 } 2238 } 2239 2240 if ((curtxbw_40mhz && curshortgi_40mhz) || 2241 (!curtxbw_40mhz && curshortgi_20mhz)) { 2242 if (macid == 0) 2243 shortgi = true; 2244 else if (macid == 1) 2245 shortgi = false; 2246 } 2247 break; 2248 default: 2249 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B); 2250 ratr_index = RATR_INX_WIRELESS_NGB; 2251 2252 if (rtlphy->rf_type == RF_1T2R) 2253 ratr_bitmap &= 0x000ff0ff; 2254 else 2255 ratr_bitmap &= 0x0f8ff0ff; 2256 break; 2257 } 2258 sta_entry->ratr_index = ratr_index; 2259 2260 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT) 2261 ratr_bitmap &= 0x0FFFFFFF; 2262 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT) 2263 ratr_bitmap &= 0x0FFFFFF0; 2264 2265 if (shortgi) { 2266 ratr_bitmap |= 0x10000000; 2267 /* Get MAX MCS available. */ 2268 ratr_value = (ratr_bitmap >> 12); 2269 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 2270 if ((1 << shortgi_rate) & ratr_value) 2271 break; 2272 } 2273 2274 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 2275 (shortgi_rate << 4) | (shortgi_rate); 2276 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate); 2277 } 2278 2279 mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf); 2280 2281 RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n", 2282 mask, ratr_bitmap); 2283 rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap); 2284 rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8))); 2285 2286 if (macid != 0) 2287 sta_entry->ratr_index = ratr_index; 2288 } 2289 2290 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw, 2291 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) 2292 { 2293 struct rtl_priv *rtlpriv = rtl_priv(hw); 2294 2295 if (rtlpriv->dm.useramask) 2296 rtl92se_update_hal_rate_mask(hw, sta, rssi_level, update_bw); 2297 else 2298 rtl92se_update_hal_rate_table(hw, sta); 2299 } 2300 2301 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw) 2302 { 2303 struct rtl_priv *rtlpriv = rtl_priv(hw); 2304 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2305 u16 sifs_timer; 2306 2307 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2308 &mac->slot_time); 2309 sifs_timer = 0x0e0e; 2310 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2311 2312 } 2313 2314 /* this ifunction is for RFKILL, it's different with windows, 2315 * because UI will disable wireless when GPIO Radio Off. 2316 * And here we not check or Disable/Enable ASPM like windows*/ 2317 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2318 { 2319 struct rtl_priv *rtlpriv = rtl_priv(hw); 2320 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2321 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2322 enum rf_pwrstate rfpwr_toset /*, cur_rfstate */; 2323 unsigned long flag = 0; 2324 bool actuallyset = false; 2325 bool turnonbypowerdomain = false; 2326 2327 /* just 8191se can check gpio before firstup, 92c/92d have fixed it */ 2328 if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter)) 2329 return false; 2330 2331 if (ppsc->swrf_processing) 2332 return false; 2333 2334 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2335 if (ppsc->rfchange_inprogress) { 2336 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2337 return false; 2338 } else { 2339 ppsc->rfchange_inprogress = true; 2340 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2341 } 2342 2343 /* cur_rfstate = ppsc->rfpwr_state;*/ 2344 2345 /* because after _rtl92s_phy_set_rfhalt, all power 2346 * closed, so we must open some power for GPIO check, 2347 * or we will always check GPIO RFOFF here, 2348 * And we should close power after GPIO check */ 2349 if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 2350 _rtl92se_power_domain_init(hw); 2351 turnonbypowerdomain = true; 2352 } 2353 2354 rfpwr_toset = _rtl92se_rf_onoff_detect(hw); 2355 2356 if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) { 2357 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2358 "RFKILL-HW Radio ON, RF ON\n"); 2359 2360 rfpwr_toset = ERFON; 2361 ppsc->hwradiooff = false; 2362 actuallyset = true; 2363 } else if ((!ppsc->hwradiooff) && (rfpwr_toset == ERFOFF)) { 2364 RT_TRACE(rtlpriv, COMP_RF, 2365 DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n"); 2366 2367 rfpwr_toset = ERFOFF; 2368 ppsc->hwradiooff = true; 2369 actuallyset = true; 2370 } 2371 2372 if (actuallyset) { 2373 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2374 ppsc->rfchange_inprogress = false; 2375 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2376 2377 /* this not include ifconfig wlan0 down case */ 2378 /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */ 2379 } else { 2380 /* because power_domain_init may be happen when 2381 * _rtl92s_phy_set_rfhalt, this will open some powers 2382 * and cause current increasing about 40 mA for ips, 2383 * rfoff and ifconfig down, so we set 2384 * _rtl92s_phy_set_rfhalt again here */ 2385 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC && 2386 turnonbypowerdomain) { 2387 _rtl92s_phy_set_rfhalt(hw); 2388 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2389 } 2390 2391 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2392 ppsc->rfchange_inprogress = false; 2393 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2394 } 2395 2396 *valid = 1; 2397 return !ppsc->hwradiooff; 2398 2399 } 2400 2401 /* Is_wepkey just used for WEP used as group & pairwise key 2402 * if pairwise is AES ang group is WEP Is_wepkey == false.*/ 2403 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr, 2404 bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all) 2405 { 2406 struct rtl_priv *rtlpriv = rtl_priv(hw); 2407 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2408 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2409 u8 *macaddr = p_macaddr; 2410 2411 u32 entry_id = 0; 2412 bool is_pairwise = false; 2413 2414 static u8 cam_const_addr[4][6] = { 2415 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2416 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2417 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2418 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2419 }; 2420 static u8 cam_const_broad[] = { 2421 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2422 }; 2423 2424 if (clear_all) { 2425 u8 idx = 0; 2426 u8 cam_offset = 0; 2427 u8 clear_number = 5; 2428 2429 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2430 2431 for (idx = 0; idx < clear_number; idx++) { 2432 rtl_cam_mark_invalid(hw, cam_offset + idx); 2433 rtl_cam_empty_entry(hw, cam_offset + idx); 2434 2435 if (idx < 5) { 2436 memset(rtlpriv->sec.key_buf[idx], 0, 2437 MAX_KEY_LEN); 2438 rtlpriv->sec.key_len[idx] = 0; 2439 } 2440 } 2441 2442 } else { 2443 switch (enc_algo) { 2444 case WEP40_ENCRYPTION: 2445 enc_algo = CAM_WEP40; 2446 break; 2447 case WEP104_ENCRYPTION: 2448 enc_algo = CAM_WEP104; 2449 break; 2450 case TKIP_ENCRYPTION: 2451 enc_algo = CAM_TKIP; 2452 break; 2453 case AESCCMP_ENCRYPTION: 2454 enc_algo = CAM_AES; 2455 break; 2456 default: 2457 pr_err("switch case %#x not processed\n", 2458 enc_algo); 2459 enc_algo = CAM_TKIP; 2460 break; 2461 } 2462 2463 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2464 macaddr = cam_const_addr[key_index]; 2465 entry_id = key_index; 2466 } else { 2467 if (is_group) { 2468 macaddr = cam_const_broad; 2469 entry_id = key_index; 2470 } else { 2471 if (mac->opmode == NL80211_IFTYPE_AP) { 2472 entry_id = rtl_cam_get_free_entry(hw, 2473 p_macaddr); 2474 if (entry_id >= TOTAL_CAM_ENTRY) { 2475 pr_err("Can not find free hw security cam entry\n"); 2476 return; 2477 } 2478 } else { 2479 entry_id = CAM_PAIRWISE_KEY_POSITION; 2480 } 2481 2482 key_index = PAIRWISE_KEYIDX; 2483 is_pairwise = true; 2484 } 2485 } 2486 2487 if (rtlpriv->sec.key_len[key_index] == 0) { 2488 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2489 "delete one entry, entry_id is %d\n", 2490 entry_id); 2491 if (mac->opmode == NL80211_IFTYPE_AP) 2492 rtl_cam_del_entry(hw, p_macaddr); 2493 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2494 } else { 2495 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2496 "add one entry\n"); 2497 if (is_pairwise) { 2498 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2499 "set Pairwise key\n"); 2500 2501 rtl_cam_add_one_entry(hw, macaddr, key_index, 2502 entry_id, enc_algo, 2503 CAM_CONFIG_NO_USEDK, 2504 rtlpriv->sec.key_buf[key_index]); 2505 } else { 2506 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2507 "set group key\n"); 2508 2509 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2510 rtl_cam_add_one_entry(hw, 2511 rtlefuse->dev_addr, 2512 PAIRWISE_KEYIDX, 2513 CAM_PAIRWISE_KEY_POSITION, 2514 enc_algo, CAM_CONFIG_NO_USEDK, 2515 rtlpriv->sec.key_buf[entry_id]); 2516 } 2517 2518 rtl_cam_add_one_entry(hw, macaddr, key_index, 2519 entry_id, enc_algo, 2520 CAM_CONFIG_NO_USEDK, 2521 rtlpriv->sec.key_buf[entry_id]); 2522 } 2523 2524 } 2525 } 2526 } 2527 2528 void rtl92se_suspend(struct ieee80211_hw *hw) 2529 { 2530 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2531 2532 rtlpci->up_first_time = true; 2533 } 2534 2535 void rtl92se_resume(struct ieee80211_hw *hw) 2536 { 2537 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2538 u32 val; 2539 2540 pci_read_config_dword(rtlpci->pdev, 0x40, &val); 2541 if ((val & 0x0000ff00) != 0) 2542 pci_write_config_dword(rtlpci->pdev, 0x40, 2543 val & 0xffff00ff); 2544 } 2545