1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../regd.h" 30 #include "../cam.h" 31 #include "../ps.h" 32 #include "../pci.h" 33 #include "reg.h" 34 #include "def.h" 35 #include "phy.h" 36 #include "dm.h" 37 #include "fw.h" 38 #include "led.h" 39 #include "hw.h" 40 41 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 42 { 43 struct rtl_priv *rtlpriv = rtl_priv(hw); 44 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 45 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 46 47 switch (variable) { 48 case HW_VAR_RCR: { 49 *((u32 *) (val)) = rtlpci->receive_config; 50 break; 51 } 52 case HW_VAR_RF_STATE: { 53 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 54 break; 55 } 56 case HW_VAR_FW_PSMODE_STATUS: { 57 *((bool *) (val)) = ppsc->fw_current_inpsmode; 58 break; 59 } 60 case HW_VAR_CORRECT_TSF: { 61 u64 tsf; 62 u32 *ptsf_low = (u32 *)&tsf; 63 u32 *ptsf_high = ((u32 *)&tsf) + 1; 64 65 *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4)); 66 *ptsf_low = rtl_read_dword(rtlpriv, TSFR); 67 68 *((u64 *) (val)) = tsf; 69 70 break; 71 } 72 case HW_VAR_MRC: { 73 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch; 74 break; 75 } 76 case HAL_DEF_WOWLAN: 77 break; 78 default: { 79 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 80 "switch case %#x not processed\n", variable); 81 break; 82 } 83 } 84 } 85 86 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 87 { 88 struct rtl_priv *rtlpriv = rtl_priv(hw); 89 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 90 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 91 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 92 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 93 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 94 95 switch (variable) { 96 case HW_VAR_ETHER_ADDR:{ 97 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]); 98 rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]); 99 break; 100 } 101 case HW_VAR_BASIC_RATE:{ 102 u16 rate_cfg = ((u16 *) val)[0]; 103 u8 rate_index = 0; 104 105 if (rtlhal->version == VERSION_8192S_ACUT) 106 rate_cfg = rate_cfg & 0x150; 107 else 108 rate_cfg = rate_cfg & 0x15f; 109 110 rate_cfg |= 0x01; 111 112 rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff); 113 rtl_write_byte(rtlpriv, RRSR + 1, 114 (rate_cfg >> 8) & 0xff); 115 116 while (rate_cfg > 0x1) { 117 rate_cfg = (rate_cfg >> 1); 118 rate_index++; 119 } 120 rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index); 121 122 break; 123 } 124 case HW_VAR_BSSID:{ 125 rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]); 126 rtl_write_word(rtlpriv, BSSIDR + 4, 127 ((u16 *)(val + 4))[0]); 128 break; 129 } 130 case HW_VAR_SIFS:{ 131 rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]); 132 rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]); 133 break; 134 } 135 case HW_VAR_SLOT_TIME:{ 136 u8 e_aci; 137 138 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 139 "HW_VAR_SLOT_TIME %x\n", val[0]); 140 141 rtl_write_byte(rtlpriv, SLOT_TIME, val[0]); 142 143 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 144 rtlpriv->cfg->ops->set_hw_reg(hw, 145 HW_VAR_AC_PARAM, 146 (&e_aci)); 147 } 148 break; 149 } 150 case HW_VAR_ACK_PREAMBLE:{ 151 u8 reg_tmp; 152 u8 short_preamble = (bool) (*val); 153 reg_tmp = (mac->cur_40_prime_sc) << 5; 154 if (short_preamble) 155 reg_tmp |= 0x80; 156 157 rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp); 158 break; 159 } 160 case HW_VAR_AMPDU_MIN_SPACE:{ 161 u8 min_spacing_to_set; 162 u8 sec_min_space; 163 164 min_spacing_to_set = *val; 165 if (min_spacing_to_set <= 7) { 166 if (rtlpriv->sec.pairwise_enc_algorithm == 167 NO_ENCRYPTION) 168 sec_min_space = 0; 169 else 170 sec_min_space = 1; 171 172 if (min_spacing_to_set < sec_min_space) 173 min_spacing_to_set = sec_min_space; 174 if (min_spacing_to_set > 5) 175 min_spacing_to_set = 5; 176 177 mac->min_space_cfg = 178 ((mac->min_space_cfg & 0xf8) | 179 min_spacing_to_set); 180 181 *val = min_spacing_to_set; 182 183 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 184 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 185 mac->min_space_cfg); 186 187 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 188 mac->min_space_cfg); 189 } 190 break; 191 } 192 case HW_VAR_SHORTGI_DENSITY:{ 193 u8 density_to_set; 194 195 density_to_set = *val; 196 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg; 197 mac->min_space_cfg |= (density_to_set << 3); 198 199 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 200 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 201 mac->min_space_cfg); 202 203 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 204 mac->min_space_cfg); 205 206 break; 207 } 208 case HW_VAR_AMPDU_FACTOR:{ 209 u8 factor_toset; 210 u8 regtoset; 211 u8 factorlevel[18] = { 212 2, 4, 4, 7, 7, 13, 13, 213 13, 2, 7, 7, 13, 13, 214 15, 15, 15, 15, 0}; 215 u8 index = 0; 216 217 factor_toset = *val; 218 if (factor_toset <= 3) { 219 factor_toset = (1 << (factor_toset + 2)); 220 if (factor_toset > 0xf) 221 factor_toset = 0xf; 222 223 for (index = 0; index < 17; index++) { 224 if (factorlevel[index] > factor_toset) 225 factorlevel[index] = 226 factor_toset; 227 } 228 229 for (index = 0; index < 8; index++) { 230 regtoset = ((factorlevel[index * 2]) | 231 (factorlevel[index * 232 2 + 1] << 4)); 233 rtl_write_byte(rtlpriv, 234 AGGLEN_LMT_L + index, 235 regtoset); 236 } 237 238 regtoset = ((factorlevel[16]) | 239 (factorlevel[17] << 4)); 240 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset); 241 242 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 243 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 244 factor_toset); 245 } 246 break; 247 } 248 case HW_VAR_AC_PARAM:{ 249 u8 e_aci = *val; 250 rtl92s_dm_init_edca_turbo(hw); 251 252 if (rtlpci->acm_method != EACMWAY2_SW) 253 rtlpriv->cfg->ops->set_hw_reg(hw, 254 HW_VAR_ACM_CTRL, 255 &e_aci); 256 break; 257 } 258 case HW_VAR_ACM_CTRL:{ 259 u8 e_aci = *val; 260 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&( 261 mac->ac[0].aifs)); 262 u8 acm = p_aci_aifsn->f.acm; 263 u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl); 264 265 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 266 0x0 : 0x1); 267 268 if (acm) { 269 switch (e_aci) { 270 case AC0_BE: 271 acm_ctrl |= AcmHw_BeqEn; 272 break; 273 case AC2_VI: 274 acm_ctrl |= AcmHw_ViqEn; 275 break; 276 case AC3_VO: 277 acm_ctrl |= AcmHw_VoqEn; 278 break; 279 default: 280 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 281 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 282 acm); 283 break; 284 } 285 } else { 286 switch (e_aci) { 287 case AC0_BE: 288 acm_ctrl &= (~AcmHw_BeqEn); 289 break; 290 case AC2_VI: 291 acm_ctrl &= (~AcmHw_ViqEn); 292 break; 293 case AC3_VO: 294 acm_ctrl &= (~AcmHw_VoqEn); 295 break; 296 default: 297 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 298 "switch case %#x not processed\n", 299 e_aci); 300 break; 301 } 302 } 303 304 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 305 "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl); 306 rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl); 307 break; 308 } 309 case HW_VAR_RCR:{ 310 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]); 311 rtlpci->receive_config = ((u32 *) (val))[0]; 312 break; 313 } 314 case HW_VAR_RETRY_LIMIT:{ 315 u8 retry_limit = val[0]; 316 317 rtl_write_word(rtlpriv, RETRY_LIMIT, 318 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 319 retry_limit << RETRY_LIMIT_LONG_SHIFT); 320 break; 321 } 322 case HW_VAR_DUAL_TSF_RST: { 323 break; 324 } 325 case HW_VAR_EFUSE_BYTES: { 326 rtlefuse->efuse_usedbytes = *((u16 *) val); 327 break; 328 } 329 case HW_VAR_EFUSE_USAGE: { 330 rtlefuse->efuse_usedpercentage = *val; 331 break; 332 } 333 case HW_VAR_IO_CMD: { 334 break; 335 } 336 case HW_VAR_WPA_CONFIG: { 337 rtl_write_byte(rtlpriv, REG_SECR, *val); 338 break; 339 } 340 case HW_VAR_SET_RPWM:{ 341 break; 342 } 343 case HW_VAR_H2C_FW_PWRMODE:{ 344 break; 345 } 346 case HW_VAR_FW_PSMODE_STATUS: { 347 ppsc->fw_current_inpsmode = *((bool *) val); 348 break; 349 } 350 case HW_VAR_H2C_FW_JOINBSSRPT:{ 351 break; 352 } 353 case HW_VAR_AID:{ 354 break; 355 } 356 case HW_VAR_CORRECT_TSF:{ 357 break; 358 } 359 case HW_VAR_MRC: { 360 bool bmrc_toset = *((bool *)val); 361 u8 u1bdata = 0; 362 363 if (bmrc_toset) { 364 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, 365 MASKBYTE0, 0x33); 366 u1bdata = (u8)rtl_get_bbreg(hw, 367 ROFDM1_TRXPATHENABLE, 368 MASKBYTE0); 369 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, 370 MASKBYTE0, 371 ((u1bdata & 0xf0) | 0x03)); 372 u1bdata = (u8)rtl_get_bbreg(hw, 373 ROFDM0_TRXPATHENABLE, 374 MASKBYTE1); 375 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, 376 MASKBYTE1, 377 (u1bdata | 0x04)); 378 379 /* Update current settings. */ 380 rtlpriv->dm.current_mrc_switch = bmrc_toset; 381 } else { 382 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, 383 MASKBYTE0, 0x13); 384 u1bdata = (u8)rtl_get_bbreg(hw, 385 ROFDM1_TRXPATHENABLE, 386 MASKBYTE0); 387 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, 388 MASKBYTE0, 389 ((u1bdata & 0xf0) | 0x01)); 390 u1bdata = (u8)rtl_get_bbreg(hw, 391 ROFDM0_TRXPATHENABLE, 392 MASKBYTE1); 393 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, 394 MASKBYTE1, (u1bdata & 0xfb)); 395 396 /* Update current settings. */ 397 rtlpriv->dm.current_mrc_switch = bmrc_toset; 398 } 399 400 break; 401 } 402 case HW_VAR_FW_LPS_ACTION: { 403 bool enter_fwlps = *((bool *)val); 404 u8 rpwm_val, fw_pwrmode; 405 bool fw_current_inps; 406 407 if (enter_fwlps) { 408 rpwm_val = 0x02; /* RF off */ 409 fw_current_inps = true; 410 rtlpriv->cfg->ops->set_hw_reg(hw, 411 HW_VAR_FW_PSMODE_STATUS, 412 (u8 *)(&fw_current_inps)); 413 rtlpriv->cfg->ops->set_hw_reg(hw, 414 HW_VAR_H2C_FW_PWRMODE, 415 &ppsc->fwctrl_psmode); 416 417 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 418 &rpwm_val); 419 } else { 420 rpwm_val = 0x0C; /* RF on */ 421 fw_pwrmode = FW_PS_ACTIVE_MODE; 422 fw_current_inps = false; 423 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 424 &rpwm_val); 425 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 426 &fw_pwrmode); 427 428 rtlpriv->cfg->ops->set_hw_reg(hw, 429 HW_VAR_FW_PSMODE_STATUS, 430 (u8 *)(&fw_current_inps)); 431 } 432 break; } 433 default: 434 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 435 "switch case %#x not processed\n", variable); 436 break; 437 } 438 439 } 440 441 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw) 442 { 443 struct rtl_priv *rtlpriv = rtl_priv(hw); 444 u8 sec_reg_value = 0x0; 445 446 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 447 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 448 rtlpriv->sec.pairwise_enc_algorithm, 449 rtlpriv->sec.group_enc_algorithm); 450 451 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 452 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 453 "not open hw encryption\n"); 454 return; 455 } 456 457 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE; 458 459 if (rtlpriv->sec.use_defaultkey) { 460 sec_reg_value |= SCR_TXUSEDK; 461 sec_reg_value |= SCR_RXUSEDK; 462 } 463 464 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n", 465 sec_reg_value); 466 467 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 468 469 } 470 471 static u8 _rtl92se_halset_sysclk(struct ieee80211_hw *hw, u8 data) 472 { 473 struct rtl_priv *rtlpriv = rtl_priv(hw); 474 u8 waitcount = 100; 475 bool bresult = false; 476 u8 tmpvalue; 477 478 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data); 479 480 /* Wait the MAC synchronized. */ 481 udelay(400); 482 483 /* Check if it is set ready. */ 484 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1); 485 bresult = ((tmpvalue & BIT(7)) == (data & BIT(7))); 486 487 if ((data & (BIT(6) | BIT(7))) == false) { 488 waitcount = 100; 489 tmpvalue = 0; 490 491 while (1) { 492 waitcount--; 493 494 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1); 495 if ((tmpvalue & BIT(6))) 496 break; 497 498 pr_err("wait for BIT(6) return value %x\n", tmpvalue); 499 if (waitcount == 0) 500 break; 501 502 udelay(10); 503 } 504 505 if (waitcount == 0) 506 bresult = false; 507 else 508 bresult = true; 509 } 510 511 return bresult; 512 } 513 514 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw) 515 { 516 struct rtl_priv *rtlpriv = rtl_priv(hw); 517 u8 u1tmp; 518 519 /* The following config GPIO function */ 520 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO)); 521 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL); 522 523 /* config GPIO3 to input */ 524 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK; 525 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp); 526 527 } 528 529 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw) 530 { 531 struct rtl_priv *rtlpriv = rtl_priv(hw); 532 u8 u1tmp; 533 u8 retval = ERFON; 534 535 /* The following config GPIO function */ 536 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO)); 537 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL); 538 539 /* config GPIO3 to input */ 540 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK; 541 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp); 542 543 /* On some of the platform, driver cannot read correct 544 * value without delay between Write_GPIO_SEL and Read_GPIO_IN */ 545 mdelay(10); 546 547 /* check GPIO3 */ 548 u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE); 549 retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF; 550 551 return retval; 552 } 553 554 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw) 555 { 556 struct rtl_priv *rtlpriv = rtl_priv(hw); 557 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 558 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 559 560 u8 i; 561 u8 tmpu1b; 562 u16 tmpu2b; 563 u8 pollingcnt = 20; 564 565 if (rtlpci->first_init) { 566 /* Reset PCIE Digital */ 567 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 568 tmpu1b &= 0xFE; 569 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b); 570 udelay(1); 571 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0)); 572 } 573 574 /* Switch to SW IO control */ 575 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 576 if (tmpu1b & BIT(7)) { 577 tmpu1b &= ~(BIT(6) | BIT(7)); 578 579 /* Set failed, return to prevent hang. */ 580 if (!_rtl92se_halset_sysclk(hw, tmpu1b)) 581 return; 582 } 583 584 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0); 585 udelay(50); 586 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34); 587 udelay(50); 588 589 /* Clear FW RPWM for FW control LPS.*/ 590 rtl_write_byte(rtlpriv, RPWM, 0x0); 591 592 /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */ 593 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 594 tmpu1b &= 0x73; 595 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b); 596 /* wait for BIT 10/11/15 to pull high automatically!! */ 597 mdelay(1); 598 599 rtl_write_byte(rtlpriv, CMDR, 0); 600 rtl_write_byte(rtlpriv, TCR, 0); 601 602 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */ 603 tmpu1b = rtl_read_byte(rtlpriv, 0x562); 604 tmpu1b |= 0x08; 605 rtl_write_byte(rtlpriv, 0x562, tmpu1b); 606 tmpu1b &= ~(BIT(3)); 607 rtl_write_byte(rtlpriv, 0x562, tmpu1b); 608 609 /* Enable AFE clock source */ 610 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL); 611 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01)); 612 /* Delay 1.5ms */ 613 mdelay(2); 614 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1); 615 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb)); 616 617 /* Enable AFE Macro Block's Bandgap */ 618 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC); 619 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0))); 620 mdelay(1); 621 622 /* Enable AFE Mbias */ 623 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC); 624 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02)); 625 mdelay(1); 626 627 /* Enable LDOA15 block */ 628 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL); 629 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0))); 630 631 /* Set Digital Vdd to Retention isolation Path. */ 632 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); 633 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11))); 634 635 /* For warm reboot NIC disappera bug. */ 636 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 637 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13))); 638 639 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68); 640 641 /* Enable AFE PLL Macro Block */ 642 /* We need to delay 100u before enabling PLL. */ 643 udelay(200); 644 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL); 645 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); 646 647 /* for divider reset */ 648 udelay(100); 649 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | 650 BIT(4) | BIT(6))); 651 udelay(10); 652 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); 653 udelay(10); 654 655 /* Enable MAC 80MHZ clock */ 656 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1); 657 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0))); 658 mdelay(1); 659 660 /* Release isolation AFE PLL & MD */ 661 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6); 662 663 /* Enable MAC clock */ 664 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR); 665 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11))); 666 667 /* Enable Core digital and enable IOREG R/W */ 668 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 669 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11))); 670 671 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 672 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7))); 673 674 /* enable REG_EN */ 675 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15))); 676 677 /* Switch the control path. */ 678 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR); 679 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2)))); 680 681 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 682 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6))); 683 if (!_rtl92se_halset_sysclk(hw, tmpu1b)) 684 return; /* Set failed, return to prevent hang. */ 685 686 rtl_write_word(rtlpriv, CMDR, 0x07FC); 687 688 /* MH We must enable the section of code to prevent load IMEM fail. */ 689 /* Load MAC register from WMAc temporarily We simulate macreg. */ 690 /* txt HW will provide MAC txt later */ 691 rtl_write_byte(rtlpriv, 0x6, 0x30); 692 rtl_write_byte(rtlpriv, 0x49, 0xf0); 693 694 rtl_write_byte(rtlpriv, 0x4b, 0x81); 695 696 rtl_write_byte(rtlpriv, 0xb5, 0x21); 697 698 rtl_write_byte(rtlpriv, 0xdc, 0xff); 699 rtl_write_byte(rtlpriv, 0xdd, 0xff); 700 rtl_write_byte(rtlpriv, 0xde, 0xff); 701 rtl_write_byte(rtlpriv, 0xdf, 0xff); 702 703 rtl_write_byte(rtlpriv, 0x11a, 0x00); 704 rtl_write_byte(rtlpriv, 0x11b, 0x00); 705 706 for (i = 0; i < 32; i++) 707 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b); 708 709 rtl_write_byte(rtlpriv, 0x236, 0xff); 710 711 rtl_write_byte(rtlpriv, 0x503, 0x22); 712 713 if (ppsc->support_aspm && !ppsc->support_backdoor) 714 rtl_write_byte(rtlpriv, 0x560, 0x40); 715 else 716 rtl_write_byte(rtlpriv, 0x560, 0x00); 717 718 rtl_write_byte(rtlpriv, DBG_PORT, 0x91); 719 720 /* Set RX Desc Address */ 721 rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma); 722 rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma); 723 724 /* Set TX Desc Address */ 725 rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma); 726 rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma); 727 rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma); 728 rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma); 729 rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma); 730 rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma); 731 rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma); 732 rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma); 733 rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma); 734 735 rtl_write_word(rtlpriv, CMDR, 0x37FC); 736 737 /* To make sure that TxDMA can ready to download FW. */ 738 /* We should reset TxDMA if IMEM RPT was not ready. */ 739 do { 740 tmpu1b = rtl_read_byte(rtlpriv, TCR); 741 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE) 742 break; 743 744 udelay(5); 745 } while (pollingcnt--); 746 747 if (pollingcnt <= 0) { 748 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 749 "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n", 750 tmpu1b); 751 tmpu1b = rtl_read_byte(rtlpriv, CMDR); 752 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN)); 753 udelay(2); 754 /* Reset TxDMA */ 755 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN); 756 } 757 758 /* After MACIO reset,we must refresh LED state. */ 759 if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) || 760 (ppsc->rfoff_reason == 0)) { 761 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 762 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0); 763 enum rf_pwrstate rfpwr_state_toset; 764 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw); 765 766 if (rfpwr_state_toset == ERFON) 767 rtl92se_sw_led_on(hw, pLed0); 768 } 769 } 770 771 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw) 772 { 773 struct rtl_priv *rtlpriv = rtl_priv(hw); 774 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 775 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 776 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 777 u8 i; 778 u16 tmpu2b; 779 780 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */ 781 782 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */ 783 /* Turn on 0x40 Command register */ 784 rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN | 785 SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN | 786 RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN)); 787 788 /* Set TCR TX DMA pre 2 FULL enable bit */ 789 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) | 790 TXDMAPRE2FULL); 791 792 /* Set RCR */ 793 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config); 794 795 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */ 796 797 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */ 798 /* Set CCK/OFDM SIFS */ 799 /* CCK SIFS shall always be 10us. */ 800 rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a); 801 rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010); 802 803 /* Set AckTimeout */ 804 rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40); 805 806 /* Beacon related */ 807 rtl_write_word(rtlpriv, BCN_INTERVAL, 100); 808 rtl_write_word(rtlpriv, ATIMWND, 2); 809 810 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */ 811 /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */ 812 /* Firmware allocate now, associate with FW internal setting.!!! */ 813 814 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */ 815 /* 5.3 Set driver info, we only accept PHY status now. */ 816 /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO */ 817 rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6)); 818 819 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */ 820 /* Set RRSR to all legacy rate and HT rate 821 * CCK rate is supported by default. 822 * CCK rate will be filtered out only when associated 823 * AP does not support it. 824 * Only enable ACK rate to OFDM 24M 825 * Disable RRSR for CCK rate in A-Cut */ 826 827 if (rtlhal->version == VERSION_8192S_ACUT) 828 rtl_write_byte(rtlpriv, RRSR, 0xf0); 829 else if (rtlhal->version == VERSION_8192S_BCUT) 830 rtl_write_byte(rtlpriv, RRSR, 0xff); 831 rtl_write_byte(rtlpriv, RRSR + 1, 0x01); 832 rtl_write_byte(rtlpriv, RRSR + 2, 0x00); 833 834 /* A-Cut IC do not support CCK rate. We forbid ARFR to */ 835 /* fallback to CCK rate */ 836 for (i = 0; i < 8; i++) { 837 /*Disable RRSR for CCK rate in A-Cut */ 838 if (rtlhal->version == VERSION_8192S_ACUT) 839 rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0); 840 } 841 842 /* Different rate use different AMPDU size */ 843 /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */ 844 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f); 845 /* MCS0/1/2/3 use max AMPDU size 4*2=8K */ 846 rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442); 847 /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */ 848 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7); 849 /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */ 850 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772); 851 /* MCS12/13/14/15 use max AMPDU size 15*2=30K */ 852 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd); 853 854 /* Set Data / Response auto rate fallack retry count */ 855 rtl_write_dword(rtlpriv, DARFRC, 0x04010000); 856 rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605); 857 rtl_write_dword(rtlpriv, RARFRC, 0x04010000); 858 rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605); 859 860 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */ 861 /* Set all rate to support SG */ 862 rtl_write_word(rtlpriv, SG_RATE, 0xFFFF); 863 864 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */ 865 /* Set NAV protection length */ 866 rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080); 867 /* CF-END Threshold */ 868 rtl_write_byte(rtlpriv, CFEND_TH, 0xFF); 869 /* Set AMPDU minimum space */ 870 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07); 871 /* Set TXOP stall control for several queue/HI/BCN/MGT/ */ 872 rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00); 873 874 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */ 875 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */ 876 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */ 877 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */ 878 /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */ 879 880 /* 14. Set driver info, we only accept PHY status now. */ 881 rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4); 882 883 /* 15. For EEPROM R/W Workaround */ 884 /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */ 885 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN); 886 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13)); 887 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL); 888 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8))); 889 890 /* 17. For EFUSE */ 891 /* We may R/W EFUSE in EEPROM mode */ 892 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) { 893 u8 tempval; 894 895 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1); 896 tempval &= 0xFE; 897 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval); 898 899 /* Change Program timing */ 900 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72); 901 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n"); 902 } 903 904 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n"); 905 906 } 907 908 static void _rtl92se_hw_configure(struct ieee80211_hw *hw) 909 { 910 struct rtl_priv *rtlpriv = rtl_priv(hw); 911 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 912 struct rtl_phy *rtlphy = &(rtlpriv->phy); 913 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 914 915 u8 reg_bw_opmode = 0; 916 u32 reg_rrsr = 0; 917 u8 regtmp = 0; 918 919 reg_bw_opmode = BW_OPMODE_20MHZ; 920 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 921 922 regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL); 923 reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp; 924 rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr); 925 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode); 926 927 /* Set Retry Limit here */ 928 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, 929 (u8 *)(&rtlpci->shortretry_limit)); 930 931 rtl_write_byte(rtlpriv, MLT, 0x8f); 932 933 /* For Min Spacing configuration. */ 934 switch (rtlphy->rf_type) { 935 case RF_1T2R: 936 case RF_1T1R: 937 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3); 938 break; 939 case RF_2T2R: 940 case RF_2T2R_GREEN: 941 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3); 942 break; 943 } 944 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg); 945 } 946 947 int rtl92se_hw_init(struct ieee80211_hw *hw) 948 { 949 struct rtl_priv *rtlpriv = rtl_priv(hw); 950 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 951 struct rtl_phy *rtlphy = &(rtlpriv->phy); 952 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 953 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 954 u8 tmp_byte = 0; 955 unsigned long flags; 956 bool rtstatus = true; 957 u8 tmp_u1b; 958 int err = false; 959 u8 i; 960 int wdcapra_add[] = { 961 EDCAPARA_BE, EDCAPARA_BK, 962 EDCAPARA_VI, EDCAPARA_VO}; 963 u8 secr_value = 0x0; 964 965 rtlpci->being_init_adapter = true; 966 967 /* As this function can take a very long time (up to 350 ms) 968 * and can be called with irqs disabled, reenable the irqs 969 * to let the other devices continue being serviced. 970 * 971 * It is safe doing so since our own interrupts will only be enabled 972 * in a subsequent step. 973 */ 974 local_save_flags(flags); 975 local_irq_enable(); 976 977 rtlpriv->intf_ops->disable_aspm(hw); 978 979 /* 1. MAC Initialize */ 980 /* Before FW download, we have to set some MAC register */ 981 _rtl92se_macconfig_before_fwdownload(hw); 982 983 rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv, 984 PMC_FSM) >> 16) & 0xF); 985 986 rtl8192se_gpiobit3_cfg_inputmode(hw); 987 988 /* 2. download firmware */ 989 rtstatus = rtl92s_download_fw(hw); 990 if (!rtstatus) { 991 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 992 "Failed to download FW. Init HW without FW now... " 993 "Please copy FW into /lib/firmware/rtlwifi\n"); 994 err = 1; 995 goto exit; 996 } 997 998 /* After FW download, we have to reset MAC register */ 999 _rtl92se_macconfig_after_fwdownload(hw); 1000 1001 /*Retrieve default FW Cmd IO map. */ 1002 rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, LBUS_MON_ADDR); 1003 rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK); 1004 1005 /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */ 1006 if (!rtl92s_phy_mac_config(hw)) { 1007 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "MAC Config failed\n"); 1008 err = rtstatus; 1009 goto exit; 1010 } 1011 1012 /* because last function modify RCR, so we update 1013 * rcr var here, or TP will unstable for receive_config 1014 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 1015 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 1016 */ 1017 rtlpci->receive_config = rtl_read_dword(rtlpriv, RCR); 1018 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 1019 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config); 1020 1021 /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */ 1022 /* We must set flag avoid BB/RF config period later!! */ 1023 rtl_write_dword(rtlpriv, CMDR, 0x37FC); 1024 1025 /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */ 1026 if (!rtl92s_phy_bb_config(hw)) { 1027 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "BB Config failed\n"); 1028 err = rtstatus; 1029 goto exit; 1030 } 1031 1032 /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */ 1033 /* Before initalizing RF. We can not use FW to do RF-R/W. */ 1034 1035 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 1036 1037 /* Before RF-R/W we must execute the IO from Scott's suggestion. */ 1038 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB); 1039 if (rtlhal->version == VERSION_8192S_ACUT) 1040 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07); 1041 else 1042 rtl_write_byte(rtlpriv, RF_CTRL, 0x07); 1043 1044 if (!rtl92s_phy_rf_config(hw)) { 1045 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n"); 1046 err = rtstatus; 1047 goto exit; 1048 } 1049 1050 /* After read predefined TXT, we must set BB/MAC/RF 1051 * register as our requirement */ 1052 1053 rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw, 1054 (enum radio_path)0, 1055 RF_CHNLBW, 1056 RFREG_OFFSET_MASK); 1057 rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw, 1058 (enum radio_path)1, 1059 RF_CHNLBW, 1060 RFREG_OFFSET_MASK); 1061 1062 /*---- Set CCK and OFDM Block "ON"----*/ 1063 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1064 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1065 1066 /*3 Set Hardware(Do nothing now) */ 1067 _rtl92se_hw_configure(hw); 1068 1069 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */ 1070 /* TX power index for different rate set. */ 1071 /* Get original hw reg values */ 1072 rtl92s_phy_get_hw_reg_originalvalue(hw); 1073 /* Write correct tx power index */ 1074 rtl92s_phy_set_txpower(hw, rtlphy->current_channel); 1075 1076 /* We must set MAC address after firmware download. */ 1077 for (i = 0; i < 6; i++) 1078 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]); 1079 1080 /* EEPROM R/W workaround */ 1081 tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG); 1082 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3))); 1083 1084 rtl_write_byte(rtlpriv, 0x4d, 0x0); 1085 1086 if (hal_get_firmwareversion(rtlpriv) >= 0x49) { 1087 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4)); 1088 tmp_byte = tmp_byte | BIT(5); 1089 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte); 1090 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF); 1091 } 1092 1093 /* We enable high power and RA related mechanism after NIC 1094 * initialized. */ 1095 if (hal_get_firmwareversion(rtlpriv) >= 0x35) { 1096 /* Fw v.53 and later. */ 1097 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT); 1098 } else if (hal_get_firmwareversion(rtlpriv) == 0x34) { 1099 /* Fw v.52. */ 1100 rtl_write_dword(rtlpriv, WFM5, FW_RA_INIT); 1101 rtl92s_phy_chk_fwcmd_iodone(hw); 1102 } else { 1103 /* Compatible earlier FW version. */ 1104 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET); 1105 rtl92s_phy_chk_fwcmd_iodone(hw); 1106 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE); 1107 rtl92s_phy_chk_fwcmd_iodone(hw); 1108 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH); 1109 rtl92s_phy_chk_fwcmd_iodone(hw); 1110 } 1111 1112 /* Add to prevent ASPM bug. */ 1113 /* Always enable hst and NIC clock request. */ 1114 rtl92s_phy_switch_ephy_parameter(hw); 1115 1116 /* Security related 1117 * 1. Clear all H/W keys. 1118 * 2. Enable H/W encryption/decryption. */ 1119 rtl_cam_reset_all_entry(hw); 1120 secr_value |= SCR_TXENCENABLE; 1121 secr_value |= SCR_RXENCENABLE; 1122 secr_value |= SCR_NOSKMC; 1123 rtl_write_byte(rtlpriv, REG_SECR, secr_value); 1124 1125 for (i = 0; i < 4; i++) 1126 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322); 1127 1128 if (rtlphy->rf_type == RF_1T2R) { 1129 bool mrc2set = true; 1130 /* Turn on B-Path */ 1131 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set); 1132 } 1133 1134 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON); 1135 rtl92s_dm_init(hw); 1136 exit: 1137 local_irq_restore(flags); 1138 rtlpci->being_init_adapter = false; 1139 return err; 1140 } 1141 1142 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 *addr) 1143 { 1144 /* This is a stub. */ 1145 } 1146 1147 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1148 { 1149 struct rtl_priv *rtlpriv = rtl_priv(hw); 1150 u32 reg_rcr; 1151 1152 if (rtlpriv->psc.rfpwr_state != ERFON) 1153 return; 1154 1155 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1156 1157 if (check_bssid) { 1158 reg_rcr |= (RCR_CBSSID); 1159 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1160 } else if (!check_bssid) { 1161 reg_rcr &= (~RCR_CBSSID); 1162 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1163 } 1164 1165 } 1166 1167 static int _rtl92se_set_media_status(struct ieee80211_hw *hw, 1168 enum nl80211_iftype type) 1169 { 1170 struct rtl_priv *rtlpriv = rtl_priv(hw); 1171 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1172 u32 temp; 1173 bt_msr &= ~MSR_LINK_MASK; 1174 1175 switch (type) { 1176 case NL80211_IFTYPE_UNSPECIFIED: 1177 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); 1178 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1179 "Set Network type to NO LINK!\n"); 1180 break; 1181 case NL80211_IFTYPE_ADHOC: 1182 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT); 1183 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1184 "Set Network type to Ad Hoc!\n"); 1185 break; 1186 case NL80211_IFTYPE_STATION: 1187 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT); 1188 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1189 "Set Network type to STA!\n"); 1190 break; 1191 case NL80211_IFTYPE_AP: 1192 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT); 1193 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1194 "Set Network type to AP!\n"); 1195 break; 1196 default: 1197 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1198 "Network type %d not supported!\n", type); 1199 return 1; 1200 1201 } 1202 1203 if (type != NL80211_IFTYPE_AP && 1204 rtlpriv->mac80211.link_state < MAC80211_LINKED) 1205 bt_msr = rtl_read_byte(rtlpriv, MSR) & ~MSR_LINK_MASK; 1206 rtl_write_byte(rtlpriv, MSR, bt_msr); 1207 1208 temp = rtl_read_dword(rtlpriv, TCR); 1209 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8))); 1210 rtl_write_dword(rtlpriv, TCR, temp | BIT(8)); 1211 1212 1213 return 0; 1214 } 1215 1216 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */ 1217 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1218 { 1219 struct rtl_priv *rtlpriv = rtl_priv(hw); 1220 1221 if (_rtl92se_set_media_status(hw, type)) 1222 return -EOPNOTSUPP; 1223 1224 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1225 if (type != NL80211_IFTYPE_AP) 1226 rtl92se_set_check_bssid(hw, true); 1227 } else { 1228 rtl92se_set_check_bssid(hw, false); 1229 } 1230 1231 return 0; 1232 } 1233 1234 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ 1235 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci) 1236 { 1237 struct rtl_priv *rtlpriv = rtl_priv(hw); 1238 rtl92s_dm_init_edca_turbo(hw); 1239 1240 switch (aci) { 1241 case AC1_BK: 1242 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f); 1243 break; 1244 case AC0_BE: 1245 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */ 1246 break; 1247 case AC2_VI: 1248 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322); 1249 break; 1250 case AC3_VO: 1251 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222); 1252 break; 1253 default: 1254 RT_ASSERT(false, "invalid aci: %d !\n", aci); 1255 break; 1256 } 1257 } 1258 1259 void rtl92se_enable_interrupt(struct ieee80211_hw *hw) 1260 { 1261 struct rtl_priv *rtlpriv = rtl_priv(hw); 1262 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1263 1264 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]); 1265 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */ 1266 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F); 1267 rtlpci->irq_enabled = true; 1268 } 1269 1270 void rtl92se_disable_interrupt(struct ieee80211_hw *hw) 1271 { 1272 struct rtl_priv *rtlpriv; 1273 struct rtl_pci *rtlpci; 1274 1275 rtlpriv = rtl_priv(hw); 1276 /* if firmware not available, no interrupts */ 1277 if (!rtlpriv || !rtlpriv->max_fw_size) 1278 return; 1279 rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1280 rtl_write_dword(rtlpriv, INTA_MASK, 0); 1281 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0); 1282 rtlpci->irq_enabled = false; 1283 } 1284 1285 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data) 1286 { 1287 struct rtl_priv *rtlpriv = rtl_priv(hw); 1288 u8 waitcnt = 100; 1289 bool result = false; 1290 u8 tmp; 1291 1292 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data); 1293 1294 /* Wait the MAC synchronized. */ 1295 udelay(400); 1296 1297 /* Check if it is set ready. */ 1298 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1); 1299 result = ((tmp & BIT(7)) == (data & BIT(7))); 1300 1301 if ((data & (BIT(6) | BIT(7))) == false) { 1302 waitcnt = 100; 1303 tmp = 0; 1304 1305 while (1) { 1306 waitcnt--; 1307 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1); 1308 1309 if ((tmp & BIT(6))) 1310 break; 1311 1312 pr_err("wait for BIT(6) return value %x\n", tmp); 1313 1314 if (waitcnt == 0) 1315 break; 1316 udelay(10); 1317 } 1318 1319 if (waitcnt == 0) 1320 result = false; 1321 else 1322 result = true; 1323 } 1324 1325 return result; 1326 } 1327 1328 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw) 1329 { 1330 struct rtl_priv *rtlpriv = rtl_priv(hw); 1331 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1332 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1333 u8 u1btmp; 1334 1335 if (rtlhal->driver_going2unload) 1336 rtl_write_byte(rtlpriv, 0x560, 0x0); 1337 1338 /* Power save for BB/RF */ 1339 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL); 1340 u1btmp |= BIT(0); 1341 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp); 1342 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0); 1343 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF); 1344 rtl_write_word(rtlpriv, CMDR, 0x57FC); 1345 udelay(100); 1346 rtl_write_word(rtlpriv, CMDR, 0x77FC); 1347 rtl_write_byte(rtlpriv, PHY_CCA, 0x0); 1348 udelay(10); 1349 rtl_write_word(rtlpriv, CMDR, 0x37FC); 1350 udelay(10); 1351 rtl_write_word(rtlpriv, CMDR, 0x77FC); 1352 udelay(10); 1353 rtl_write_word(rtlpriv, CMDR, 0x57FC); 1354 rtl_write_word(rtlpriv, CMDR, 0x0000); 1355 1356 if (rtlhal->driver_going2unload) { 1357 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1)); 1358 u1btmp &= ~(BIT(0)); 1359 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp); 1360 } 1361 1362 u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 1363 1364 /* Add description. After switch control path. register 1365 * after page1 will be invisible. We can not do any IO 1366 * for register>0x40. After resume&MACIO reset, we need 1367 * to remember previous reg content. */ 1368 if (u1btmp & BIT(7)) { 1369 u1btmp &= ~(BIT(6) | BIT(7)); 1370 if (!_rtl92s_set_sysclk(hw, u1btmp)) { 1371 pr_err("Switch ctrl path fail\n"); 1372 return; 1373 } 1374 } 1375 1376 /* Power save for MAC */ 1377 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS && 1378 !rtlhal->driver_going2unload) { 1379 /* enable LED function */ 1380 rtl_write_byte(rtlpriv, 0x03, 0xF9); 1381 /* SW/HW radio off or halt adapter!! For example S3/S4 */ 1382 } else { 1383 /* LED function disable. Power range is about 8mA now. */ 1384 /* if write 0xF1 disconnet_pci power 1385 * ifconfig wlan0 down power are both high 35:70 */ 1386 /* if write oxF9 disconnet_pci power 1387 * ifconfig wlan0 down power are both low 12:45*/ 1388 rtl_write_byte(rtlpriv, 0x03, 0xF9); 1389 } 1390 1391 rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70); 1392 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68); 1393 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x00); 1394 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34); 1395 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E); 1396 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1397 1398 } 1399 1400 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw) 1401 { 1402 struct rtl_priv *rtlpriv = rtl_priv(hw); 1403 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1404 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1405 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0); 1406 1407 if (rtlpci->up_first_time == 1) 1408 return; 1409 1410 if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS) 1411 rtl92se_sw_led_on(hw, pLed0); 1412 else 1413 rtl92se_sw_led_off(hw, pLed0); 1414 } 1415 1416 1417 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw) 1418 { 1419 struct rtl_priv *rtlpriv = rtl_priv(hw); 1420 u16 tmpu2b; 1421 u8 tmpu1b; 1422 1423 rtlpriv->psc.pwrdomain_protect = true; 1424 1425 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 1426 if (tmpu1b & BIT(7)) { 1427 tmpu1b &= ~(BIT(6) | BIT(7)); 1428 if (!_rtl92s_set_sysclk(hw, tmpu1b)) { 1429 rtlpriv->psc.pwrdomain_protect = false; 1430 return; 1431 } 1432 } 1433 1434 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0); 1435 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34); 1436 1437 /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */ 1438 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1439 1440 /* If IPS we need to turn LED on. So we not 1441 * not disable BIT 3/7 of reg3. */ 1442 if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW)) 1443 tmpu1b &= 0xFB; 1444 else 1445 tmpu1b &= 0x73; 1446 1447 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b); 1448 /* wait for BIT 10/11/15 to pull high automatically!! */ 1449 mdelay(1); 1450 1451 rtl_write_byte(rtlpriv, CMDR, 0); 1452 rtl_write_byte(rtlpriv, TCR, 0); 1453 1454 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */ 1455 tmpu1b = rtl_read_byte(rtlpriv, 0x562); 1456 tmpu1b |= 0x08; 1457 rtl_write_byte(rtlpriv, 0x562, tmpu1b); 1458 tmpu1b &= ~(BIT(3)); 1459 rtl_write_byte(rtlpriv, 0x562, tmpu1b); 1460 1461 /* Enable AFE clock source */ 1462 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL); 1463 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01)); 1464 /* Delay 1.5ms */ 1465 udelay(1500); 1466 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1); 1467 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb)); 1468 1469 /* Enable AFE Macro Block's Bandgap */ 1470 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC); 1471 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0))); 1472 mdelay(1); 1473 1474 /* Enable AFE Mbias */ 1475 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC); 1476 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02)); 1477 mdelay(1); 1478 1479 /* Enable LDOA15 block */ 1480 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL); 1481 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0))); 1482 1483 /* Set Digital Vdd to Retention isolation Path. */ 1484 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); 1485 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11))); 1486 1487 1488 /* For warm reboot NIC disappera bug. */ 1489 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1490 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13))); 1491 1492 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68); 1493 1494 /* Enable AFE PLL Macro Block */ 1495 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL); 1496 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4))); 1497 /* Enable MAC 80MHZ clock */ 1498 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1); 1499 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0))); 1500 mdelay(1); 1501 1502 /* Release isolation AFE PLL & MD */ 1503 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6); 1504 1505 /* Enable MAC clock */ 1506 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR); 1507 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11))); 1508 1509 /* Enable Core digital and enable IOREG R/W */ 1510 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1511 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11))); 1512 /* enable REG_EN */ 1513 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15))); 1514 1515 /* Switch the control path. */ 1516 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR); 1517 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2)))); 1518 1519 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1)); 1520 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6))); 1521 if (!_rtl92s_set_sysclk(hw, tmpu1b)) { 1522 rtlpriv->psc.pwrdomain_protect = false; 1523 return; 1524 } 1525 1526 rtl_write_word(rtlpriv, CMDR, 0x37FC); 1527 1528 /* After MACIO reset,we must refresh LED state. */ 1529 _rtl92se_gen_refreshledstate(hw); 1530 1531 rtlpriv->psc.pwrdomain_protect = false; 1532 } 1533 1534 void rtl92se_card_disable(struct ieee80211_hw *hw) 1535 { 1536 struct rtl_priv *rtlpriv = rtl_priv(hw); 1537 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1538 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1539 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1540 enum nl80211_iftype opmode; 1541 u8 wait = 30; 1542 1543 rtlpriv->intf_ops->enable_aspm(hw); 1544 1545 if (rtlpci->driver_is_goingto_unload || 1546 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1547 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1548 1549 /* we should chnge GPIO to input mode 1550 * this will drop away current about 25mA*/ 1551 rtl8192se_gpiobit3_cfg_inputmode(hw); 1552 1553 /* this is very important for ips power save */ 1554 while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) { 1555 if (rtlpriv->psc.pwrdomain_protect) 1556 mdelay(20); 1557 else 1558 break; 1559 } 1560 1561 mac->link_state = MAC80211_NOLINK; 1562 opmode = NL80211_IFTYPE_UNSPECIFIED; 1563 _rtl92se_set_media_status(hw, opmode); 1564 1565 _rtl92s_phy_set_rfhalt(hw); 1566 udelay(100); 1567 } 1568 1569 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta, 1570 u32 *p_intb) 1571 { 1572 struct rtl_priv *rtlpriv = rtl_priv(hw); 1573 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1574 1575 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 1576 rtl_write_dword(rtlpriv, ISR, *p_inta); 1577 1578 *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1]; 1579 rtl_write_dword(rtlpriv, ISR + 4, *p_intb); 1580 } 1581 1582 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw) 1583 { 1584 struct rtl_priv *rtlpriv = rtl_priv(hw); 1585 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1586 u16 bcntime_cfg = 0; 1587 u16 bcn_cw = 6, bcn_ifs = 0xf; 1588 u16 atim_window = 2; 1589 1590 /* ATIM Window (in unit of TU). */ 1591 rtl_write_word(rtlpriv, ATIMWND, atim_window); 1592 1593 /* Beacon interval (in unit of TU). */ 1594 rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval); 1595 1596 /* DrvErlyInt (in unit of TU). (Time to send 1597 * interrupt to notify driver to change 1598 * beacon content) */ 1599 rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4); 1600 1601 /* BcnDMATIM(in unit of us). Indicates the 1602 * time before TBTT to perform beacon queue DMA */ 1603 rtl_write_word(rtlpriv, BCN_DMATIME, 256); 1604 1605 /* Force beacon frame transmission even 1606 * after receiving beacon frame from 1607 * other ad hoc STA */ 1608 rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100); 1609 1610 /* Beacon Time Configuration */ 1611 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1612 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT); 1613 1614 /* TODO: bcn_ifs may required to be changed on ASIC */ 1615 bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS; 1616 1617 /*for beacon changed */ 1618 rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval); 1619 } 1620 1621 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw) 1622 { 1623 struct rtl_priv *rtlpriv = rtl_priv(hw); 1624 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1625 u16 bcn_interval = mac->beacon_interval; 1626 1627 /* Beacon interval (in unit of TU). */ 1628 rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval); 1629 /* 2008.10.24 added by tynli for beacon changed. */ 1630 rtl92s_phy_set_beacon_hwreg(hw, bcn_interval); 1631 } 1632 1633 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw, 1634 u32 add_msr, u32 rm_msr) 1635 { 1636 struct rtl_priv *rtlpriv = rtl_priv(hw); 1637 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1638 1639 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n", 1640 add_msr, rm_msr); 1641 1642 if (add_msr) 1643 rtlpci->irq_mask[0] |= add_msr; 1644 1645 if (rm_msr) 1646 rtlpci->irq_mask[0] &= (~rm_msr); 1647 1648 rtl92se_disable_interrupt(hw); 1649 rtl92se_enable_interrupt(hw); 1650 } 1651 1652 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw) 1653 { 1654 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1655 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1656 u8 efuse_id; 1657 1658 rtlhal->ic_class = IC_INFERIORITY_A; 1659 1660 /* Only retrieving while using EFUSE. */ 1661 if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) && 1662 !rtlefuse->autoload_failflag) { 1663 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET); 1664 1665 if (efuse_id == 0xfe) 1666 rtlhal->ic_class = IC_INFERIORITY_B; 1667 } 1668 } 1669 1670 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw) 1671 { 1672 struct rtl_priv *rtlpriv = rtl_priv(hw); 1673 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1674 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1675 struct device *dev = &rtl_pcipriv(hw)->dev.pdev->dev; 1676 u16 i, usvalue; 1677 u16 eeprom_id; 1678 u8 tempval; 1679 u8 hwinfo[HWSET_MAX_SIZE_92S]; 1680 u8 rf_path, index; 1681 1682 switch (rtlefuse->epromtype) { 1683 case EEPROM_BOOT_EFUSE: 1684 rtl_efuse_shadow_map_update(hw); 1685 break; 1686 1687 case EEPROM_93C46: 1688 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1689 "RTL819X Not boot from eeprom, check it !!\n"); 1690 return; 1691 1692 default: 1693 dev_warn(dev, "no efuse data\n"); 1694 return; 1695 } 1696 1697 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0], 1698 HWSET_MAX_SIZE_92S); 1699 1700 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP", 1701 hwinfo, HWSET_MAX_SIZE_92S); 1702 1703 eeprom_id = *((u16 *)&hwinfo[0]); 1704 if (eeprom_id != RTL8190_EEPROM_ID) { 1705 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1706 "EEPROM ID(%#x) is invalid!!\n", eeprom_id); 1707 rtlefuse->autoload_failflag = true; 1708 } else { 1709 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1710 rtlefuse->autoload_failflag = false; 1711 } 1712 1713 if (rtlefuse->autoload_failflag) 1714 return; 1715 1716 _rtl8192se_get_IC_Inferiority(hw); 1717 1718 /* Read IC Version && Channel Plan */ 1719 /* VID, DID SE 0xA-D */ 1720 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID]; 1721 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID]; 1722 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID]; 1723 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID]; 1724 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION]; 1725 1726 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1727 "EEPROMId = 0x%4x\n", eeprom_id); 1728 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1729 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid); 1730 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1731 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did); 1732 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1733 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid); 1734 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1735 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid); 1736 1737 for (i = 0; i < 6; i += 2) { 1738 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i]; 1739 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; 1740 } 1741 1742 for (i = 0; i < 6; i++) 1743 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]); 1744 1745 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); 1746 1747 /* Get Tx Power Level by Channel */ 1748 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */ 1749 /* 92S suupport RF A & B */ 1750 for (rf_path = 0; rf_path < 2; rf_path++) { 1751 for (i = 0; i < 3; i++) { 1752 /* Read CCK RF A & B Tx power */ 1753 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] = 1754 hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i]; 1755 1756 /* Read OFDM RF A & B Tx power for 1T */ 1757 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1758 hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i]; 1759 1760 /* Read OFDM RF A & B Tx power for 2T */ 1761 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][i] 1762 = hwinfo[EEPROM_TXPOWERBASE + 12 + 1763 rf_path * 3 + i]; 1764 } 1765 } 1766 1767 for (rf_path = 0; rf_path < 2; rf_path++) 1768 for (i = 0; i < 3; i++) 1769 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1770 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", 1771 rf_path, i, 1772 rtlefuse->eeprom_chnlarea_txpwr_cck 1773 [rf_path][i]); 1774 for (rf_path = 0; rf_path < 2; rf_path++) 1775 for (i = 0; i < 3; i++) 1776 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1777 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 1778 rf_path, i, 1779 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1780 [rf_path][i]); 1781 for (rf_path = 0; rf_path < 2; rf_path++) 1782 for (i = 0; i < 3; i++) 1783 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1784 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 1785 rf_path, i, 1786 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1787 [rf_path][i]); 1788 1789 for (rf_path = 0; rf_path < 2; rf_path++) { 1790 1791 /* Assign dedicated channel tx power */ 1792 for (i = 0; i < 14; i++) { 1793 /* channel 1~3 use the same Tx Power Level. */ 1794 if (i < 3) 1795 index = 0; 1796 /* Channel 4-8 */ 1797 else if (i < 8) 1798 index = 1; 1799 /* Channel 9-14 */ 1800 else 1801 index = 2; 1802 1803 /* Record A & B CCK /OFDM - 1T/2T Channel area 1804 * tx power */ 1805 rtlefuse->txpwrlevel_cck[rf_path][i] = 1806 rtlefuse->eeprom_chnlarea_txpwr_cck 1807 [rf_path][index]; 1808 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 1809 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s 1810 [rf_path][index]; 1811 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 1812 rtlefuse->eprom_chnl_txpwr_ht40_2sdf 1813 [rf_path][index]; 1814 } 1815 1816 for (i = 0; i < 14; i++) { 1817 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1818 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", 1819 rf_path, i, 1820 rtlefuse->txpwrlevel_cck[rf_path][i], 1821 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 1822 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 1823 } 1824 } 1825 1826 for (rf_path = 0; rf_path < 2; rf_path++) { 1827 for (i = 0; i < 3; i++) { 1828 /* Read Power diff limit. */ 1829 rtlefuse->eeprom_pwrgroup[rf_path][i] = 1830 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i]; 1831 } 1832 } 1833 1834 for (rf_path = 0; rf_path < 2; rf_path++) { 1835 /* Fill Pwr group */ 1836 for (i = 0; i < 14; i++) { 1837 /* Chanel 1-3 */ 1838 if (i < 3) 1839 index = 0; 1840 /* Channel 4-8 */ 1841 else if (i < 8) 1842 index = 1; 1843 /* Channel 9-13 */ 1844 else 1845 index = 2; 1846 1847 rtlefuse->pwrgroup_ht20[rf_path][i] = 1848 (rtlefuse->eeprom_pwrgroup[rf_path][index] & 1849 0xf); 1850 rtlefuse->pwrgroup_ht40[rf_path][i] = 1851 ((rtlefuse->eeprom_pwrgroup[rf_path][index] & 1852 0xf0) >> 4); 1853 1854 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1855 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", 1856 rf_path, i, 1857 rtlefuse->pwrgroup_ht20[rf_path][i]); 1858 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1859 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", 1860 rf_path, i, 1861 rtlefuse->pwrgroup_ht40[rf_path][i]); 1862 } 1863 } 1864 1865 for (i = 0; i < 14; i++) { 1866 /* Read tx power difference between HT OFDM 20/40 MHZ */ 1867 /* channel 1-3 */ 1868 if (i < 3) 1869 index = 0; 1870 /* Channel 4-8 */ 1871 else if (i < 8) 1872 index = 1; 1873 /* Channel 9-14 */ 1874 else 1875 index = 2; 1876 1877 tempval = hwinfo[EEPROM_TX_PWR_HT20_DIFF + index] & 0xff; 1878 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 1879 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 1880 ((tempval >> 4) & 0xF); 1881 1882 /* Read OFDM<->HT tx power diff */ 1883 /* Channel 1-3 */ 1884 if (i < 3) 1885 index = 0; 1886 /* Channel 4-8 */ 1887 else if (i < 8) 1888 index = 0x11; 1889 /* Channel 9-14 */ 1890 else 1891 index = 1; 1892 1893 tempval = hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index] & 0xff; 1894 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = 1895 (tempval & 0xF); 1896 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 1897 ((tempval >> 4) & 0xF); 1898 1899 tempval = hwinfo[TX_PWR_SAFETY_CHK]; 1900 rtlefuse->txpwr_safetyflag = (tempval & 0x01); 1901 } 1902 1903 rtlefuse->eeprom_regulatory = 0; 1904 if (rtlefuse->eeprom_version >= 2) { 1905 /* BIT(0)~2 */ 1906 if (rtlefuse->eeprom_version >= 4) 1907 rtlefuse->eeprom_regulatory = 1908 (hwinfo[EEPROM_REGULATORY] & 0x7); 1909 else /* BIT(0) */ 1910 rtlefuse->eeprom_regulatory = 1911 (hwinfo[EEPROM_REGULATORY] & 0x1); 1912 } 1913 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1914 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 1915 1916 for (i = 0; i < 14; i++) 1917 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1918 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", 1919 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 1920 for (i = 0; i < 14; i++) 1921 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1922 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", 1923 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 1924 for (i = 0; i < 14; i++) 1925 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1926 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", 1927 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 1928 for (i = 0; i < 14; i++) 1929 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1930 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", 1931 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 1932 1933 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1934 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag); 1935 1936 /* Read RF-indication and Tx Power gain 1937 * index diff of legacy to HT OFDM rate. */ 1938 tempval = hwinfo[EEPROM_RFIND_POWERDIFF] & 0xff; 1939 rtlefuse->eeprom_txpowerdiff = tempval; 1940 rtlefuse->legacy_httxpowerdiff = 1941 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0]; 1942 1943 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1944 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff); 1945 1946 /* Get TSSI value for each path. */ 1947 usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A]; 1948 rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8); 1949 usvalue = hwinfo[EEPROM_TSSI_B]; 1950 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff); 1951 1952 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 1953 rtlefuse->eeprom_tssi[RF90_PATH_A], 1954 rtlefuse->eeprom_tssi[RF90_PATH_B]); 1955 1956 /* Read antenna tx power offset of B/C/D to A from EEPROM */ 1957 /* and read ThermalMeter from EEPROM */ 1958 tempval = hwinfo[EEPROM_THERMALMETER]; 1959 rtlefuse->eeprom_thermalmeter = tempval; 1960 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1961 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1962 1963 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */ 1964 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f); 1965 rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100; 1966 1967 /* Read CrystalCap from EEPROM */ 1968 tempval = hwinfo[EEPROM_CRYSTALCAP] >> 4; 1969 rtlefuse->eeprom_crystalcap = tempval; 1970 /* CrystalCap, BIT(12)~15 */ 1971 rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap; 1972 1973 /* Read IC Version && Channel Plan */ 1974 /* Version ID, Channel plan */ 1975 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN]; 1976 rtlefuse->txpwr_fromeprom = true; 1977 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1978 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan); 1979 1980 /* Read Customer ID or Board Type!!! */ 1981 tempval = hwinfo[EEPROM_BOARDTYPE]; 1982 /* Change RF type definition */ 1983 if (tempval == 0) 1984 rtlphy->rf_type = RF_2T2R; 1985 else if (tempval == 1) 1986 rtlphy->rf_type = RF_1T2R; 1987 else if (tempval == 2) 1988 rtlphy->rf_type = RF_1T2R; 1989 else if (tempval == 3) 1990 rtlphy->rf_type = RF_1T1R; 1991 1992 /* 1T2R but 1SS (1x1 receive combining) */ 1993 rtlefuse->b1x1_recvcombine = false; 1994 if (rtlphy->rf_type == RF_1T2R) { 1995 tempval = rtl_read_byte(rtlpriv, 0x07); 1996 if (!(tempval & BIT(0))) { 1997 rtlefuse->b1x1_recvcombine = true; 1998 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1999 "RF_TYPE=1T2R but only 1SS\n"); 2000 } 2001 } 2002 rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine; 2003 rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMID]; 2004 2005 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n", 2006 rtlefuse->eeprom_oemid); 2007 2008 /* set channel paln to world wide 13 */ 2009 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13; 2010 } 2011 2012 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw) 2013 { 2014 struct rtl_priv *rtlpriv = rtl_priv(hw); 2015 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2016 u8 tmp_u1b = 0; 2017 2018 tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD); 2019 2020 if (tmp_u1b & BIT(4)) { 2021 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 2022 rtlefuse->epromtype = EEPROM_93C46; 2023 } else { 2024 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 2025 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 2026 } 2027 2028 if (tmp_u1b & BIT(5)) { 2029 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 2030 rtlefuse->autoload_failflag = false; 2031 _rtl92se_read_adapter_info(hw); 2032 } else { 2033 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n"); 2034 rtlefuse->autoload_failflag = true; 2035 } 2036 } 2037 2038 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw, 2039 struct ieee80211_sta *sta) 2040 { 2041 struct rtl_priv *rtlpriv = rtl_priv(hw); 2042 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2043 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2044 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2045 u32 ratr_value; 2046 u8 ratr_index = 0; 2047 u8 nmode = mac->ht_enable; 2048 u8 mimo_ps = IEEE80211_SMPS_OFF; 2049 u16 shortgi_rate = 0; 2050 u32 tmp_ratr_value = 0; 2051 u8 curtxbw_40mhz = mac->bw_40; 2052 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2053 1 : 0; 2054 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2055 1 : 0; 2056 enum wireless_mode wirelessmode = mac->mode; 2057 2058 if (rtlhal->current_bandtype == BAND_ON_5G) 2059 ratr_value = sta->supp_rates[1] << 4; 2060 else 2061 ratr_value = sta->supp_rates[0]; 2062 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2063 ratr_value = 0xfff; 2064 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 2065 sta->ht_cap.mcs.rx_mask[0] << 12); 2066 switch (wirelessmode) { 2067 case WIRELESS_MODE_B: 2068 ratr_value &= 0x0000000D; 2069 break; 2070 case WIRELESS_MODE_G: 2071 ratr_value &= 0x00000FF5; 2072 break; 2073 case WIRELESS_MODE_N_24G: 2074 case WIRELESS_MODE_N_5G: 2075 nmode = 1; 2076 if (mimo_ps == IEEE80211_SMPS_STATIC) { 2077 ratr_value &= 0x0007F005; 2078 } else { 2079 u32 ratr_mask; 2080 2081 if (get_rf_type(rtlphy) == RF_1T2R || 2082 get_rf_type(rtlphy) == RF_1T1R) { 2083 if (curtxbw_40mhz) 2084 ratr_mask = 0x000ff015; 2085 else 2086 ratr_mask = 0x000ff005; 2087 } else { 2088 if (curtxbw_40mhz) 2089 ratr_mask = 0x0f0ff015; 2090 else 2091 ratr_mask = 0x0f0ff005; 2092 } 2093 2094 ratr_value &= ratr_mask; 2095 } 2096 break; 2097 default: 2098 if (rtlphy->rf_type == RF_1T2R) 2099 ratr_value &= 0x000ff0ff; 2100 else 2101 ratr_value &= 0x0f0ff0ff; 2102 2103 break; 2104 } 2105 2106 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT) 2107 ratr_value &= 0x0FFFFFFF; 2108 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT) 2109 ratr_value &= 0x0FFFFFF0; 2110 2111 if (nmode && ((curtxbw_40mhz && 2112 curshortgi_40mhz) || (!curtxbw_40mhz && 2113 curshortgi_20mhz))) { 2114 2115 ratr_value |= 0x10000000; 2116 tmp_ratr_value = (ratr_value >> 12); 2117 2118 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 2119 if ((1 << shortgi_rate) & tmp_ratr_value) 2120 break; 2121 } 2122 2123 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 2124 (shortgi_rate << 4) | (shortgi_rate); 2125 2126 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate); 2127 } 2128 2129 rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value); 2130 if (ratr_value & 0xfffff000) 2131 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N); 2132 else 2133 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG); 2134 2135 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", 2136 rtl_read_dword(rtlpriv, ARFR0)); 2137 } 2138 2139 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw, 2140 struct ieee80211_sta *sta, 2141 u8 rssi_level) 2142 { 2143 struct rtl_priv *rtlpriv = rtl_priv(hw); 2144 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2145 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2146 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2147 struct rtl_sta_info *sta_entry = NULL; 2148 u32 ratr_bitmap; 2149 u8 ratr_index = 0; 2150 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; 2151 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2152 1 : 0; 2153 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2154 1 : 0; 2155 enum wireless_mode wirelessmode = 0; 2156 bool shortgi = false; 2157 u32 ratr_value = 0; 2158 u8 shortgi_rate = 0; 2159 u32 mask = 0; 2160 u32 band = 0; 2161 bool bmulticast = false; 2162 u8 macid = 0; 2163 u8 mimo_ps = IEEE80211_SMPS_OFF; 2164 2165 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 2166 wirelessmode = sta_entry->wireless_mode; 2167 if (mac->opmode == NL80211_IFTYPE_STATION) 2168 curtxbw_40mhz = mac->bw_40; 2169 else if (mac->opmode == NL80211_IFTYPE_AP || 2170 mac->opmode == NL80211_IFTYPE_ADHOC) 2171 macid = sta->aid + 1; 2172 2173 if (rtlhal->current_bandtype == BAND_ON_5G) 2174 ratr_bitmap = sta->supp_rates[1] << 4; 2175 else 2176 ratr_bitmap = sta->supp_rates[0]; 2177 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2178 ratr_bitmap = 0xfff; 2179 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 2180 sta->ht_cap.mcs.rx_mask[0] << 12); 2181 switch (wirelessmode) { 2182 case WIRELESS_MODE_B: 2183 band |= WIRELESS_11B; 2184 ratr_index = RATR_INX_WIRELESS_B; 2185 if (ratr_bitmap & 0x0000000c) 2186 ratr_bitmap &= 0x0000000d; 2187 else 2188 ratr_bitmap &= 0x0000000f; 2189 break; 2190 case WIRELESS_MODE_G: 2191 band |= (WIRELESS_11G | WIRELESS_11B); 2192 ratr_index = RATR_INX_WIRELESS_GB; 2193 2194 if (rssi_level == 1) 2195 ratr_bitmap &= 0x00000f00; 2196 else if (rssi_level == 2) 2197 ratr_bitmap &= 0x00000ff0; 2198 else 2199 ratr_bitmap &= 0x00000ff5; 2200 break; 2201 case WIRELESS_MODE_A: 2202 band |= WIRELESS_11A; 2203 ratr_index = RATR_INX_WIRELESS_A; 2204 ratr_bitmap &= 0x00000ff0; 2205 break; 2206 case WIRELESS_MODE_N_24G: 2207 case WIRELESS_MODE_N_5G: 2208 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B); 2209 ratr_index = RATR_INX_WIRELESS_NGB; 2210 2211 if (mimo_ps == IEEE80211_SMPS_STATIC) { 2212 if (rssi_level == 1) 2213 ratr_bitmap &= 0x00070000; 2214 else if (rssi_level == 2) 2215 ratr_bitmap &= 0x0007f000; 2216 else 2217 ratr_bitmap &= 0x0007f005; 2218 } else { 2219 if (rtlphy->rf_type == RF_1T2R || 2220 rtlphy->rf_type == RF_1T1R) { 2221 if (rssi_level == 1) { 2222 ratr_bitmap &= 0x000f0000; 2223 } else if (rssi_level == 3) { 2224 ratr_bitmap &= 0x000fc000; 2225 } else if (rssi_level == 5) { 2226 ratr_bitmap &= 0x000ff000; 2227 } else { 2228 if (curtxbw_40mhz) 2229 ratr_bitmap &= 0x000ff015; 2230 else 2231 ratr_bitmap &= 0x000ff005; 2232 } 2233 } else { 2234 if (rssi_level == 1) { 2235 ratr_bitmap &= 0x0f8f0000; 2236 } else if (rssi_level == 3) { 2237 ratr_bitmap &= 0x0f8fc000; 2238 } else if (rssi_level == 5) { 2239 ratr_bitmap &= 0x0f8ff000; 2240 } else { 2241 if (curtxbw_40mhz) 2242 ratr_bitmap &= 0x0f8ff015; 2243 else 2244 ratr_bitmap &= 0x0f8ff005; 2245 } 2246 } 2247 } 2248 2249 if ((curtxbw_40mhz && curshortgi_40mhz) || 2250 (!curtxbw_40mhz && curshortgi_20mhz)) { 2251 if (macid == 0) 2252 shortgi = true; 2253 else if (macid == 1) 2254 shortgi = false; 2255 } 2256 break; 2257 default: 2258 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B); 2259 ratr_index = RATR_INX_WIRELESS_NGB; 2260 2261 if (rtlphy->rf_type == RF_1T2R) 2262 ratr_bitmap &= 0x000ff0ff; 2263 else 2264 ratr_bitmap &= 0x0f8ff0ff; 2265 break; 2266 } 2267 sta_entry->ratr_index = ratr_index; 2268 2269 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT) 2270 ratr_bitmap &= 0x0FFFFFFF; 2271 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT) 2272 ratr_bitmap &= 0x0FFFFFF0; 2273 2274 if (shortgi) { 2275 ratr_bitmap |= 0x10000000; 2276 /* Get MAX MCS available. */ 2277 ratr_value = (ratr_bitmap >> 12); 2278 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 2279 if ((1 << shortgi_rate) & ratr_value) 2280 break; 2281 } 2282 2283 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 2284 (shortgi_rate << 4) | (shortgi_rate); 2285 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate); 2286 } 2287 2288 mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf); 2289 2290 RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n", 2291 mask, ratr_bitmap); 2292 rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap); 2293 rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8))); 2294 2295 if (macid != 0) 2296 sta_entry->ratr_index = ratr_index; 2297 } 2298 2299 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw, 2300 struct ieee80211_sta *sta, u8 rssi_level) 2301 { 2302 struct rtl_priv *rtlpriv = rtl_priv(hw); 2303 2304 if (rtlpriv->dm.useramask) 2305 rtl92se_update_hal_rate_mask(hw, sta, rssi_level); 2306 else 2307 rtl92se_update_hal_rate_table(hw, sta); 2308 } 2309 2310 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw) 2311 { 2312 struct rtl_priv *rtlpriv = rtl_priv(hw); 2313 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2314 u16 sifs_timer; 2315 2316 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2317 &mac->slot_time); 2318 sifs_timer = 0x0e0e; 2319 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2320 2321 } 2322 2323 /* this ifunction is for RFKILL, it's different with windows, 2324 * because UI will disable wireless when GPIO Radio Off. 2325 * And here we not check or Disable/Enable ASPM like windows*/ 2326 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2327 { 2328 struct rtl_priv *rtlpriv = rtl_priv(hw); 2329 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2330 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2331 enum rf_pwrstate rfpwr_toset /*, cur_rfstate */; 2332 unsigned long flag = 0; 2333 bool actuallyset = false; 2334 bool turnonbypowerdomain = false; 2335 2336 /* just 8191se can check gpio before firstup, 92c/92d have fixed it */ 2337 if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter)) 2338 return false; 2339 2340 if (ppsc->swrf_processing) 2341 return false; 2342 2343 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2344 if (ppsc->rfchange_inprogress) { 2345 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2346 return false; 2347 } else { 2348 ppsc->rfchange_inprogress = true; 2349 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2350 } 2351 2352 /* cur_rfstate = ppsc->rfpwr_state;*/ 2353 2354 /* because after _rtl92s_phy_set_rfhalt, all power 2355 * closed, so we must open some power for GPIO check, 2356 * or we will always check GPIO RFOFF here, 2357 * And we should close power after GPIO check */ 2358 if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 2359 _rtl92se_power_domain_init(hw); 2360 turnonbypowerdomain = true; 2361 } 2362 2363 rfpwr_toset = _rtl92se_rf_onoff_detect(hw); 2364 2365 if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) { 2366 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2367 "RFKILL-HW Radio ON, RF ON\n"); 2368 2369 rfpwr_toset = ERFON; 2370 ppsc->hwradiooff = false; 2371 actuallyset = true; 2372 } else if ((!ppsc->hwradiooff) && (rfpwr_toset == ERFOFF)) { 2373 RT_TRACE(rtlpriv, COMP_RF, 2374 DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n"); 2375 2376 rfpwr_toset = ERFOFF; 2377 ppsc->hwradiooff = true; 2378 actuallyset = true; 2379 } 2380 2381 if (actuallyset) { 2382 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2383 ppsc->rfchange_inprogress = false; 2384 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2385 2386 /* this not include ifconfig wlan0 down case */ 2387 /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */ 2388 } else { 2389 /* because power_domain_init may be happen when 2390 * _rtl92s_phy_set_rfhalt, this will open some powers 2391 * and cause current increasing about 40 mA for ips, 2392 * rfoff and ifconfig down, so we set 2393 * _rtl92s_phy_set_rfhalt again here */ 2394 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC && 2395 turnonbypowerdomain) { 2396 _rtl92s_phy_set_rfhalt(hw); 2397 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2398 } 2399 2400 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2401 ppsc->rfchange_inprogress = false; 2402 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2403 } 2404 2405 *valid = 1; 2406 return !ppsc->hwradiooff; 2407 2408 } 2409 2410 /* Is_wepkey just used for WEP used as group & pairwise key 2411 * if pairwise is AES ang group is WEP Is_wepkey == false.*/ 2412 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr, 2413 bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all) 2414 { 2415 struct rtl_priv *rtlpriv = rtl_priv(hw); 2416 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2417 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2418 u8 *macaddr = p_macaddr; 2419 2420 u32 entry_id = 0; 2421 bool is_pairwise = false; 2422 2423 static u8 cam_const_addr[4][6] = { 2424 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2425 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2426 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2427 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2428 }; 2429 static u8 cam_const_broad[] = { 2430 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2431 }; 2432 2433 if (clear_all) { 2434 u8 idx = 0; 2435 u8 cam_offset = 0; 2436 u8 clear_number = 5; 2437 2438 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2439 2440 for (idx = 0; idx < clear_number; idx++) { 2441 rtl_cam_mark_invalid(hw, cam_offset + idx); 2442 rtl_cam_empty_entry(hw, cam_offset + idx); 2443 2444 if (idx < 5) { 2445 memset(rtlpriv->sec.key_buf[idx], 0, 2446 MAX_KEY_LEN); 2447 rtlpriv->sec.key_len[idx] = 0; 2448 } 2449 } 2450 2451 } else { 2452 switch (enc_algo) { 2453 case WEP40_ENCRYPTION: 2454 enc_algo = CAM_WEP40; 2455 break; 2456 case WEP104_ENCRYPTION: 2457 enc_algo = CAM_WEP104; 2458 break; 2459 case TKIP_ENCRYPTION: 2460 enc_algo = CAM_TKIP; 2461 break; 2462 case AESCCMP_ENCRYPTION: 2463 enc_algo = CAM_AES; 2464 break; 2465 default: 2466 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2467 "switch case %#x not processed\n", enc_algo); 2468 enc_algo = CAM_TKIP; 2469 break; 2470 } 2471 2472 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2473 macaddr = cam_const_addr[key_index]; 2474 entry_id = key_index; 2475 } else { 2476 if (is_group) { 2477 macaddr = cam_const_broad; 2478 entry_id = key_index; 2479 } else { 2480 if (mac->opmode == NL80211_IFTYPE_AP) { 2481 entry_id = rtl_cam_get_free_entry(hw, 2482 p_macaddr); 2483 if (entry_id >= TOTAL_CAM_ENTRY) { 2484 RT_TRACE(rtlpriv, 2485 COMP_SEC, DBG_EMERG, 2486 "Can not find free hw security cam entry\n"); 2487 return; 2488 } 2489 } else { 2490 entry_id = CAM_PAIRWISE_KEY_POSITION; 2491 } 2492 2493 key_index = PAIRWISE_KEYIDX; 2494 is_pairwise = true; 2495 } 2496 } 2497 2498 if (rtlpriv->sec.key_len[key_index] == 0) { 2499 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2500 "delete one entry, entry_id is %d\n", 2501 entry_id); 2502 if (mac->opmode == NL80211_IFTYPE_AP) 2503 rtl_cam_del_entry(hw, p_macaddr); 2504 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2505 } else { 2506 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2507 "add one entry\n"); 2508 if (is_pairwise) { 2509 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2510 "set Pairwise key\n"); 2511 2512 rtl_cam_add_one_entry(hw, macaddr, key_index, 2513 entry_id, enc_algo, 2514 CAM_CONFIG_NO_USEDK, 2515 rtlpriv->sec.key_buf[key_index]); 2516 } else { 2517 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2518 "set group key\n"); 2519 2520 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2521 rtl_cam_add_one_entry(hw, 2522 rtlefuse->dev_addr, 2523 PAIRWISE_KEYIDX, 2524 CAM_PAIRWISE_KEY_POSITION, 2525 enc_algo, CAM_CONFIG_NO_USEDK, 2526 rtlpriv->sec.key_buf[entry_id]); 2527 } 2528 2529 rtl_cam_add_one_entry(hw, macaddr, key_index, 2530 entry_id, enc_algo, 2531 CAM_CONFIG_NO_USEDK, 2532 rtlpriv->sec.key_buf[entry_id]); 2533 } 2534 2535 } 2536 } 2537 } 2538 2539 void rtl92se_suspend(struct ieee80211_hw *hw) 2540 { 2541 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2542 2543 rtlpci->up_first_time = true; 2544 } 2545 2546 void rtl92se_resume(struct ieee80211_hw *hw) 2547 { 2548 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2549 u32 val; 2550 2551 pci_read_config_dword(rtlpci->pdev, 0x40, &val); 2552 if ((val & 0x0000ff00) != 0) 2553 pci_write_config_dword(rtlpci->pdev, 0x40, 2554 val & 0xffff00ff); 2555 } 2556