1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 #ifndef __REALTEK_FIRMWARE92S_H__ 26 #define __REALTEK_FIRMWARE92S_H__ 27 28 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 29 #define RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE 90000 30 #define RTL8190_CPU_START_OFFSET 0x80 31 /* Firmware Local buffer size. 64k */ 32 #define MAX_FIRMWARE_CODE_SIZE 0xFF00 33 34 #define RT_8192S_FIRMWARE_HDR_SIZE 80 35 #define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE 32 36 37 /* support till 64 bit bus width OS */ 38 #define MAX_DEV_ADDR_SIZE 8 39 #define MAX_FIRMWARE_INFORMATION_SIZE 32 40 #define MAX_802_11_HEADER_LENGTH (40 + \ 41 MAX_FIRMWARE_INFORMATION_SIZE) 42 #define ENCRYPTION_MAX_OVERHEAD 128 43 #define MAX_FRAGMENT_COUNT 8 44 #define MAX_TRANSMIT_BUFFER_SIZE (1600 + \ 45 (MAX_802_11_HEADER_LENGTH + \ 46 ENCRYPTION_MAX_OVERHEAD) *\ 47 MAX_FRAGMENT_COUNT) 48 49 #define H2C_TX_CMD_HDR_LEN 8 50 51 /* The following DM control code are for Reg0x364, */ 52 #define FW_DIG_ENABLE_CTL BIT(0) 53 #define FW_HIGH_PWR_ENABLE_CTL BIT(1) 54 #define FW_SS_CTL BIT(2) 55 #define FW_RA_INIT_CTL BIT(3) 56 #define FW_RA_BG_CTL BIT(4) 57 #define FW_RA_N_CTL BIT(5) 58 #define FW_PWR_TRK_CTL BIT(6) 59 #define FW_IQK_CTL BIT(7) 60 #define FW_FA_CTL BIT(8) 61 #define FW_DRIVER_CTRL_DM_CTL BIT(9) 62 #define FW_PAPE_CTL_BY_SW_HW BIT(10) 63 #define FW_DISABLE_ALL_DM 0 64 #define FW_PWR_TRK_PARAM_CLR 0x0000ffff 65 #define FW_RA_PARAM_CLR 0xffff0000 66 67 enum desc_packet_type { 68 DESC_PACKET_TYPE_INIT = 0, 69 DESC_PACKET_TYPE_NORMAL = 1, 70 }; 71 72 /* 8-bytes alignment required */ 73 struct fw_priv { 74 /* --- long word 0 ---- */ 75 /* 0x12: CE product, 0x92: IT product */ 76 u8 signature_0; 77 /* 0x87: CE product, 0x81: IT product */ 78 u8 signature_1; 79 /* 0x81: PCI-AP, 01:PCIe, 02: 92S-U, 80 * 0x82: USB-AP, 0x12: 72S-U, 03:SDIO */ 81 u8 hci_sel; 82 /* the same value as reigster value */ 83 u8 chip_version; 84 /* customer ID low byte */ 85 u8 customer_id_0; 86 /* customer ID high byte */ 87 u8 customer_id_1; 88 /* 0x11: 1T1R, 0x12: 1T2R, 89 * 0x92: 1T2R turbo, 0x22: 2T2R */ 90 u8 rf_config; 91 /* 4: 4EP, 6: 6EP, 11: 11EP */ 92 u8 usb_ep_num; 93 94 /* --- long word 1 ---- */ 95 /* regulatory class bit map 0 */ 96 u8 regulatory_class_0; 97 /* regulatory class bit map 1 */ 98 u8 regulatory_class_1; 99 /* regulatory class bit map 2 */ 100 u8 regulatory_class_2; 101 /* regulatory class bit map 3 */ 102 u8 regulatory_class_3; 103 /* 0:SWSI, 1:HWSI, 2:HWPI */ 104 u8 rfintfs; 105 u8 def_nettype; 106 u8 rsvd010; 107 u8 rsvd011; 108 109 /* --- long word 2 ---- */ 110 /* 0x00: normal, 0x03: MACLBK, 0x01: PHYLBK */ 111 u8 lbk_mode; 112 /* 1: for MP use, 0: for normal 113 * driver (to be discussed) */ 114 u8 mp_mode; 115 u8 rsvd020; 116 u8 rsvd021; 117 u8 rsvd022; 118 u8 rsvd023; 119 u8 rsvd024; 120 u8 rsvd025; 121 122 /* --- long word 3 ---- */ 123 /* QoS enable */ 124 u8 qos_en; 125 /* 40MHz BW enable */ 126 /* 4181 convert AMSDU to AMPDU, 0: disable */ 127 u8 bw_40mhz_en; 128 u8 amsdu2ampdu_en; 129 /* 11n AMPDU enable */ 130 u8 ampdu_en; 131 /* FW offloads, 0: driver handles */ 132 u8 rate_control_offload; 133 /* FW offloads, 0: driver handles */ 134 u8 aggregation_offload; 135 u8 rsvd030; 136 u8 rsvd031; 137 138 /* --- long word 4 ---- */ 139 /* 1. FW offloads, 0: driver handles */ 140 u8 beacon_offload; 141 /* 2. FW offloads, 0: driver handles */ 142 u8 mlme_offload; 143 /* 3. FW offloads, 0: driver handles */ 144 u8 hwpc_offload; 145 /* 4. FW offloads, 0: driver handles */ 146 u8 tcp_checksum_offload; 147 /* 5. FW offloads, 0: driver handles */ 148 u8 tcp_offload; 149 /* 6. FW offloads, 0: driver handles */ 150 u8 ps_control_offload; 151 /* 7. FW offloads, 0: driver handles */ 152 u8 wwlan_offload; 153 u8 rsvd040; 154 155 /* --- long word 5 ---- */ 156 /* tcp tx packet length low byte */ 157 u8 tcp_tx_frame_len_L; 158 /* tcp tx packet length high byte */ 159 u8 tcp_tx_frame_len_H; 160 /* tcp rx packet length low byte */ 161 u8 tcp_rx_frame_len_L; 162 /* tcp rx packet length high byte */ 163 u8 tcp_rx_frame_len_H; 164 u8 rsvd050; 165 u8 rsvd051; 166 u8 rsvd052; 167 u8 rsvd053; 168 }; 169 170 /* 8-byte alinment required */ 171 struct fw_hdr { 172 173 /* --- LONG WORD 0 ---- */ 174 u16 signature; 175 /* 0x8000 ~ 0x8FFF for FPGA version, 176 * 0x0000 ~ 0x7FFF for ASIC version, */ 177 u16 version; 178 /* define the size of boot loader */ 179 u32 dmem_size; 180 181 182 /* --- LONG WORD 1 ---- */ 183 /* define the size of FW in IMEM */ 184 u32 img_imem_size; 185 /* define the size of FW in SRAM */ 186 u32 img_sram_size; 187 188 /* --- LONG WORD 2 ---- */ 189 /* define the size of DMEM variable */ 190 u32 fw_priv_size; 191 u32 rsvd0; 192 193 /* --- LONG WORD 3 ---- */ 194 u32 rsvd1; 195 u32 rsvd2; 196 197 struct fw_priv fwpriv; 198 199 } ; 200 201 enum fw_status { 202 FW_STATUS_INIT = 0, 203 FW_STATUS_LOAD_IMEM = 1, 204 FW_STATUS_LOAD_EMEM = 2, 205 FW_STATUS_LOAD_DMEM = 3, 206 FW_STATUS_READY = 4, 207 }; 208 209 struct rt_firmware { 210 struct fw_hdr *pfwheader; 211 enum fw_status fwstatus; 212 u16 firmwareversion; 213 u8 fw_imem[RTL8190_MAX_FIRMWARE_CODE_SIZE]; 214 u8 fw_emem[RTL8190_MAX_FIRMWARE_CODE_SIZE]; 215 u32 fw_imem_len; 216 u32 fw_emem_len; 217 u8 sz_fw_tmpbuffer[RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE]; 218 u32 sz_fw_tmpbufferlen; 219 u16 cmdpacket_fragthresold; 220 }; 221 222 struct h2c_set_pwrmode_parm { 223 u8 mode; 224 u8 flag_low_traffic_en; 225 u8 flag_lpnav_en; 226 u8 flag_rf_low_snr_en; 227 /* 1: dps, 0: 32k */ 228 u8 flag_dps_en; 229 u8 bcn_rx_en; 230 u8 bcn_pass_cnt; 231 /* beacon TO (ms). ¡§=0¡¨ no limit. */ 232 u8 bcn_to; 233 u16 bcn_itv; 234 /* only for VOIP mode. */ 235 u8 app_itv; 236 u8 awake_bcn_itvl; 237 u8 smart_ps; 238 /* unit: 100 ms */ 239 u8 bcn_pass_period; 240 }; 241 242 struct h2c_joinbss_rpt_parm { 243 u8 opmode; 244 u8 ps_qos_info; 245 u8 bssid[6]; 246 u16 bcnitv; 247 u16 aid; 248 } ; 249 250 struct h2c_wpa_ptk { 251 /* EAPOL-Key Key Confirmation Key (KCK) */ 252 u8 kck[16]; 253 /* EAPOL-Key Key Encryption Key (KEK) */ 254 u8 kek[16]; 255 /* Temporal Key 1 (TK1) */ 256 u8 tk1[16]; 257 union { 258 /* Temporal Key 2 (TK2) */ 259 u8 tk2[16]; 260 struct { 261 u8 tx_mic_key[8]; 262 u8 rx_mic_key[8]; 263 } athu; 264 } u; 265 }; 266 267 struct h2c_wpa_two_way_parm { 268 /* algorithm TKIP or AES */ 269 u8 pairwise_en_alg; 270 u8 group_en_alg; 271 struct h2c_wpa_ptk wpa_ptk_value; 272 } ; 273 274 enum h2c_cmd { 275 FW_H2C_SETPWRMODE = 0, 276 FW_H2C_JOINBSSRPT = 1, 277 FW_H2C_WOWLAN_UPDATE_GTK = 2, 278 FW_H2C_WOWLAN_UPDATE_IV = 3, 279 FW_H2C_WOWLAN_OFFLOAD = 4, 280 }; 281 282 enum fw_h2c_cmd { 283 H2C_READ_MACREG_CMD, /*0*/ 284 H2C_WRITE_MACREG_CMD, 285 H2C_READBB_CMD, 286 H2C_WRITEBB_CMD, 287 H2C_READRF_CMD, 288 H2C_WRITERF_CMD, /*5*/ 289 H2C_READ_EEPROM_CMD, 290 H2C_WRITE_EEPROM_CMD, 291 H2C_READ_EFUSE_CMD, 292 H2C_WRITE_EFUSE_CMD, 293 H2C_READ_CAM_CMD, /*10*/ 294 H2C_WRITE_CAM_CMD, 295 H2C_SETBCNITV_CMD, 296 H2C_SETMBIDCFG_CMD, 297 H2C_JOINBSS_CMD, 298 H2C_DISCONNECT_CMD, /*15*/ 299 H2C_CREATEBSS_CMD, 300 H2C_SETOPMode_CMD, 301 H2C_SITESURVEY_CMD, 302 H2C_SETAUTH_CMD, 303 H2C_SETKEY_CMD, /*20*/ 304 H2C_SETSTAKEY_CMD, 305 H2C_SETASSOCSTA_CMD, 306 H2C_DELASSOCSTA_CMD, 307 H2C_SETSTAPWRSTATE_CMD, 308 H2C_SETBASICRATE_CMD, /*25*/ 309 H2C_GETBASICRATE_CMD, 310 H2C_SETDATARATE_CMD, 311 H2C_GETDATARATE_CMD, 312 H2C_SETPHYINFO_CMD, 313 H2C_GETPHYINFO_CMD, /*30*/ 314 H2C_SETPHY_CMD, 315 H2C_GETPHY_CMD, 316 H2C_READRSSI_CMD, 317 H2C_READGAIN_CMD, 318 H2C_SETATIM_CMD, /*35*/ 319 H2C_SETPWRMODE_CMD, 320 H2C_JOINBSSRPT_CMD, 321 H2C_SETRATABLE_CMD, 322 H2C_GETRATABLE_CMD, 323 H2C_GETCCXREPORT_CMD, /*40*/ 324 H2C_GETDTMREPORT_CMD, 325 H2C_GETTXRATESTATICS_CMD, 326 H2C_SETUSBSUSPEND_CMD, 327 H2C_SETH2CLBK_CMD, 328 H2C_TMP1, /*45*/ 329 H2C_WOWLAN_UPDATE_GTK_CMD, 330 H2C_WOWLAN_FW_OFFLOAD, 331 H2C_TMP2, 332 H2C_TMP3, 333 H2C_WOWLAN_UPDATE_IV_CMD, /*50*/ 334 H2C_TMP4, 335 }; 336 337 /* The following macros are used for FW 338 * CMD map and parameter updated. */ 339 #define FW_CMD_IO_CLR(rtlpriv, _Bit) \ 340 do { \ 341 udelay(1000); \ 342 rtlpriv->rtlhal.fwcmd_iomap &= (~_Bit); \ 343 } while (0) 344 345 #define FW_CMD_IO_UPDATE(rtlpriv, _val) \ 346 rtlpriv->rtlhal.fwcmd_iomap = _val; 347 348 #define FW_CMD_IO_SET(rtlpriv, _val) \ 349 do { \ 350 rtl_write_word(rtlpriv, LBUS_MON_ADDR, (u16)_val); \ 351 FW_CMD_IO_UPDATE(rtlpriv, _val); \ 352 } while (0) 353 354 #define FW_CMD_PARA_SET(rtlpriv, _val) \ 355 do { \ 356 rtl_write_dword(rtlpriv, LBUS_ADDR_MASK, _val); \ 357 rtlpriv->rtlhal.fwcmd_ioparam = _val; \ 358 } while (0) 359 360 #define FW_CMD_IO_QUERY(rtlpriv) \ 361 (u16)(rtlpriv->rtlhal.fwcmd_iomap) 362 #define FW_CMD_IO_PARA_QUERY(rtlpriv) \ 363 ((u32)(rtlpriv->rtlhal.fwcmd_ioparam)) 364 365 int rtl92s_download_fw(struct ieee80211_hw *hw); 366 void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode); 367 void rtl92s_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, 368 u8 mstatus, u8 ps_qosinfo); 369 370 #endif 371 372