1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 #ifndef __REALTEK_FIRMWARE92S_H__ 30 #define __REALTEK_FIRMWARE92S_H__ 31 32 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 33 #define RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE 90000 34 #define RTL8190_CPU_START_OFFSET 0x80 35 /* Firmware Local buffer size. 64k */ 36 #define MAX_FIRMWARE_CODE_SIZE 0xFF00 37 38 #define RT_8192S_FIRMWARE_HDR_SIZE 80 39 #define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE 32 40 41 /* support till 64 bit bus width OS */ 42 #define MAX_DEV_ADDR_SIZE 8 43 #define MAX_FIRMWARE_INFORMATION_SIZE 32 44 #define MAX_802_11_HEADER_LENGTH (40 + \ 45 MAX_FIRMWARE_INFORMATION_SIZE) 46 #define ENCRYPTION_MAX_OVERHEAD 128 47 #define MAX_FRAGMENT_COUNT 8 48 #define MAX_TRANSMIT_BUFFER_SIZE (1600 + \ 49 (MAX_802_11_HEADER_LENGTH + \ 50 ENCRYPTION_MAX_OVERHEAD) *\ 51 MAX_FRAGMENT_COUNT) 52 53 #define H2C_TX_CMD_HDR_LEN 8 54 55 /* The following DM control code are for Reg0x364, */ 56 #define FW_DIG_ENABLE_CTL BIT(0) 57 #define FW_HIGH_PWR_ENABLE_CTL BIT(1) 58 #define FW_SS_CTL BIT(2) 59 #define FW_RA_INIT_CTL BIT(3) 60 #define FW_RA_BG_CTL BIT(4) 61 #define FW_RA_N_CTL BIT(5) 62 #define FW_PWR_TRK_CTL BIT(6) 63 #define FW_IQK_CTL BIT(7) 64 #define FW_FA_CTL BIT(8) 65 #define FW_DRIVER_CTRL_DM_CTL BIT(9) 66 #define FW_PAPE_CTL_BY_SW_HW BIT(10) 67 #define FW_DISABLE_ALL_DM 0 68 #define FW_PWR_TRK_PARAM_CLR 0x0000ffff 69 #define FW_RA_PARAM_CLR 0xffff0000 70 71 enum desc_packet_type { 72 DESC_PACKET_TYPE_INIT = 0, 73 DESC_PACKET_TYPE_NORMAL = 1, 74 }; 75 76 /* 8-bytes alignment required */ 77 struct fw_priv { 78 /* --- long word 0 ---- */ 79 /* 0x12: CE product, 0x92: IT product */ 80 u8 signature_0; 81 /* 0x87: CE product, 0x81: IT product */ 82 u8 signature_1; 83 /* 0x81: PCI-AP, 01:PCIe, 02: 92S-U, 84 * 0x82: USB-AP, 0x12: 72S-U, 03:SDIO */ 85 u8 hci_sel; 86 /* the same value as reigster value */ 87 u8 chip_version; 88 /* customer ID low byte */ 89 u8 customer_id_0; 90 /* customer ID high byte */ 91 u8 customer_id_1; 92 /* 0x11: 1T1R, 0x12: 1T2R, 93 * 0x92: 1T2R turbo, 0x22: 2T2R */ 94 u8 rf_config; 95 /* 4: 4EP, 6: 6EP, 11: 11EP */ 96 u8 usb_ep_num; 97 98 /* --- long word 1 ---- */ 99 /* regulatory class bit map 0 */ 100 u8 regulatory_class_0; 101 /* regulatory class bit map 1 */ 102 u8 regulatory_class_1; 103 /* regulatory class bit map 2 */ 104 u8 regulatory_class_2; 105 /* regulatory class bit map 3 */ 106 u8 regulatory_class_3; 107 /* 0:SWSI, 1:HWSI, 2:HWPI */ 108 u8 rfintfs; 109 u8 def_nettype; 110 u8 rsvd010; 111 u8 rsvd011; 112 113 /* --- long word 2 ---- */ 114 /* 0x00: normal, 0x03: MACLBK, 0x01: PHYLBK */ 115 u8 lbk_mode; 116 /* 1: for MP use, 0: for normal 117 * driver (to be discussed) */ 118 u8 mp_mode; 119 u8 rsvd020; 120 u8 rsvd021; 121 u8 rsvd022; 122 u8 rsvd023; 123 u8 rsvd024; 124 u8 rsvd025; 125 126 /* --- long word 3 ---- */ 127 /* QoS enable */ 128 u8 qos_en; 129 /* 40MHz BW enable */ 130 /* 4181 convert AMSDU to AMPDU, 0: disable */ 131 u8 bw_40mhz_en; 132 u8 amsdu2ampdu_en; 133 /* 11n AMPDU enable */ 134 u8 ampdu_en; 135 /* FW offloads, 0: driver handles */ 136 u8 rate_control_offload; 137 /* FW offloads, 0: driver handles */ 138 u8 aggregation_offload; 139 u8 rsvd030; 140 u8 rsvd031; 141 142 /* --- long word 4 ---- */ 143 /* 1. FW offloads, 0: driver handles */ 144 u8 beacon_offload; 145 /* 2. FW offloads, 0: driver handles */ 146 u8 mlme_offload; 147 /* 3. FW offloads, 0: driver handles */ 148 u8 hwpc_offload; 149 /* 4. FW offloads, 0: driver handles */ 150 u8 tcp_checksum_offload; 151 /* 5. FW offloads, 0: driver handles */ 152 u8 tcp_offload; 153 /* 6. FW offloads, 0: driver handles */ 154 u8 ps_control_offload; 155 /* 7. FW offloads, 0: driver handles */ 156 u8 wwlan_offload; 157 u8 rsvd040; 158 159 /* --- long word 5 ---- */ 160 /* tcp tx packet length low byte */ 161 u8 tcp_tx_frame_len_L; 162 /* tcp tx packet length high byte */ 163 u8 tcp_tx_frame_len_H; 164 /* tcp rx packet length low byte */ 165 u8 tcp_rx_frame_len_L; 166 /* tcp rx packet length high byte */ 167 u8 tcp_rx_frame_len_H; 168 u8 rsvd050; 169 u8 rsvd051; 170 u8 rsvd052; 171 u8 rsvd053; 172 }; 173 174 /* 8-byte alinment required */ 175 struct fw_hdr { 176 177 /* --- LONG WORD 0 ---- */ 178 u16 signature; 179 /* 0x8000 ~ 0x8FFF for FPGA version, 180 * 0x0000 ~ 0x7FFF for ASIC version, */ 181 u16 version; 182 /* define the size of boot loader */ 183 u32 dmem_size; 184 185 186 /* --- LONG WORD 1 ---- */ 187 /* define the size of FW in IMEM */ 188 u32 img_imem_size; 189 /* define the size of FW in SRAM */ 190 u32 img_sram_size; 191 192 /* --- LONG WORD 2 ---- */ 193 /* define the size of DMEM variable */ 194 u32 fw_priv_size; 195 u32 rsvd0; 196 197 /* --- LONG WORD 3 ---- */ 198 u32 rsvd1; 199 u32 rsvd2; 200 201 struct fw_priv fwpriv; 202 203 } ; 204 205 enum fw_status { 206 FW_STATUS_INIT = 0, 207 FW_STATUS_LOAD_IMEM = 1, 208 FW_STATUS_LOAD_EMEM = 2, 209 FW_STATUS_LOAD_DMEM = 3, 210 FW_STATUS_READY = 4, 211 }; 212 213 struct rt_firmware { 214 struct fw_hdr *pfwheader; 215 enum fw_status fwstatus; 216 u16 firmwareversion; 217 u8 fw_imem[RTL8190_MAX_FIRMWARE_CODE_SIZE]; 218 u8 fw_emem[RTL8190_MAX_FIRMWARE_CODE_SIZE]; 219 u32 fw_imem_len; 220 u32 fw_emem_len; 221 u8 sz_fw_tmpbuffer[RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE]; 222 u32 sz_fw_tmpbufferlen; 223 u16 cmdpacket_fragthresold; 224 }; 225 226 struct h2c_set_pwrmode_parm { 227 u8 mode; 228 u8 flag_low_traffic_en; 229 u8 flag_lpnav_en; 230 u8 flag_rf_low_snr_en; 231 /* 1: dps, 0: 32k */ 232 u8 flag_dps_en; 233 u8 bcn_rx_en; 234 u8 bcn_pass_cnt; 235 /* beacon TO (ms). ¡§=0¡¨ no limit. */ 236 u8 bcn_to; 237 u16 bcn_itv; 238 /* only for VOIP mode. */ 239 u8 app_itv; 240 u8 awake_bcn_itvl; 241 u8 smart_ps; 242 /* unit: 100 ms */ 243 u8 bcn_pass_period; 244 }; 245 246 struct h2c_joinbss_rpt_parm { 247 u8 opmode; 248 u8 ps_qos_info; 249 u8 bssid[6]; 250 u16 bcnitv; 251 u16 aid; 252 } ; 253 254 struct h2c_wpa_ptk { 255 /* EAPOL-Key Key Confirmation Key (KCK) */ 256 u8 kck[16]; 257 /* EAPOL-Key Key Encryption Key (KEK) */ 258 u8 kek[16]; 259 /* Temporal Key 1 (TK1) */ 260 u8 tk1[16]; 261 union { 262 /* Temporal Key 2 (TK2) */ 263 u8 tk2[16]; 264 struct { 265 u8 tx_mic_key[8]; 266 u8 rx_mic_key[8]; 267 } athu; 268 } u; 269 }; 270 271 struct h2c_wpa_two_way_parm { 272 /* algorithm TKIP or AES */ 273 u8 pairwise_en_alg; 274 u8 group_en_alg; 275 struct h2c_wpa_ptk wpa_ptk_value; 276 } ; 277 278 enum h2c_cmd { 279 FW_H2C_SETPWRMODE = 0, 280 FW_H2C_JOINBSSRPT = 1, 281 FW_H2C_WOWLAN_UPDATE_GTK = 2, 282 FW_H2C_WOWLAN_UPDATE_IV = 3, 283 FW_H2C_WOWLAN_OFFLOAD = 4, 284 }; 285 286 enum fw_h2c_cmd { 287 H2C_READ_MACREG_CMD, /*0*/ 288 H2C_WRITE_MACREG_CMD, 289 H2C_READBB_CMD, 290 H2C_WRITEBB_CMD, 291 H2C_READRF_CMD, 292 H2C_WRITERF_CMD, /*5*/ 293 H2C_READ_EEPROM_CMD, 294 H2C_WRITE_EEPROM_CMD, 295 H2C_READ_EFUSE_CMD, 296 H2C_WRITE_EFUSE_CMD, 297 H2C_READ_CAM_CMD, /*10*/ 298 H2C_WRITE_CAM_CMD, 299 H2C_SETBCNITV_CMD, 300 H2C_SETMBIDCFG_CMD, 301 H2C_JOINBSS_CMD, 302 H2C_DISCONNECT_CMD, /*15*/ 303 H2C_CREATEBSS_CMD, 304 H2C_SETOPMode_CMD, 305 H2C_SITESURVEY_CMD, 306 H2C_SETAUTH_CMD, 307 H2C_SETKEY_CMD, /*20*/ 308 H2C_SETSTAKEY_CMD, 309 H2C_SETASSOCSTA_CMD, 310 H2C_DELASSOCSTA_CMD, 311 H2C_SETSTAPWRSTATE_CMD, 312 H2C_SETBASICRATE_CMD, /*25*/ 313 H2C_GETBASICRATE_CMD, 314 H2C_SETDATARATE_CMD, 315 H2C_GETDATARATE_CMD, 316 H2C_SETPHYINFO_CMD, 317 H2C_GETPHYINFO_CMD, /*30*/ 318 H2C_SETPHY_CMD, 319 H2C_GETPHY_CMD, 320 H2C_READRSSI_CMD, 321 H2C_READGAIN_CMD, 322 H2C_SETATIM_CMD, /*35*/ 323 H2C_SETPWRMODE_CMD, 324 H2C_JOINBSSRPT_CMD, 325 H2C_SETRATABLE_CMD, 326 H2C_GETRATABLE_CMD, 327 H2C_GETCCXREPORT_CMD, /*40*/ 328 H2C_GETDTMREPORT_CMD, 329 H2C_GETTXRATESTATICS_CMD, 330 H2C_SETUSBSUSPEND_CMD, 331 H2C_SETH2CLBK_CMD, 332 H2C_TMP1, /*45*/ 333 H2C_WOWLAN_UPDATE_GTK_CMD, 334 H2C_WOWLAN_FW_OFFLOAD, 335 H2C_TMP2, 336 H2C_TMP3, 337 H2C_WOWLAN_UPDATE_IV_CMD, /*50*/ 338 H2C_TMP4, 339 }; 340 341 /* The following macros are used for FW 342 * CMD map and parameter updated. */ 343 #define FW_CMD_IO_CLR(rtlpriv, _Bit) \ 344 do { \ 345 udelay(1000); \ 346 rtlpriv->rtlhal.fwcmd_iomap &= (~_Bit); \ 347 } while (0) 348 349 #define FW_CMD_IO_UPDATE(rtlpriv, _val) \ 350 rtlpriv->rtlhal.fwcmd_iomap = _val; 351 352 #define FW_CMD_IO_SET(rtlpriv, _val) \ 353 do { \ 354 rtl_write_word(rtlpriv, LBUS_MON_ADDR, (u16)_val); \ 355 FW_CMD_IO_UPDATE(rtlpriv, _val); \ 356 } while (0) 357 358 #define FW_CMD_PARA_SET(rtlpriv, _val) \ 359 do { \ 360 rtl_write_dword(rtlpriv, LBUS_ADDR_MASK, _val); \ 361 rtlpriv->rtlhal.fwcmd_ioparam = _val; \ 362 } while (0) 363 364 #define FW_CMD_IO_QUERY(rtlpriv) \ 365 (u16)(rtlpriv->rtlhal.fwcmd_iomap) 366 #define FW_CMD_IO_PARA_QUERY(rtlpriv) \ 367 ((u32)(rtlpriv->rtlhal.fwcmd_ioparam)) 368 369 int rtl92s_download_fw(struct ieee80211_hw *hw); 370 void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode); 371 void rtl92s_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, 372 u8 mstatus, u8 ps_qosinfo); 373 374 #endif 375 376