1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 #ifndef __RTL_92S_DM_H__ 30 #define __RTL_92S_DM_H__ 31 32 enum dm_dig_alg { 33 DIG_ALGO_BY_FALSE_ALARM = 0, 34 DIG_ALGO_BY_RSSI = 1, 35 DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM = 2, 36 DIG_ALGO_BY_TOW_PORT = 3, 37 DIG_ALGO_MAX 38 }; 39 40 enum dm_dig_two_port_alg { 41 DIG_TWO_PORT_ALGO_RSSI = 0, 42 DIG_TWO_PORT_ALGO_FALSE_ALARM = 1, 43 }; 44 45 enum dm_dig_dbg { 46 DM_DBG_OFF = 0, 47 DM_DBG_ON = 1, 48 DM_DBG_MAX 49 }; 50 51 enum dm_dig_sta { 52 DM_STA_DIG_OFF = 0, 53 DM_STA_DIG_ON, 54 DM_STA_DIG_MAX 55 }; 56 57 enum dm_ratr_sta { 58 DM_RATR_STA_HIGH = 0, 59 DM_RATR_STA_MIDDLEHIGH = 1, 60 DM_RATR_STA_MIDDLE = 2, 61 DM_RATR_STA_MIDDLELOW = 3, 62 DM_RATR_STA_LOW = 4, 63 DM_RATR_STA_ULTRALOW = 5, 64 DM_RATR_STA_MAX 65 }; 66 67 #define DM_TYPE_BYFW 0 68 #define DM_TYPE_BYDRIVER 1 69 70 #define TX_HIGH_PWR_LEVEL_NORMAL 0 71 #define TX_HIGH_PWR_LEVEL_LEVEL1 1 72 #define TX_HIGH_PWR_LEVEL_LEVEL2 2 73 74 #define HAL_DM_DIG_DISABLE BIT(0) /* Disable Dig */ 75 #define HAL_DM_HIPWR_DISABLE BIT(1) /* Disable High Power */ 76 77 #define TX_HIGHPWR_LEVEL_NORMAL 0 78 #define TX_HIGHPWR_LEVEL_NORMAL1 1 79 #define TX_HIGHPWR_LEVEL_NORMAL2 2 80 81 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 82 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 83 84 #define DM_DIG_HIGH_PWR_THRESH_HIGH 75 85 #define DM_DIG_HIGH_PWR_THRESH_LOW 70 86 #define DM_DIG_MIN_Netcore 0x12 87 88 void rtl92s_dm_watchdog(struct ieee80211_hw *hw); 89 void rtl92s_dm_init(struct ieee80211_hw *hw); 90 void rtl92s_dm_init_edca_turbo(struct ieee80211_hw *hw); 91 92 #endif 93