1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../base.h" 28 #include "../core.h" 29 #include "reg.h" 30 #include "def.h" 31 #include "phy.h" 32 #include "dm.h" 33 #include "fw.h" 34 35 static const u32 edca_setting_dl[PEER_MAX] = { 36 0xa44f, /* 0 UNKNOWN */ 37 0x5ea44f, /* 1 REALTEK_90 */ 38 0x5ea44f, /* 2 REALTEK_92SE */ 39 0xa630, /* 3 BROAD */ 40 0xa44f, /* 4 RAL */ 41 0xa630, /* 5 ATH */ 42 0xa630, /* 6 CISCO */ 43 0xa42b, /* 7 MARV */ 44 }; 45 46 static const u32 edca_setting_dl_gmode[PEER_MAX] = { 47 0x4322, /* 0 UNKNOWN */ 48 0xa44f, /* 1 REALTEK_90 */ 49 0x5ea44f, /* 2 REALTEK_92SE */ 50 0xa42b, /* 3 BROAD */ 51 0x5e4322, /* 4 RAL */ 52 0x4322, /* 5 ATH */ 53 0xa430, /* 6 CISCO */ 54 0x5ea44f, /* 7 MARV */ 55 }; 56 57 static const u32 edca_setting_ul[PEER_MAX] = { 58 0x5e4322, /* 0 UNKNOWN */ 59 0xa44f, /* 1 REALTEK_90 */ 60 0x5ea44f, /* 2 REALTEK_92SE */ 61 0x5ea322, /* 3 BROAD */ 62 0x5ea422, /* 4 RAL */ 63 0x5ea322, /* 5 ATH */ 64 0x3ea44f, /* 6 CISCO */ 65 0x5ea44f, /* 7 MARV */ 66 }; 67 68 static void _rtl92s_dm_check_edca_turbo(struct ieee80211_hw *hw) 69 { 70 struct rtl_priv *rtlpriv = rtl_priv(hw); 71 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 72 73 static u64 last_txok_cnt; 74 static u64 last_rxok_cnt; 75 u64 cur_txok_cnt = 0; 76 u64 cur_rxok_cnt = 0; 77 78 u32 edca_be_ul = edca_setting_ul[mac->vendor]; 79 u32 edca_be_dl = edca_setting_dl[mac->vendor]; 80 u32 edca_gmode = edca_setting_dl_gmode[mac->vendor]; 81 82 if (mac->link_state != MAC80211_LINKED) { 83 rtlpriv->dm.current_turbo_edca = false; 84 goto dm_checkedcaturbo_exit; 85 } 86 87 if ((!rtlpriv->dm.is_any_nonbepkts) && 88 (!rtlpriv->dm.disable_framebursting)) { 89 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt; 90 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt; 91 92 if (rtlpriv->phy.rf_type == RF_1T2R) { 93 if (cur_txok_cnt > 4 * cur_rxok_cnt) { 94 /* Uplink TP is present. */ 95 if (rtlpriv->dm.is_cur_rdlstate || 96 !rtlpriv->dm.current_turbo_edca) { 97 rtl_write_dword(rtlpriv, EDCAPARA_BE, 98 edca_be_ul); 99 rtlpriv->dm.is_cur_rdlstate = false; 100 } 101 } else {/* Balance TP is present. */ 102 if (!rtlpriv->dm.is_cur_rdlstate || 103 !rtlpriv->dm.current_turbo_edca) { 104 if (mac->mode == WIRELESS_MODE_G || 105 mac->mode == WIRELESS_MODE_B) 106 rtl_write_dword(rtlpriv, 107 EDCAPARA_BE, 108 edca_gmode); 109 else 110 rtl_write_dword(rtlpriv, 111 EDCAPARA_BE, 112 edca_be_dl); 113 rtlpriv->dm.is_cur_rdlstate = true; 114 } 115 } 116 rtlpriv->dm.current_turbo_edca = true; 117 } else { 118 if (cur_rxok_cnt > 4 * cur_txok_cnt) { 119 if (!rtlpriv->dm.is_cur_rdlstate || 120 !rtlpriv->dm.current_turbo_edca) { 121 if (mac->mode == WIRELESS_MODE_G || 122 mac->mode == WIRELESS_MODE_B) 123 rtl_write_dword(rtlpriv, 124 EDCAPARA_BE, 125 edca_gmode); 126 else 127 rtl_write_dword(rtlpriv, 128 EDCAPARA_BE, 129 edca_be_dl); 130 rtlpriv->dm.is_cur_rdlstate = true; 131 } 132 } else { 133 if (rtlpriv->dm.is_cur_rdlstate || 134 !rtlpriv->dm.current_turbo_edca) { 135 rtl_write_dword(rtlpriv, EDCAPARA_BE, 136 edca_be_ul); 137 rtlpriv->dm.is_cur_rdlstate = false; 138 } 139 } 140 rtlpriv->dm.current_turbo_edca = true; 141 } 142 } else { 143 if (rtlpriv->dm.current_turbo_edca) { 144 u8 tmp = AC0_BE; 145 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, 146 &tmp); 147 rtlpriv->dm.current_turbo_edca = false; 148 } 149 } 150 151 dm_checkedcaturbo_exit: 152 rtlpriv->dm.is_any_nonbepkts = false; 153 last_txok_cnt = rtlpriv->stats.txbytesunicast; 154 last_rxok_cnt = rtlpriv->stats.rxbytesunicast; 155 } 156 157 static void _rtl92s_dm_txpowertracking_callback_thermalmeter( 158 struct ieee80211_hw *hw) 159 { 160 struct rtl_priv *rtlpriv = rtl_priv(hw); 161 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 162 u8 thermalvalue = 0; 163 u32 fw_cmd = 0; 164 165 rtlpriv->dm.txpower_trackinginit = true; 166 167 thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f); 168 169 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 170 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermal meter 0x%x\n", 171 thermalvalue, 172 rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter); 173 174 if (thermalvalue) { 175 rtlpriv->dm.thermalvalue = thermalvalue; 176 if (hal_get_firmwareversion(rtlpriv) >= 0x35) { 177 rtl92s_phy_set_fw_cmd(hw, FW_CMD_TXPWR_TRACK_THERMAL); 178 } else { 179 fw_cmd = (FW_TXPWR_TRACK_THERMAL | 180 (rtlpriv->efuse.thermalmeter[0] << 8) | 181 (thermalvalue << 16)); 182 183 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, 184 "Write to FW Thermal Val = 0x%x\n", fw_cmd); 185 186 rtl_write_dword(rtlpriv, WFM5, fw_cmd); 187 rtl92s_phy_chk_fwcmd_iodone(hw); 188 } 189 } 190 191 rtlpriv->dm.txpowercount = 0; 192 } 193 194 static void _rtl92s_dm_check_txpowertracking_thermalmeter( 195 struct ieee80211_hw *hw) 196 { 197 struct rtl_priv *rtlpriv = rtl_priv(hw); 198 struct rtl_phy *rtlphy = &(rtlpriv->phy); 199 u8 tx_power_checkcnt = 5; 200 201 /* 2T2R TP issue */ 202 if (rtlphy->rf_type == RF_2T2R) 203 return; 204 205 if (!rtlpriv->dm.txpower_tracking) 206 return; 207 208 if (rtlpriv->dm.txpowercount <= tx_power_checkcnt) { 209 rtlpriv->dm.txpowercount++; 210 return; 211 } 212 213 if (!rtlpriv->dm.tm_trigger) { 214 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, 215 RFREG_OFFSET_MASK, 0x60); 216 rtlpriv->dm.tm_trigger = 1; 217 } else { 218 _rtl92s_dm_txpowertracking_callback_thermalmeter(hw); 219 rtlpriv->dm.tm_trigger = 0; 220 } 221 } 222 223 static void _rtl92s_dm_refresh_rateadaptive_mask(struct ieee80211_hw *hw) 224 { 225 struct rtl_priv *rtlpriv = rtl_priv(hw); 226 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 227 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 228 struct rate_adaptive *ra = &(rtlpriv->ra); 229 struct ieee80211_sta *sta = NULL; 230 u32 low_rssi_thresh = 0; 231 u32 middle_rssi_thresh = 0; 232 u32 high_rssi_thresh = 0; 233 234 if (is_hal_stop(rtlhal)) 235 return; 236 237 if (!rtlpriv->dm.useramask) 238 return; 239 240 if (hal_get_firmwareversion(rtlpriv) >= 61 && 241 !rtlpriv->dm.inform_fw_driverctrldm) { 242 rtl92s_phy_set_fw_cmd(hw, FW_CMD_CTRL_DM_BY_DRIVER); 243 rtlpriv->dm.inform_fw_driverctrldm = true; 244 } 245 246 if ((mac->link_state == MAC80211_LINKED) && 247 (mac->opmode == NL80211_IFTYPE_STATION)) { 248 switch (ra->pre_ratr_state) { 249 case DM_RATR_STA_HIGH: 250 high_rssi_thresh = 40; 251 middle_rssi_thresh = 30; 252 low_rssi_thresh = 20; 253 break; 254 case DM_RATR_STA_MIDDLE: 255 high_rssi_thresh = 44; 256 middle_rssi_thresh = 30; 257 low_rssi_thresh = 20; 258 break; 259 case DM_RATR_STA_LOW: 260 high_rssi_thresh = 44; 261 middle_rssi_thresh = 34; 262 low_rssi_thresh = 20; 263 break; 264 case DM_RATR_STA_ULTRALOW: 265 high_rssi_thresh = 44; 266 middle_rssi_thresh = 34; 267 low_rssi_thresh = 24; 268 break; 269 default: 270 high_rssi_thresh = 44; 271 middle_rssi_thresh = 34; 272 low_rssi_thresh = 24; 273 break; 274 } 275 276 if (rtlpriv->dm.undec_sm_pwdb > (long)high_rssi_thresh) { 277 ra->ratr_state = DM_RATR_STA_HIGH; 278 } else if (rtlpriv->dm.undec_sm_pwdb > 279 (long)middle_rssi_thresh) { 280 ra->ratr_state = DM_RATR_STA_LOW; 281 } else if (rtlpriv->dm.undec_sm_pwdb > 282 (long)low_rssi_thresh) { 283 ra->ratr_state = DM_RATR_STA_LOW; 284 } else { 285 ra->ratr_state = DM_RATR_STA_ULTRALOW; 286 } 287 288 if (ra->pre_ratr_state != ra->ratr_state) { 289 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, 290 "RSSI = %ld RSSI_LEVEL = %d PreState = %d, CurState = %d\n", 291 rtlpriv->dm.undec_sm_pwdb, ra->ratr_state, 292 ra->pre_ratr_state, ra->ratr_state); 293 294 rcu_read_lock(); 295 sta = rtl_find_sta(hw, mac->bssid); 296 if (sta) 297 rtlpriv->cfg->ops->update_rate_tbl(hw, sta, 298 ra->ratr_state, 299 true); 300 rcu_read_unlock(); 301 302 ra->pre_ratr_state = ra->ratr_state; 303 } 304 } 305 } 306 307 static void _rtl92s_dm_switch_baseband_mrc(struct ieee80211_hw *hw) 308 { 309 struct rtl_priv *rtlpriv = rtl_priv(hw); 310 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 311 struct rtl_phy *rtlphy = &(rtlpriv->phy); 312 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 313 bool current_mrc; 314 bool enable_mrc = true; 315 long tmpentry_maxpwdb = 0; 316 u8 rssi_a = 0; 317 u8 rssi_b = 0; 318 319 if (is_hal_stop(rtlhal)) 320 return; 321 322 if ((rtlphy->rf_type == RF_1T1R) || (rtlphy->rf_type == RF_2T2R)) 323 return; 324 325 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_MRC, (u8 *)(¤t_mrc)); 326 327 if (mac->link_state >= MAC80211_LINKED) { 328 if (rtlpriv->dm.undec_sm_pwdb > tmpentry_maxpwdb) { 329 rssi_a = rtlpriv->stats.rx_rssi_percentage[RF90_PATH_A]; 330 rssi_b = rtlpriv->stats.rx_rssi_percentage[RF90_PATH_B]; 331 } 332 } 333 334 /* MRC settings would NOT affect TP on Wireless B mode. */ 335 if (mac->mode != WIRELESS_MODE_B) { 336 if ((rssi_a == 0) && (rssi_b == 0)) { 337 enable_mrc = true; 338 } else if (rssi_b > 30) { 339 /* Turn on B-Path */ 340 enable_mrc = true; 341 } else if (rssi_b < 5) { 342 /* Turn off B-path */ 343 enable_mrc = false; 344 /* Take care of RSSI differentiation. */ 345 } else if (rssi_a > 15 && (rssi_a >= rssi_b)) { 346 if ((rssi_a - rssi_b) > 15) 347 /* Turn off B-path */ 348 enable_mrc = false; 349 else if ((rssi_a - rssi_b) < 10) 350 /* Turn on B-Path */ 351 enable_mrc = true; 352 else 353 enable_mrc = current_mrc; 354 } else { 355 /* Turn on B-Path */ 356 enable_mrc = true; 357 } 358 } 359 360 /* Update MRC settings if needed. */ 361 if (enable_mrc != current_mrc) 362 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, 363 (u8 *)&enable_mrc); 364 365 } 366 367 void rtl92s_dm_init_edca_turbo(struct ieee80211_hw *hw) 368 { 369 struct rtl_priv *rtlpriv = rtl_priv(hw); 370 371 rtlpriv->dm.current_turbo_edca = false; 372 rtlpriv->dm.is_any_nonbepkts = false; 373 rtlpriv->dm.is_cur_rdlstate = false; 374 } 375 376 static void _rtl92s_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw) 377 { 378 struct rtl_priv *rtlpriv = rtl_priv(hw); 379 struct rate_adaptive *ra = &(rtlpriv->ra); 380 381 ra->ratr_state = DM_RATR_STA_MAX; 382 ra->pre_ratr_state = DM_RATR_STA_MAX; 383 384 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER && 385 hal_get_firmwareversion(rtlpriv) >= 60) 386 rtlpriv->dm.useramask = true; 387 else 388 rtlpriv->dm.useramask = false; 389 390 rtlpriv->dm.useramask = false; 391 rtlpriv->dm.inform_fw_driverctrldm = false; 392 } 393 394 static void _rtl92s_dm_init_txpowertracking_thermalmeter( 395 struct ieee80211_hw *hw) 396 { 397 struct rtl_priv *rtlpriv = rtl_priv(hw); 398 399 rtlpriv->dm.txpower_tracking = true; 400 rtlpriv->dm.txpowercount = 0; 401 rtlpriv->dm.txpower_trackinginit = false; 402 } 403 404 static void _rtl92s_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) 405 { 406 struct rtl_priv *rtlpriv = rtl_priv(hw); 407 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt); 408 u32 ret_value; 409 410 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); 411 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); 412 413 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); 414 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); 415 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); 416 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); 417 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); 418 419 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + 420 falsealm_cnt->cnt_rate_illegal + falsealm_cnt->cnt_crc8_fail + 421 falsealm_cnt->cnt_mcs_fail; 422 423 /* read CCK false alarm */ 424 ret_value = rtl_get_bbreg(hw, 0xc64, MASKDWORD); 425 falsealm_cnt->cnt_cck_fail = (ret_value & 0xffff); 426 falsealm_cnt->cnt_all = falsealm_cnt->cnt_ofdm_fail + 427 falsealm_cnt->cnt_cck_fail; 428 } 429 430 static void rtl92s_backoff_enable_flag(struct ieee80211_hw *hw) 431 { 432 struct rtl_priv *rtlpriv = rtl_priv(hw); 433 struct dig_t *digtable = &rtlpriv->dm_digtable; 434 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt); 435 436 if (falsealm_cnt->cnt_all > digtable->fa_highthresh) { 437 if ((digtable->back_val - 6) < 438 digtable->backoffval_range_min) 439 digtable->back_val = digtable->backoffval_range_min; 440 else 441 digtable->back_val -= 6; 442 } else if (falsealm_cnt->cnt_all < digtable->fa_lowthresh) { 443 if ((digtable->back_val + 6) > 444 digtable->backoffval_range_max) 445 digtable->back_val = 446 digtable->backoffval_range_max; 447 else 448 digtable->back_val += 6; 449 } 450 } 451 452 static void _rtl92s_dm_initial_gain_sta_beforeconnect(struct ieee80211_hw *hw) 453 { 454 struct rtl_priv *rtlpriv = rtl_priv(hw); 455 struct dig_t *digtable = &rtlpriv->dm_digtable; 456 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt); 457 static u8 initialized, force_write; 458 u8 initial_gain = 0; 459 460 if ((digtable->pre_sta_cstate == digtable->cur_sta_cstate) || 461 (digtable->cur_sta_cstate == DIG_STA_BEFORE_CONNECT)) { 462 if (digtable->cur_sta_cstate == DIG_STA_BEFORE_CONNECT) { 463 if (rtlpriv->psc.rfpwr_state != ERFON) 464 return; 465 466 if (digtable->backoff_enable_flag) 467 rtl92s_backoff_enable_flag(hw); 468 else 469 digtable->back_val = DM_DIG_BACKOFF_MAX; 470 471 if ((digtable->rssi_val + 10 - digtable->back_val) > 472 digtable->rx_gain_max) 473 digtable->cur_igvalue = 474 digtable->rx_gain_max; 475 else if ((digtable->rssi_val + 10 - digtable->back_val) 476 < digtable->rx_gain_min) 477 digtable->cur_igvalue = 478 digtable->rx_gain_min; 479 else 480 digtable->cur_igvalue = digtable->rssi_val + 10 481 - digtable->back_val; 482 483 if (falsealm_cnt->cnt_all > 10000) 484 digtable->cur_igvalue = 485 (digtable->cur_igvalue > 0x33) ? 486 digtable->cur_igvalue : 0x33; 487 488 if (falsealm_cnt->cnt_all > 16000) 489 digtable->cur_igvalue = 490 digtable->rx_gain_max; 491 /* connected -> connected or disconnected -> disconnected */ 492 } else { 493 /* Firmware control DIG, do nothing in driver dm */ 494 return; 495 } 496 /* disconnected -> connected or connected -> 497 * disconnected or beforeconnect->(dis)connected */ 498 } else { 499 /* Enable FW DIG */ 500 digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX; 501 rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_ENABLE); 502 503 digtable->back_val = DM_DIG_BACKOFF_MAX; 504 digtable->cur_igvalue = rtlpriv->phy.default_initialgain[0]; 505 digtable->pre_igvalue = 0; 506 return; 507 } 508 509 /* Forced writing to prevent from fw-dig overwriting. */ 510 if (digtable->pre_igvalue != rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, 511 MASKBYTE0)) 512 force_write = 1; 513 514 if ((digtable->pre_igvalue != digtable->cur_igvalue) || 515 !initialized || force_write) { 516 /* Disable FW DIG */ 517 rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_DISABLE); 518 519 initial_gain = (u8)digtable->cur_igvalue; 520 521 /* Set initial gain. */ 522 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, initial_gain); 523 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, initial_gain); 524 digtable->pre_igvalue = digtable->cur_igvalue; 525 initialized = 1; 526 force_write = 0; 527 } 528 } 529 530 static void _rtl92s_dm_ctrl_initgain_bytwoport(struct ieee80211_hw *hw) 531 { 532 struct rtl_priv *rtlpriv = rtl_priv(hw); 533 struct dig_t *dig = &rtlpriv->dm_digtable; 534 535 if (rtlpriv->mac80211.act_scanning) 536 return; 537 538 /* Decide the current status and if modify initial gain or not */ 539 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED || 540 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC) 541 dig->cur_sta_cstate = DIG_STA_CONNECT; 542 else 543 dig->cur_sta_cstate = DIG_STA_DISCONNECT; 544 545 dig->rssi_val = rtlpriv->dm.undec_sm_pwdb; 546 547 /* Change dig mode to rssi */ 548 if (dig->cur_sta_cstate != DIG_STA_DISCONNECT) { 549 if (dig->dig_twoport_algorithm == 550 DIG_TWO_PORT_ALGO_FALSE_ALARM) { 551 dig->dig_twoport_algorithm = DIG_TWO_PORT_ALGO_RSSI; 552 rtl92s_phy_set_fw_cmd(hw, FW_CMD_DIG_MODE_SS); 553 } 554 } 555 556 _rtl92s_dm_false_alarm_counter_statistics(hw); 557 _rtl92s_dm_initial_gain_sta_beforeconnect(hw); 558 559 dig->pre_sta_cstate = dig->cur_sta_cstate; 560 } 561 562 static void _rtl92s_dm_ctrl_initgain_byrssi(struct ieee80211_hw *hw) 563 { 564 struct rtl_priv *rtlpriv = rtl_priv(hw); 565 struct rtl_phy *rtlphy = &(rtlpriv->phy); 566 struct dig_t *digtable = &rtlpriv->dm_digtable; 567 568 /* 2T2R TP issue */ 569 if (rtlphy->rf_type == RF_2T2R) 570 return; 571 572 if (!rtlpriv->dm.dm_initialgain_enable) 573 return; 574 575 if (digtable->dig_enable_flag == false) 576 return; 577 578 _rtl92s_dm_ctrl_initgain_bytwoport(hw); 579 } 580 581 static void _rtl92s_dm_dynamic_txpower(struct ieee80211_hw *hw) 582 { 583 struct rtl_priv *rtlpriv = rtl_priv(hw); 584 struct rtl_phy *rtlphy = &(rtlpriv->phy); 585 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 586 long undec_sm_pwdb; 587 long txpwr_threshold_lv1, txpwr_threshold_lv2; 588 589 /* 2T2R TP issue */ 590 if (rtlphy->rf_type == RF_2T2R) 591 return; 592 593 if (!rtlpriv->dm.dynamic_txpower_enable || 594 rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) { 595 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL; 596 return; 597 } 598 599 if ((mac->link_state < MAC80211_LINKED) && 600 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) { 601 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 602 "Not connected to any\n"); 603 604 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL; 605 606 rtlpriv->dm.last_dtp_lvl = TX_HIGHPWR_LEVEL_NORMAL; 607 return; 608 } 609 610 if (mac->link_state >= MAC80211_LINKED) { 611 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 612 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb; 613 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 614 "AP Client PWDB = 0x%lx\n", 615 undec_sm_pwdb); 616 } else { 617 undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb; 618 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 619 "STA Default Port PWDB = 0x%lx\n", 620 undec_sm_pwdb); 621 } 622 } else { 623 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb; 624 625 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 626 "AP Ext Port PWDB = 0x%lx\n", 627 undec_sm_pwdb); 628 } 629 630 txpwr_threshold_lv2 = TX_POWER_NEAR_FIELD_THRESH_LVL2; 631 txpwr_threshold_lv1 = TX_POWER_NEAR_FIELD_THRESH_LVL1; 632 633 if (rtl_get_bbreg(hw, 0xc90, MASKBYTE0) == 1) 634 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL; 635 else if (undec_sm_pwdb >= txpwr_threshold_lv2) 636 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL2; 637 else if ((undec_sm_pwdb < (txpwr_threshold_lv2 - 3)) && 638 (undec_sm_pwdb >= txpwr_threshold_lv1)) 639 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL1; 640 else if (undec_sm_pwdb < (txpwr_threshold_lv1 - 3)) 641 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL; 642 643 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) 644 rtl92s_phy_set_txpower(hw, rtlphy->current_channel); 645 646 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl; 647 } 648 649 static void _rtl92s_dm_init_dig(struct ieee80211_hw *hw) 650 { 651 struct rtl_priv *rtlpriv = rtl_priv(hw); 652 struct dig_t *digtable = &rtlpriv->dm_digtable; 653 654 /* Disable DIG scheme now.*/ 655 digtable->dig_enable_flag = true; 656 digtable->backoff_enable_flag = true; 657 658 if ((rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) && 659 (hal_get_firmwareversion(rtlpriv) >= 0x3c)) 660 digtable->dig_algorithm = DIG_ALGO_BY_TOW_PORT; 661 else 662 digtable->dig_algorithm = 663 DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM; 664 665 digtable->dig_twoport_algorithm = DIG_TWO_PORT_ALGO_RSSI; 666 digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX; 667 /* off=by real rssi value, on=by digtable->rssi_val for new dig */ 668 digtable->dig_dbgmode = DM_DBG_OFF; 669 digtable->dig_slgorithm_switch = 0; 670 671 /* 2007/10/04 MH Define init gain threshol. */ 672 digtable->dig_state = DM_STA_DIG_MAX; 673 digtable->dig_highpwrstate = DM_STA_DIG_MAX; 674 675 digtable->cur_sta_cstate = DIG_STA_DISCONNECT; 676 digtable->pre_sta_cstate = DIG_STA_DISCONNECT; 677 digtable->cur_ap_cstate = DIG_AP_DISCONNECT; 678 digtable->pre_ap_cstate = DIG_AP_DISCONNECT; 679 680 digtable->rssi_lowthresh = DM_DIG_THRESH_LOW; 681 digtable->rssi_highthresh = DM_DIG_THRESH_HIGH; 682 683 digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW; 684 digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH; 685 686 digtable->rssi_highpower_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW; 687 digtable->rssi_highpower_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH; 688 689 /* for dig debug rssi value */ 690 digtable->rssi_val = 50; 691 digtable->back_val = DM_DIG_BACKOFF_MAX; 692 digtable->rx_gain_max = DM_DIG_MAX; 693 694 digtable->rx_gain_min = DM_DIG_MIN; 695 696 digtable->backoffval_range_max = DM_DIG_BACKOFF_MAX; 697 digtable->backoffval_range_min = DM_DIG_BACKOFF_MIN; 698 } 699 700 static void _rtl92s_dm_init_dynamic_txpower(struct ieee80211_hw *hw) 701 { 702 struct rtl_priv *rtlpriv = rtl_priv(hw); 703 704 if ((hal_get_firmwareversion(rtlpriv) >= 60) && 705 (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)) 706 rtlpriv->dm.dynamic_txpower_enable = true; 707 else 708 rtlpriv->dm.dynamic_txpower_enable = false; 709 710 rtlpriv->dm.last_dtp_lvl = TX_HIGHPWR_LEVEL_NORMAL; 711 rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL; 712 } 713 714 void rtl92s_dm_init(struct ieee80211_hw *hw) 715 { 716 struct rtl_priv *rtlpriv = rtl_priv(hw); 717 718 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER; 719 rtlpriv->dm.undec_sm_pwdb = -1; 720 721 _rtl92s_dm_init_dynamic_txpower(hw); 722 rtl92s_dm_init_edca_turbo(hw); 723 _rtl92s_dm_init_rate_adaptive_mask(hw); 724 _rtl92s_dm_init_txpowertracking_thermalmeter(hw); 725 _rtl92s_dm_init_dig(hw); 726 727 rtl_write_dword(rtlpriv, WFM5, FW_CCA_CHK_ENABLE); 728 } 729 730 void rtl92s_dm_watchdog(struct ieee80211_hw *hw) 731 { 732 _rtl92s_dm_check_edca_turbo(hw); 733 _rtl92s_dm_check_txpowertracking_thermalmeter(hw); 734 _rtl92s_dm_ctrl_initgain_byrssi(hw); 735 _rtl92s_dm_dynamic_txpower(hw); 736 _rtl92s_dm_refresh_rateadaptive_mask(hw); 737 _rtl92s_dm_switch_baseband_mrc(hw); 738 } 739 740