1 /******************************************************************************
2  *
3  * Copyright(c) 2009-2012  Realtek Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17  *
18  * The full GNU General Public License is included in this distribution in the
19  * file called LICENSE.
20  *
21  * Contact Information:
22  * wlanfae <wlanfae@realtek.com>
23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24  * Hsinchu 300, Taiwan.
25  *
26  * Larry Finger <Larry.Finger@lwfinger.net>
27  *
28  *****************************************************************************/
29 #ifndef __REALTEK_92S_DEF_H__
30 #define __REALTEK_92S_DEF_H__
31 
32 #define RX_MPDU_QUEUE				0
33 #define RX_CMD_QUEUE				1
34 
35 #define SHORT_SLOT_TIME				9
36 #define NON_SHORT_SLOT_TIME			20
37 
38 /* Queue Select Value in TxDesc */
39 #define QSLT_BK					0x2
40 #define QSLT_BE					0x0
41 #define QSLT_VI					0x5
42 #define QSLT_VO					0x6
43 #define QSLT_BEACON				0x10
44 #define QSLT_HIGH				0x11
45 #define QSLT_MGNT				0x12
46 #define QSLT_CMD				0x13
47 
48 /* Tx Desc */
49 #define TX_DESC_SIZE_RTL8192S			(16 * 4)
50 #define TX_CMDDESC_SIZE_RTL8192S		(16 * 4)
51 
52 /* Define a macro that takes a le32 word, converts it to host ordering,
53  * right shifts by a specified count, creates a mask of the specified
54  * bit count, and extracts that number of bits.
55  */
56 
57 #define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask)		\
58 	((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) &	\
59 	BIT_LEN_MASK_32(__mask))
60 
61 /* Define a macro that clears a bit field in an le32 word and
62  * sets the specified value into that bit field. The resulting
63  * value remains in le32 ordering; however, it is properly converted
64  * to host ordering for the clear and set operations before conversion
65  * back to le32.
66  */
67 
68 #define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val)	\
69 	(*(__le32 *)(__pdesc) =					\
70 	(cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) &	\
71 	(~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) |	\
72 	(((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
73 
74 /* macros to read/write various fields in RX or TX descriptors */
75 
76 /* Dword 0 */
77 #define SET_TX_DESC_PKT_SIZE(__pdesc, __val)			\
78 	SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
79 #define SET_TX_DESC_OFFSET(__pdesc, __val)			\
80 	SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
81 #define SET_TX_DESC_TYPE(__pdesc, __val)			\
82 	SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val)
83 #define SET_TX_DESC_LAST_SEG(__pdesc, __val)			\
84 	SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
85 #define SET_TX_DESC_FIRST_SEG(__pdesc, __val)			\
86 	SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
87 #define SET_TX_DESC_LINIP(__pdesc, __val)			\
88 	SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
89 #define SET_TX_DESC_AMSDU(__pdesc, __val)			\
90 	SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
91 #define SET_TX_DESC_GREEN_FIELD(__pdesc, __val)			\
92 	SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
93 #define SET_TX_DESC_OWN(__pdesc, __val)				\
94 	SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
95 
96 #define GET_TX_DESC_OWN(__pdesc)				\
97 	SHIFT_AND_MASK_LE(__pdesc, 31, 1)
98 
99 /* Dword 1 */
100 #define SET_TX_DESC_MACID(__pdesc, __val)			\
101 	SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val)
102 #define SET_TX_DESC_MORE_DATA(__pdesc, __val)			\
103 	SET_BITS_OFFSET_LE(__pdesc + 4, 5, 1, __val)
104 #define SET_TX_DESC_MORE_FRAG(__pdesc, __val)			\
105 	SET_BITS_OFFSET_LE(__pdesc + 4, 6, 1, __val)
106 #define SET_TX_DESC_PIFS(__pdesc, __val)			\
107 	SET_BITS_OFFSET_LE(__pdesc + 4, 7, 1, __val)
108 #define SET_TX_DESC_QUEUE_SEL(__pdesc, __val)			\
109 	SET_BITS_OFFSET_LE(__pdesc + 4, 8, 5, __val)
110 #define SET_TX_DESC_ACK_POLICY(__pdesc, __val)			\
111 	SET_BITS_OFFSET_LE(__pdesc + 4, 13, 2, __val)
112 #define SET_TX_DESC_NO_ACM(__pdesc, __val)			\
113 	SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val)
114 #define SET_TX_DESC_NON_QOS(__pdesc, __val)			\
115 	SET_BITS_OFFSET_LE(__pdesc + 4, 16, 1, __val)
116 #define SET_TX_DESC_KEY_ID(__pdesc, __val)			\
117 	SET_BITS_OFFSET_LE(__pdesc + 4, 17, 2, __val)
118 #define SET_TX_DESC_OUI(__pdesc, __val)				\
119 	SET_BITS_OFFSET_LE(__pdesc + 4, 19, 1, __val)
120 #define SET_TX_DESC_PKT_TYPE(__pdesc, __val)			\
121 	SET_BITS_OFFSET_LE(__pdesc + 4, 20, 1, __val)
122 #define SET_TX_DESC_EN_DESC_ID(__pdesc, __val)			\
123 	SET_BITS_OFFSET_LE(__pdesc + 4, 21, 1, __val)
124 #define SET_TX_DESC_SEC_TYPE(__pdesc, __val)			\
125 	SET_BITS_OFFSET_LE(__pdesc + 4, 22, 2, __val)
126 #define SET_TX_DESC_WDS(__pdesc, __val)				\
127 	SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val)
128 #define SET_TX_DESC_HTC(__pdesc, __val)				\
129 	SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val)
130 #define SET_TX_DESC_PKT_OFFSET(__pdesc, __val)			\
131 	SET_BITS_OFFSET_LE(__pdesc + 4, 26, 5, __val)
132 #define SET_TX_DESC_HWPC(__pdesc, __val)			\
133 	SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val)
134 
135 /* Dword 2 */
136 #define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val)		\
137 	SET_BITS_OFFSET_LE(__pdesc + 8, 0, 6, __val)
138 #define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val)		\
139 	SET_BITS_OFFSET_LE(__pdesc + 8, 6, 1, __val)
140 #define SET_TX_DESC_TSFL(__pdesc, __val)			\
141 	SET_BITS_OFFSET_LE(__pdesc + 8, 7, 5, __val)
142 #define SET_TX_DESC_RTS_RETRY_COUNT(__pdesc, __val)		\
143 	SET_BITS_OFFSET_LE(__pdesc + 8, 12, 6, __val)
144 #define SET_TX_DESC_DATA_RETRY_COUNT(__pdesc, __val)		\
145 	SET_BITS_OFFSET_LE(__pdesc + 8, 18, 6, __val)
146 #define	SET_TX_DESC_RSVD_MACID(__pdesc, __val)			\
147 	SET_BITS_OFFSET_LE(((__pdesc) + 8), 24, 5, __val)
148 #define SET_TX_DESC_AGG_ENABLE(__pdesc, __val)			\
149 	SET_BITS_OFFSET_LE(__pdesc + 8, 29, 1, __val)
150 #define SET_TX_DESC_AGG_BREAK(__pdesc, __val)			\
151 	SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val)
152 #define SET_TX_DESC_OWN_MAC(__pdesc, __val)			\
153 	SET_BITS_OFFSET_LE(__pdesc + 8, 31, 1, __val)
154 
155 /* Dword 3 */
156 #define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val)		\
157 	SET_BITS_OFFSET_LE(__pdesc + 12, 0, 8, __val)
158 #define SET_TX_DESC_TAIL_PAGE(__pdesc, __val)			\
159 	SET_BITS_OFFSET_LE(__pdesc + 12, 8, 8, __val)
160 #define SET_TX_DESC_SEQ(__pdesc, __val)				\
161 	SET_BITS_OFFSET_LE(__pdesc + 12, 16, 12, __val)
162 #define SET_TX_DESC_FRAG(__pdesc, __val)			\
163 	SET_BITS_OFFSET_LE(__pdesc + 12, 28, 4, __val)
164 
165 /* Dword 4 */
166 #define SET_TX_DESC_RTS_RATE(__pdesc, __val)			\
167 	SET_BITS_OFFSET_LE(__pdesc + 16, 0, 6, __val)
168 #define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val)		\
169 	SET_BITS_OFFSET_LE(__pdesc + 16, 6, 1, __val)
170 #define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val)		\
171 	SET_BITS_OFFSET_LE(__pdesc + 16, 7, 4, __val)
172 #define SET_TX_DESC_CTS_ENABLE(__pdesc, __val)			\
173 	SET_BITS_OFFSET_LE(__pdesc + 16, 11, 1, __val)
174 #define SET_TX_DESC_RTS_ENABLE(__pdesc, __val)			\
175 	SET_BITS_OFFSET_LE(__pdesc + 16, 12, 1, __val)
176 #define SET_TX_DESC_RA_BRSR_ID(__pdesc, __val)			\
177 	SET_BITS_OFFSET_LE(__pdesc + 16, 13, 3, __val)
178 #define SET_TX_DESC_TXHT(__pdesc, __val)			\
179 	SET_BITS_OFFSET_LE(__pdesc + 16, 16, 1, __val)
180 #define SET_TX_DESC_TX_SHORT(__pdesc, __val)			\
181 	SET_BITS_OFFSET_LE(__pdesc + 16, 17, 1, __val)
182 #define SET_TX_DESC_TX_BANDWIDTH(__pdesc, __val)		\
183 	SET_BITS_OFFSET_LE(__pdesc + 16, 18, 1, __val)
184 #define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val)		\
185 	SET_BITS_OFFSET_LE(__pdesc + 16, 19, 2, __val)
186 #define SET_TX_DESC_TX_STBC(__pdesc, __val)			\
187 	SET_BITS_OFFSET_LE(__pdesc + 16, 21, 2, __val)
188 #define SET_TX_DESC_TX_REVERSE_DIRECTION(__pdesc, __val)	\
189 	SET_BITS_OFFSET_LE(__pdesc + 16, 23, 1, __val)
190 #define SET_TX_DESC_RTS_HT(__pdesc, __val)			\
191 	SET_BITS_OFFSET_LE(__pdesc + 16, 24, 1, __val)
192 #define SET_TX_DESC_RTS_SHORT(__pdesc, __val)			\
193 	SET_BITS_OFFSET_LE(__pdesc + 16, 25, 1, __val)
194 #define SET_TX_DESC_RTS_BANDWIDTH(__pdesc, __val)		\
195 	SET_BITS_OFFSET_LE(__pdesc + 16, 26, 1, __val)
196 #define SET_TX_DESC_RTS_SUB_CARRIER(__pdesc, __val)		\
197 	SET_BITS_OFFSET_LE(__pdesc + 16, 27, 2, __val)
198 #define SET_TX_DESC_RTS_STBC(__pdesc, __val)			\
199 	SET_BITS_OFFSET_LE(__pdesc + 16, 29, 2, __val)
200 #define SET_TX_DESC_USER_RATE(__pdesc, __val)			\
201 	SET_BITS_OFFSET_LE(__pdesc + 16, 31, 1, __val)
202 
203 /* Dword 5 */
204 #define SET_TX_DESC_PACKET_ID(__pdesc, __val)			\
205 	SET_BITS_OFFSET_LE(__pdesc + 20, 0, 9, __val)
206 #define SET_TX_DESC_TX_RATE(__pdesc, __val)			\
207 	SET_BITS_OFFSET_LE(__pdesc + 20, 9, 6, __val)
208 #define SET_TX_DESC_DISABLE_FB(__pdesc, __val)			\
209 	SET_BITS_OFFSET_LE(__pdesc + 20, 15, 1, __val)
210 #define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val)		\
211 	SET_BITS_OFFSET_LE(__pdesc + 20, 16, 5, __val)
212 #define SET_TX_DESC_TX_AGC(__pdesc, __val)			\
213 	SET_BITS_OFFSET_LE(__pdesc + 20, 21, 11, __val)
214 
215 /* Dword 6 */
216 #define SET_TX_DESC_IP_CHECK_SUM(__pdesc, __val)		\
217 	SET_BITS_OFFSET_LE(__pdesc + 24, 0, 16, __val)
218 #define SET_TX_DESC_TCP_CHECK_SUM(__pdesc, __val)		\
219 	SET_BITS_OFFSET_LE(__pdesc + 24, 16, 16, __val)
220 
221 /* Dword 7 */
222 #define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val)		\
223 	SET_BITS_OFFSET_LE(__pdesc + 28, 0, 16, __val)
224 #define SET_TX_DESC_IP_HEADER_OFFSET(__pdesc, __val)		\
225 	SET_BITS_OFFSET_LE(__pdesc + 28, 16, 8, __val)
226 #define SET_TX_DESC_TCP_ENABLE(__pdesc, __val)			\
227 	SET_BITS_OFFSET_LE(__pdesc + 28, 31, 1, __val)
228 
229 /* Dword 8 */
230 #define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val)		\
231 	SET_BITS_OFFSET_LE(__pdesc + 32, 0, 32, __val)
232 #define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc)			\
233 	SHIFT_AND_MASK_LE(__pdesc + 32, 0, 32)
234 
235 /* Dword 9 */
236 #define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val)		\
237 	SET_BITS_OFFSET_LE(__pdesc + 36, 0, 32, __val)
238 
239 /* Because the PCI Tx descriptors are chaied at the
240  * initialization and all the NextDescAddresses in
241  * these descriptors cannot not be cleared (,or
242  * driver/HW cannot find the next descriptor), the
243  * offset 36 (NextDescAddresses) is reserved when
244  * the desc is cleared. */
245 #define	TX_DESC_NEXT_DESC_OFFSET			36
246 #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size)		\
247 	memset(__pdesc, 0, min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET))
248 
249 /* Rx Desc */
250 #define RX_STATUS_DESC_SIZE				24
251 #define RX_DRV_INFO_SIZE_UNIT				8
252 
253 /* DWORD 0 */
254 #define SET_RX_STATUS_DESC_PKT_LEN(__pdesc, __val)		\
255 	SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
256 #define SET_RX_STATUS_DESC_CRC32(__pdesc, __val)		\
257 	SET_BITS_OFFSET_LE(__pdesc, 14, 1, __val)
258 #define SET_RX_STATUS_DESC_ICV(__pdesc, __val)			\
259 	SET_BITS_OFFSET_LE(__pdesc, 15, 1, __val)
260 #define SET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc, __val)		\
261 	SET_BITS_OFFSET_LE(__pdesc, 16, 4, __val)
262 #define SET_RX_STATUS_DESC_SECURITY(__pdesc, __val)		\
263 	SET_BITS_OFFSET_LE(__pdesc, 20, 3, __val)
264 #define SET_RX_STATUS_DESC_QOS(__pdesc, __val)			\
265 	SET_BITS_OFFSET_LE(__pdesc, 23, 1, __val)
266 #define SET_RX_STATUS_DESC_SHIFT(__pdesc, __val)		\
267 	SET_BITS_OFFSET_LE(__pdesc, 24, 2, __val)
268 #define SET_RX_STATUS_DESC_PHY_STATUS(__pdesc, __val)		\
269 	SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
270 #define SET_RX_STATUS_DESC_SWDEC(__pdesc, __val)		\
271 	SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
272 #define SET_RX_STATUS_DESC_LAST_SEG(__pdesc, __val)		\
273 	SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
274 #define SET_RX_STATUS_DESC_FIRST_SEG(__pdesc, __val)		\
275 	SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
276 #define SET_RX_STATUS_DESC_EOR(__pdesc, __val)			\
277 	SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
278 #define SET_RX_STATUS_DESC_OWN(__pdesc, __val)			\
279 	SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
280 
281 #define GET_RX_STATUS_DESC_PKT_LEN(__pdesc)			\
282 	SHIFT_AND_MASK_LE(__pdesc, 0, 14)
283 #define GET_RX_STATUS_DESC_CRC32(__pdesc)			\
284 	SHIFT_AND_MASK_LE(__pdesc, 14, 1)
285 #define GET_RX_STATUS_DESC_ICV(__pdesc)				\
286 	SHIFT_AND_MASK_LE(__pdesc, 15, 1)
287 #define GET_RX_STATUS_DESC_DRVINFO_SIZE(__pdesc)		\
288 	SHIFT_AND_MASK_LE(__pdesc, 16, 4)
289 #define GET_RX_STATUS_DESC_SECURITY(__pdesc)			\
290 	SHIFT_AND_MASK_LE(__pdesc, 20, 3)
291 #define GET_RX_STATUS_DESC_QOS(__pdesc)				\
292 	SHIFT_AND_MASK_LE(__pdesc, 23, 1)
293 #define GET_RX_STATUS_DESC_SHIFT(__pdesc)			\
294 	SHIFT_AND_MASK_LE(__pdesc, 24, 2)
295 #define GET_RX_STATUS_DESC_PHY_STATUS(__pdesc)			\
296 	SHIFT_AND_MASK_LE(__pdesc, 26, 1)
297 #define GET_RX_STATUS_DESC_SWDEC(__pdesc)			\
298 	SHIFT_AND_MASK_LE(__pdesc, 27, 1)
299 #define GET_RX_STATUS_DESC_LAST_SEG(__pdesc)			\
300 	SHIFT_AND_MASK_LE(__pdesc, 28, 1)
301 #define GET_RX_STATUS_DESC_FIRST_SEG(__pdesc)			\
302 	SHIFT_AND_MASK_LE(__pdesc, 29, 1)
303 #define GET_RX_STATUS_DESC_EOR(__pdesc)				\
304 	SHIFT_AND_MASK_LE(__pdesc, 30, 1)
305 #define GET_RX_STATUS_DESC_OWN(__pdesc)				\
306 	SHIFT_AND_MASK_LE(__pdesc, 31, 1)
307 
308 /* DWORD 1 */
309 #define SET_RX_STATUS_DESC_MACID(__pdesc, __val)		\
310 	SET_BITS_OFFSET_LE(__pdesc + 4, 0, 5, __val)
311 #define SET_RX_STATUS_DESC_TID(__pdesc, __val)			\
312 	SET_BITS_OFFSET_LE(__pdesc + 4, 5, 4, __val)
313 #define SET_RX_STATUS_DESC_PAGGR(__pdesc, __val)		\
314 	SET_BITS_OFFSET_LE(__pdesc + 4, 14, 1, __val)
315 #define SET_RX_STATUS_DESC_FAGGR(__pdesc, __val)		\
316 	SET_BITS_OFFSET_LE(__pdesc + 4, 15, 1, __val)
317 #define SET_RX_STATUS_DESC_A1_FIT(__pdesc, __val)		\
318 	SET_BITS_OFFSET_LE(__pdesc + 4, 16, 4, __val)
319 #define SET_RX_STATUS_DESC_A2_FIT(__pdesc, __val)		\
320 	SET_BITS_OFFSET_LE(__pdesc + 4, 20, 4, __val)
321 #define SET_RX_STATUS_DESC_PAM(__pdesc, __val)			\
322 	SET_BITS_OFFSET_LE(__pdesc + 4, 24, 1, __val)
323 #define SET_RX_STATUS_DESC_PWR(__pdesc, __val)			\
324 	SET_BITS_OFFSET_LE(__pdesc + 4, 25, 1, __val)
325 #define SET_RX_STATUS_DESC_MOREDATA(__pdesc, __val)		\
326 	SET_BITS_OFFSET_LE(__pdesc + 4, 26, 1, __val)
327 #define SET_RX_STATUS_DESC_MOREFRAG(__pdesc, __val)		\
328 	SET_BITS_OFFSET_LE(__pdesc + 4, 27, 1, __val)
329 #define SET_RX_STATUS_DESC_TYPE(__pdesc, __val)			\
330 	SET_BITS_OFFSET_LE(__pdesc + 4, 28, 2, __val)
331 #define SET_RX_STATUS_DESC_MC(__pdesc, __val)			\
332 	SET_BITS_OFFSET_LE(__pdesc + 4, 30, 1, __val)
333 #define SET_RX_STATUS_DESC_BC(__pdesc, __val)			\
334 	SET_BITS_OFFSET_LE(__pdesc + 4, 31, 1, __val)
335 
336 #define GET_RX_STATUS_DEC_MACID(__pdesc)			\
337 	SHIFT_AND_MASK_LE(__pdesc + 4, 0, 5)
338 #define GET_RX_STATUS_DESC_TID(__pdesc)				\
339 	SHIFT_AND_MASK_LE(__pdesc + 4, 5, 4)
340 #define GET_RX_STATUS_DESC_PAGGR(__pdesc)			\
341 	SHIFT_AND_MASK_LE(__pdesc + 4, 14, 1)
342 #define GET_RX_STATUS_DESC_FAGGR(__pdesc)			\
343 	SHIFT_AND_MASK_LE(__pdesc + 4, 15, 1)
344 #define GET_RX_STATUS_DESC_A1_FIT(__pdesc)			\
345 	SHIFT_AND_MASK_LE(__pdesc + 4, 16, 4)
346 #define GET_RX_STATUS_DESC_A2_FIT(__pdesc)			\
347 	SHIFT_AND_MASK_LE(__pdesc + 4, 20, 4)
348 #define GET_RX_STATUS_DESC_PAM(__pdesc)				\
349 	SHIFT_AND_MASK_LE(__pdesc + 4, 24, 1)
350 #define GET_RX_STATUS_DESC_PWR(__pdesc)				\
351 	SHIFT_AND_MASK_LE(__pdesc + 4, 25, 1)
352 #define GET_RX_STATUS_DESC_MORE_DATA(__pdesc)			\
353 	SHIFT_AND_MASK_LE(__pdesc + 4, 26, 1)
354 #define GET_RX_STATUS_DESC_MORE_FRAG(__pdesc)			\
355 	SHIFT_AND_MASK_LE(__pdesc + 4, 27, 1)
356 #define GET_RX_STATUS_DESC_TYPE(__pdesc)			\
357 	SHIFT_AND_MASK_LE(__pdesc + 4, 28, 2)
358 #define GET_RX_STATUS_DESC_MC(__pdesc)				\
359 	SHIFT_AND_MASK_LE(__pdesc + 4, 30, 1)
360 #define GET_RX_STATUS_DESC_BC(__pdesc)				\
361 	SHIFT_AND_MASK_LE(__pdesc + 4, 31, 1)
362 
363 /* DWORD 2 */
364 #define SET_RX_STATUS_DESC_SEQ(__pdesc, __val)			\
365 	SET_BITS_OFFSET_LE(__pdesc + 8, 0, 12, __val)
366 #define SET_RX_STATUS_DESC_FRAG(__pdesc, __val)			\
367 	SET_BITS_OFFSET_LE(__pdesc + 8, 12, 4, __val)
368 #define SET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc, __val)		\
369 	SET_BITS_OFFSET_LE(__pdesc + 8, 16, 8, __val)
370 #define SET_RX_STATUS_DESC_NEXT_IND(__pdesc, __val)		\
371 	SET_BITS_OFFSET_LE(__pdesc + 8, 30, 1, __val)
372 
373 #define GET_RX_STATUS_DESC_SEQ(__pdesc)				\
374 	SHIFT_AND_MASK_LE(__pdesc + 8, 0, 12)
375 #define GET_RX_STATUS_DESC_FRAG(__pdesc)			\
376 	SHIFT_AND_MASK_LE(__pdesc + 8, 12, 4)
377 #define GET_RX_STATUS_DESC_NEXT_PKTLEN(__pdesc)			\
378 	SHIFT_AND_MASK_LE(__pdesc + 8, 16, 8)
379 #define GET_RX_STATUS_DESC_NEXT_IND(__pdesc)			\
380 	SHIFT_AND_MASK_LE(__pdesc + 8, 30, 1)
381 
382 /* DWORD 3 */
383 #define SET_RX_STATUS_DESC_RX_MCS(__pdesc, __val)		\
384 	SET_BITS_OFFSET_LE(__pdesc + 12, 0, 6, __val)
385 #define SET_RX_STATUS_DESC_RX_HT(__pdesc, __val)		\
386 	SET_BITS_OFFSET_LE(__pdesc + 12, 6, 1, __val)
387 #define SET_RX_STATUS_DESC_AMSDU(__pdesc, __val)		\
388 	SET_BITS_OFFSET_LE(__pdesc + 12, 7, 1, __val)
389 #define SET_RX_STATUS_DESC_SPLCP(__pdesc, __val)		\
390 	SET_BITS_OFFSET_LE(__pdesc + 12, 8, 1, __val)
391 #define SET_RX_STATUS_DESC_BW(__pdesc, __val)			\
392 	SET_BITS_OFFSET_LE(__pdesc + 12, 9, 1, __val)
393 #define SET_RX_STATUS_DESC_HTC(__pdesc, __val)			\
394 	SET_BITS_OFFSET_LE(__pdesc + 12, 10, 1, __val)
395 #define SET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc, __val)		\
396 	SET_BITS_OFFSET_LE(__pdesc + 12, 11, 1, __val)
397 #define SET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc, __val)		\
398 	SET_BITS_OFFSET_LE(__pdesc + 12, 12, 1, __val)
399 #define SET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc, __val)	\
400 	SET_BITS_OFFSET_LE(__pdesc + 12, 13, 1, __val)
401 #define SET_RX_STATUS_DESC_HWPC_ERR(__pdesc, __val)		\
402 	SET_BITS_OFFSET_LE(__pdesc + 12, 14, 1, __val)
403 #define SET_RX_STATUS_DESC_HWPC_IND(__pdesc, __val)		\
404 	SET_BITS_OFFSET_LE(__pdesc + 12, 15, 1, __val)
405 #define SET_RX_STATUS_DESC_IV0(__pdesc, __val)			\
406 	SET_BITS_OFFSET_LE(__pdesc + 12, 16, 16, __val)
407 
408 #define GET_RX_STATUS_DESC_RX_MCS(__pdesc)			\
409 	SHIFT_AND_MASK_LE(__pdesc + 12, 0, 6)
410 #define GET_RX_STATUS_DESC_RX_HT(__pdesc)			\
411 	SHIFT_AND_MASK_LE(__pdesc + 12, 6, 1)
412 #define GET_RX_STATUS_DESC_AMSDU(__pdesc)			\
413 	SHIFT_AND_MASK_LE(__pdesc + 12, 7, 1)
414 #define GET_RX_STATUS_DESC_SPLCP(__pdesc)			\
415 	SHIFT_AND_MASK_LE(__pdesc + 12, 8, 1)
416 #define GET_RX_STATUS_DESC_BW(__pdesc)				\
417 	SHIFT_AND_MASK_LE(__pdesc + 12, 9, 1)
418 #define GET_RX_STATUS_DESC_HTC(__pdesc)				\
419 	SHIFT_AND_MASK_LE(__pdesc + 12, 10, 1)
420 #define GET_RX_STATUS_DESC_TCP_CHK_RPT(__pdesc)			\
421 	SHIFT_AND_MASK_LE(__pdesc + 12, 11, 1)
422 #define GET_RX_STATUS_DESC_IP_CHK_RPT(__pdesc)			\
423 	SHIFT_AND_MASK_LE(__pdesc + 12, 12, 1)
424 #define GET_RX_STATUS_DESC_TCP_CHK_VALID(__pdesc)		\
425 	SHIFT_AND_MASK_LE(__pdesc + 12, 13, 1)
426 #define GET_RX_STATUS_DESC_HWPC_ERR(__pdesc)			\
427 	SHIFT_AND_MASK_LE(__pdesc + 12, 14, 1)
428 #define GET_RX_STATUS_DESC_HWPC_IND(__pdesc)			\
429 	SHIFT_AND_MASK_LE(__pdesc + 12, 15, 1)
430 #define GET_RX_STATUS_DESC_IV0(__pdesc)				\
431 	SHIFT_AND_MASK_LE(__pdesc + 12, 16, 16)
432 
433 /* DWORD 4 */
434 #define SET_RX_STATUS_DESC_IV1(__pdesc, __val)			\
435 	SET_BITS_OFFSET_LE(__pdesc + 16, 0, 32, __val)
436 #define GET_RX_STATUS_DESC_IV1(__pdesc)				\
437 	SHIFT_AND_MASK_LE(__pdesc + 16, 0, 32)
438 
439 /* DWORD 5 */
440 #define SET_RX_STATUS_DESC_TSFL(__pdesc, __val)			\
441 	SET_BITS_OFFSET_LE(__pdesc + 20, 0, 32, __val)
442 #define GET_RX_STATUS_DESC_TSFL(__pdesc)			\
443 	SHIFT_AND_MASK_LE(__pdesc + 20, 0, 32)
444 
445 /* DWORD 6 */
446 #define SET_RX_STATUS__DESC_BUFF_ADDR(__pdesc, __val)	\
447 	SET_BITS_OFFSET_LE(__pdesc + 24, 0, 32, __val)
448 #define GET_RX_STATUS_DESC_BUFF_ADDR(__pdesc)			\
449 	SHIFT_AND_MASK_LE(__pdesc + 24, 0, 32)
450 
451 #define SE_RX_HAL_IS_CCK_RATE(_pdesc)\
452 	(GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE1M ||	\
453 	 GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE2M ||	\
454 	 GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE5_5M ||\
455 	 GET_RX_STATUS_DESC_RX_MCS(_pdesc) == DESC_RATE11M)
456 
457 enum rf_optype {
458 	RF_OP_BY_SW_3WIRE = 0,
459 	RF_OP_BY_FW,
460 	RF_OP_MAX
461 };
462 
463 enum ic_inferiority {
464 	IC_INFERIORITY_A = 0,
465 	IC_INFERIORITY_B = 1,
466 };
467 
468 enum fwcmd_iotype {
469 	/* For DIG DM */
470 	FW_CMD_DIG_ENABLE = 0,
471 	FW_CMD_DIG_DISABLE = 1,
472 	FW_CMD_DIG_HALT = 2,
473 	FW_CMD_DIG_RESUME = 3,
474 	/* For High Power DM */
475 	FW_CMD_HIGH_PWR_ENABLE = 4,
476 	FW_CMD_HIGH_PWR_DISABLE = 5,
477 	/* For Rate adaptive DM */
478 	FW_CMD_RA_RESET = 6,
479 	FW_CMD_RA_ACTIVE = 7,
480 	FW_CMD_RA_REFRESH_N = 8,
481 	FW_CMD_RA_REFRESH_BG = 9,
482 	FW_CMD_RA_INIT = 10,
483 	/* For FW supported IQK */
484 	FW_CMD_IQK_INIT = 11,
485 	/* Tx power tracking switch,
486 	 * MP driver only */
487 	FW_CMD_TXPWR_TRACK_ENABLE = 12,
488 	/* Tx power tracking switch,
489 	 * MP driver only */
490 	FW_CMD_TXPWR_TRACK_DISABLE = 13,
491 	/* Tx power tracking with thermal
492 	 * indication, for Normal driver */
493 	FW_CMD_TXPWR_TRACK_THERMAL = 14,
494 	FW_CMD_PAUSE_DM_BY_SCAN = 15,
495 	FW_CMD_RESUME_DM_BY_SCAN = 16,
496 	FW_CMD_RA_REFRESH_N_COMB = 17,
497 	FW_CMD_RA_REFRESH_BG_COMB = 18,
498 	FW_CMD_ANTENNA_SW_ENABLE = 19,
499 	FW_CMD_ANTENNA_SW_DISABLE = 20,
500 	/* Tx Status report for CCX from FW */
501 	FW_CMD_TX_FEEDBACK_CCX_ENABLE = 21,
502 	/* Indifate firmware that driver
503 	 * enters LPS, For PS-Poll issue */
504 	FW_CMD_LPS_ENTER = 22,
505 	/* Indicate firmware that driver
506 	 * leave LPS*/
507 	FW_CMD_LPS_LEAVE = 23,
508 	/* Set DIG mode to signal strength */
509 	FW_CMD_DIG_MODE_SS = 24,
510 	/* Set DIG mode to false alarm. */
511 	FW_CMD_DIG_MODE_FA = 25,
512 	FW_CMD_ADD_A2_ENTRY = 26,
513 	FW_CMD_CTRL_DM_BY_DRIVER = 27,
514 	FW_CMD_CTRL_DM_BY_DRIVER_NEW = 28,
515 	FW_CMD_PAPE_CONTROL = 29,
516 	FW_CMD_IQK_ENABLE = 30,
517 };
518 
519 /* Driver info contain PHY status
520  * and other variabel size info
521  * PHY Status content as below
522  */
523 struct  rx_fwinfo {
524 	/* DWORD 0 */
525 	u8 gain_trsw[4];
526 	/* DWORD 1 */
527 	u8 pwdb_all;
528 	u8 cfosho[4];
529 	/* DWORD 2 */
530 	u8 cfotail[4];
531 	/* DWORD 3 */
532 	s8 rxevm[2];
533 	s8 rxsnr[4];
534 	/* DWORD 4 */
535 	u8 pdsnr[2];
536 	/* DWORD 5 */
537 	u8 csi_current[2];
538 	u8 csi_target[2];
539 	/* DWORD 6 */
540 	u8 sigevm;
541 	u8 max_ex_pwr;
542 	u8 ex_intf_flag:1;
543 	u8 sgi_en:1;
544 	u8 rxsc:2;
545 	u8 reserve:4;
546 };
547 
548 struct phy_sts_cck_8192s_t {
549 	u8 adc_pwdb_x[4];
550 	u8 sq_rpt;
551 	u8 cck_agc_rpt;
552 };
553 
554 #endif
555 
556