1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2014 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __RTL92E_TRX_H__ 27 #define __RTL92E_TRX_H__ 28 29 #define TX_DESC_SIZE 64 30 31 #define RX_DRV_INFO_SIZE_UNIT 8 32 33 #define TX_DESC_NEXT_DESC_OFFSET 40 34 #define USB_HWDESC_HEADER_LEN 40 35 36 #define RX_DESC_SIZE 24 37 #define MAX_RECEIVE_BUFFER_SIZE 8192 38 39 #define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \ 40 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 16, __val) 41 #define SET_TX_DESC_OFFSET(__pdesc, __val) \ 42 SET_BITS_TO_LE_4BYTE(__pdesc, 16, 8, __val) 43 #define SET_TX_DESC_BMC(__pdesc, __val) \ 44 SET_BITS_TO_LE_4BYTE(__pdesc, 24, 1, __val) 45 #define SET_TX_DESC_HTC(__pdesc, __val) \ 46 SET_BITS_TO_LE_4BYTE(__pdesc, 25, 1, __val) 47 #define SET_TX_DESC_LAST_SEG(__pdesc, __val) \ 48 SET_BITS_TO_LE_4BYTE(__pdesc, 26, 1, __val) 49 #define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \ 50 SET_BITS_TO_LE_4BYTE(__pdesc, 27, 1, __val) 51 #define SET_TX_DESC_LINIP(__pdesc, __val) \ 52 SET_BITS_TO_LE_4BYTE(__pdesc, 28, 1, __val) 53 #define SET_TX_DESC_NO_ACM(__pdesc, __val) \ 54 SET_BITS_TO_LE_4BYTE(__pdesc, 29, 1, __val) 55 #define SET_TX_DESC_GF(__pdesc, __val) \ 56 SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val) 57 #define SET_TX_DESC_OWN(__pdesc, __val) \ 58 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val) 59 60 #define GET_TX_DESC_PKT_SIZE(__pdesc) \ 61 LE_BITS_TO_4BYTE(__pdesc, 0, 16) 62 #define GET_TX_DESC_OFFSET(__pdesc) \ 63 LE_BITS_TO_4BYTE(__pdesc, 16, 8) 64 #define GET_TX_DESC_BMC(__pdesc) \ 65 LE_BITS_TO_4BYTE(__pdesc, 24, 1) 66 #define GET_TX_DESC_HTC(__pdesc) \ 67 LE_BITS_TO_4BYTE(__pdesc, 25, 1) 68 #define GET_TX_DESC_LAST_SEG(__pdesc) \ 69 LE_BITS_TO_4BYTE(__pdesc, 26, 1) 70 #define GET_TX_DESC_FIRST_SEG(__pdesc) \ 71 LE_BITS_TO_4BYTE(__pdesc, 27, 1) 72 #define GET_TX_DESC_LINIP(__pdesc) \ 73 LE_BITS_TO_4BYTE(__pdesc, 28, 1) 74 #define GET_TX_DESC_NO_ACM(__pdesc) \ 75 LE_BITS_TO_4BYTE(__pdesc, 29, 1) 76 #define GET_TX_DESC_GF(__pdesc) \ 77 LE_BITS_TO_4BYTE(__pdesc, 30, 1) 78 #define GET_TX_DESC_OWN(__pdesc) \ 79 LE_BITS_TO_4BYTE(__pdesc, 31, 1) 80 81 #define SET_TX_DESC_MACID(__pdesc, __val) \ 82 SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 7, __val) 83 #define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \ 84 SET_BITS_TO_LE_4BYTE(__pdesc+4, 8, 5, __val) 85 #define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \ 86 SET_BITS_TO_LE_4BYTE(__pdesc+4, 13, 1, __val) 87 #define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \ 88 SET_BITS_TO_LE_4BYTE(__pdesc+4, 14, 1, __val) 89 #define SET_TX_DESC_PIFS(__pdesc, __val) \ 90 SET_BITS_TO_LE_4BYTE(__pdesc+4, 15, 1, __val) 91 #define SET_TX_DESC_RATE_ID(__pdesc, __val) \ 92 SET_BITS_TO_LE_4BYTE(__pdesc+4, 16, 5, __val) 93 #define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \ 94 SET_BITS_TO_LE_4BYTE(__pdesc+4, 21, 1, __val) 95 #define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \ 96 SET_BITS_TO_LE_4BYTE(__pdesc+4, 22, 2, __val) 97 #define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \ 98 SET_BITS_TO_LE_4BYTE(__pdesc+4, 24, 5, __val) 99 #define SET_TX_DESC_MORE_DATA(__pdesc, __val) \ 100 SET_BITS_TO_LE_4BYTE(__pdesc+4, 29, 1, __val) 101 #define SET_TX_DESC_TXOP_PS_CAP(__pdesc, __val) \ 102 SET_BITS_TO_LE_4BYTE(__pdesc+4, 30, 1, __val) 103 #define SET_TX_DESC_TXOP_PS_MODE(__pdesc, __val) \ 104 SET_BITS_TO_LE_4BYTE(__pdesc+4, 31, 1, __val) 105 106 #define GET_TX_DESC_MACID(__pdesc) \ 107 LE_BITS_TO_4BYTE(__pdesc+4, 0, 5) 108 #define GET_TX_DESC_AGG_ENABLE(__pdesc) \ 109 LE_BITS_TO_4BYTE(__pdesc+4, 5, 1) 110 #define GET_TX_DESC_AGG_BREAK(__pdesc) \ 111 LE_BITS_TO_4BYTE(__pdesc+4, 6, 1) 112 #define GET_TX_DESC_RDG_ENABLE(__pdesc) \ 113 LE_BITS_TO_4BYTE(__pdesc+4, 7, 1) 114 #define GET_TX_DESC_QUEUE_SEL(__pdesc) \ 115 LE_BITS_TO_4BYTE(__pdesc+4, 8, 5) 116 #define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \ 117 LE_BITS_TO_4BYTE(__pdesc+4, 13, 1) 118 #define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \ 119 LE_BITS_TO_4BYTE(__pdesc+4, 14, 1) 120 #define GET_TX_DESC_PIFS(__pdesc) \ 121 LE_BITS_TO_4BYTE(__pdesc+4, 15, 1) 122 #define GET_TX_DESC_RATE_ID(__pdesc) \ 123 LE_BITS_TO_4BYTE(__pdesc+4, 16, 4) 124 #define GET_TX_DESC_NAV_USE_HDR(__pdesc) \ 125 LE_BITS_TO_4BYTE(__pdesc+4, 20, 1) 126 #define GET_TX_DESC_EN_DESC_ID(__pdesc) \ 127 LE_BITS_TO_4BYTE(__pdesc+4, 21, 1) 128 #define GET_TX_DESC_SEC_TYPE(__pdesc) \ 129 LE_BITS_TO_4BYTE(__pdesc+4, 22, 2) 130 #define GET_TX_DESC_PKT_OFFSET(__pdesc) \ 131 LE_BITS_TO_4BYTE(__pdesc+4, 24, 5) 132 133 #define SET_TX_DESC_PAID(__pdesc, __val) \ 134 SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 9, __val) 135 #define SET_TX_DESC_CCA_RTS(__pdesc, __val) \ 136 SET_BITS_TO_LE_4BYTE(__pdesc+8, 10, 2, __val) 137 #define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \ 138 SET_BITS_TO_LE_4BYTE(__pdesc+8, 12, 1, __val) 139 #define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \ 140 SET_BITS_TO_LE_4BYTE(__pdesc+8, 13, 1, __val) 141 #define SET_TX_DESC_NULL_0(__pdesc, __val) \ 142 SET_BITS_TO_LE_4BYTE(__pdesc+8, 14, 1, __val) 143 #define SET_TX_DESC_NULL_1(__pdesc, __val) \ 144 SET_BITS_TO_LE_4BYTE((__pdesc) + 8, 15, 1, __val) 145 #define SET_TX_DESC_BK(__pdesc, __val) \ 146 SET_BITS_TO_LE_4BYTE(__pdesc+8, 16, 1, __val) 147 #define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \ 148 SET_BITS_TO_LE_4BYTE(__pdesc+8, 17, 1, __val) 149 #define SET_TX_DESC_RAW(__pdesc, __val) \ 150 SET_BITS_TO_LE_4BYTE(__pdesc+8, 18, 1, __val) 151 #define SET_TX_DESC_SPE_RPT(__pdesc, __val) \ 152 SET_BITS_TO_LE_4BYTE((__pdesc) + 8, 19, 1, __val) 153 #define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \ 154 SET_BITS_TO_LE_4BYTE(__pdesc+8, 20, 3, __val) 155 #define SET_TX_DESC_BT_NULL(__pdesc, __val) \ 156 SET_BITS_TO_LE_4BYTE(__pdesc+8, 23, 1, __val) 157 #define SET_TX_DESC_GID(__pdesc, __val) \ 158 SET_BITS_TO_LE_4BYTE(__pdesc+8, 24, 6, __val) 159 160 #define SET_TX_DESC_WHEADER_LEN(__pdesc, __val) \ 161 SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 4, __val) 162 #define SET_TX_DESC_CHK_EN(__pdesc, __val) \ 163 SET_BITS_TO_LE_4BYTE(__pdesc+12, 4, 1, __val) 164 #define SET_TX_DESC_EARLY_RATE(__pdesc, __val) \ 165 SET_BITS_TO_LE_4BYTE(__pdesc+12, 5, 1, __val) 166 #define SET_TX_DESC_HWSEQ_SEL(__pdesc, __val) \ 167 SET_BITS_TO_LE_4BYTE(__pdesc+12, 6, 2, __val) 168 #define SET_TX_DESC_USE_RATE(__pdesc, __val) \ 169 SET_BITS_TO_LE_4BYTE(__pdesc+12, 8, 1, __val) 170 #define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \ 171 SET_BITS_TO_LE_4BYTE(__pdesc+12, 9, 1, __val) 172 #define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \ 173 SET_BITS_TO_LE_4BYTE(__pdesc+12, 10, 1, __val) 174 #define SET_TX_DESC_CTS2SELF(__pdesc, __val) \ 175 SET_BITS_TO_LE_4BYTE(__pdesc+12, 11, 1, __val) 176 #define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \ 177 SET_BITS_TO_LE_4BYTE(__pdesc+12, 12, 1, __val) 178 #define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \ 179 SET_BITS_TO_LE_4BYTE(__pdesc+12, 13, 1, __val) 180 #define SET_TX_DESC_HW_PORT_ID(__pdesc, __val) \ 181 SET_BITS_TO_LE_4BYTE(__pdesc+12, 14, 1, __val) 182 #define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \ 183 SET_BITS_TO_LE_4BYTE(__pdesc+12, 15, 1, __val) 184 #define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \ 185 SET_BITS_TO_LE_4BYTE(__pdesc+12, 16, 1, __val) 186 #define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \ 187 SET_BITS_TO_LE_4BYTE(__pdesc+12, 17, 5, __val) 188 #define SET_TX_DESC_NDPA(__pdesc, __val) \ 189 SET_BITS_TO_LE_4BYTE(__pdesc+12, 22, 2, __val) 190 #define SET_TX_DESC_AMPDU_MAX_TIME(__pdesc, __val) \ 191 SET_BITS_TO_LE_4BYTE(__pdesc+12, 24, 8, __val) 192 193 /* Dword 4 */ 194 #define SET_TX_DESC_TX_RATE(__pdesc, __val) \ 195 SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 7, __val) 196 #define SET_TX_DESC_TRY_RATE(__pdesc, __val) \ 197 SET_BITS_TO_LE_4BYTE(__pdesc+16, 7, 1, __val) 198 #define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \ 199 SET_BITS_TO_LE_4BYTE(__pdesc+16, 8, 5, __val) 200 #define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \ 201 SET_BITS_TO_LE_4BYTE(__pdesc+16, 13, 4, __val) 202 #define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \ 203 SET_BITS_TO_LE_4BYTE(__pdesc+16, 17, 1, __val) 204 #define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \ 205 SET_BITS_TO_LE_4BYTE(__pdesc+16, 18, 6, __val) 206 #define SET_TX_DESC_RTS_RATE(__pdesc, __val) \ 207 SET_BITS_TO_LE_4BYTE(__pdesc+16, 24, 5, __val) 208 #define SET_TX_DESC_PCTS_ENABLE(__pdesc, __val) \ 209 SET_BITS_TO_LE_4BYTE(__pdesc+16, 29, 1, __val) 210 #define SET_TX_DESC_PCTS_MASK_IDX(__pdesc, __val) \ 211 SET_BITS_TO_LE_4BYTE(__pdesc+16, 30, 2, __val) 212 213 /* Dword 5 */ 214 #define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \ 215 SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 4, __val) 216 #define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \ 217 SET_BITS_TO_LE_4BYTE(__pdesc+20, 4, 1, __val) 218 #define SET_TX_DESC_DATA_BW(__pdesc, __val) \ 219 SET_BITS_TO_LE_4BYTE(__pdesc+20, 5, 2, __val) 220 #define SET_TX_DESC_DATA_LDPC(__pdesc, __val) \ 221 SET_BITS_TO_LE_4BYTE(__pdesc+20, 7, 1, __val) 222 #define SET_TX_DESC_DATA_STBC(__pdesc, __val) \ 223 SET_BITS_TO_LE_4BYTE(__pdesc+20, 8, 2, __val) 224 #define SET_TX_DESC_VCS_STBC(__pdesc, __val) \ 225 SET_BITS_TO_LE_4BYTE(__pdesc+20, 10, 2, __val) 226 #define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \ 227 SET_BITS_TO_LE_4BYTE(__pdesc+20, 12, 1, __val) 228 #define SET_TX_DESC_RTS_SC(__pdesc, __val) \ 229 SET_BITS_TO_LE_4BYTE(__pdesc+20, 13, 4, __val) 230 #define SET_TX_DESC_TX_ANT(__pdesc, __val) \ 231 SET_BITS_TO_LE_4BYTE(__pdesc+20, 24, 4, __val) 232 #define SET_TX_DESC_TX_POWER_0_PSET(__pdesc, __val) \ 233 SET_BITS_TO_LE_4BYTE(__pdesc+20, 28, 3, __val) 234 235 /* Dword 6 */ 236 #define SET_TX_DESC_SW_DEFINE(__pdesc, __val) \ 237 SET_BITS_TO_LE_4BYTE((__pdesc) + 24, 0, 12, __val) 238 #define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \ 239 SET_BITS_TO_LE_4BYTE((__pdesc) + 24, 16, 3, __val) 240 #define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \ 241 SET_BITS_TO_LE_4BYTE((__pdesc) + 24, 19, 3, __val) 242 #define SET_TX_DESC_ANTSEL_C(__pdesc, __val) \ 243 SET_BITS_TO_LE_4BYTE((__pdesc) + 24, 22, 3, __val) 244 #define SET_TX_DESC_ANTSEL_D(__pdesc, __val) \ 245 SET_BITS_TO_LE_4BYTE((__pdesc) + 24, 25, 3, __val) 246 247 /* Dword 7 */ 248 #define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \ 249 SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 16, __val) 250 #define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \ 251 SET_BITS_TO_LE_4BYTE(__pdesc+28, 24, 8, __val) 252 253 /* Dword 8 */ 254 #define SET_TX_DESC_RTS_RC(__pdesc, __val) \ 255 SET_BITS_TO_LE_4BYTE(__pdesc+32, 0, 6, __val) 256 #define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \ 257 SET_BITS_TO_LE_4BYTE(__pdesc+32, 6, 2, __val) 258 #define SET_TX_DESC_DATA_RC(__pdesc, __val) \ 259 SET_BITS_TO_LE_4BYTE(__pdesc+32, 8, 6, __val) 260 #define SET_TX_DESC_ENABLE_HW_SELECT(__pdesc, __val) \ 261 SET_BITS_TO_LE_4BYTE(__pdesc+32, 15, 1, __val) 262 #define SET_TX_DESC_NEXT_HEAD_PAGE(__pdesc, __val) \ 263 SET_BITS_TO_LE_4BYTE(__pdesc+32, 16, 8, __val) 264 #define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \ 265 SET_BITS_TO_LE_4BYTE(__pdesc+32, 24, 8, __val) 266 267 /* Dword 9 */ 268 #define SET_TX_DESC_PADDING_LENGTH(__pdesc, __val) \ 269 SET_BITS_TO_LE_4BYTE(__pdesc+36, 0, 11, __val) 270 #define SET_TX_DESC_TXBF_PATH(__pdesc, __val) \ 271 SET_BITS_TO_LE_4BYTE(__pdesc+36, 11, 1, __val) 272 #define SET_TX_DESC_SEQ(__pdesc, __val) \ 273 SET_BITS_TO_LE_4BYTE(__pdesc+36, 12, 12, __val) 274 #define SET_TX_DESC_FINAL_DATA_RATE(__pdesc, __val) \ 275 SET_BITS_TO_LE_4BYTE(__pdesc+36, 24, 8, __val) 276 277 /* Dword 10 */ 278 #define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \ 279 SET_BITS_TO_LE_4BYTE(__pdesc+40, 0, 32, __val) 280 281 /* Dword 11*/ 282 #define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \ 283 SET_BITS_TO_LE_4BYTE(__pdesc+48, 0, 32, __val) 284 285 #define SET_EARLYMODE_PKTNUM(__paddr, __val) \ 286 SET_BITS_TO_LE_4BYTE(__paddr, 0, 4, __val) 287 #define SET_EARLYMODE_LEN0(__paddr, __val) \ 288 SET_BITS_TO_LE_4BYTE(__paddr, 4, 15, __val) 289 #define SET_EARLYMODE_LEN1(__paddr, __val) \ 290 SET_BITS_TO_LE_4BYTE(__paddr, 16, 2, __val) 291 #define SET_EARLYMODE_LEN1_1(__paddr, __val) \ 292 SET_BITS_TO_LE_4BYTE(__paddr, 19, 13, __val) 293 #define SET_EARLYMODE_LEN1_2(__paddr, __val) \ 294 SET_BITS_TO_LE_4BYTE(__paddr+4, 0, 2, __val) 295 #define SET_EARLYMODE_LEN2(__paddr, __val) \ 296 SET_BITS_TO_LE_4BYTE(__paddr+4, 2, 15, __val) 297 #define SET_EARLYMODE_LEN2_1(__paddr, __val) \ 298 SET_BITS_TO_LE_4BYTE(__paddr, 2, 4, __val) 299 #define SET_EARLYMODE_LEN2_2(__paddr, __val) \ 300 SET_BITS_TO_LE_4BYTE(__paddr+4, 0, 8, __val) 301 #define SET_EARLYMODE_LEN3(__paddr, __val) \ 302 SET_BITS_TO_LE_4BYTE(__paddr+4, 17, 15, __val) 303 #define SET_EARLYMODE_LEN4(__paddr, __val) \ 304 SET_BITS_TO_LE_4BYTE(__paddr+4, 20, 12, __val) 305 306 /* TX/RX buffer descriptor */ 307 308 #define SET_TX_EXTBUFF_DESC_LEN(__pdesc, __val, __set) \ 309 SET_BITS_TO_LE_4BYTE(__pdesc+(__set*16), 0, 16, __val) 310 #define SET_TX_EXTBUFF_DESC_ADDR_LOW(__pdesc, __val, __set)\ 311 SET_BITS_TO_LE_4BYTE(__pdesc+(__set*16)+4, 0, 32, __val) 312 #define SET_TX_EXTBUFF_DESC_ADDR_HIGH(__pdesc, __val, __set)\ 313 SET_BITS_TO_LE_4BYTE(__pdesc+(__set*16)+8, 0, 32, __val) 314 315 /* for Txfilldescroptor92ee, fill the desc content. */ 316 #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pdesc, __offset, __val) \ 317 SET_BITS_TO_LE_4BYTE((__pdesc) + ((__offset) * 16), 0, 16, __val) 318 #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pdesc, __offset, __val) \ 319 SET_BITS_TO_LE_4BYTE((__pdesc) + ((__offset) * 16), 31, 1, __val) 320 #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pdesc, __offset, __val) \ 321 SET_BITS_TO_LE_4BYTE((__pdesc) + ((__offset) * 16) + 4, 0, 32, __val) 322 #define SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(pbd, off, val, dma64) \ 323 (dma64 ? SET_BITS_TO_LE_4BYTE((pbd) + ((off) * 16) + 8, 0, 32, val) : 0) 324 #define GET_TXBUFFER_DESC_ADDR_LOW(__pdesc, __offset) \ 325 LE_BITS_TO_4BYTE((__pdesc) + ((__offset) * 16) + 4, 0, 32) 326 #define GET_TXBUFFER_DESC_ADDR_HIGH(pbd, off, dma64) \ 327 (dma64 ? LE_BITS_TO_4BYTE((pbd) + ((off) * 16) + 8, 0, 32) : 0) 328 329 /* Dword 0 */ 330 #define SET_TX_BUFF_DESC_LEN_0(__pdesc, __val) \ 331 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val) 332 #define SET_TX_BUFF_DESC_PSB(__pdesc, __val) \ 333 SET_BITS_TO_LE_4BYTE(__pdesc, 16, 15, __val) 334 #define SET_TX_BUFF_DESC_OWN(__pdesc, __val) \ 335 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val) 336 337 /* Dword 1 */ 338 #define SET_TX_BUFF_DESC_ADDR_LOW_0(__pdesc, __val) \ 339 SET_BITS_TO_LE_4BYTE((__pdesc) + 4, 0, 32, __val) 340 /* Dword 2 */ 341 #define SET_TX_BUFF_DESC_ADDR_HIGH_0(bdesc, val, dma64) \ 342 SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(bdesc, 0, val, dma64) 343 /* Dword 3 / RESERVED 0 */ 344 345 /* RX buffer */ 346 347 /* DWORD 0 */ 348 #define SET_RX_BUFFER_DESC_DATA_LENGTH(__status, __val) \ 349 SET_BITS_TO_LE_4BYTE(__status, 0, 14, __val) 350 #define SET_RX_BUFFER_DESC_LS(__status, __val) \ 351 SET_BITS_TO_LE_4BYTE(__status, 15, 1, __val) 352 #define SET_RX_BUFFER_DESC_FS(__status, __val) \ 353 SET_BITS_TO_LE_4BYTE(__status, 16, 1, __val) 354 #define SET_RX_BUFFER_DESC_TOTAL_LENGTH(__status, __val) \ 355 SET_BITS_TO_LE_4BYTE(__status, 16, 15, __val) 356 357 #define GET_RX_BUFFER_DESC_OWN(__status) \ 358 LE_BITS_TO_4BYTE(__status, 31, 1) 359 #define GET_RX_BUFFER_DESC_LS(__status) \ 360 LE_BITS_TO_4BYTE(__status, 15, 1) 361 #define GET_RX_BUFFER_DESC_FS(__status) \ 362 LE_BITS_TO_4BYTE(__status, 16, 1) 363 #define GET_RX_BUFFER_DESC_TOTAL_LENGTH(__status) \ 364 LE_BITS_TO_4BYTE(__status, 16, 15) 365 366 /* DWORD 1 */ 367 #define SET_RX_BUFFER_PHYSICAL_LOW(__status, __val) \ 368 SET_BITS_TO_LE_4BYTE(__status+4, 0, 32, __val) 369 370 /* DWORD 2 */ 371 #define SET_RX_BUFFER_PHYSICAL_HIGH(__rx_status_desc, __val, dma64) \ 372 (dma64 ? SET_BITS_TO_LE_4BYTE((__rx_status_desc) + 8, 0, 32, __val) : 0) 373 374 #define GET_RX_DESC_PKT_LEN(__pdesc) \ 375 LE_BITS_TO_4BYTE(__pdesc, 0, 14) 376 #define GET_RX_DESC_CRC32(__pdesc) \ 377 LE_BITS_TO_4BYTE(__pdesc, 14, 1) 378 #define GET_RX_DESC_ICV(__pdesc) \ 379 LE_BITS_TO_4BYTE(__pdesc, 15, 1) 380 #define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \ 381 LE_BITS_TO_4BYTE(__pdesc, 16, 4) 382 #define GET_RX_DESC_SECURITY(__pdesc) \ 383 LE_BITS_TO_4BYTE(__pdesc, 20, 3) 384 #define GET_RX_DESC_QOS(__pdesc) \ 385 LE_BITS_TO_4BYTE(__pdesc, 23, 1) 386 #define GET_RX_DESC_SHIFT(__pdesc) \ 387 LE_BITS_TO_4BYTE(__pdesc, 24, 2) 388 #define GET_RX_DESC_PHYST(__pdesc) \ 389 LE_BITS_TO_4BYTE(__pdesc, 26, 1) 390 #define GET_RX_DESC_SWDEC(__pdesc) \ 391 LE_BITS_TO_4BYTE(__pdesc, 27, 1) 392 #define GET_RX_DESC_LS(__pdesc) \ 393 LE_BITS_TO_4BYTE(__pdesc, 28, 1) 394 #define GET_RX_DESC_FS(__pdesc) \ 395 LE_BITS_TO_4BYTE(__pdesc, 29, 1) 396 #define GET_RX_DESC_EOR(__pdesc) \ 397 LE_BITS_TO_4BYTE(__pdesc, 30, 1) 398 #define GET_RX_DESC_OWN(__pdesc) \ 399 LE_BITS_TO_4BYTE(__pdesc, 31, 1) 400 401 #define SET_RX_DESC_PKT_LEN(__pdesc, __val) \ 402 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val) 403 #define SET_RX_DESC_EOR(__pdesc, __val) \ 404 SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val) 405 #define SET_RX_DESC_OWN(__pdesc, __val) \ 406 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val) 407 408 #define GET_RX_DESC_MACID(__pdesc) \ 409 LE_BITS_TO_4BYTE(__pdesc+4, 0, 7) 410 #define GET_RX_DESC_TID(__pdesc) \ 411 LE_BITS_TO_4BYTE(__pdesc+4, 8, 4) 412 #define GET_RX_DESC_MACID_VLD(__pdesc) \ 413 LE_BITS_TO_4BYTE(__pdesc+4, 12, 1) 414 #define GET_RX_DESC_AMSDU(__pdesc) \ 415 LE_BITS_TO_4BYTE(__pdesc+4, 13, 1) 416 #define GET_RX_DESC_RXID_MATCH(__pdesc) \ 417 LE_BITS_TO_4BYTE(__pdesc+4, 14, 1) 418 #define GET_RX_DESC_PAGGR(__pdesc) \ 419 LE_BITS_TO_4BYTE(__pdesc+4, 15, 1) 420 #define GET_RX_DESC_A1_FIT(__pdesc) \ 421 LE_BITS_TO_4BYTE(__pdesc+4, 16, 4) 422 #define GET_RX_DESC_TCPOFFLOAD_CHKERR(__pdesc) \ 423 LE_BITS_TO_4BYTE(__pdesc+4, 20, 1) 424 #define GET_RX_DESC_TCPOFFLOAD_IPVER(__pdesc) \ 425 LE_BITS_TO_4BYTE(__pdesc+4, 21, 1) 426 #define GET_RX_DESC_TCPOFFLOAD_IS_TCPUDP(__pdesc) \ 427 LE_BITS_TO_4BYTE(__pdesc+4, 22, 1) 428 #define GET_RX_DESC_TCPOFFLOAD_CHK_VLD(__pdesc) \ 429 LE_BITS_TO_4BYTE(__pdesc+4, 23, 1) 430 #define GET_RX_DESC_PAM(__pdesc) \ 431 LE_BITS_TO_4BYTE(__pdesc+4, 24, 1) 432 #define GET_RX_DESC_PWR(__pdesc) \ 433 LE_BITS_TO_4BYTE(__pdesc+4, 25, 1) 434 #define GET_RX_DESC_MD(__pdesc) \ 435 LE_BITS_TO_4BYTE(__pdesc+4, 26, 1) 436 #define GET_RX_DESC_MF(__pdesc) \ 437 LE_BITS_TO_4BYTE(__pdesc+4, 27, 1) 438 #define GET_RX_DESC_TYPE(__pdesc) \ 439 LE_BITS_TO_4BYTE(__pdesc+4, 28, 2) 440 #define GET_RX_DESC_MC(__pdesc) \ 441 LE_BITS_TO_4BYTE(__pdesc+4, 30, 1) 442 #define GET_RX_DESC_BC(__pdesc) \ 443 LE_BITS_TO_4BYTE(__pdesc+4, 31, 1) 444 #define GET_RX_DESC_SEQ(__pdesc) \ 445 LE_BITS_TO_4BYTE(__pdesc+8, 0, 12) 446 #define GET_RX_DESC_FRAG(__pdesc) \ 447 LE_BITS_TO_4BYTE(__pdesc+8, 12, 4) 448 #define GET_RX_DESC_RX_IS_QOS(__pdesc) \ 449 LE_BITS_TO_4BYTE(__pdesc+8, 16, 1) 450 #define GET_RX_STATUS_DESC_RPT_SEL(__pdesc) \ 451 LE_BITS_TO_4BYTE(__pdesc+8, 28, 1) 452 453 #define GET_RX_DESC_RXMCS(__pdesc) \ 454 LE_BITS_TO_4BYTE(__pdesc+12, 0, 7) 455 #define GET_RX_DESC_HTC(__pdesc) \ 456 LE_BITS_TO_4BYTE(__pdesc+12, 10, 1) 457 #define GET_RX_STATUS_DESC_EOSP(__pdesc) \ 458 LE_BITS_TO_4BYTE(__pdesc+12, 11, 1) 459 #define GET_RX_STATUS_DESC_BSSID_FIT(__pdesc) \ 460 LE_BITS_TO_4BYTE(__pdesc+12, 12, 2) 461 #define GET_RX_STATUS_DESC_DMA_AGG_NUM(__pdesc) \ 462 LE_BITS_TO_4BYTE(__pdesc+12, 16, 8) 463 #define GET_RX_STATUS_DESC_PATTERN_MATCH(__pdesc) \ 464 LE_BITS_TO_4BYTE(__pdesc+12, 29, 1) 465 #define GET_RX_STATUS_DESC_UNICAST_MATCH(__pdesc) \ 466 LE_BITS_TO_4BYTE(__pdesc+12, 30, 1) 467 #define GET_RX_STATUS_DESC_MAGIC_MATCH(__pdesc) \ 468 LE_BITS_TO_4BYTE(__pdesc+12, 31, 1) 469 470 #define GET_RX_DESC_TSFL(__pdesc) \ 471 LE_BITS_TO_4BYTE(__pdesc+20, 0, 32) 472 473 #define GET_RX_DESC_BUFF_ADDR(__pdesc) \ 474 LE_BITS_TO_4BYTE(__pdesc+24, 0, 32) 475 #define GET_RX_DESC_BUFF_ADDR64(__pdesc) \ 476 LE_BITS_TO_4BYTE(__pdesc+28, 0, 32) 477 478 #define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \ 479 SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val) 480 #define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \ 481 SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val) 482 483 /* TX report 2 format in Rx desc*/ 484 485 #define GET_RX_RPT2_DESC_PKT_LEN(__status) \ 486 LE_BITS_TO_4BYTE(__status, 0, 9) 487 #define GET_RX_RPT2_DESC_MACID_VALID_1(__status) \ 488 LE_BITS_TO_4BYTE(__status+16, 0, 32) 489 #define GET_RX_RPT2_DESC_MACID_VALID_2(__status) \ 490 LE_BITS_TO_4BYTE(__status+20, 0, 32) 491 492 #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \ 493 do { \ 494 if (_size > TX_DESC_NEXT_DESC_OFFSET) \ 495 memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \ 496 else \ 497 memset(__pdesc, 0, _size); \ 498 } while (0) 499 500 #define RTL92EE_RX_HAL_IS_CCK_RATE(rxmcs)\ 501 (rxmcs == DESC_RATE1M ||\ 502 rxmcs == DESC_RATE2M ||\ 503 rxmcs == DESC_RATE5_5M ||\ 504 rxmcs == DESC_RATE11M) 505 506 #define IS_LITTLE_ENDIAN 1 507 508 struct phy_rx_agc_info_t { 509 #if IS_LITTLE_ENDIAN 510 u8 gain:7, trsw:1; 511 #else 512 u8 trsw:1, gain:7; 513 #endif 514 }; 515 516 struct phy_status_rpt { 517 struct phy_rx_agc_info_t path_agc[2]; 518 u8 ch_corr[2]; 519 u8 cck_sig_qual_ofdm_pwdb_all; 520 u8 cck_agc_rpt_ofdm_cfosho_a; 521 u8 cck_rpt_b_ofdm_cfosho_b; 522 u8 rsvd_1; 523 u8 noise_power_db_msb; 524 u8 path_cfotail[2]; 525 u8 pcts_mask[2]; 526 u8 stream_rxevm[2]; 527 u8 path_rxsnr[2]; 528 u8 noise_power_db_lsb; 529 u8 rsvd_2[3]; 530 u8 stream_csi[2]; 531 u8 stream_target_csi[2]; 532 u8 sig_evm; 533 u8 rsvd_3; 534 #if IS_LITTLE_ENDIAN 535 u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/ 536 u8 sgi_en:1; 537 u8 rxsc:2; 538 u8 idle_long:1; 539 u8 r_ant_train_en:1; 540 u8 ant_sel_b:1; 541 u8 ant_sel:1; 542 #else /* _BIG_ENDIAN_ */ 543 u8 ant_sel:1; 544 u8 ant_sel_b:1; 545 u8 r_ant_train_en:1; 546 u8 idle_long:1; 547 u8 rxsc:2; 548 u8 sgi_en:1; 549 u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/ 550 #endif 551 } __packed; 552 553 struct rx_fwinfo { 554 u8 gain_trsw[4]; 555 u8 pwdb_all; 556 u8 cfosho[4]; 557 u8 cfotail[4]; 558 s8 rxevm[2]; 559 s8 rxsnr[4]; 560 u8 pdsnr[2]; 561 u8 csi_current[2]; 562 u8 csi_target[2]; 563 u8 sigevm; 564 u8 max_ex_pwr; 565 u8 ex_intf_flag:1; 566 u8 sgi_en:1; 567 u8 rxsc:2; 568 u8 reserve:4; 569 } __packed; 570 571 struct tx_desc { 572 u32 pktsize:16; 573 u32 offset:8; 574 u32 bmc:1; 575 u32 htc:1; 576 u32 lastseg:1; 577 u32 firstseg:1; 578 u32 linip:1; 579 u32 noacm:1; 580 u32 gf:1; 581 u32 own:1; 582 583 u32 macid:6; 584 u32 rsvd0:2; 585 u32 queuesel:5; 586 u32 rd_nav_ext:1; 587 u32 lsig_txop_en:1; 588 u32 pifs:1; 589 u32 rateid:4; 590 u32 nav_usehdr:1; 591 u32 en_descid:1; 592 u32 sectype:2; 593 u32 pktoffset:8; 594 595 u32 rts_rc:6; 596 u32 data_rc:6; 597 u32 agg_en:1; 598 u32 rdg_en:1; 599 u32 bar_retryht:2; 600 u32 agg_break:1; 601 u32 morefrag:1; 602 u32 raw:1; 603 u32 ccx:1; 604 u32 ampdudensity:3; 605 u32 bt_int:1; 606 u32 ant_sela:1; 607 u32 ant_selb:1; 608 u32 txant_cck:2; 609 u32 txant_l:2; 610 u32 txant_ht:2; 611 612 u32 nextheadpage:8; 613 u32 tailpage:8; 614 u32 seq:12; 615 u32 cpu_handle:1; 616 u32 tag1:1; 617 u32 trigger_int:1; 618 u32 hwseq_en:1; 619 620 u32 rtsrate:5; 621 u32 apdcfe:1; 622 u32 qos:1; 623 u32 hwseq_ssn:1; 624 u32 userrate:1; 625 u32 dis_rtsfb:1; 626 u32 dis_datafb:1; 627 u32 cts2self:1; 628 u32 rts_en:1; 629 u32 hwrts_en:1; 630 u32 portid:1; 631 u32 pwr_status:3; 632 u32 waitdcts:1; 633 u32 cts2ap_en:1; 634 u32 txsc:2; 635 u32 stbc:2; 636 u32 txshort:1; 637 u32 txbw:1; 638 u32 rtsshort:1; 639 u32 rtsbw:1; 640 u32 rtssc:2; 641 u32 rtsstbc:2; 642 643 u32 txrate:6; 644 u32 shortgi:1; 645 u32 ccxt:1; 646 u32 txrate_fb_lmt:5; 647 u32 rtsrate_fb_lmt:4; 648 u32 retrylmt_en:1; 649 u32 txretrylmt:6; 650 u32 usb_txaggnum:8; 651 652 u32 txagca:5; 653 u32 txagcb:5; 654 u32 usemaxlen:1; 655 u32 maxaggnum:5; 656 u32 mcsg1maxlen:4; 657 u32 mcsg2maxlen:4; 658 u32 mcsg3maxlen:4; 659 u32 mcs7sgimaxlen:4; 660 661 u32 txbuffersize:16; 662 u32 sw_offset30:8; 663 u32 sw_offset31:4; 664 u32 rsvd1:1; 665 u32 antsel_c:1; 666 u32 null_0:1; 667 u32 null_1:1; 668 669 u32 txbuffaddr; 670 u32 txbufferaddr64; 671 u32 nextdescaddress; 672 u32 nextdescaddress64; 673 674 u32 reserve_pass_pcie_mm_limit[4]; 675 } __packed; 676 677 struct rx_desc { 678 u32 length:14; 679 u32 crc32:1; 680 u32 icverror:1; 681 u32 drv_infosize:4; 682 u32 security:3; 683 u32 qos:1; 684 u32 shift:2; 685 u32 phystatus:1; 686 u32 swdec:1; 687 u32 lastseg:1; 688 u32 firstseg:1; 689 u32 eor:1; 690 u32 own:1; 691 692 u32 macid:6; 693 u32 tid:4; 694 u32 hwrsvd:5; 695 u32 paggr:1; 696 u32 faggr:1; 697 u32 a1_fit:4; 698 u32 a2_fit:4; 699 u32 pam:1; 700 u32 pwr:1; 701 u32 moredata:1; 702 u32 morefrag:1; 703 u32 type:2; 704 u32 mc:1; 705 u32 bc:1; 706 707 u32 seq:12; 708 u32 frag:4; 709 u32 nextpktlen:14; 710 u32 nextind:1; 711 u32 rsvd:1; 712 713 u32 rxmcs:6; 714 u32 rxht:1; 715 u32 amsdu:1; 716 u32 splcp:1; 717 u32 bandwidth:1; 718 u32 htc:1; 719 u32 tcpchk_rpt:1; 720 u32 ipcchk_rpt:1; 721 u32 tcpchk_valid:1; 722 u32 hwpcerr:1; 723 u32 hwpcind:1; 724 u32 iv0:16; 725 726 u32 iv1; 727 728 u32 tsfl; 729 730 u32 bufferaddress; 731 u32 bufferaddress64; 732 733 } __packed; 734 735 void rtl92ee_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc, 736 u8 queue_index); 737 u16 rtl92ee_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw, 738 u8 queue_index); 739 u16 rtl92ee_get_available_desc(struct ieee80211_hw *hw, u8 queue_index); 740 void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw, 741 u8 *tx_bd_desc, u8 *desc, u8 queue_index, 742 struct sk_buff *skb, dma_addr_t addr); 743 744 void rtl92ee_tx_fill_desc(struct ieee80211_hw *hw, 745 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 746 u8 *pbd_desc_tx, 747 struct ieee80211_tx_info *info, 748 struct ieee80211_sta *sta, 749 struct sk_buff *skb, 750 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc); 751 bool rtl92ee_rx_query_desc(struct ieee80211_hw *hw, 752 struct rtl_stats *status, 753 struct ieee80211_rx_status *rx_status, 754 u8 *pdesc, struct sk_buff *skb); 755 void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 756 u8 desc_name, u8 *val); 757 758 u64 rtl92ee_get_desc(struct ieee80211_hw *hw, 759 u8 *pdesc, bool istx, u8 desc_name); 760 bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index); 761 void rtl92ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue); 762 void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, 763 bool firstseg, bool lastseg, 764 struct sk_buff *skb); 765 #endif 766