1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2009-2014 Realtek Corporation.*/ 3 4 #include "../wifi.h" 5 #include "../pci.h" 6 #include "../base.h" 7 #include "../stats.h" 8 #include "reg.h" 9 #include "def.h" 10 #include "phy.h" 11 #include "trx.h" 12 #include "led.h" 13 #include "dm.h" 14 #include "fw.h" 15 16 static u8 _rtl92ee_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue) 17 { 18 __le16 fc = rtl_get_fc(skb); 19 20 if (unlikely(ieee80211_is_beacon(fc))) 21 return QSLT_BEACON; 22 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) 23 return QSLT_MGNT; 24 25 return skb->priority; 26 } 27 28 static void _rtl92ee_query_rxphystatus(struct ieee80211_hw *hw, 29 struct rtl_stats *pstatus, u8 *pdesc, 30 struct rx_fwinfo *p_drvinfo, 31 bool bpacket_match_bssid, 32 bool bpacket_toself, 33 bool packet_beacon) 34 { 35 struct rtl_priv *rtlpriv = rtl_priv(hw); 36 struct phy_status_rpt *p_phystrpt = (struct phy_status_rpt *)p_drvinfo; 37 s8 rx_pwr_all = 0, rx_pwr[4]; 38 u8 rf_rx_num = 0, evm, pwdb_all; 39 u8 i, max_spatial_stream; 40 u32 rssi, total_rssi = 0; 41 bool is_cck = pstatus->is_cck; 42 u8 lan_idx, vga_idx; 43 44 /* Record it for next packet processing */ 45 pstatus->packet_matchbssid = bpacket_match_bssid; 46 pstatus->packet_toself = bpacket_toself; 47 pstatus->packet_beacon = packet_beacon; 48 pstatus->rx_mimo_signalquality[0] = -1; 49 pstatus->rx_mimo_signalquality[1] = -1; 50 51 if (is_cck) { 52 u8 cck_highpwr; 53 u8 cck_agc_rpt; 54 /* CCK Driver info Structure is not the same as OFDM packet. */ 55 cck_agc_rpt = p_phystrpt->cck_agc_rpt_ofdm_cfosho_a; 56 57 /* (1)Hardware does not provide RSSI for CCK 58 * (2)PWDB, Average PWDB cacluated by 59 * hardware (for rate adaptive) 60 */ 61 cck_highpwr = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 62 BIT(9)); 63 64 lan_idx = ((cck_agc_rpt & 0xE0) >> 5); 65 vga_idx = (cck_agc_rpt & 0x1f); 66 switch (lan_idx) { 67 case 7: /*VGA_idx = 27~2*/ 68 if (vga_idx <= 27) 69 rx_pwr_all = -100 + 2 * (27 - vga_idx); 70 else 71 rx_pwr_all = -100; 72 break; 73 case 6: /*VGA_idx = 2~0*/ 74 rx_pwr_all = -48 + 2 * (2 - vga_idx); 75 break; 76 case 5: /*VGA_idx = 7~5*/ 77 rx_pwr_all = -42 + 2 * (7 - vga_idx); 78 break; 79 case 4: /*VGA_idx = 7~4*/ 80 rx_pwr_all = -36 + 2 * (7 - vga_idx); 81 break; 82 case 3: /*VGA_idx = 7~0*/ 83 rx_pwr_all = -24 + 2 * (7 - vga_idx); 84 break; 85 case 2: /*VGA_idx = 5~0*/ 86 if (cck_highpwr) 87 rx_pwr_all = -12 + 2 * (5 - vga_idx); 88 else 89 rx_pwr_all = -6 + 2 * (5 - vga_idx); 90 break; 91 case 1: 92 rx_pwr_all = 8 - 2 * vga_idx; 93 break; 94 case 0: 95 rx_pwr_all = 14 - 2 * vga_idx; 96 break; 97 default: 98 break; 99 } 100 rx_pwr_all += 16; 101 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all); 102 103 if (!cck_highpwr) { 104 if (pwdb_all >= 80) 105 pwdb_all = ((pwdb_all - 80) << 1) + 106 ((pwdb_all - 80) >> 1) + 80; 107 else if ((pwdb_all <= 78) && (pwdb_all >= 20)) 108 pwdb_all += 3; 109 if (pwdb_all > 100) 110 pwdb_all = 100; 111 } 112 113 pstatus->rx_pwdb_all = pwdb_all; 114 pstatus->bt_rx_rssi_percentage = pwdb_all; 115 pstatus->recvsignalpower = rx_pwr_all; 116 117 /* (3) Get Signal Quality (EVM) */ 118 if (bpacket_match_bssid) { 119 u8 sq, sq_rpt; 120 121 if (pstatus->rx_pwdb_all > 40) { 122 sq = 100; 123 } else { 124 sq_rpt = p_phystrpt->cck_sig_qual_ofdm_pwdb_all; 125 if (sq_rpt > 64) 126 sq = 0; 127 else if (sq_rpt < 20) 128 sq = 100; 129 else 130 sq = ((64 - sq_rpt) * 100) / 44; 131 } 132 133 pstatus->signalquality = sq; 134 pstatus->rx_mimo_signalquality[0] = sq; 135 pstatus->rx_mimo_signalquality[1] = -1; 136 } 137 } else { 138 /* (1)Get RSSI for HT rate */ 139 for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) { 140 /* we will judge RF RX path now. */ 141 if (rtlpriv->dm.rfpath_rxenable[i]) 142 rf_rx_num++; 143 144 rx_pwr[i] = ((p_phystrpt->path_agc[i].gain & 0x3f) * 2) 145 - 110; 146 147 pstatus->rx_pwr[i] = rx_pwr[i]; 148 /* Translate DBM to percentage. */ 149 rssi = rtl_query_rxpwrpercentage(rx_pwr[i]); 150 total_rssi += rssi; 151 152 pstatus->rx_mimo_signalstrength[i] = (u8)rssi; 153 } 154 155 /* (2)PWDB, Average PWDB cacluated by 156 * hardware (for rate adaptive) 157 */ 158 rx_pwr_all = ((p_phystrpt->cck_sig_qual_ofdm_pwdb_all >> 1) 159 & 0x7f) - 110; 160 161 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all); 162 pstatus->rx_pwdb_all = pwdb_all; 163 pstatus->bt_rx_rssi_percentage = pwdb_all; 164 pstatus->rxpower = rx_pwr_all; 165 pstatus->recvsignalpower = rx_pwr_all; 166 167 /* (3)EVM of HT rate */ 168 if (pstatus->rate >= DESC_RATEMCS8 && 169 pstatus->rate <= DESC_RATEMCS15) 170 max_spatial_stream = 2; 171 else 172 max_spatial_stream = 1; 173 174 for (i = 0; i < max_spatial_stream; i++) { 175 evm = rtl_evm_db_to_percentage( 176 p_phystrpt->stream_rxevm[i]); 177 178 if (bpacket_match_bssid) { 179 /* Fill value in RFD, Get the first 180 * spatial stream only 181 */ 182 if (i == 0) 183 pstatus->signalquality = (u8)(evm & 184 0xff); 185 pstatus->rx_mimo_signalquality[i] = (u8)(evm & 186 0xff); 187 } 188 } 189 190 if (bpacket_match_bssid) { 191 for (i = RF90_PATH_A; i <= RF90_PATH_B; i++) 192 rtl_priv(hw)->dm.cfo_tail[i] = 193 (int)p_phystrpt->path_cfotail[i]; 194 195 if (rtl_priv(hw)->dm.packet_count == 0xffffffff) 196 rtl_priv(hw)->dm.packet_count = 0; 197 else 198 rtl_priv(hw)->dm.packet_count++; 199 } 200 } 201 202 /* UI BSS List signal strength(in percentage), 203 * make it good looking, from 0~100. 204 */ 205 if (is_cck) 206 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw, 207 pwdb_all)); 208 else if (rf_rx_num != 0) 209 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw, 210 total_rssi /= rf_rx_num)); 211 } 212 213 static void _rtl92ee_translate_rx_signal_stuff(struct ieee80211_hw *hw, 214 struct sk_buff *skb, 215 struct rtl_stats *pstatus, 216 u8 *pdesc, 217 struct rx_fwinfo *p_drvinfo) 218 { 219 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 220 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 221 struct ieee80211_hdr *hdr; 222 u8 *tmp_buf; 223 u8 *praddr; 224 u8 *psaddr; 225 __le16 fc; 226 bool packet_matchbssid, packet_toself, packet_beacon; 227 228 tmp_buf = skb->data + pstatus->rx_drvinfo_size + 229 pstatus->rx_bufshift + 24; 230 231 hdr = (struct ieee80211_hdr *)tmp_buf; 232 fc = hdr->frame_control; 233 praddr = hdr->addr1; 234 psaddr = ieee80211_get_SA(hdr); 235 ether_addr_copy(pstatus->psaddr, psaddr); 236 237 packet_matchbssid = (!ieee80211_is_ctl(fc) && 238 (ether_addr_equal(mac->bssid, 239 ieee80211_has_tods(fc) ? 240 hdr->addr1 : 241 ieee80211_has_fromds(fc) ? 242 hdr->addr2 : hdr->addr3)) && 243 (!pstatus->hwerror) && (!pstatus->crc) && 244 (!pstatus->icv)); 245 246 packet_toself = packet_matchbssid && 247 (ether_addr_equal(praddr, rtlefuse->dev_addr)); 248 249 if (ieee80211_is_beacon(fc)) 250 packet_beacon = true; 251 else 252 packet_beacon = false; 253 254 if (packet_beacon && packet_matchbssid) 255 rtl_priv(hw)->dm.dbginfo.num_qry_beacon_pkt++; 256 257 if (packet_matchbssid && ieee80211_is_data_qos(hdr->frame_control) && 258 !is_multicast_ether_addr(ieee80211_get_DA(hdr))) { 259 struct ieee80211_qos_hdr *hdr_qos = 260 (struct ieee80211_qos_hdr *)tmp_buf; 261 u16 tid = le16_to_cpu(hdr_qos->qos_ctrl) & 0xf; 262 263 if (tid != 0 && tid != 3) 264 rtl_priv(hw)->dm.dbginfo.num_non_be_pkt++; 265 } 266 267 _rtl92ee_query_rxphystatus(hw, pstatus, pdesc, p_drvinfo, 268 packet_matchbssid, packet_toself, 269 packet_beacon); 270 rtl_process_phyinfo(hw, tmp_buf, pstatus); 271 } 272 273 static void _rtl92ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc, 274 u8 *virtualaddress) 275 { 276 u32 dwtmp = 0; 277 278 memset(virtualaddress, 0, 8); 279 280 SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num); 281 if (ptcb_desc->empkt_num == 1) { 282 dwtmp = ptcb_desc->empkt_len[0]; 283 } else { 284 dwtmp = ptcb_desc->empkt_len[0]; 285 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4; 286 dwtmp += ptcb_desc->empkt_len[1]; 287 } 288 SET_EARLYMODE_LEN0(virtualaddress, dwtmp); 289 290 if (ptcb_desc->empkt_num <= 3) { 291 dwtmp = ptcb_desc->empkt_len[2]; 292 } else { 293 dwtmp = ptcb_desc->empkt_len[2]; 294 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4; 295 dwtmp += ptcb_desc->empkt_len[3]; 296 } 297 SET_EARLYMODE_LEN1(virtualaddress, dwtmp); 298 if (ptcb_desc->empkt_num <= 5) { 299 dwtmp = ptcb_desc->empkt_len[4]; 300 } else { 301 dwtmp = ptcb_desc->empkt_len[4]; 302 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4; 303 dwtmp += ptcb_desc->empkt_len[5]; 304 } 305 SET_EARLYMODE_LEN2_1(virtualaddress, dwtmp & 0xF); 306 SET_EARLYMODE_LEN2_2(virtualaddress, dwtmp >> 4); 307 if (ptcb_desc->empkt_num <= 7) { 308 dwtmp = ptcb_desc->empkt_len[6]; 309 } else { 310 dwtmp = ptcb_desc->empkt_len[6]; 311 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4; 312 dwtmp += ptcb_desc->empkt_len[7]; 313 } 314 SET_EARLYMODE_LEN3(virtualaddress, dwtmp); 315 if (ptcb_desc->empkt_num <= 9) { 316 dwtmp = ptcb_desc->empkt_len[8]; 317 } else { 318 dwtmp = ptcb_desc->empkt_len[8]; 319 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4; 320 dwtmp += ptcb_desc->empkt_len[9]; 321 } 322 SET_EARLYMODE_LEN4(virtualaddress, dwtmp); 323 } 324 325 bool rtl92ee_rx_query_desc(struct ieee80211_hw *hw, 326 struct rtl_stats *status, 327 struct ieee80211_rx_status *rx_status, 328 u8 *pdesc, struct sk_buff *skb) 329 { 330 struct rtl_priv *rtlpriv = rtl_priv(hw); 331 struct rx_fwinfo *p_drvinfo; 332 struct ieee80211_hdr *hdr; 333 u32 phystatus = GET_RX_DESC_PHYST(pdesc); 334 u8 wake_match; 335 336 if (GET_RX_STATUS_DESC_RPT_SEL(pdesc) == 0) 337 status->packet_report_type = NORMAL_RX; 338 else 339 status->packet_report_type = C2H_PACKET; 340 status->length = (u16)GET_RX_DESC_PKT_LEN(pdesc); 341 status->rx_drvinfo_size = (u8)GET_RX_DESC_DRV_INFO_SIZE(pdesc) * 342 RX_DRV_INFO_SIZE_UNIT; 343 status->rx_bufshift = (u8)(GET_RX_DESC_SHIFT(pdesc) & 0x03); 344 status->icv = (u16)GET_RX_DESC_ICV(pdesc); 345 status->crc = (u16)GET_RX_DESC_CRC32(pdesc); 346 status->hwerror = (status->crc | status->icv); 347 status->decrypted = !GET_RX_DESC_SWDEC(pdesc); 348 status->rate = (u8)GET_RX_DESC_RXMCS(pdesc); 349 status->isampdu = (bool)(GET_RX_DESC_PAGGR(pdesc) == 1); 350 status->timestamp_low = GET_RX_DESC_TSFL(pdesc); 351 status->is_cck = RTL92EE_RX_HAL_IS_CCK_RATE(status->rate); 352 353 status->macid = GET_RX_DESC_MACID(pdesc); 354 if (GET_RX_STATUS_DESC_PATTERN_MATCH(pdesc)) 355 wake_match = BIT(2); 356 else if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc)) 357 wake_match = BIT(1); 358 else if (GET_RX_STATUS_DESC_UNICAST_MATCH(pdesc)) 359 wake_match = BIT(0); 360 else 361 wake_match = 0; 362 if (wake_match) 363 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD, 364 "GGGGGGGGGGGGGet Wakeup Packet!! WakeMatch=%d\n", 365 wake_match); 366 rx_status->freq = hw->conf.chandef.chan->center_freq; 367 rx_status->band = hw->conf.chandef.chan->band; 368 369 hdr = (struct ieee80211_hdr *)(skb->data + status->rx_drvinfo_size + 370 status->rx_bufshift + 24); 371 372 if (status->crc) 373 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 374 375 if (status->rx_is40mhzpacket) 376 rx_status->bw = RATE_INFO_BW_40; 377 378 if (status->is_ht) 379 rx_status->encoding = RX_ENC_HT; 380 381 rx_status->flag |= RX_FLAG_MACTIME_START; 382 383 /* hw will set status->decrypted true, if it finds the 384 * frame is open data frame or mgmt frame. 385 * So hw will not decryption robust managment frame 386 * for IEEE80211w but still set status->decrypted 387 * true, so here we should set it back to undecrypted 388 * for IEEE80211w frame, and mac80211 sw will help 389 * to decrypt it 390 */ 391 if (status->decrypted) { 392 if ((!_ieee80211_is_robust_mgmt_frame(hdr)) && 393 (ieee80211_has_protected(hdr->frame_control))) 394 rx_status->flag |= RX_FLAG_DECRYPTED; 395 else 396 rx_status->flag &= ~RX_FLAG_DECRYPTED; 397 } 398 399 /* rate_idx: index of data rate into band's 400 * supported rates or MCS index if HT rates 401 * are use (RX_FLAG_HT) 402 * Notice: this is diff with windows define 403 */ 404 rx_status->rate_idx = rtlwifi_rate_mapping(hw, status->is_ht, 405 false, status->rate); 406 407 rx_status->mactime = status->timestamp_low; 408 if (phystatus) { 409 p_drvinfo = (struct rx_fwinfo *)(skb->data + 410 status->rx_bufshift + 24); 411 412 _rtl92ee_translate_rx_signal_stuff(hw, skb, status, pdesc, 413 p_drvinfo); 414 } 415 rx_status->signal = status->recvsignalpower + 10; 416 if (status->packet_report_type == TX_REPORT2) { 417 status->macid_valid_entry[0] = 418 GET_RX_RPT2_DESC_MACID_VALID_1(pdesc); 419 status->macid_valid_entry[1] = 420 GET_RX_RPT2_DESC_MACID_VALID_2(pdesc); 421 } 422 return true; 423 } 424 425 /*in Windows, this == Rx_92EE_Interrupt*/ 426 void rtl92ee_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc, 427 u8 queue_index) 428 { 429 u8 first_seg = 0; 430 u8 last_seg = 0; 431 u16 total_len = 0; 432 u16 read_cnt = 0; 433 434 if (header_desc == NULL) 435 return; 436 437 total_len = (u16)GET_RX_BUFFER_DESC_TOTAL_LENGTH(header_desc); 438 439 first_seg = (u8)GET_RX_BUFFER_DESC_FS(header_desc); 440 441 last_seg = (u8)GET_RX_BUFFER_DESC_LS(header_desc); 442 443 while (total_len == 0 && first_seg == 0 && last_seg == 0) { 444 read_cnt++; 445 total_len = (u16)GET_RX_BUFFER_DESC_TOTAL_LENGTH(header_desc); 446 first_seg = (u8)GET_RX_BUFFER_DESC_FS(header_desc); 447 last_seg = (u8)GET_RX_BUFFER_DESC_LS(header_desc); 448 449 if (read_cnt > 20) 450 break; 451 } 452 } 453 454 u16 rtl92ee_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw, u8 queue_index) 455 { 456 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 457 struct rtl_priv *rtlpriv = rtl_priv(hw); 458 u16 read_point = 0, write_point = 0, remind_cnt = 0; 459 u32 tmp_4byte = 0; 460 static bool start_rx; 461 462 tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_TXBD_IDX); 463 read_point = (u16)((tmp_4byte>>16) & 0x7ff); 464 write_point = (u16)(tmp_4byte & 0x7ff); 465 466 if (write_point != rtlpci->rx_ring[queue_index].next_rx_rp) { 467 RT_TRACE(rtlpriv, COMP_RXDESC, DBG_DMESG, 468 "!!!write point is 0x%x, reg 0x3B4 value is 0x%x\n", 469 write_point, tmp_4byte); 470 tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_TXBD_IDX); 471 read_point = (u16)((tmp_4byte>>16) & 0x7ff); 472 write_point = (u16)(tmp_4byte & 0x7ff); 473 } 474 475 if (read_point > 0) 476 start_rx = true; 477 if (!start_rx) 478 return 0; 479 480 remind_cnt = calc_fifo_space(read_point, write_point, 481 RTL_PCI_MAX_RX_COUNT); 482 483 if (remind_cnt == 0) 484 return 0; 485 486 rtlpci->rx_ring[queue_index].next_rx_rp = write_point; 487 488 return remind_cnt; 489 } 490 491 static u16 get_desc_addr_fr_q_idx(u16 queue_index) 492 { 493 u16 desc_address = REG_BEQ_TXBD_IDX; 494 495 switch (queue_index) { 496 case BK_QUEUE: 497 desc_address = REG_BKQ_TXBD_IDX; 498 break; 499 case BE_QUEUE: 500 desc_address = REG_BEQ_TXBD_IDX; 501 break; 502 case VI_QUEUE: 503 desc_address = REG_VIQ_TXBD_IDX; 504 break; 505 case VO_QUEUE: 506 desc_address = REG_VOQ_TXBD_IDX; 507 break; 508 case BEACON_QUEUE: 509 desc_address = REG_BEQ_TXBD_IDX; 510 break; 511 case TXCMD_QUEUE: 512 desc_address = REG_BEQ_TXBD_IDX; 513 break; 514 case MGNT_QUEUE: 515 desc_address = REG_MGQ_TXBD_IDX; 516 break; 517 case HIGH_QUEUE: 518 desc_address = REG_HI0Q_TXBD_IDX; 519 break; 520 case HCCA_QUEUE: 521 desc_address = REG_BEQ_TXBD_IDX; 522 break; 523 default: 524 break; 525 } 526 return desc_address; 527 } 528 529 u16 rtl92ee_get_available_desc(struct ieee80211_hw *hw, u8 q_idx) 530 { 531 struct rtl_priv *rtlpriv = rtl_priv(hw); 532 u16 point_diff = 0; 533 u16 current_tx_read_point = 0, current_tx_write_point = 0; 534 u32 tmp_4byte; 535 536 tmp_4byte = rtl_read_dword(rtlpriv, 537 get_desc_addr_fr_q_idx(q_idx)); 538 current_tx_read_point = (u16)((tmp_4byte >> 16) & 0x0fff); 539 current_tx_write_point = (u16)((tmp_4byte) & 0x0fff); 540 541 point_diff = calc_fifo_space(current_tx_read_point, 542 current_tx_write_point, 543 TX_DESC_NUM_92E); 544 545 return point_diff; 546 } 547 548 void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw, 549 u8 *tx_bd_desc, u8 *desc, u8 queue_index, 550 struct sk_buff *skb, dma_addr_t addr) 551 { 552 struct rtl_priv *rtlpriv = rtl_priv(hw); 553 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 554 u32 pkt_len = skb->len; 555 u16 desc_size = 40; /*tx desc size*/ 556 u32 psblen = 0; 557 u16 tx_page_size = 0; 558 u32 total_packet_size = 0; 559 u16 current_bd_desc; 560 u8 i = 0; 561 u16 real_desc_size = 0x28; 562 u16 append_early_mode_size = 0; 563 u8 segmentnum = 1 << (RTL8192EE_SEG_NUM + 1); 564 dma_addr_t desc_dma_addr; 565 bool dma64 = rtlpriv->cfg->mod_params->dma64; 566 567 tx_page_size = 2; 568 current_bd_desc = rtlpci->tx_ring[queue_index].cur_tx_wp; 569 570 total_packet_size = desc_size+pkt_len; 571 572 if (rtlpriv->rtlhal.earlymode_enable) { 573 if (queue_index < BEACON_QUEUE) { 574 append_early_mode_size = 8; 575 total_packet_size += append_early_mode_size; 576 } 577 } 578 579 if (tx_page_size > 0) { 580 psblen = (pkt_len + real_desc_size + append_early_mode_size) / 581 (tx_page_size * 128); 582 583 if (psblen * (tx_page_size * 128) < total_packet_size) 584 psblen += 1; 585 } 586 587 /* tx desc addr */ 588 desc_dma_addr = rtlpci->tx_ring[queue_index].dma + 589 (current_bd_desc * TX_DESC_SIZE); 590 591 /* Reset */ 592 SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, 0); 593 SET_TX_BUFF_DESC_PSB(tx_bd_desc, 0); 594 SET_TX_BUFF_DESC_OWN(tx_bd_desc, 0); 595 596 for (i = 1; i < segmentnum; i++) { 597 SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, i, 0); 598 SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, i, 0); 599 SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, i, 0); 600 SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(tx_bd_desc, i, 0, dma64); 601 } 602 603 /* Clear all status */ 604 CLEAR_PCI_TX_DESC_CONTENT(desc, TX_DESC_SIZE); 605 606 if (rtlpriv->rtlhal.earlymode_enable) { 607 if (queue_index < BEACON_QUEUE) { 608 /* This if needs braces */ 609 SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size + 8); 610 } else { 611 SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size); 612 } 613 } else { 614 SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size); 615 } 616 SET_TX_BUFF_DESC_PSB(tx_bd_desc, psblen); 617 SET_TX_BUFF_DESC_ADDR_LOW_0(tx_bd_desc, desc_dma_addr); 618 SET_TX_BUFF_DESC_ADDR_HIGH_0(tx_bd_desc, ((u64)desc_dma_addr >> 32), 619 dma64); 620 621 SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, 1, pkt_len); 622 /* don't using extendsion mode. */ 623 SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, 1, 0); 624 SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, 1, addr); 625 SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(tx_bd_desc, 1, 626 ((u64)addr >> 32), dma64); 627 628 SET_TX_DESC_PKT_SIZE(desc, (u16)(pkt_len)); 629 SET_TX_DESC_TX_BUFFER_SIZE(desc, (u16)(pkt_len)); 630 } 631 632 void rtl92ee_tx_fill_desc(struct ieee80211_hw *hw, 633 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 634 u8 *pbd_desc_tx, 635 struct ieee80211_tx_info *info, 636 struct ieee80211_sta *sta, 637 struct sk_buff *skb, 638 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc) 639 { 640 struct rtl_priv *rtlpriv = rtl_priv(hw); 641 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 642 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 643 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 644 struct rtlwifi_tx_info *tx_info = rtl_tx_skb_cb_info(skb); 645 u8 *pdesc = (u8 *)pdesc_tx; 646 u16 seq_number; 647 __le16 fc = hdr->frame_control; 648 unsigned int buf_len = 0; 649 u8 fw_qsel = _rtl92ee_map_hwqueue_to_fwqueue(skb, hw_queue); 650 bool firstseg = ((hdr->seq_ctrl & 651 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0); 652 bool lastseg = ((hdr->frame_control & 653 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0); 654 dma_addr_t mapping; 655 u8 bw_40 = 0; 656 u8 short_gi = 0; 657 658 if (mac->opmode == NL80211_IFTYPE_STATION) { 659 bw_40 = mac->bw_40; 660 } else if (mac->opmode == NL80211_IFTYPE_AP || 661 mac->opmode == NL80211_IFTYPE_ADHOC) { 662 if (sta) 663 bw_40 = sta->ht_cap.cap & 664 IEEE80211_HT_CAP_SUP_WIDTH_20_40; 665 } 666 seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 667 rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc); 668 /* reserve 8 byte for AMPDU early mode */ 669 if (rtlhal->earlymode_enable) { 670 skb_push(skb, EM_HDR_LEN); 671 memset(skb->data, 0, EM_HDR_LEN); 672 } 673 buf_len = skb->len; 674 mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len, 675 PCI_DMA_TODEVICE); 676 if (pci_dma_mapping_error(rtlpci->pdev, mapping)) { 677 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, 678 "DMA mapping error\n"); 679 return; 680 } 681 682 if (pbd_desc_tx != NULL) 683 rtl92ee_pre_fill_tx_bd_desc(hw, pbd_desc_tx, pdesc, hw_queue, 684 skb, mapping); 685 686 if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) { 687 firstseg = true; 688 lastseg = true; 689 } 690 if (firstseg) { 691 if (rtlhal->earlymode_enable) { 692 SET_TX_DESC_PKT_OFFSET(pdesc, 1); 693 SET_TX_DESC_OFFSET(pdesc, 694 USB_HWDESC_HEADER_LEN + EM_HDR_LEN); 695 if (ptcb_desc->empkt_num) { 696 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, 697 "Insert 8 byte.pTcb->EMPktNum:%d\n", 698 ptcb_desc->empkt_num); 699 _rtl92ee_insert_emcontent(ptcb_desc, 700 (u8 *)(skb->data)); 701 } 702 } else { 703 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN); 704 } 705 706 707 SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate); 708 709 if (ieee80211_is_mgmt(fc)) { 710 ptcb_desc->use_driver_rate = true; 711 } else { 712 if (rtlpriv->ra.is_special_data) { 713 ptcb_desc->use_driver_rate = true; 714 SET_TX_DESC_TX_RATE(pdesc, DESC_RATE11M); 715 } else { 716 ptcb_desc->use_driver_rate = false; 717 } 718 } 719 720 if (ptcb_desc->hw_rate > DESC_RATEMCS0) 721 short_gi = (ptcb_desc->use_shortgi) ? 1 : 0; 722 else 723 short_gi = (ptcb_desc->use_shortpreamble) ? 1 : 0; 724 725 if (info->flags & IEEE80211_TX_CTL_AMPDU) { 726 SET_TX_DESC_AGG_ENABLE(pdesc, 1); 727 SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14); 728 } 729 SET_TX_DESC_SEQ(pdesc, seq_number); 730 SET_TX_DESC_RTS_ENABLE(pdesc, 731 ((ptcb_desc->rts_enable && 732 !ptcb_desc->cts_enable) ? 1 : 0)); 733 SET_TX_DESC_HW_RTS_ENABLE(pdesc, 0); 734 SET_TX_DESC_CTS2SELF(pdesc, 735 ((ptcb_desc->cts_enable) ? 1 : 0)); 736 737 SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate); 738 SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc); 739 SET_TX_DESC_RTS_SHORT(pdesc, 740 ((ptcb_desc->rts_rate <= DESC_RATE54M) ? 741 (ptcb_desc->rts_use_shortpreamble ? 1 : 0) : 742 (ptcb_desc->rts_use_shortgi ? 1 : 0))); 743 744 if (ptcb_desc->tx_enable_sw_calc_duration) 745 SET_TX_DESC_NAV_USE_HDR(pdesc, 1); 746 747 if (bw_40) { 748 if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) { 749 SET_TX_DESC_DATA_BW(pdesc, 1); 750 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3); 751 } else { 752 SET_TX_DESC_DATA_BW(pdesc, 0); 753 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 754 mac->cur_40_prime_sc); 755 } 756 } else { 757 SET_TX_DESC_DATA_BW(pdesc, 0); 758 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0); 759 } 760 761 SET_TX_DESC_LINIP(pdesc, 0); 762 if (sta) { 763 u8 ampdu_density = sta->ht_cap.ampdu_density; 764 765 SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density); 766 } 767 if (info->control.hw_key) { 768 struct ieee80211_key_conf *key = info->control.hw_key; 769 770 switch (key->cipher) { 771 case WLAN_CIPHER_SUITE_WEP40: 772 case WLAN_CIPHER_SUITE_WEP104: 773 case WLAN_CIPHER_SUITE_TKIP: 774 SET_TX_DESC_SEC_TYPE(pdesc, 0x1); 775 break; 776 case WLAN_CIPHER_SUITE_CCMP: 777 SET_TX_DESC_SEC_TYPE(pdesc, 0x3); 778 break; 779 default: 780 SET_TX_DESC_SEC_TYPE(pdesc, 0x0); 781 break; 782 } 783 } 784 785 SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel); 786 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F); 787 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF); 788 SET_TX_DESC_DISABLE_FB(pdesc, 789 ptcb_desc->disable_ratefallback ? 1 : 0); 790 SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0); 791 792 /*SET_TX_DESC_PWR_STATUS(pdesc, pwr_status);*/ 793 /* Set TxRate and RTSRate in TxDesc */ 794 /* This prevent Tx initial rate of new-coming packets */ 795 /* from being overwritten by retried packet rate.*/ 796 if (!ptcb_desc->use_driver_rate) { 797 /*SET_TX_DESC_RTS_RATE(pdesc, 0x08); */ 798 /* SET_TX_DESC_TX_RATE(pdesc, 0x0b); */ 799 } 800 if (ieee80211_is_data_qos(fc)) { 801 if (mac->rdg_en) { 802 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, 803 "Enable RDG function.\n"); 804 SET_TX_DESC_RDG_ENABLE(pdesc, 1); 805 SET_TX_DESC_HTC(pdesc, 1); 806 } 807 } 808 /* tx report */ 809 rtl_set_tx_report(ptcb_desc, pdesc, hw, tx_info); 810 } 811 812 SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0)); 813 SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0)); 814 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping); 815 if (rtlpriv->dm.useramask) { 816 SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index); 817 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id); 818 } else { 819 SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index); 820 SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index); 821 } 822 823 SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1)); 824 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || 825 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) { 826 SET_TX_DESC_BMC(pdesc, 1); 827 } 828 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n"); 829 } 830 831 void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw, 832 u8 *pdesc, bool firstseg, 833 bool lastseg, struct sk_buff *skb) 834 { 835 struct rtl_priv *rtlpriv = rtl_priv(hw); 836 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 837 u8 fw_queue = QSLT_BEACON; 838 dma_addr_t mapping = pci_map_single(rtlpci->pdev, 839 skb->data, skb->len, 840 PCI_DMA_TODEVICE); 841 u8 txdesc_len = 40; 842 843 if (pci_dma_mapping_error(rtlpci->pdev, mapping)) { 844 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, 845 "DMA mapping error\n"); 846 return; 847 } 848 CLEAR_PCI_TX_DESC_CONTENT(pdesc, txdesc_len); 849 850 if (firstseg) 851 SET_TX_DESC_OFFSET(pdesc, txdesc_len); 852 853 SET_TX_DESC_TX_RATE(pdesc, DESC_RATE1M); 854 855 SET_TX_DESC_SEQ(pdesc, 0); 856 857 SET_TX_DESC_LINIP(pdesc, 0); 858 859 SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue); 860 861 SET_TX_DESC_FIRST_SEG(pdesc, 1); 862 SET_TX_DESC_LAST_SEG(pdesc, 1); 863 864 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len)); 865 866 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping); 867 868 SET_TX_DESC_RATE_ID(pdesc, 7); 869 SET_TX_DESC_MACID(pdesc, 0); 870 871 SET_TX_DESC_OWN(pdesc, 1); 872 873 SET_TX_DESC_PKT_SIZE((u8 *)pdesc, (u16)(skb->len)); 874 875 SET_TX_DESC_FIRST_SEG(pdesc, 1); 876 SET_TX_DESC_LAST_SEG(pdesc, 1); 877 878 SET_TX_DESC_OFFSET(pdesc, 40); 879 880 SET_TX_DESC_USE_RATE(pdesc, 1); 881 882 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD, 883 "H2C Tx Cmd Content\n", pdesc, txdesc_len); 884 } 885 886 void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, 887 u8 desc_name, u8 *val) 888 { 889 struct rtl_priv *rtlpriv = rtl_priv(hw); 890 u8 q_idx = *val; 891 bool dma64 = rtlpriv->cfg->mod_params->dma64; 892 893 if (istx) { 894 switch (desc_name) { 895 case HW_DESC_TX_NEXTDESC_ADDR: 896 SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *)val); 897 break; 898 case HW_DESC_OWN:{ 899 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 900 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[q_idx]; 901 u16 max_tx_desc = ring->entries; 902 903 if (q_idx == BEACON_QUEUE) { 904 ring->cur_tx_wp = 0; 905 ring->cur_tx_rp = 0; 906 SET_TX_BUFF_DESC_OWN(pdesc, 1); 907 return; 908 } 909 910 /* make sure tx desc is available by caller */ 911 ring->cur_tx_wp = ((ring->cur_tx_wp + 1) % max_tx_desc); 912 913 rtl_write_word(rtlpriv, 914 get_desc_addr_fr_q_idx(q_idx), 915 ring->cur_tx_wp); 916 } 917 break; 918 } 919 } else { 920 switch (desc_name) { 921 case HW_DESC_RX_PREPARE: 922 SET_RX_BUFFER_DESC_LS(pdesc, 0); 923 SET_RX_BUFFER_DESC_FS(pdesc, 0); 924 SET_RX_BUFFER_DESC_TOTAL_LENGTH(pdesc, 0); 925 926 SET_RX_BUFFER_DESC_DATA_LENGTH(pdesc, 927 MAX_RECEIVE_BUFFER_SIZE + 928 RX_DESC_SIZE); 929 930 SET_RX_BUFFER_PHYSICAL_LOW(pdesc, (*(dma_addr_t *)val) & 931 DMA_BIT_MASK(32)); 932 SET_RX_BUFFER_PHYSICAL_HIGH(pdesc, 933 ((u64)(*(dma_addr_t *)val) 934 >> 32), 935 dma64); 936 break; 937 case HW_DESC_RXERO: 938 SET_RX_DESC_EOR(pdesc, 1); 939 break; 940 default: 941 WARN_ONCE(true, 942 "rtl8192ee: ERR rxdesc :%d not processed\n", 943 desc_name); 944 break; 945 } 946 } 947 } 948 949 u64 rtl92ee_get_desc(struct ieee80211_hw *hw, 950 u8 *pdesc, bool istx, u8 desc_name) 951 { 952 struct rtl_priv *rtlpriv = rtl_priv(hw); 953 u64 ret = 0; 954 bool dma64 = rtlpriv->cfg->mod_params->dma64; 955 956 if (istx) { 957 switch (desc_name) { 958 case HW_DESC_OWN: 959 ret = GET_TX_DESC_OWN(pdesc); 960 break; 961 case HW_DESC_TXBUFF_ADDR: 962 ret = GET_TXBUFFER_DESC_ADDR_LOW(pdesc, 1); 963 ret |= (u64)GET_TXBUFFER_DESC_ADDR_HIGH(pdesc, 1, 964 dma64) << 32; 965 break; 966 default: 967 WARN_ONCE(true, 968 "rtl8192ee: ERR txdesc :%d not processed\n", 969 desc_name); 970 break; 971 } 972 } else { 973 switch (desc_name) { 974 case HW_DESC_OWN: 975 ret = GET_RX_DESC_OWN(pdesc); 976 break; 977 case HW_DESC_RXPKT_LEN: 978 ret = GET_RX_DESC_PKT_LEN(pdesc); 979 break; 980 case HW_DESC_RXBUFF_ADDR: 981 ret = GET_RX_DESC_BUFF_ADDR(pdesc); 982 break; 983 default: 984 WARN_ONCE(true, 985 "rtl8192ee: ERR rxdesc :%d not processed\n", 986 desc_name); 987 break; 988 } 989 } 990 return ret; 991 } 992 993 bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index) 994 { 995 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 996 struct rtl_priv *rtlpriv = rtl_priv(hw); 997 u16 read_point, write_point; 998 bool ret = false; 999 static u8 stop_report_cnt; 1000 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; 1001 1002 { 1003 u16 cur_tx_rp, cur_tx_wp; 1004 u32 tmpu32 = 0; 1005 1006 tmpu32 = 1007 rtl_read_dword(rtlpriv, 1008 get_desc_addr_fr_q_idx(hw_queue)); 1009 cur_tx_rp = (u16)((tmpu32 >> 16) & 0x0fff); 1010 cur_tx_wp = (u16)(tmpu32 & 0x0fff); 1011 1012 /* don't need to update ring->cur_tx_wp */ 1013 ring->cur_tx_rp = cur_tx_rp; 1014 } 1015 1016 read_point = ring->cur_tx_rp; 1017 write_point = ring->cur_tx_wp; 1018 1019 if (write_point > read_point) { 1020 if (index < write_point && index >= read_point) 1021 ret = false; 1022 else 1023 ret = true; 1024 } else if (write_point < read_point) { 1025 if (index > write_point && index < read_point) 1026 ret = true; 1027 else 1028 ret = false; 1029 } else { 1030 if (index != read_point) 1031 ret = true; 1032 } 1033 1034 if (hw_queue == BEACON_QUEUE) 1035 ret = true; 1036 1037 if (rtlpriv->rtlhal.driver_is_goingto_unload || 1038 rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS) 1039 ret = true; 1040 1041 if (hw_queue < BEACON_QUEUE) { 1042 if (!ret) 1043 stop_report_cnt++; 1044 else 1045 stop_report_cnt = 0; 1046 } 1047 1048 return ret; 1049 } 1050 1051 void rtl92ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue) 1052 { 1053 } 1054