1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2014 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../core.h" 28 #include "../pci.h" 29 #include "reg.h" 30 #include "def.h" 31 #include "phy.h" 32 #include "dm.h" 33 #include "hw.h" 34 #include "sw.h" 35 #include "fw.h" 36 #include "trx.h" 37 #include "led.h" 38 #include "table.h" 39 40 #include "../btcoexist/rtl_btc.h" 41 42 #include <linux/vmalloc.h> 43 #include <linux/module.h> 44 45 static void rtl92ee_init_aspm_vars(struct ieee80211_hw *hw) 46 { 47 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 48 49 /*close ASPM for AMD defaultly */ 50 rtlpci->const_amdpci_aspm = 0; 51 52 /** 53 * ASPM PS mode. 54 * 0 - Disable ASPM, 55 * 1 - Enable ASPM without Clock Req, 56 * 2 - Enable ASPM with Clock Req, 57 * 3 - Alwyas Enable ASPM with Clock Req, 58 * 4 - Always Enable ASPM without Clock Req. 59 * set defult to RTL8192CE:3 RTL8192E:2 60 */ 61 rtlpci->const_pci_aspm = 3; 62 63 /*Setting for PCI-E device */ 64 rtlpci->const_devicepci_aspm_setting = 0x03; 65 66 /*Setting for PCI-E bridge */ 67 rtlpci->const_hostpci_aspm_setting = 0x02; 68 69 /** 70 * In Hw/Sw Radio Off situation. 71 * 0 - Default, 72 * 1 - From ASPM setting without low Mac Pwr, 73 * 2 - From ASPM setting with low Mac Pwr, 74 * 3 - Bus D3 75 * set default to RTL8192CE:0 RTL8192SE:2 76 */ 77 rtlpci->const_hwsw_rfoff_d3 = 0; 78 79 /** 80 * This setting works for those device with 81 * backdoor ASPM setting such as EPHY setting. 82 * 0 - Not support ASPM, 83 * 1 - Support ASPM, 84 * 2 - According to chipset. 85 */ 86 rtlpci->const_support_pciaspm = 1; 87 } 88 89 int rtl92ee_init_sw_vars(struct ieee80211_hw *hw) 90 { 91 struct rtl_priv *rtlpriv = rtl_priv(hw); 92 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 93 int err = 0; 94 char *fw_name; 95 96 rtl92ee_bt_reg_init(hw); 97 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support; 98 rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer(); 99 100 rtlpriv->dm.dm_initialgain_enable = 1; 101 rtlpriv->dm.dm_flag = 0; 102 rtlpriv->dm.disable_framebursting = 0; 103 rtlpci->transmit_config = CFENDFORM | BIT(15); 104 105 /*just 2.4G band*/ 106 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G; 107 rtlpriv->rtlhal.bandset = BAND_ON_2_4G; 108 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY; 109 110 rtlpci->receive_config = (RCR_APPFCS | 111 RCR_APP_MIC | 112 RCR_APP_ICV | 113 RCR_APP_PHYST_RXFF | 114 RCR_HTC_LOC_CTRL | 115 RCR_AMF | 116 RCR_ACF | 117 RCR_ACRC32 | 118 RCR_AB | 119 RCR_AM | 120 RCR_APM | 121 0); 122 123 rtlpci->irq_mask[0] = (u32)(IMR_PSTIMEOUT | 124 IMR_C2HCMD | 125 IMR_HIGHDOK | 126 IMR_MGNTDOK | 127 IMR_BKDOK | 128 IMR_BEDOK | 129 IMR_VIDOK | 130 IMR_VODOK | 131 IMR_RDU | 132 IMR_ROK | 133 0); 134 rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0); 135 136 /* for LPS & IPS */ 137 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; 138 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; 139 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; 140 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support; 141 if (rtlpriv->cfg->mod_params->disable_watchdog) 142 pr_info("watchdog disabled\n"); 143 rtlpriv->psc.reg_fwctrl_lps = 3; 144 rtlpriv->psc.reg_max_lps_awakeintvl = 5; 145 /* for ASPM, you can close aspm through 146 * set const_support_pciaspm = 0 147 */ 148 rtl92ee_init_aspm_vars(hw); 149 150 if (rtlpriv->psc.reg_fwctrl_lps == 1) 151 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE; 152 else if (rtlpriv->psc.reg_fwctrl_lps == 2) 153 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE; 154 else if (rtlpriv->psc.reg_fwctrl_lps == 3) 155 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE; 156 157 /* for early mode */ 158 rtlpriv->rtlhal.earlymode_enable = false; 159 160 /*low power */ 161 rtlpriv->psc.low_power_enable = false; 162 163 /* for firmware buf */ 164 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000); 165 if (!rtlpriv->rtlhal.pfirmware) { 166 pr_err("Can't alloc buffer for fw\n"); 167 return 1; 168 } 169 170 /* request fw */ 171 fw_name = "rtlwifi/rtl8192eefw.bin"; 172 173 rtlpriv->max_fw_size = 0x8000; 174 pr_info("Using firmware %s\n", fw_name); 175 err = request_firmware_nowait(THIS_MODULE, 1, fw_name, 176 rtlpriv->io.dev, GFP_KERNEL, hw, 177 rtl_fw_cb); 178 if (err) { 179 pr_err("Failed to request firmware!\n"); 180 return 1; 181 } 182 183 return 0; 184 } 185 186 void rtl92ee_deinit_sw_vars(struct ieee80211_hw *hw) 187 { 188 struct rtl_priv *rtlpriv = rtl_priv(hw); 189 190 if (rtlpriv->rtlhal.pfirmware) { 191 vfree(rtlpriv->rtlhal.pfirmware); 192 rtlpriv->rtlhal.pfirmware = NULL; 193 } 194 } 195 196 /* get bt coexist status */ 197 bool rtl92ee_get_btc_status(void) 198 { 199 return true; 200 } 201 202 static struct rtl_hal_ops rtl8192ee_hal_ops = { 203 .init_sw_vars = rtl92ee_init_sw_vars, 204 .deinit_sw_vars = rtl92ee_deinit_sw_vars, 205 .read_eeprom_info = rtl92ee_read_eeprom_info, 206 .interrupt_recognized = rtl92ee_interrupt_recognized,/*need check*/ 207 .hw_init = rtl92ee_hw_init, 208 .hw_disable = rtl92ee_card_disable, 209 .hw_suspend = rtl92ee_suspend, 210 .hw_resume = rtl92ee_resume, 211 .enable_interrupt = rtl92ee_enable_interrupt, 212 .disable_interrupt = rtl92ee_disable_interrupt, 213 .set_network_type = rtl92ee_set_network_type, 214 .set_chk_bssid = rtl92ee_set_check_bssid, 215 .set_qos = rtl92ee_set_qos, 216 .set_bcn_reg = rtl92ee_set_beacon_related_registers, 217 .set_bcn_intv = rtl92ee_set_beacon_interval, 218 .update_interrupt_mask = rtl92ee_update_interrupt_mask, 219 .get_hw_reg = rtl92ee_get_hw_reg, 220 .set_hw_reg = rtl92ee_set_hw_reg, 221 .update_rate_tbl = rtl92ee_update_hal_rate_tbl, 222 .pre_fill_tx_bd_desc = rtl92ee_pre_fill_tx_bd_desc, 223 .rx_desc_buff_remained_cnt = rtl92ee_rx_desc_buff_remained_cnt, 224 .rx_check_dma_ok = rtl92ee_rx_check_dma_ok, 225 .fill_tx_desc = rtl92ee_tx_fill_desc, 226 .fill_tx_cmddesc = rtl92ee_tx_fill_cmddesc, 227 .query_rx_desc = rtl92ee_rx_query_desc, 228 .set_channel_access = rtl92ee_update_channel_access_setting, 229 .radio_onoff_checking = rtl92ee_gpio_radio_on_off_checking, 230 .set_bw_mode = rtl92ee_phy_set_bw_mode, 231 .switch_channel = rtl92ee_phy_sw_chnl, 232 .dm_watchdog = rtl92ee_dm_watchdog, 233 .scan_operation_backup = rtl92ee_phy_scan_operation_backup, 234 .set_rf_power_state = rtl92ee_phy_set_rf_power_state, 235 .led_control = rtl92ee_led_control, 236 .set_desc = rtl92ee_set_desc, 237 .get_desc = rtl92ee_get_desc, 238 .is_tx_desc_closed = rtl92ee_is_tx_desc_closed, 239 .get_available_desc = rtl92ee_get_available_desc, 240 .tx_polling = rtl92ee_tx_polling, 241 .enable_hw_sec = rtl92ee_enable_hw_security_config, 242 .set_key = rtl92ee_set_key, 243 .init_sw_leds = rtl92ee_init_sw_leds, 244 .get_bbreg = rtl92ee_phy_query_bb_reg, 245 .set_bbreg = rtl92ee_phy_set_bb_reg, 246 .get_rfreg = rtl92ee_phy_query_rf_reg, 247 .set_rfreg = rtl92ee_phy_set_rf_reg, 248 .fill_h2c_cmd = rtl92ee_fill_h2c_cmd, 249 .get_btc_status = rtl92ee_get_btc_status, 250 .rx_command_packet = rtl92ee_rx_command_packet, 251 .c2h_content_parsing = rtl92ee_c2h_content_parsing, 252 }; 253 254 static struct rtl_mod_params rtl92ee_mod_params = { 255 .sw_crypto = false, 256 .inactiveps = true, 257 .swctrl_lps = false, 258 .fwctrl_lps = true, 259 .msi_support = true, 260 .debug_level = 0, 261 .debug_mask = 0, 262 }; 263 264 static const struct rtl_hal_cfg rtl92ee_hal_cfg = { 265 .bar_id = 2, 266 .write_readback = true, 267 .name = "rtl92ee_pci", 268 .ops = &rtl8192ee_hal_ops, 269 .mod_params = &rtl92ee_mod_params, 270 271 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, 272 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, 273 .maps[SYS_CLK] = REG_SYS_CLKR, 274 .maps[MAC_RCR_AM] = AM, 275 .maps[MAC_RCR_AB] = AB, 276 .maps[MAC_RCR_ACRC32] = ACRC32, 277 .maps[MAC_RCR_ACF] = ACF, 278 .maps[MAC_RCR_AAP] = AAP, 279 .maps[MAC_HIMR] = REG_HIMR, 280 .maps[MAC_HIMRE] = REG_HIMRE, 281 282 .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS, 283 284 .maps[EFUSE_TEST] = REG_EFUSE_TEST, 285 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, 286 .maps[EFUSE_CLK] = 0, 287 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, 288 .maps[EFUSE_PWC_EV12V] = PWC_EV12V, 289 .maps[EFUSE_FEN_ELDR] = FEN_ELDR, 290 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN, 291 .maps[EFUSE_ANA8M] = ANA8M, 292 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE, 293 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, 294 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, 295 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES, 296 297 .maps[RWCAM] = REG_CAMCMD, 298 .maps[WCAMI] = REG_CAMWRITE, 299 .maps[RCAMO] = REG_CAMREAD, 300 .maps[CAMDBG] = REG_CAMDBG, 301 .maps[SECR] = REG_SECCFG, 302 .maps[SEC_CAM_NONE] = CAM_NONE, 303 .maps[SEC_CAM_WEP40] = CAM_WEP40, 304 .maps[SEC_CAM_TKIP] = CAM_TKIP, 305 .maps[SEC_CAM_AES] = CAM_AES, 306 .maps[SEC_CAM_WEP104] = CAM_WEP104, 307 308 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, 309 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, 310 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, 311 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, 312 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, 313 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, 314 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, 315 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, 316 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, 317 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, 318 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, 319 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, 320 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, 321 322 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, 323 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, 324 .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0, 325 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, 326 .maps[RTL_IMR_RDU] = IMR_RDU, 327 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, 328 .maps[RTL_IMR_BDOK] = IMR_BCNDOK0, 329 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, 330 .maps[RTL_IMR_TBDER] = IMR_TBDER, 331 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, 332 .maps[RTL_IMR_TBDOK] = IMR_TBDOK, 333 .maps[RTL_IMR_BKDOK] = IMR_BKDOK, 334 .maps[RTL_IMR_BEDOK] = IMR_BEDOK, 335 .maps[RTL_IMR_VIDOK] = IMR_VIDOK, 336 .maps[RTL_IMR_VODOK] = IMR_VODOK, 337 .maps[RTL_IMR_ROK] = IMR_ROK, 338 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER), 339 340 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M, 341 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M, 342 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M, 343 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M, 344 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M, 345 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M, 346 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M, 347 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M, 348 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M, 349 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M, 350 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M, 351 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M, 352 353 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7, 354 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15, 355 }; 356 357 static struct pci_device_id rtl92ee_pci_ids[] = { 358 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x818B, rtl92ee_hal_cfg)}, 359 {}, 360 }; 361 362 MODULE_DEVICE_TABLE(pci, rtl92ee_pci_ids); 363 364 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 365 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>"); 366 MODULE_LICENSE("GPL"); 367 MODULE_DESCRIPTION("Realtek 8192EE 802.11n PCI wireless"); 368 MODULE_FIRMWARE("rtlwifi/rtl8192eefw.bin"); 369 370 module_param_named(swenc, rtl92ee_mod_params.sw_crypto, bool, 0444); 371 module_param_named(debug_level, rtl92ee_mod_params.debug_level, int, 0644); 372 module_param_named(debug_mask, rtl92ee_mod_params.debug_mask, ullong, 0644); 373 module_param_named(ips, rtl92ee_mod_params.inactiveps, bool, 0444); 374 module_param_named(swlps, rtl92ee_mod_params.swctrl_lps, bool, 0444); 375 module_param_named(fwlps, rtl92ee_mod_params.fwctrl_lps, bool, 0444); 376 module_param_named(msi, rtl92ee_mod_params.msi_support, bool, 0444); 377 module_param_named(disable_watchdog, rtl92ee_mod_params.disable_watchdog, 378 bool, 0444); 379 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); 380 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n"); 381 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n"); 382 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n"); 383 MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n"); 384 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)"); 385 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)"); 386 MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n"); 387 388 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume); 389 390 static struct pci_driver rtl92ee_driver = { 391 .name = KBUILD_MODNAME, 392 .id_table = rtl92ee_pci_ids, 393 .probe = rtl_pci_probe, 394 .remove = rtl_pci_disconnect, 395 .driver.pm = &rtlwifi_pm_ops, 396 }; 397 398 module_pci_driver(rtl92ee_driver); 399