1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2014 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __RTL92E_REG_H__ 27 #define __RTL92E_REG_H__ 28 29 #define TXPKT_BUF_SELECT 0x69 30 #define RXPKT_BUF_SELECT 0xA5 31 #define DISABLE_TRXPKT_BUF_ACCESS 0x0 32 33 #define REG_SYS_ISO_CTRL 0x0000 34 #define REG_SYS_FUNC_EN 0x0002 35 #define REG_APS_FSMCO 0x0004 36 #define REG_SYS_CLKR 0x0008 37 #define REG_9346CR 0x000A 38 #define REG_EE_VPD 0x000C 39 #define REG_SYS_SWR_CTRL1 0x0010 40 #define REG_SPS0_CTRL 0x0011 41 #define REG_SYS_SWR_CTRL2 0x0014 42 #define REG_SYS_SWR_CTRL3 0x0018 43 #define REG_RSV_CTRL 0x001C 44 #define REG_RF_CTRL 0x001F 45 #define REG_LPLDO_CTRL 0x0023 46 #define REG_AFE_CTRL1 0x0024 47 #define REG_AFE_XTAL_CTRL 0x0024 48 #define REG_AFE_CTRL2 0x0028 49 #define REG_MAC_PHY_CTRL 0x002c 50 #define REG_AFE_CTRL3 0x002c 51 #define REG_EFUSE_CTRL 0x0030 52 #define REG_EFUSE_TEST 0x0034 53 #define REG_PWR_DATA 0x0038 54 #define REG_CAL_TIMER 0x003C 55 #define REG_ACLK_MON 0x003E 56 #define REG_GPIO_MUXCFG 0x0040 57 #define REG_GPIO_IO_SEL 0x0042 58 #define REG_MAC_PINMUX_CFG 0x0043 59 #define REG_GPIO_PIN_CTRL 0x0044 60 #define REG_GPIO_INTM 0x0048 61 #define REG_LEDCFG0 0x004C 62 #define REG_LEDCFG1 0x004D 63 #define REG_LEDCFG2 0x004E 64 #define REG_LEDCFG3 0x004F 65 #define REG_FSIMR 0x0050 66 #define REG_FSISR 0x0054 67 #define REG_HSIMR 0x0058 68 #define REG_HSISR 0x005c 69 #define REG_SDIO_CTRL 0x0070 70 #define REG_OPT_CTRL 0x0074 71 #define REG_GPIO_OUTPUT 0x006c 72 #define REG_AFE_CTRL4 0x0078 73 #define REG_MCUFWDL 0x0080 74 75 #define REG_HIMR 0x00B0 76 #define REG_HISR 0x00B4 77 #define REG_HIMRE 0x00B8 78 #define REG_HISRE 0x00BC 79 80 #define REG_PMC_DBG_CTRL2 0x00CC 81 #define REG_EFUSE_ACCESS 0x00CF 82 #define REG_HPON_FSM 0x00EC 83 #define REG_SYS_CFG1 0x00F0 84 #define REG_MAC_PHY_CTRL_NORMAL 0x00F8 85 #define REG_SYS_CFG2 0x00FC 86 87 #define REG_CR 0x0100 88 #define REG_PBP 0x0104 89 #define REG_PKT_BUFF_ACCESS_CTRL 0x0106 90 #define REG_TRXDMA_CTRL 0x010C 91 #define REG_TRXFF_BNDY 0x0114 92 #define REG_TRXFF_STATUS 0x0118 93 #define REG_RXFF_PTR 0x011C 94 95 #define REG_CPWM 0x012F 96 #define REG_FWIMR 0x0130 97 #define REG_FWISR 0x0134 98 #define REG_PKTBUF_DBG_CTRL 0x0140 99 #define REG_RXPKTBUF_CTRL 0x0142 100 #define REG_PKTBUF_DBG_DATA_L 0x0144 101 #define REG_PKTBUF_DBG_DATA_H 0x0148 102 103 #define REG_TC0_CTRL 0x0150 104 #define REG_TC1_CTRL 0x0154 105 #define REG_TC2_CTRL 0x0158 106 #define REG_TC3_CTRL 0x015C 107 #define REG_TC4_CTRL 0x0160 108 #define REG_TCUNIT_BASE 0x0164 109 #define REG_RSVD3 0x0168 110 #define REG_C2HEVT_MSG_NORMAL 0x01A0 111 #define REG_C2HEVT_CLEAR 0x01AF 112 #define REG_MCUTST_1 0x01c0 113 #define REG_MCUTST_WOWLAN 0x01C7 114 #define REG_FMETHR 0x01C8 115 #define REG_HMETFR 0x01CC 116 #define REG_HMEBOX_0 0x01D0 117 #define REG_HMEBOX_1 0x01D4 118 #define REG_HMEBOX_2 0x01D8 119 #define REG_HMEBOX_3 0x01DC 120 121 #define REG_LLT_INIT 0x01E0 122 123 #define REG_HMEBOX_EXT_0 0x01F0 124 #define REG_HMEBOX_EXT_1 0x01F4 125 #define REG_HMEBOX_EXT_2 0x01F8 126 #define REG_HMEBOX_EXT_3 0x01FC 127 128 /*----------------------------------------------------- 129 * 130 * 0x0200h ~ 0x027Fh TXDMA Configuration 131 * 132 *----------------------------------------------------- 133 */ 134 #define REG_RQPN 0x0200 135 #define REG_FIFOPAGE 0x0204 136 #define REG_DWBCN0_CTRL 0x0208 137 #define REG_TXDMA_OFFSET_CHK 0x020C 138 #define REG_TXDMA_STATUS 0x0210 139 #define REG_RQPN_NPQ 0x0214 140 #define REG_AUTO_LLT 0x0224 141 #define REG_DWBCN1_CTRL 0x0228 142 143 /*----------------------------------------------------- 144 * 145 * 0x0280h ~ 0x02FFh RXDMA Configuration 146 * 147 *----------------------------------------------------- 148 */ 149 #define REG_RXDMA_AGG_PG_TH 0x0280 150 #define REG_FW_UPD_RDPTR 0x0284 151 #define REG_RXDMA_CONTROL 0x0286 152 #define REG_RXPKT_NUM 0x0287 153 #define REG_RXDMA_STATUS 0x0288 154 #define REG_RXDMA_PRO 0x0290 155 #define REG_EARLY_MODE_CONTROL 0x02BC 156 #define REG_RSVD5 0x02F0 157 #define REG_RSVD6 0x02F4 158 159 /*----------------------------------------------------- 160 * 161 * 0x0300h ~ 0x03FFh PCIe 162 * 163 *----------------------------------------------------- 164 */ 165 #define REG_PCIE_CTRL_REG 0x0300 166 #define REG_INT_MIG 0x0304 167 #define REG_BCNQ_DESA 0x0308 168 #define REG_MGQ_DESA 0x0310 169 #define REG_VOQ_DESA 0x0318 170 #define REG_VIQ_DESA 0x0320 171 #define REG_BEQ_DESA 0x0328 172 #define REG_BKQ_DESA 0x0330 173 #define REG_RX_DESA 0x0338 174 #define REG_HQ0_DESA 0x0340 175 #define REG_HQ1_DESA 0x0348 176 #define REG_HQ2_DESA 0x0350 177 #define REG_HQ3_DESA 0x0358 178 #define REG_HQ4_DESA 0x0360 179 #define REG_HQ5_DESA 0x0368 180 #define REG_HQ6_DESA 0x0370 181 #define REG_HQ7_DESA 0x0378 182 #define REG_MGQ_TXBD_NUM 0x0380 183 #define REG_RX_RXBD_NUM 0x0382 184 #define REG_VOQ_TXBD_NUM 0x0384 185 #define REG_VIQ_TXBD_NUM 0x0386 186 #define REG_BEQ_TXBD_NUM 0x0388 187 #define REG_BKQ_TXBD_NUM 0x038A 188 #define REG_HI0Q_TXBD_NUM 0x038C 189 #define REG_HI1Q_TXBD_NUM 0x038E 190 #define REG_HI2Q_TXBD_NUM 0x0390 191 #define REG_HI3Q_TXBD_NUM 0x0392 192 #define REG_HI4Q_TXBD_NUM 0x0394 193 #define REG_HI5Q_TXBD_NUM 0x0396 194 #define REG_HI6Q_TXBD_NUM 0x0398 195 #define REG_HI7Q_TXBD_NUM 0x039A 196 #define REG_TSFTIMER_HCI 0x039C 197 /*Read Write Point*/ 198 #define REG_VOQ_TXBD_IDX 0x03A0 199 #define REG_VIQ_TXBD_IDX 0x03A4 200 #define REG_BEQ_TXBD_IDX 0x03A8 201 #define REG_BKQ_TXBD_IDX 0x03AC 202 #define REG_MGQ_TXBD_IDX 0x03B0 203 #define REG_RXQ_TXBD_IDX 0x03B4 204 205 #define REG_HI0Q_TXBD_IDX 0x03B8 206 #define REG_HI1Q_TXBD_IDX 0x03BC 207 #define REG_HI2Q_TXBD_IDX 0x03C0 208 #define REG_HI3Q_TXBD_IDX 0x03C4 209 210 #define REG_HI4Q_TXBD_IDX 0x03C8 211 #define REG_HI5Q_TXBD_IDX 0x03CC 212 #define REG_HI6Q_TXBD_IDX 0x03D0 213 #define REG_HI7Q_TXBD_IDX 0x03D4 214 #define REG_PCIE_HCPWM 0x03D8 215 #define REG_PCIE_CTRL2 0x03DB 216 #define REG_PCIE_HRPWM 0x03DC 217 #define REG_H2C_MSG_DRV2FW_INFO 0x03E0 218 #define REG_PCIE_C2H_MSG_REQUEST 0x03E4 219 #define REG_BACKDOOR_DBI_WDATA 0x03E8 220 #define REG_BACKDOOR_DBI_RDATA 0x03EC 221 #define REG_BACKDOOR_DBI_DATA 0x03F0 222 #define REG_MDIO 0x03F4 223 #define REG_MDIO_DATA 0x03F8 224 225 #define REG_HDAQ_DESA_NODEF 0x0000 226 #define REG_CMDQ_DESA_NODEF 0x0000 227 /* spec version 11 228 *----------------------------------------------------- 229 * 230 * 0x0400h ~ 0x047Fh Protocol Configuration 231 * 232 *----------------------------------------------------- 233 */ 234 #define REG_VOQ_INFORMATION 0x0400 235 #define REG_VIQ_INFORMATION 0x0404 236 #define REG_BEQ_INFORMATION 0x0408 237 #define REG_BKQ_INFORMATION 0x040C 238 #define REG_MGQ_INFORMATION 0x0410 239 #define REG_HGQ_INFORMATION 0x0414 240 #define REG_BCNQ_INFORMATION 0x0418 241 #define REG_TXPKT_EMPTY 0x041A 242 243 #define REG_FWHW_TXQ_CTRL 0x0420 244 #define REG_HWSEQ_CTRL 0x0423 245 #define REG_BCNQ_BDNY 0x0424 246 #define REG_MGQ_BDNY 0x0425 247 #define REG_LIFECTRL_CTRL 0x0426 248 #define REG_MULTI_BCNQ_OFFSET 0x0427 249 #define REG_SPEC_SIFS 0x0428 250 #define REG_RETRY_LIMIT 0x042A 251 #define REG_TXBF_CTRL 0x042C 252 #define REG_DARFRC 0x0430 253 #define REG_RARFRC 0x0438 254 #define REG_RRSR 0x0440 255 #define REG_ARFR0 0x0444 256 #define REG_ARFR1 0x044C 257 #define REG_AMPDU_MAX_TIME 0x0456 258 #define REG_BCNQ1_BDNY 0x0457 259 #define REG_AGGLEN_LMT 0x0458 260 #define REG_AMPDU_MIN_SPACE 0x045C 261 #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 262 #define REG_NDPA_OPT_CTRL 0x045F 263 #define REG_FAST_EDCA_CTRL 0x0460 264 #define REG_RD_RESP_PKT_TH 0x0463 265 #define REG_POWER_STAGE1 0x04B4 266 #define REG_POWER_STAGE2 0x04B8 267 #define REG_AMPDU_BURST_MODE 0x04BC 268 #define REG_PKT_VO_VI_LIFE_TIME 0x04C0 269 #define REG_PKT_BE_BK_LIFE_TIME 0x04C2 270 #define REG_STBC_SETTING 0x04C4 271 #define REG_PROT_MODE_CTRL 0x04C8 272 #define REG_MAX_AGGR_NUM 0x04CA 273 #define REG_RTS_MAX_AGGR_NUM 0x04CB 274 #define REG_BAR_MODE_CTRL 0x04CC 275 #define REG_RA_TRY_RATE_AGG_LMT 0x04CF 276 #define REG_MACID_PKT_DROP0 0x04D0 277 278 /*----------------------------------------------------- 279 * 280 * 0x0500h ~ 0x05FFh EDCA Configuration 281 * 282 *----------------------------------------------------- 283 */ 284 #define REG_EDCA_VO_PARAM 0x0500 285 #define REG_EDCA_VI_PARAM 0x0504 286 #define REG_EDCA_BE_PARAM 0x0508 287 #define REG_EDCA_BK_PARAM 0x050C 288 #define REG_BCNTCFG 0x0510 289 #define REG_PIFS 0x0512 290 #define REG_RDG_PIFS 0x0513 291 #define REG_SIFS_CTX 0x0514 292 #define REG_SIFS_TRX 0x0516 293 #define REG_AGGR_BREAK_TIME 0x051A 294 #define REG_SLOT 0x051B 295 #define REG_TX_PTCL_CTRL 0x0520 296 #define REG_TXPAUSE 0x0522 297 #define REG_DIS_TXREQ_CLR 0x0523 298 #define REG_RD_CTRL 0x0524 299 300 #define REG_TBTT_PROHIBIT 0x0540 301 #define REG_RD_NAV_NXT 0x0544 302 #define REG_NAV_PROT_LEN 0x0546 303 #define REG_BCN_CTRL 0x0550 304 #define REG_BCN_CTRL_1 0x0551 305 #define REG_MBID_NUM 0x0552 306 #define REG_DUAL_TSF_RST 0x0553 307 #define REG_BCN_INTERVAL 0x0554 308 #define REG_DRVERLYINT 0x0558 309 #define REG_BCNDMATIM 0x0559 310 #define REG_ATIMWND 0x055A 311 #define REG_BCN_MAX_ERR 0x055D 312 #define REG_RXTSF_OFFSET_CCK 0x055E 313 #define REG_RXTSF_OFFSET_OFDM 0x055F 314 #define REG_TSFTR 0x0560 315 #define REG_CTWND 0x0572 316 #define REG_PSTIMER 0x0580 317 #define REG_TIMER0 0x0584 318 #define REG_TIMER1 0x0588 319 #define REG_BCN_PREDL_ITV 0x058F 320 #define REG_ACMHWCTRL 0x05C0 321 322 /*----------------------------------------------------- 323 * 324 * 0x0600h ~ 0x07FFh WMAC Configuration 325 * 326 *----------------------------------------------------- 327 */ 328 #define REG_MAC_CR 0x0600 329 #define REG_BWOPMODE 0x0603 330 #define REG_TCR 0x0604 331 #define REG_RCR 0x0608 332 #define REG_RX_PKT_LIMIT 0x060C 333 #define REG_RX_DLK_TIME 0x060D 334 #define REG_RX_DRVINFO_SZ 0x060F 335 336 #define REG_MACID 0x0610 337 #define REG_BSSID 0x0618 338 #define REG_MAR 0x0620 339 #define REG_MBIDCAMCFG 0x0628 340 341 #define REG_USTIME_EDCA 0x0638 342 #define REG_MAC_SPEC_SIFS 0x063A 343 #define REG_RESP_SIFS_CCK 0x063C 344 #define REG_RESP_SIFS_OFDM 0x063E 345 #define REG_ACKTO 0x0640 346 #define REG_CTS2TO 0x0641 347 #define REG_EIFS 0x0642 348 349 #define REG_NAV_UPPER 0x0652 350 351 /* Security*/ 352 #define REG_CAMCMD 0x0670 353 #define REG_CAMWRITE 0x0674 354 #define REG_CAMREAD 0x0678 355 #define REG_CAMDBG 0x067C 356 #define REG_SECCFG 0x0680 357 358 /* Power*/ 359 #define REG_WOW_CTRL 0x0690 360 #define REG_PS_RX_INFO 0x0692 361 #define REG_UAPSD_TID 0x0693 362 #define REG_WKFMCAM_NUM 0x0698 363 #define REG_WKFMCAM_RWD 0x069C 364 #define REG_RXFLTMAP0 0x06A0 365 #define REG_RXFLTMAP1 0x06A2 366 #define REG_RXFLTMAP2 0x06A4 367 #define REG_BCN_PSR_RPT 0x06A8 368 #define REG_BT_COEX_TABLE 0x06C0 369 #define REG_BFMER0_INFO 0x06E4 370 #define REG_BFMER1_INFO 0x06EC 371 #define REG_CSI_RPT_PARAM_BW20 0x06F4 372 #define REG_CSI_RPT_PARAM_BW40 0x06F8 373 #define REG_CSI_RPT_PARAM_BW80 0x06FC 374 /* Hardware Port 2*/ 375 #define REG_MACID1 0x0700 376 #define REG_BSSID1 0x0708 377 #define REG_BFMEE_SEL 0x0714 378 #define REG_SND_PTCL_CTRL 0x0718 379 380 #define CR9346 REG_9346CR 381 #define MSR (REG_CR + 2) 382 #define ISR REG_HISR 383 #define TSFR REG_TSFTR 384 385 #define MACIDR0 REG_MACID 386 #define MACIDR4 (REG_MACID + 4) 387 388 #define PBP REG_PBP 389 390 #define IDR0 MACIDR0 391 #define IDR4 MACIDR4 392 393 #define UNUSED_REGISTER 0x1BF 394 #define DCAM UNUSED_REGISTER 395 #define PSR UNUSED_REGISTER 396 #define BBADDR UNUSED_REGISTER 397 #define PHYDATAR UNUSED_REGISTER 398 399 #define INVALID_BBRF_VALUE 0x12345678 400 401 #define MAX_MSS_DENSITY_2T 0x13 402 #define MAX_MSS_DENSITY_1T 0x0A 403 404 #define CMDEEPROM_EN BIT(5) 405 #define CMDEEPROM_SEL BIT(4) 406 #define CMD9346CR_9356SEL BIT(4) 407 #define AUTOLOAD_EEPROM (CMDEEPROM_EN | CMDEEPROM_SEL) 408 #define AUTOLOAD_EFUSE CMDEEPROM_EN 409 410 #define GPIOSEL_GPIO 0 411 #define GPIOSEL_ENBT BIT(5) 412 413 #define GPIO_IN REG_GPIO_PIN_CTRL 414 #define GPIO_OUT (REG_GPIO_PIN_CTRL + 1) 415 #define GPIO_IO_SEL (REG_GPIO_PIN_CTRL + 2) 416 #define GPIO_MOD (REG_GPIO_PIN_CTRL + 3) 417 418 #define MSR_NOLINK 0x00 419 #define MSR_ADHOC 0x01 420 #define MSR_INFRA 0x02 421 #define MSR_AP 0x03 422 423 #define RRSR_RSC_OFFSET 21 424 #define RRSR_SHORT_OFFSET 23 425 #define RRSR_RSC_BW_40M 0x600000 426 #define RRSR_RSC_UPSUBCHNL 0x400000 427 #define RRSR_RSC_LOWSUBCHNL 0x200000 428 #define RRSR_SHORT 0x800000 429 #define RRSR_1M BIT(0) 430 #define RRSR_2M BIT(1) 431 #define RRSR_5_5M BIT(2) 432 #define RRSR_11M BIT(3) 433 #define RRSR_6M BIT(4) 434 #define RRSR_9M BIT(5) 435 #define RRSR_12M BIT(6) 436 #define RRSR_18M BIT(7) 437 #define RRSR_24M BIT(8) 438 #define RRSR_36M BIT(9) 439 #define RRSR_48M BIT(10) 440 #define RRSR_54M BIT(11) 441 #define RRSR_MCS0 BIT(12) 442 #define RRSR_MCS1 BIT(13) 443 #define RRSR_MCS2 BIT(14) 444 #define RRSR_MCS3 BIT(15) 445 #define RRSR_MCS4 BIT(16) 446 #define RRSR_MCS5 BIT(17) 447 #define RRSR_MCS6 BIT(18) 448 #define RRSR_MCS7 BIT(19) 449 #define BRSR_ACKSHORTPMB BIT(23) 450 451 #define RATR_1M 0x00000001 452 #define RATR_2M 0x00000002 453 #define RATR_55M 0x00000004 454 #define RATR_11M 0x00000008 455 #define RATR_6M 0x00000010 456 #define RATR_9M 0x00000020 457 #define RATR_12M 0x00000040 458 #define RATR_18M 0x00000080 459 #define RATR_24M 0x00000100 460 #define RATR_36M 0x00000200 461 #define RATR_48M 0x00000400 462 #define RATR_54M 0x00000800 463 #define RATR_MCS0 0x00001000 464 #define RATR_MCS1 0x00002000 465 #define RATR_MCS2 0x00004000 466 #define RATR_MCS3 0x00008000 467 #define RATR_MCS4 0x00010000 468 #define RATR_MCS5 0x00020000 469 #define RATR_MCS6 0x00040000 470 #define RATR_MCS7 0x00080000 471 #define RATR_MCS8 0x00100000 472 #define RATR_MCS9 0x00200000 473 #define RATR_MCS10 0x00400000 474 #define RATR_MCS11 0x00800000 475 #define RATR_MCS12 0x01000000 476 #define RATR_MCS13 0x02000000 477 #define RATR_MCS14 0x04000000 478 #define RATR_MCS15 0x08000000 479 480 #define RATE_1M BIT(0) 481 #define RATE_2M BIT(1) 482 #define RATE_5_5M BIT(2) 483 #define RATE_11M BIT(3) 484 #define RATE_6M BIT(4) 485 #define RATE_9M BIT(5) 486 #define RATE_12M BIT(6) 487 #define RATE_18M BIT(7) 488 #define RATE_24M BIT(8) 489 #define RATE_36M BIT(9) 490 #define RATE_48M BIT(10) 491 #define RATE_54M BIT(11) 492 #define RATE_MCS0 BIT(12) 493 #define RATE_MCS1 BIT(13) 494 #define RATE_MCS2 BIT(14) 495 #define RATE_MCS3 BIT(15) 496 #define RATE_MCS4 BIT(16) 497 #define RATE_MCS5 BIT(17) 498 #define RATE_MCS6 BIT(18) 499 #define RATE_MCS7 BIT(19) 500 #define RATE_MCS8 BIT(20) 501 #define RATE_MCS9 BIT(21) 502 #define RATE_MCS10 BIT(22) 503 #define RATE_MCS11 BIT(23) 504 #define RATE_MCS12 BIT(24) 505 #define RATE_MCS13 BIT(25) 506 #define RATE_MCS14 BIT(26) 507 #define RATE_MCS15 BIT(27) 508 509 #define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) 510 #define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\ 511 RATR_24M | RATR_36M | RATR_48M | RATR_54M) 512 #define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\ 513 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\ 514 RATR_MCS6 | RATR_MCS7) 515 #define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\ 516 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 |\ 517 RATR_MCS14 | RATR_MCS15) 518 519 #define BW_OPMODE_20MHZ BIT(2) 520 #define BW_OPMODE_5G BIT(1) 521 #define CAM_VALID BIT(15) 522 #define CAM_NOTVALID 0x0000 523 #define CAM_USEDK BIT(5) 524 525 #define CAM_NONE 0x0 526 #define CAM_WEP40 0x01 527 #define CAM_TKIP 0x02 528 #define CAM_AES 0x04 529 #define CAM_WEP104 0x05 530 531 #define TOTAL_CAM_ENTRY 32 532 #define HALF_CAM_ENTRY 16 533 534 #define CAM_WRITE BIT(16) 535 #define CAM_READ 0x00000000 536 #define CAM_POLLINIG BIT(31) 537 538 #define SCR_USEDK 0x01 539 #define SCR_TXSEC_ENABLE 0x02 540 #define SCR_RXSEC_ENABLE 0x04 541 542 /********************************************* 543 * 8192EE IMR/ISR bits 544 **********************************************/ 545 #define IMR_DISABLED 0x0 546 /* IMR DW0(0x0060-0063) Bit 0-31 */ 547 #define IMR_TIMER2 BIT(31) 548 #define IMR_TIMER1 BIT(30) 549 #define IMR_PSTIMEOUT BIT(29) 550 #define IMR_GTINT4 BIT(28) 551 #define IMR_GTINT3 BIT(27) 552 #define IMR_TBDER BIT(26) 553 #define IMR_TBDOK BIT(25) 554 #define IMR_TSF_BIT32_TOGGLE BIT(24) 555 #define IMR_BCNDMAINT0 BIT(20) 556 #define IMR_BCNDOK0 BIT(16) 557 #define IMR_BCNDMAINT_E BIT(14) 558 #define IMR_ATIMEND BIT(12) 559 #define IMR_HISR1_IND_INT BIT(11) 560 #define IMR_C2HCMD BIT(10) 561 #define IMR_CPWM2 BIT(9) 562 #define IMR_CPWM BIT(8) 563 #define IMR_HIGHDOK BIT(7) 564 #define IMR_MGNTDOK BIT(6) 565 #define IMR_BKDOK BIT(5) 566 #define IMR_BEDOK BIT(4) 567 #define IMR_VIDOK BIT(3) 568 #define IMR_VODOK BIT(2) 569 #define IMR_RDU BIT(1) 570 #define IMR_ROK BIT(0) 571 572 /* IMR DW1(0x00B4-00B7) Bit 0-31 */ 573 #define IMR_MCUERR BIT(28) 574 #define IMR_BCNDMAINT7 BIT(27) 575 #define IMR_BCNDMAINT6 BIT(26) 576 #define IMR_BCNDMAINT5 BIT(25) 577 #define IMR_BCNDMAINT4 BIT(24) 578 #define IMR_BCNDMAINT3 BIT(23) 579 #define IMR_BCNDMAINT2 BIT(22) 580 #define IMR_BCNDMAINT1 BIT(21) 581 #define IMR_BCNDOK7 BIT(20) 582 #define IMR_BCNDOK6 BIT(19) 583 #define IMR_BCNDOK5 BIT(18) 584 #define IMR_BCNDOK4 BIT(17) 585 #define IMR_BCNDOK3 BIT(16) 586 #define IMR_BCNDOK2 BIT(15) 587 #define IMR_BCNDOK1 BIT(14) 588 #define IMR_ATIMEND_E BIT(13) 589 #define IMR_TXERR BIT(11) 590 #define IMR_RXERR BIT(10) 591 #define IMR_TXFOVW BIT(9) 592 #define IMR_RXFOVW BIT(8) 593 594 #define HWSET_MAX_SIZE 512 595 #define EFUSE_MAX_SECTION 64 596 #define EFUSE_REAL_CONTENT_LEN 256 597 #define EFUSE_OOB_PROTECT_BYTES 18 598 599 #define EEPROM_DEFAULT_TSSI 0x0 600 #define EEPROM_DEFAULT_TXPOWERDIFF 0x0 601 #define EEPROM_DEFAULT_CRYSTALCAP 0x5 602 #define EEPROM_DEFAULT_BOARDTYPE 0x02 603 #define EEPROM_DEFAULT_TXPOWER 0x1010 604 #define EEPROM_DEFAULT_HT2T_TXPWR 0x10 605 606 #define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 607 #define EEPROM_DEFAULT_THERMALMETER 0x1A 608 #define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0 609 #define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5 610 #define EEPROM_DEFAULT_TXPOWERLEVEL 0x22 611 #define EEPROM_DEFAULT_HT40_2SDIFF 0x0 612 #define EEPROM_DEFAULT_HT20_DIFF 2 613 #define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 614 #define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 615 #define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 616 617 #define RF_OPTION1 0x79 618 #define RF_OPTION2 0x7A 619 #define RF_OPTION3 0x7B 620 #define RF_OPTION4 0x7C 621 622 #define EEPROM_DEFAULT_PID 0x1234 623 #define EEPROM_DEFAULT_VID 0x5678 624 #define EEPROM_DEFAULT_CUSTOMERID 0xAB 625 #define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD 626 #define EEPROM_DEFAULT_VERSION 0 627 628 #define EEPROM_CHANNEL_PLAN_FCC 0x0 629 #define EEPROM_CHANNEL_PLAN_IC 0x1 630 #define EEPROM_CHANNEL_PLAN_ETSI 0x2 631 #define EEPROM_CHANNEL_PLAN_SPAIN 0x3 632 #define EEPROM_CHANNEL_PLAN_FRANCE 0x4 633 #define EEPROM_CHANNEL_PLAN_MKK 0x5 634 #define EEPROM_CHANNEL_PLAN_MKK1 0x6 635 #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 636 #define EEPROM_CHANNEL_PLAN_TELEC 0x8 637 #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 638 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 639 #define EEPROM_CHANNEL_PLAN_NCC 0xB 640 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 641 642 #define EEPROM_CID_DEFAULT 0x0 643 #define EEPROM_CID_TOSHIBA 0x4 644 #define EEPROM_CID_CCX 0x10 645 #define EEPROM_CID_QMI 0x0D 646 #define EEPROM_CID_WHQL 0xFE 647 648 #define RTL8192E_EEPROM_ID 0x8129 649 650 #define EEPROM_HPON 0x02 651 #define EEPROM_CLK 0x06 652 #define EEPROM_TESTR 0x08 653 654 #define EEPROM_TXPOWERCCK 0x10 655 #define EEPROM_TXPOWERHT40_1S 0x16 656 #define EEPROM_TXPOWERHT20DIFF 0x1B 657 #define EEPROM_TXPOWER_OFDMDIFF 0x1B 658 659 #define EEPROM_TX_PWR_INX 0x10 660 661 #define EEPROM_CHANNELPLAN 0xB8 662 #define EEPROM_XTAL_92E 0xB9 663 #define EEPROM_THERMAL_METER_92E 0xBA 664 #define EEPROM_IQK_LCK_92E 0xBB 665 666 #define EEPROM_RF_BOARD_OPTION_92E 0xC1 667 #define EEPROM_RF_FEATURE_OPTION_92E 0xC2 668 #define EEPROM_RF_BT_SETTING_92E 0xC3 669 #define EEPROM_VERSION 0xC4 670 #define EEPROM_CUSTOMER_ID 0xC5 671 #define EEPROM_RF_ANTENNA_OPT_92E 0xC9 672 673 #define EEPROM_MAC_ADDR 0xD0 674 #define EEPROM_VID 0xD6 675 #define EEPROM_DID 0xD8 676 #define EEPROM_SVID 0xDA 677 #define EEPROM_SMID 0xDC 678 679 #define STOPBECON BIT(6) 680 #define STOPHIGHT BIT(5) 681 #define STOPMGT BIT(4) 682 #define STOPVO BIT(3) 683 #define STOPVI BIT(2) 684 #define STOPBE BIT(1) 685 #define STOPBK BIT(0) 686 687 #define RCR_APPFCS BIT(31) 688 #define RCR_APP_MIC BIT(30) 689 #define RCR_APP_ICV BIT(29) 690 #define RCR_APP_PHYST_RXFF BIT(28) 691 #define RCR_APP_BA_SSN BIT(27) 692 #define RCR_ENMBID BIT(24) 693 #define RCR_LSIGEN BIT(23) 694 #define RCR_MFBEN BIT(22) 695 #define RCR_HTC_LOC_CTRL BIT(14) 696 #define RCR_AMF BIT(13) 697 #define RCR_ACF BIT(12) 698 #define RCR_ADF BIT(11) 699 #define RCR_AICV BIT(9) 700 #define RCR_ACRC32 BIT(8) 701 #define RCR_CBSSID_BCN BIT(7) 702 #define RCR_CBSSID_DATA BIT(6) 703 #define RCR_CBSSID RCR_CBSSID_DATA 704 #define RCR_APWRMGT BIT(5) 705 #define RCR_ADD3 BIT(4) 706 #define RCR_AB BIT(3) 707 #define RCR_AM BIT(2) 708 #define RCR_APM BIT(1) 709 #define RCR_AAP BIT(0) 710 #define RCR_MXDMA_OFFSET 8 711 #define RCR_FIFO_OFFSET 13 712 713 #define RSV_CTRL 0x001C 714 #define RD_CTRL 0x0524 715 716 #define REG_USB_INFO 0xFE17 717 #define REG_USB_SPECIAL_OPTION 0xFE55 718 #define REG_USB_DMA_AGG_TO 0xFE5B 719 #define REG_USB_AGG_TO 0xFE5C 720 #define REG_USB_AGG_TH 0xFE5D 721 722 #define REG_USB_VID 0xFE60 723 #define REG_USB_PID 0xFE62 724 #define REG_USB_OPTIONAL 0xFE64 725 #define REG_USB_CHIRP_K 0xFE65 726 #define REG_USB_PHY 0xFE66 727 #define REG_USB_MAC_ADDR 0xFE70 728 #define REG_USB_HRPWM 0xFE58 729 #define REG_USB_HCPWM 0xFE57 730 731 #define SW18_FPWM BIT(3) 732 733 #define ISO_MD2PP BIT(0) 734 #define ISO_UA2USB BIT(1) 735 #define ISO_UD2CORE BIT(2) 736 #define ISO_PA2PCIE BIT(3) 737 #define ISO_PD2CORE BIT(4) 738 #define ISO_IP2MAC BIT(5) 739 #define ISO_DIOP BIT(6) 740 #define ISO_DIOE BIT(7) 741 #define ISO_EB2CORE BIT(8) 742 #define ISO_DIOR BIT(9) 743 744 #define PWC_EV25V BIT(14) 745 #define PWC_EV12V BIT(15) 746 747 #define FEN_BBRSTB BIT(0) 748 #define FEN_BB_GLB_RSTN BIT(1) 749 #define FEN_USBA BIT(2) 750 #define FEN_UPLL BIT(3) 751 #define FEN_USBD BIT(4) 752 #define FEN_DIO_PCIE BIT(5) 753 #define FEN_PCIEA BIT(6) 754 #define FEN_PPLL BIT(7) 755 #define FEN_PCIED BIT(8) 756 #define FEN_DIOE BIT(9) 757 #define FEN_CPUEN BIT(10) 758 #define FEN_DCORE BIT(11) 759 #define FEN_ELDR BIT(12) 760 #define FEN_DIO_RF BIT(13) 761 #define FEN_HWPDN BIT(14) 762 #define FEN_MREGEN BIT(15) 763 764 #define PFM_LDALL BIT(0) 765 #define PFM_ALDN BIT(1) 766 #define PFM_LDKP BIT(2) 767 #define PFM_WOWL BIT(3) 768 #define ENPDN BIT(4) 769 #define PDN_PL BIT(5) 770 #define APFM_ONMAC BIT(8) 771 #define APFM_OFF BIT(9) 772 #define APFM_RSM BIT(10) 773 #define AFSM_HSUS BIT(11) 774 #define AFSM_PCIE BIT(12) 775 #define APDM_MAC BIT(13) 776 #define APDM_HOST BIT(14) 777 #define APDM_HPDN BIT(15) 778 #define RDY_MACON BIT(16) 779 #define SUS_HOST BIT(17) 780 #define ROP_ALD BIT(20) 781 #define ROP_PWR BIT(21) 782 #define ROP_SPS BIT(22) 783 #define SOP_MRST BIT(25) 784 #define SOP_FUSE BIT(26) 785 #define SOP_ABG BIT(27) 786 #define SOP_AMB BIT(28) 787 #define SOP_RCK BIT(29) 788 #define SOP_A8M BIT(30) 789 #define XOP_BTCK BIT(31) 790 791 #define ANAD16V_EN BIT(0) 792 #define ANA8M BIT(1) 793 #define MACSLP BIT(4) 794 #define LOADER_CLK_EN BIT(5) 795 #define _80M_SSC_DIS BIT(7) 796 #define _80M_SSC_EN_HO BIT(8) 797 #define PHY_SSC_RSTB BIT(9) 798 #define SEC_CLK_EN BIT(10) 799 #define MAC_CLK_EN BIT(11) 800 #define SYS_CLK_EN BIT(12) 801 #define RING_CLK_EN BIT(13) 802 803 #define BOOT_FROM_EEPROM BIT(4) 804 #define EEPROM_EN BIT(5) 805 806 #define AFE_BGEN BIT(0) 807 #define AFE_MBEN BIT(1) 808 #define MAC_ID_EN BIT(7) 809 810 #define WLOCK_ALL BIT(0) 811 #define WLOCK_00 BIT(1) 812 #define WLOCK_04 BIT(2) 813 #define WLOCK_08 BIT(3) 814 #define WLOCK_40 BIT(4) 815 #define R_DIS_PRST_0 BIT(5) 816 #define R_DIS_PRST_1 BIT(6) 817 #define LOCK_ALL_EN BIT(7) 818 819 #define RF_EN BIT(0) 820 #define RF_RSTB BIT(1) 821 #define RF_SDMRSTB BIT(2) 822 823 #define LDA15_EN BIT(0) 824 #define LDA15_STBY BIT(1) 825 #define LDA15_OBUF BIT(2) 826 #define LDA15_REG_VOS BIT(3) 827 #define _LDA15_VOADJ(x) (((x) & 0x7) << 4) 828 829 #define LDV12_EN BIT(0) 830 #define LDV12_SDBY BIT(1) 831 #define LPLDO_HSM BIT(2) 832 #define LPLDO_LSM_DIS BIT(3) 833 #define _LDV12_VADJ(x) (((x) & 0xF) << 4) 834 835 #define XTAL_EN BIT(0) 836 #define XTAL_BSEL BIT(1) 837 #define _XTAL_BOSC(x) (((x) & 0x3) << 2) 838 #define _XTAL_CADJ(x) (((x) & 0xF) << 4) 839 #define XTAL_GATE_USB BIT(8) 840 #define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) 841 #define XTAL_GATE_AFE BIT(11) 842 #define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) 843 #define XTAL_RF_GATE BIT(14) 844 #define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) 845 #define XTAL_GATE_DIG BIT(17) 846 #define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) 847 #define XTAL_BT_GATE BIT(20) 848 #define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) 849 #define _XTAL_GPIO(x) (((x) & 0x7) << 23) 850 851 #define CKDLY_AFE BIT(26) 852 #define CKDLY_USB BIT(27) 853 #define CKDLY_DIG BIT(28) 854 #define CKDLY_BT BIT(29) 855 856 #define APLL_EN BIT(0) 857 #define APLL_320_EN BIT(1) 858 #define APLL_FREF_SEL BIT(2) 859 #define APLL_EDGE_SEL BIT(3) 860 #define APLL_WDOGB BIT(4) 861 #define APLL_LPFEN BIT(5) 862 863 #define APLL_REF_CLK_13MHZ 0x1 864 #define APLL_REF_CLK_19_2MHZ 0x2 865 #define APLL_REF_CLK_20MHZ 0x3 866 #define APLL_REF_CLK_25MHZ 0x4 867 #define APLL_REF_CLK_26MHZ 0x5 868 #define APLL_REF_CLK_38_4MHZ 0x6 869 #define APLL_REF_CLK_40MHZ 0x7 870 871 #define APLL_320EN BIT(14) 872 #define APLL_80EN BIT(15) 873 #define APLL_1MEN BIT(24) 874 875 #define ALD_EN BIT(18) 876 #define EF_PD BIT(19) 877 #define EF_FLAG BIT(31) 878 879 #define EF_TRPT BIT(7) 880 #define LDOE25_EN BIT(31) 881 882 #define RSM_EN BIT(0) 883 #define TIMER_EN BIT(4) 884 885 #define TRSW0EN BIT(2) 886 #define TRSW1EN BIT(3) 887 #define EROM_EN BIT(4) 888 #define ENBT BIT(5) 889 #define ENUART BIT(8) 890 #define UART_910 BIT(9) 891 #define ENPMAC BIT(10) 892 #define SIC_SWRST BIT(11) 893 #define ENSIC BIT(12) 894 #define SIC_23 BIT(13) 895 #define ENHDP BIT(14) 896 #define SIC_LBK BIT(15) 897 898 #define LED0PL BIT(4) 899 #define LED1PL BIT(12) 900 #define LED0DIS BIT(7) 901 902 #define MCUFWDL_EN BIT(0) 903 #define MCUFWDL_RDY BIT(1) 904 #define FWDL_CHKSUM_RPT BIT(2) 905 #define MACINI_RDY BIT(3) 906 #define BBINI_RDY BIT(4) 907 #define RFINI_RDY BIT(5) 908 #define WINTINI_RDY BIT(6) 909 #define CPRST BIT(23) 910 911 #define XCLK_VLD BIT(0) 912 #define ACLK_VLD BIT(1) 913 #define UCLK_VLD BIT(2) 914 #define PCLK_VLD BIT(3) 915 #define PCIRSTB BIT(4) 916 #define V15_VLD BIT(5) 917 #define TRP_B15V_EN BIT(7) 918 #define SIC_IDLE BIT(8) 919 #define BD_MAC2 BIT(9) 920 #define BD_MAC1 BIT(10) 921 #define IC_MACPHY_MODE BIT(11) 922 #define VENDOR_ID BIT(19) 923 #define PAD_HWPD_IDN BIT(22) 924 #define TRP_VAUX_EN BIT(23) 925 #define TRP_BT_EN BIT(24) 926 #define BD_PKG_SEL BIT(25) 927 #define BD_HCI_SEL BIT(26) 928 #define TYPE_ID BIT(27) 929 930 #define CHIP_VER_RTL_MASK 0xF000 931 #define CHIP_VER_RTL_SHIFT 12 932 933 #define REG_LBMODE (REG_CR + 3) 934 935 #define HCI_TXDMA_EN BIT(0) 936 #define HCI_RXDMA_EN BIT(1) 937 #define TXDMA_EN BIT(2) 938 #define RXDMA_EN BIT(3) 939 #define PROTOCOL_EN BIT(4) 940 #define SCHEDULE_EN BIT(5) 941 #define MACTXEN BIT(6) 942 #define MACRXEN BIT(7) 943 #define ENSWBCN BIT(8) 944 #define ENSEC BIT(9) 945 946 #define _NETTYPE(x) (((x) & 0x3) << 16) 947 #define MASK_NETTYPE 0x30000 948 #define NT_NO_LINK 0x0 949 #define NT_LINK_AD_HOC 0x1 950 #define NT_LINK_AP 0x2 951 #define NT_AS_AP 0x3 952 953 #define _LBMODE(x) (((x) & 0xF) << 24) 954 #define MASK_LBMODE 0xF000000 955 #define LOOPBACK_NORMAL 0x0 956 #define LOOPBACK_IMMEDIATELY 0xB 957 #define LOOPBACK_MAC_DELAY 0x3 958 #define LOOPBACK_PHY 0x1 959 #define LOOPBACK_DMA 0x7 960 961 #define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 962 #define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 963 #define _PSRX_MASK 0xF 964 #define _PSTX_MASK 0xF0 965 #define _PSRX(x) (x) 966 #define _PSTX(x) ((x) << 4) 967 968 #define PBP_64 0x0 969 #define PBP_128 0x1 970 #define PBP_256 0x2 971 #define PBP_512 0x3 972 #define PBP_1024 0x4 973 974 #define RXDMA_ARBBW_EN BIT(0) 975 #define RXSHFT_EN BIT(1) 976 #define RXDMA_AGG_EN BIT(2) 977 #define QS_VO_QUEUE BIT(8) 978 #define QS_VI_QUEUE BIT(9) 979 #define QS_BE_QUEUE BIT(10) 980 #define QS_BK_QUEUE BIT(11) 981 #define QS_MANAGER_QUEUE BIT(12) 982 #define QS_HIGH_QUEUE BIT(13) 983 984 #define HQSEL_VOQ BIT(0) 985 #define HQSEL_VIQ BIT(1) 986 #define HQSEL_BEQ BIT(2) 987 #define HQSEL_BKQ BIT(3) 988 #define HQSEL_MGTQ BIT(4) 989 #define HQSEL_HIQ BIT(5) 990 991 #define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 992 #define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 993 #define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) 994 #define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) 995 #define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 996 #define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 997 998 #define QUEUE_LOW 1 999 #define QUEUE_NORMAL 2 1000 #define QUEUE_HIGH 3 1001 1002 #define _LLT_NO_ACTIVE 0x0 1003 #define _LLT_WRITE_ACCESS 0x1 1004 #define _LLT_READ_ACCESS 0x2 1005 1006 #define _LLT_INIT_DATA(x) ((x) & 0xFF) 1007 #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 1008 #define _LLT_OP(x) (((x) & 0x3) << 30) 1009 #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 1010 1011 #define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) 1012 #define BB_WRITE_EN BIT(30) 1013 #define BB_READ_EN BIT(31) 1014 1015 #define _HPQ(x) ((x) & 0xFF) 1016 #define _LPQ(x) (((x) & 0xFF) << 8) 1017 #define _PUBQ(x) (((x) & 0xFF) << 16) 1018 #define _NPQ(x) ((x) & 0xFF) 1019 1020 #define HPQ_PUBLIC_DIS BIT(24) 1021 #define LPQ_PUBLIC_DIS BIT(25) 1022 #define LD_RQPN BIT(31) 1023 1024 #define BCN_VALID BIT(16) 1025 #define BCN_HEAD(x) (((x) & 0xFF) << 8) 1026 #define BCN_HEAD_MASK 0xFF00 1027 1028 #define BLK_DESC_NUM_SHIFT 4 1029 #define BLK_DESC_NUM_MASK 0xF 1030 1031 #define DROP_DATA_EN BIT(9) 1032 1033 #define EN_AMPDU_RTY_NEW BIT(7) 1034 1035 #define _INIRTSMCS_SEL(x) ((x) & 0x3F) 1036 1037 #define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 1038 #define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 1039 1040 #define RATE_REG_BITMAP_ALL 0xFFFFF 1041 1042 #define _RRSC_BITMAP(x) ((x) & 0xFFFFF) 1043 1044 #define _RRSR_RSC(x) (((x) & 0x3) << 21) 1045 #define RRSR_RSC_RESERVED 0x0 1046 #define RRSR_RSC_UPPER_SUBCHANNEL 0x1 1047 #define RRSR_RSC_LOWER_SUBCHANNEL 0x2 1048 #define RRSR_RSC_DUPLICATE_MODE 0x3 1049 1050 #define USE_SHORT_G1 BIT(20) 1051 1052 #define _AGGLMT_MCS0(x) ((x) & 0xF) 1053 #define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) 1054 #define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) 1055 #define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) 1056 #define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) 1057 #define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) 1058 #define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) 1059 #define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) 1060 1061 #define RETRY_LIMIT_SHORT_SHIFT 8 1062 #define RETRY_LIMIT_LONG_SHIFT 0 1063 1064 #define _DARF_RC1(x) ((x) & 0x1F) 1065 #define _DARF_RC2(x) (((x) & 0x1F) << 8) 1066 #define _DARF_RC3(x) (((x) & 0x1F) << 16) 1067 #define _DARF_RC4(x) (((x) & 0x1F) << 24) 1068 #define _DARF_RC5(x) ((x) & 0x1F) 1069 #define _DARF_RC6(x) (((x) & 0x1F) << 8) 1070 #define _DARF_RC7(x) (((x) & 0x1F) << 16) 1071 #define _DARF_RC8(x) (((x) & 0x1F) << 24) 1072 1073 #define _RARF_RC1(x) ((x) & 0x1F) 1074 #define _RARF_RC2(x) (((x) & 0x1F) << 8) 1075 #define _RARF_RC3(x) (((x) & 0x1F) << 16) 1076 #define _RARF_RC4(x) (((x) & 0x1F) << 24) 1077 #define _RARF_RC5(x) ((x) & 0x1F) 1078 #define _RARF_RC6(x) (((x) & 0x1F) << 8) 1079 #define _RARF_RC7(x) (((x) & 0x1F) << 16) 1080 #define _RARF_RC8(x) (((x) & 0x1F) << 24) 1081 1082 #define AC_PARAM_TXOP_LIMIT_OFFSET 16 1083 #define AC_PARAM_ECW_MAX_OFFSET 12 1084 #define AC_PARAM_ECW_MIN_OFFSET 8 1085 #define AC_PARAM_AIFS_OFFSET 0 1086 1087 #define _AIFS(x) (x) 1088 #define _ECW_MAX_MIN(x) ((x) << 8) 1089 #define _TXOP_LIMIT(x) ((x) << 16) 1090 1091 #define _BCNIFS(x) ((x) & 0xFF) 1092 #define _BCNECW(x) ((((x) & 0xF)) << 8) 1093 1094 #define _LRL(x) ((x) & 0x3F) 1095 #define _SRL(x) (((x) & 0x3F) << 8) 1096 1097 #define _SIFS_CCK_CTX(x) ((x) & 0xFF) 1098 #define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8) 1099 1100 #define _SIFS_OFDM_CTX(x) ((x) & 0xFF) 1101 #define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8) 1102 1103 #define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) 1104 1105 #define DIS_EDCA_CNT_DWN BIT(11) 1106 1107 #define EN_MBSSID BIT(1) 1108 #define EN_TXBCN_RPT BIT(2) 1109 #define EN_BCN_FUNCTION BIT(3) 1110 1111 #define TSFTR_RST BIT(0) 1112 #define TSFTR1_RST BIT(1) 1113 1114 #define STOP_BCNQ BIT(6) 1115 1116 #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 1117 #define DIS_TSF_UDT0_TEST_CHIP BIT(5) 1118 1119 #define ACMHW_HWEN BIT(0) 1120 #define ACMHW_BEQEN BIT(1) 1121 #define ACMHW_VIQEN BIT(2) 1122 #define ACMHW_VOQEN BIT(3) 1123 #define ACMHW_BEQSTATUS BIT(4) 1124 #define ACMHW_VIQSTATUS BIT(5) 1125 #define ACMHW_VOQSTATUS BIT(6) 1126 1127 #define APSDOFF BIT(6) 1128 #define APSDOFF_STATUS BIT(7) 1129 1130 #define BW_20MHZ BIT(2) 1131 1132 #define RATE_BITMAP_ALL 0xFFFFF 1133 1134 #define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 1135 1136 #define TSFRST BIT(0) 1137 #define DIS_GCLK BIT(1) 1138 #define PAD_SEL BIT(2) 1139 #define PWR_ST BIT(6) 1140 #define PWRBIT_OW_EN BIT(7) 1141 #define ACRC BIT(8) 1142 #define CFENDFORM BIT(9) 1143 #define ICV BIT(10) 1144 1145 #define AAP BIT(0) 1146 #define APM BIT(1) 1147 #define AM BIT(2) 1148 #define AB BIT(3) 1149 #define ADD3 BIT(4) 1150 #define APWRMGT BIT(5) 1151 #define CBSSID BIT(6) 1152 #define CBSSID_DATA BIT(6) 1153 #define CBSSID_BCN BIT(7) 1154 #define ACRC32 BIT(8) 1155 #define AICV BIT(9) 1156 #define ADF BIT(11) 1157 #define ACF BIT(12) 1158 #define AMF BIT(13) 1159 #define HTC_LOC_CTRL BIT(14) 1160 #define UC_DATA_EN BIT(16) 1161 #define BM_DATA_EN BIT(17) 1162 #define MFBEN BIT(22) 1163 #define LSIGEN BIT(23) 1164 #define ENMBID BIT(24) 1165 #define APP_BASSN BIT(27) 1166 #define APP_PHYSTS BIT(28) 1167 #define APP_ICV BIT(29) 1168 #define APP_MIC BIT(30) 1169 #define APP_FCS BIT(31) 1170 1171 #define _MIN_SPACE(x) ((x) & 0x7) 1172 #define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) 1173 1174 #define RXERR_TYPE_OFDM_PPDU 0 1175 #define RXERR_TYPE_OFDM_FALSE_ALARM 1 1176 #define RXERR_TYPE_OFDM_MPDU_OK 2 1177 #define RXERR_TYPE_OFDM_MPDU_FAIL 3 1178 #define RXERR_TYPE_CCK_PPDU 4 1179 #define RXERR_TYPE_CCK_FALSE_ALARM 5 1180 #define RXERR_TYPE_CCK_MPDU_OK 6 1181 #define RXERR_TYPE_CCK_MPDU_FAIL 7 1182 #define RXERR_TYPE_HT_PPDU 8 1183 #define RXERR_TYPE_HT_FALSE_ALARM 9 1184 #define RXERR_TYPE_HT_MPDU_TOTAL 10 1185 #define RXERR_TYPE_HT_MPDU_OK 11 1186 #define RXERR_TYPE_HT_MPDU_FAIL 12 1187 #define RXERR_TYPE_RX_FULL_DROP 15 1188 1189 #define RXERR_COUNTER_MASK 0xFFFFF 1190 #define RXERR_RPT_RST BIT(27) 1191 #define _RXERR_RPT_SEL(type) ((type) << 28) 1192 1193 #define SCR_TXUSEDK BIT(0) 1194 #define SCR_RXUSEDK BIT(1) 1195 #define SCR_TXENCENABLE BIT(2) 1196 #define SCR_RXDECENABLE BIT(3) 1197 #define SCR_SKBYA2 BIT(4) 1198 #define SCR_NOSKMC BIT(5) 1199 #define SCR_TXBCUSEDK BIT(6) 1200 #define SCR_RXBCUSEDK BIT(7) 1201 1202 #define USB_IS_HIGH_SPEED 0 1203 #define USB_IS_FULL_SPEED 1 1204 #define USB_SPEED_MASK BIT(5) 1205 1206 #define USB_NORMAL_SIE_EP_MASK 0xF 1207 #define USB_NORMAL_SIE_EP_SHIFT 4 1208 1209 #define USB_TEST_EP_MASK 0x30 1210 #define USB_TEST_EP_SHIFT 4 1211 1212 #define USB_AGG_EN BIT(3) 1213 1214 #define MAC_ADDR_LEN 6 1215 #define LAST_ENTRY_OF_TX_PKT_BUFFER 175 1216 1217 #define POLLING_LLT_THRESHOLD 20 1218 #define POLLING_READY_TIMEOUT_COUNT 3000 1219 1220 #define MAX_MSS_DENSITY_2T 0x13 1221 #define MAX_MSS_DENSITY_1T 0x0A 1222 1223 #define EPROM_CMD_OPERATING_MODE_MASK ((1 << 7) | (1 << 6)) 1224 #define EPROM_CMD_CONFIG 0x3 1225 #define EPROM_CMD_LOAD 1 1226 1227 #define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE 1228 1229 #define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1230 1231 #define RPMAC_RESET 0x100 1232 #define RPMAC_TXSTART 0x104 1233 #define RPMAC_TXLEGACYSIG 0x108 1234 #define RPMAC_TXHTSIG1 0x10c 1235 #define RPMAC_TXHTSIG2 0x110 1236 #define RPMAC_PHYDEBUG 0x114 1237 #define RPMAC_TXPACKETNUM 0x118 1238 #define RPMAC_TXIDLE 0x11c 1239 #define RPMAC_TXMACHEADER0 0x120 1240 #define RPMAC_TXMACHEADER1 0x124 1241 #define RPMAC_TXMACHEADER2 0x128 1242 #define RPMAC_TXMACHEADER3 0x12c 1243 #define RPMAC_TXMACHEADER4 0x130 1244 #define RPMAC_TXMACHEADER5 0x134 1245 #define RPMAC_TXDADATYPE 0x138 1246 #define RPMAC_TXRANDOMSEED 0x13c 1247 #define RPMAC_CCKPLCPPREAMBLE 0x140 1248 #define RPMAC_CCKPLCPHEADER 0x144 1249 #define RPMAC_CCKCRC16 0x148 1250 #define RPMAC_OFDMRXCRC32OK 0x170 1251 #define RPMAC_OFDMRXCRC32ER 0x174 1252 #define RPMAC_OFDMRXPARITYER 0x178 1253 #define RPMAC_OFDMRXCRC8ER 0x17c 1254 #define RPMAC_CCKCRXRC16ER 0x180 1255 #define RPMAC_CCKCRXRC32ER 0x184 1256 #define RPMAC_CCKCRXRC32OK 0x188 1257 #define RPMAC_TXSTATUS 0x18c 1258 1259 #define RFPGA0_RFMOD 0x800 1260 1261 #define RFPGA0_TXINFO 0x804 1262 #define RFPGA0_PSDFUNCTION 0x808 1263 1264 #define RFPGA0_TXGAINSTAGE 0x80c 1265 1266 #define RFPGA0_RFTIMING1 0x810 1267 #define RFPGA0_RFTIMING2 0x814 1268 1269 #define RFPGA0_XA_HSSIPARAMETER1 0x820 1270 #define RFPGA0_XA_HSSIPARAMETER2 0x824 1271 #define RFPGA0_XB_HSSIPARAMETER1 0x828 1272 #define RFPGA0_XB_HSSIPARAMETER2 0x82c 1273 1274 #define RFPGA0_XA_LSSIPARAMETER 0x840 1275 #define RFPGA0_XB_LSSIPARAMETER 0x844 1276 1277 #define RFPGA0_RFWAKEUPPARAMETER 0x850 1278 #define RFPGA0_RFSLEEPUPPARAMETER 0x854 1279 1280 #define RFPGA0_XAB_SWITCHCONTROL 0x858 1281 #define RFPGA0_XCD_SWITCHCONTROL 0x85c 1282 1283 #define RFPGA0_XA_RFINTERFACEOE 0x860 1284 #define RFPGA0_XB_RFINTERFACEOE 0x864 1285 1286 #define RFPGA0_XAB_RFINTERFACESW 0x870 1287 #define RFPGA0_XCD_RFINTERFACESW 0x874 1288 1289 #define RFPGA0_XAB_RFPARAMETER 0x878 1290 #define RFPGA0_XCD_RFPARAMETER 0x87c 1291 1292 #define RFPGA0_ANALOGPARAMETER1 0x880 1293 #define RFPGA0_ANALOGPARAMETER2 0x884 1294 #define RFPGA0_ANALOGPARAMETER3 0x888 1295 #define RFPGA0_ANALOGPARAMETER4 0x88c 1296 1297 #define RFPGA0_XA_LSSIREADBACK 0x8a0 1298 #define RFPGA0_XB_LSSIREADBACK 0x8a4 1299 #define RFPGA0_XC_LSSIREADBACK 0x8a8 1300 #define RFPGA0_XD_LSSIREADBACK 0x8ac 1301 1302 #define RFPGA0_PSDREPORT 0x8b4 1303 #define TRANSCEIVEA_HSPI_READBACK 0x8b8 1304 #define TRANSCEIVEB_HSPI_READBACK 0x8bc 1305 #define REG_SC_CNT 0x8c4 1306 #define RFPGA0_XAB_RFINTERFACERB 0x8e0 1307 #define RFPGA0_XCD_RFINTERFACERB 0x8e4 1308 1309 #define RFPGA1_RFMOD 0x900 1310 1311 #define RFPGA1_TXBLOCK 0x904 1312 #define RFPGA1_DEBUGSELECT 0x908 1313 #define RFPGA1_TXINFO 0x90c 1314 1315 #define RCCK0_SYSTEM 0xa00 1316 1317 #define RCCK0_AFESETTING 0xa04 1318 #define RCCK0_CCA 0xa08 1319 1320 #define RCCK0_RXAGC1 0xa0c 1321 #define RCCK0_RXAGC2 0xa10 1322 1323 #define RCCK0_RXHP 0xa14 1324 1325 #define RCCK0_DSPPARAMETER1 0xa18 1326 #define RCCK0_DSPPARAMETER2 0xa1c 1327 1328 #define RCCK0_TXFILTER1 0xa20 1329 #define RCCK0_TXFILTER2 0xa24 1330 #define RCCK0_DEBUGPORT 0xa28 1331 #define RCCK0_FALSEALARMREPORT 0xa2c 1332 #define RCCK0_TRSSIREPORT 0xa50 1333 #define RCCK0_RXREPORT 0xa54 1334 #define RCCK0_FACOUNTERLOWER 0xa5c 1335 #define RCCK0_FACOUNTERUPPER 0xa58 1336 #define RCCK0_CCA_CNT 0xa60 1337 1338 /* PageB(0xB00) */ 1339 #define RPDP_ANTA 0xb00 1340 #define RPDP_ANTA_4 0xb04 1341 #define RPDP_ANTA_8 0xb08 1342 #define RPDP_ANTA_C 0xb0c 1343 #define RPDP_ANTA_10 0xb10 1344 #define RPDP_ANTA_14 0xb14 1345 #define RPDP_ANTA_18 0xb18 1346 #define RPDP_ANTA_1C 0xb1c 1347 #define RPDP_ANTA_20 0xb20 1348 #define RPDP_ANTA_24 0xb24 1349 1350 #define RCONFIG_PMPD_ANTA 0xb28 1351 #define RCONFIG_RAM64x16 0xb2c 1352 1353 #define RBNDA 0xb30 1354 #define RHSSIPAR 0xb34 1355 1356 #define RCONFIG_ANTA 0xb68 1357 #define RCONFIG_ANTB 0xb6c 1358 1359 #define RPDP_ANTB 0xb70 1360 #define RPDP_ANTB_4 0xb74 1361 #define RPDP_ANTB_8 0xb78 1362 #define RPDP_ANTB_C 0xb7c 1363 #define RPDP_ANTB_10 0xb80 1364 #define RPDP_ANTB_14 0xb84 1365 #define RPDP_ANTB_18 0xb88 1366 #define RPDP_ANTB_1C 0xb8c 1367 #define RPDP_ANTB_20 0xb90 1368 #define RPDP_ANTB_24 0xb94 1369 1370 #define RCONFIG_PMPD_ANTB 0xb98 1371 1372 #define RBNDB 0xba0 1373 1374 #define RAPK 0xbd8 1375 #define RPM_RX0_ANTA 0xbdc 1376 #define RPM_RX1_ANTA 0xbe0 1377 #define RPM_RX2_ANTA 0xbe4 1378 #define RPM_RX3_ANTA 0xbe8 1379 #define RPM_RX0_ANTB 0xbec 1380 #define RPM_RX1_ANTB 0xbf0 1381 #define RPM_RX2_ANTB 0xbf4 1382 #define RPM_RX3_ANTB 0xbf8 1383 1384 /*Page C*/ 1385 #define ROFDM0_LSTF 0xc00 1386 1387 #define ROFDM0_TRXPATHENABLE 0xc04 1388 #define ROFDM0_TRMUXPAR 0xc08 1389 #define ROFDM0_TRSWISOLATION 0xc0c 1390 1391 #define ROFDM0_XARXAFE 0xc10 1392 #define ROFDM0_XARXIQIMBALANCE 0xc14 1393 #define ROFDM0_XBRXAFE 0xc18 1394 #define ROFDM0_XBRXIQIMBALANCE 0xc1c 1395 #define ROFDM0_XCRXAFE 0xc20 1396 #define ROFDM0_XCRXIQIMBANLANCE 0xc24 1397 #define ROFDM0_XDRXAFE 0xc28 1398 #define ROFDM0_XDRXIQIMBALANCE 0xc2c 1399 1400 #define ROFDM0_RXDETECTOR1 0xc30 1401 #define ROFDM0_RXDETECTOR2 0xc34 1402 #define ROFDM0_RXDETECTOR3 0xc38 1403 #define ROFDM0_RXDETECTOR4 0xc3c 1404 1405 #define ROFDM0_RXDSP 0xc40 1406 #define ROFDM0_CFOANDDAGC 0xc44 1407 #define ROFDM0_CCADROPTHRESHOLD 0xc48 1408 #define ROFDM0_ECCATHRESHOLD 0xc4c 1409 1410 #define ROFDM0_XAAGCCORE1 0xc50 1411 #define ROFDM0_XAAGCCORE2 0xc54 1412 #define ROFDM0_XBAGCCORE1 0xc58 1413 #define ROFDM0_XBAGCCORE2 0xc5c 1414 #define ROFDM0_XCAGCCORE1 0xc60 1415 #define ROFDM0_XCAGCCORE2 0xc64 1416 #define ROFDM0_XDAGCCORE1 0xc68 1417 #define ROFDM0_XDAGCCORE2 0xc6c 1418 1419 #define ROFDM0_AGCPARAMETER1 0xc70 1420 #define ROFDM0_AGCPARAMETER2 0xc74 1421 #define ROFDM0_AGCRSSITABLE 0xc78 1422 #define ROFDM0_HTSTFAGC 0xc7c 1423 1424 #define ROFDM0_XATXIQIMBALANCE 0xc80 1425 #define ROFDM0_XATXAFE 0xc84 1426 #define ROFDM0_XBTXIQIMBALANCE 0xc88 1427 #define ROFDM0_XBTXAFE 0xc8c 1428 #define ROFDM0_XCTXIQIMBALANCE 0xc90 1429 #define ROFDM0_XCTXAFE 0xc94 1430 #define ROFDM0_XDTXIQIMBALANCE 0xc98 1431 #define ROFDM0_XDTXAFE 0xc9c 1432 1433 #define ROFDM0_RXIQEXTANTA 0xca0 1434 #define ROFDM0_TXCOEFF1 0xca4 1435 #define ROFDM0_TXCOEFF2 0xca8 1436 #define ROFDM0_TXCOEFF3 0xcac 1437 #define ROFDM0_TXCOEFF4 0xcb0 1438 #define ROFDM0_TXCOEFF5 0xcb4 1439 #define ROFDM0_TXCOEFF6 0xcb8 1440 1441 #define ROFDM0_RXHPPARAMETER 0xce0 1442 #define ROFDM0_TXPSEUDONOISEWGT 0xce4 1443 #define ROFDM0_FRAMESYNC 0xcf0 1444 #define ROFDM0_DFSREPORT 0xcf4 1445 1446 #define ROFDM1_LSTF 0xd00 1447 #define ROFDM1_TRXPATHENABLE 0xd04 1448 1449 #define ROFDM1_CF0 0xd08 1450 #define ROFDM1_CSI1 0xd10 1451 #define ROFDM1_SBD 0xd14 1452 #define ROFDM1_CSI2 0xd18 1453 #define ROFDM1_CFOTRACKING 0xd2c 1454 #define ROFDM1_TRXMESAURE1 0xd34 1455 #define ROFDM1_INTFDET 0xd3c 1456 #define ROFDM1_PSEUDONOISESTATEAB 0xd50 1457 #define ROFDM1_PSEUDONOISESTATECD 0xd54 1458 #define ROFDM1_RXPSEUDONOISEWGT 0xd58 1459 1460 #define ROFDM_PHYCOUNTER1 0xda0 1461 #define ROFDM_PHYCOUNTER2 0xda4 1462 #define ROFDM_PHYCOUNTER3 0xda8 1463 1464 #define ROFDM_SHORTCFOAB 0xdac 1465 #define ROFDM_SHORTCFOCD 0xdb0 1466 #define ROFDM_LONGCFOAB 0xdb4 1467 #define ROFDM_LONGCFOCD 0xdb8 1468 #define ROFDM_TAILCF0AB 0xdbc 1469 #define ROFDM_TAILCF0CD 0xdc0 1470 #define ROFDM_PWMEASURE1 0xdc4 1471 #define ROFDM_PWMEASURE2 0xdc8 1472 #define ROFDM_BWREPORT 0xdcc 1473 #define ROFDM_AGCREPORT 0xdd0 1474 #define ROFDM_RXSNR 0xdd4 1475 #define ROFDM_RXEVMCSI 0xdd8 1476 #define ROFDM_SIGREPORT 0xddc 1477 1478 #define RTXAGC_A_RATE18_06 0xe00 1479 #define RTXAGC_A_RATE54_24 0xe04 1480 #define RTXAGC_A_CCK1_MCS32 0xe08 1481 #define RTXAGC_A_MCS03_MCS00 0xe10 1482 #define RTXAGC_A_MCS07_MCS04 0xe14 1483 #define RTXAGC_A_MCS11_MCS08 0xe18 1484 #define RTXAGC_A_MCS15_MCS12 0xe1c 1485 1486 #define RTXAGC_B_RATE18_06 0x830 1487 #define RTXAGC_B_RATE54_24 0x834 1488 #define RTXAGC_B_CCK1_55_MCS32 0x838 1489 #define RTXAGC_B_MCS03_MCS00 0x83c 1490 #define RTXAGC_B_MCS07_MCS04 0x848 1491 #define RTXAGC_B_MCS11_MCS08 0x84c 1492 #define RTXAGC_B_MCS15_MCS12 0x868 1493 #define RTXAGC_B_CCK11_A_CCK2_11 0x86c 1494 1495 #define RFPGA0_IQK 0xe28 1496 #define RTX_IQK_TONE_A 0xe30 1497 #define RRX_IQK_TONE_A 0xe34 1498 #define RTX_IQK_PI_A 0xe38 1499 #define RRX_IQK_PI_A 0xe3c 1500 1501 #define RTX_IQK 0xe40 1502 #define RRX_IQK 0xe44 1503 #define RIQK_AGC_PTS 0xe48 1504 #define RIQK_AGC_RSP 0xe4c 1505 #define RTX_IQK_TONE_B 0xe50 1506 #define RRX_IQK_TONE_B 0xe54 1507 #define RTX_IQK_PI_B 0xe58 1508 #define RRX_IQK_PI_B 0xe5c 1509 #define RIQK_AGC_CONT 0xe60 1510 1511 #define RBLUE_TOOTH 0xe6c 1512 #define RRX_WAIT_CCA 0xe70 1513 #define RTX_CCK_RFON 0xe74 1514 #define RTX_CCK_BBON 0xe78 1515 #define RTX_OFDM_RFON 0xe7c 1516 #define RTX_OFDM_BBON 0xe80 1517 #define RTX_TO_RX 0xe84 1518 #define RTX_TO_TX 0xe88 1519 #define RRX_CCK 0xe8c 1520 1521 #define RTX_POWER_BEFORE_IQK_A 0xe94 1522 #define RTX_POWER_AFTER_IQK_A 0xe9c 1523 1524 #define RRX_POWER_BEFORE_IQK_A 0xea0 1525 #define RRX_POWER_BEFORE_IQK_A_2 0xea4 1526 #define RRX_POWER_AFTER_IQK_A 0xea8 1527 #define RRX_POWER_AFTER_IQK_A_2 0xeac 1528 1529 #define RTX_POWER_BEFORE_IQK_B 0xeb4 1530 #define RTX_POWER_AFTER_IQK_B 0xebc 1531 1532 #define RRX_POWER_BEFORE_IQK_B 0xec0 1533 #define RRX_POWER_BEFORE_IQK_B_2 0xec4 1534 #define RRX_POWER_AFTER_IQK_B 0xec8 1535 #define RRX_POWER_AFTER_IQK_B_2 0xecc 1536 1537 #define RRX_OFDM 0xed0 1538 #define RRX_WAIT_RIFS 0xed4 1539 #define RRX_TO_RX 0xed8 1540 #define RSTANDBY 0xedc 1541 #define RSLEEP 0xee0 1542 #define RPMPD_ANAEN 0xeec 1543 1544 #define RZEBRA1_HSSIENABLE 0x0 1545 #define RZEBRA1_TRXENABLE1 0x1 1546 #define RZEBRA1_TRXENABLE2 0x2 1547 #define RZEBRA1_AGC 0x4 1548 #define RZEBRA1_CHARGEPUMP 0x5 1549 #define RZEBRA1_CHANNEL 0x7 1550 1551 #define RZEBRA1_TXGAIN 0x8 1552 #define RZEBRA1_TXLPF 0x9 1553 #define RZEBRA1_RXLPF 0xb 1554 #define RZEBRA1_RXHPFCORNER 0xc 1555 1556 #define RGLOBALCTRL 0 1557 #define RRTL8256_TXLPF 19 1558 #define RRTL8256_RXLPF 11 1559 #define RRTL8258_TXLPF 0x11 1560 #define RRTL8258_RXLPF 0x13 1561 #define RRTL8258_RSSILPF 0xa 1562 1563 #define RF_AC 0x00 1564 1565 #define RF_IQADJ_G1 0x01 1566 #define RF_IQADJ_G2 0x02 1567 #define RF_POW_TRSW 0x05 1568 1569 #define RF_GAIN_RX 0x06 1570 #define RF_GAIN_TX 0x07 1571 1572 #define RF_TXM_IDAC 0x08 1573 #define RF_BS_IQGEN 0x0F 1574 1575 #define RF_MODE1 0x10 1576 #define RF_MODE2 0x11 1577 1578 #define RF_RX_AGC_HP 0x12 1579 #define RF_TX_AGC 0x13 1580 #define RF_BIAS 0x14 1581 #define RF_IPA 0x15 1582 #define RF_POW_ABILITY 0x17 1583 #define RF_MODE_AG 0x18 1584 #define RRFCHANNEL 0x18 1585 #define RF_CHNLBW 0x18 1586 #define RF_TOP 0x19 1587 1588 #define RF_RX_G1 0x1A 1589 #define RF_RX_G2 0x1B 1590 1591 #define RF_RX_BB2 0x1C 1592 #define RF_RX_BB1 0x1D 1593 1594 #define RF_RCK1 0x1E 1595 #define RF_RCK2 0x1F 1596 1597 #define RF_TX_G1 0x20 1598 #define RF_TX_G2 0x21 1599 #define RF_TX_G3 0x22 1600 1601 #define RF_TX_BB1 0x23 1602 #define RF_T_METER 0x42 1603 1604 #define RF_SYN_G1 0x25 1605 #define RF_SYN_G2 0x26 1606 #define RF_SYN_G3 0x27 1607 #define RF_SYN_G4 0x28 1608 #define RF_SYN_G5 0x29 1609 #define RF_SYN_G6 0x2A 1610 #define RF_SYN_G7 0x2B 1611 #define RF_SYN_G8 0x2C 1612 1613 #define RF_RCK_OS 0x30 1614 #define RF_TXPA_G1 0x31 1615 #define RF_TXPA_G2 0x32 1616 #define RF_TXPA_G3 0x33 1617 1618 #define RF_TX_BIAS_A 0x35 1619 #define RF_TX_BIAS_D 0x36 1620 #define RF_LOBF_9 0x38 1621 #define RF_RXRF_A3 0x3C 1622 #define RF_TRSW 0x3F 1623 1624 #define RF_TXRF_A2 0x41 1625 #define RF_TXPA_G4 0x46 1626 #define RF_TXPA_A4 0x4B 1627 1628 #define RF_WE_LUT 0xEF 1629 1630 #define BBBRESETB 0x100 1631 #define BGLOBALRESETB 0x200 1632 #define BOFDMTXSTART 0x4 1633 #define BCCKTXSTART 0x8 1634 #define BCRC32DEBUG 0x100 1635 #define BPMACLOOPBACK 0x10 1636 #define BTXLSIG 0xffffff 1637 #define BOFDMTXRATE 0xf 1638 #define BOFDMTXRESERVED 0x10 1639 #define BOFDMTXLENGTH 0x1ffe0 1640 #define BOFDMTXPARITY 0x20000 1641 #define BTXHTSIG1 0xffffff 1642 #define BTXHTMCSRATE 0x7f 1643 #define BTXHTBW 0x80 1644 #define BTXHTLENGTH 0xffff00 1645 #define BTXHTSIG2 0xffffff 1646 #define BTXHTSMOOTHING 0x1 1647 #define BTXHTSOUNDING 0x2 1648 #define BTXHTRESERVED 0x4 1649 #define BTXHTAGGREATION 0x8 1650 #define BTXHTSTBC 0x30 1651 #define BTXHTADVANCECODING 0x40 1652 #define BTXHTSHORTGI 0x80 1653 #define BTXHTNUMBERHT_LTF 0x300 1654 #define BTXHTCRC8 0x3fc00 1655 #define BCOUNTERRESET 0x10000 1656 #define BNUMOFOFDMTX 0xffff 1657 #define BNUMOFCCKTX 0xffff0000 1658 #define BTXIDLEINTERVAL 0xffff 1659 #define BOFDMSERVICE 0xffff0000 1660 #define BTXMACHEADER 0xffffffff 1661 #define BTXDATAINIT 0xff 1662 #define BTXHTMODE 0x100 1663 #define BTXDATATYPE 0x30000 1664 #define BTXRANDOMSEED 0xffffffff 1665 #define BCCKTXPREAMBLE 0x1 1666 #define BCCKTXSFD 0xffff0000 1667 #define BCCKTXSIG 0xff 1668 #define BCCKTXSERVICE 0xff00 1669 #define BCCKLENGTHEXT 0x8000 1670 #define BCCKTXLENGHT 0xffff0000 1671 #define BCCKTXCRC16 0xffff 1672 #define BCCKTXSTATUS 0x1 1673 #define BOFDMTXSTATUS 0x2 1674 #define IS_BB_REG_OFFSET_92S(_offset) \ 1675 ((_offset >= 0x800) && (_offset <= 0xfff)) 1676 1677 #define BRFMOD 0x1 1678 #define BJAPANMODE 0x2 1679 #define BCCKTXSC 0x30 1680 #define BCCKEN 0x1000000 1681 #define BOFDMEN 0x2000000 1682 1683 #define BOFDMRXADCPHASE 0x10000 1684 #define BOFDMTXDACPHASE 0x40000 1685 #define BXATXAGC 0x3f 1686 1687 #define BXBTXAGC 0xf00 1688 #define BXCTXAGC 0xf000 1689 #define BXDTXAGC 0xf0000 1690 1691 #define BPASTART 0xf0000000 1692 #define BTRSTART 0x00f00000 1693 #define BRFSTART 0x0000f000 1694 #define BBBSTART 0x000000f0 1695 #define BBBCCKSTART 0x0000000f 1696 #define BPAEND 0xf 1697 #define BTREND 0x0f000000 1698 #define BRFEND 0x000f0000 1699 #define BCCAMASK 0x000000f0 1700 #define BR2RCCAMASK 0x00000f00 1701 #define BHSSI_R2TDELAY 0xf8000000 1702 #define BHSSI_T2RDELAY 0xf80000 1703 #define BCONTXHSSI 0x400 1704 #define BIGFROMCCK 0x200 1705 #define BAGCADDRESS 0x3f 1706 #define BRXHPTX 0x7000 1707 #define BRXHP2RX 0x38000 1708 #define BRXHPCCKINI 0xc0000 1709 #define BAGCTXCODE 0xc00000 1710 #define BAGCRXCODE 0x300000 1711 1712 #define B3WIREDATALENGTH 0x800 1713 #define B3WIREADDREAALENGTH 0x400 1714 1715 #define B3WIRERFPOWERDOWN 0x1 1716 #define B5GPAPEPOLARITY 0x40000000 1717 #define B2GPAPEPOLARITY 0x80000000 1718 #define BRFSW_TXDEFAULTANT 0x3 1719 #define BRFSW_TXOPTIONANT 0x30 1720 #define BRFSW_RXDEFAULTANT 0x300 1721 #define BRFSW_RXOPTIONANT 0x3000 1722 #define BRFSI_3WIREDATA 0x1 1723 #define BRFSI_3WIRECLOCK 0x2 1724 #define BRFSI_3WIRELOAD 0x4 1725 #define BRFSI_3WIRERW 0x8 1726 #define BRFSI_3WIRE 0xf 1727 1728 #define BRFSI_RFENV 0x10 1729 1730 #define BRFSI_TRSW 0x20 1731 #define BRFSI_TRSWB 0x40 1732 #define BRFSI_ANTSW 0x100 1733 #define BRFSI_ANTSWB 0x200 1734 #define BRFSI_PAPE 0x400 1735 #define BRFSI_PAPE5G 0x800 1736 #define BBANDSELECT 0x1 1737 #define BHTSIG2_GI 0x80 1738 #define BHTSIG2_SMOOTHING 0x01 1739 #define BHTSIG2_SOUNDING 0x02 1740 #define BHTSIG2_AGGREATON 0x08 1741 #define BHTSIG2_STBC 0x30 1742 #define BHTSIG2_ADVCODING 0x40 1743 #define BHTSIG2_NUMOFHTLTF 0x300 1744 #define BHTSIG2_CRC8 0x3fc 1745 #define BHTSIG1_MCS 0x7f 1746 #define BHTSIG1_BANDWIDTH 0x80 1747 #define BHTSIG1_HTLENGTH 0xffff 1748 #define BLSIG_RATE 0xf 1749 #define BLSIG_RESERVED 0x10 1750 #define BLSIG_LENGTH 0x1fffe 1751 #define BLSIG_PARITY 0x20 1752 #define BCCKRXPHASE 0x4 1753 1754 #define BLSSIREADADDRESS 0x7f800000 1755 #define BLSSIREADEDGE 0x80000000 1756 1757 #define BLSSIREADBACKDATA 0xfffff 1758 1759 #define BLSSIREADOKFLAG 0x1000 1760 #define BCCKSAMPLERATE 0x8 1761 #define BREGULATOR0STANDBY 0x1 1762 #define BREGULATORPLLSTANDBY 0x2 1763 #define BREGULATOR1STANDBY 0x4 1764 #define BPLLPOWERUP 0x8 1765 #define BDPLLPOWERUP 0x10 1766 #define BDA10POWERUP 0x20 1767 #define BAD7POWERUP 0x200 1768 #define BDA6POWERUP 0x2000 1769 #define BXTALPOWERUP 0x4000 1770 #define B40MDCLKPOWERUP 0x8000 1771 #define BDA6DEBUGMODE 0x20000 1772 #define BDA6SWING 0x380000 1773 1774 #define BADCLKPHASE 0x4000000 1775 #define B80MCLKDELAY 0x18000000 1776 #define BAFEWATCHDOGENABLE 0x20000000 1777 1778 #define BXTALCAP01 0xc0000000 1779 #define BXTALCAP23 0x3 1780 #define BXTALCAP92X 0x0f000000 1781 #define BXTALCAP 0x0f000000 1782 1783 #define BINTDIFCLKENABLE 0x400 1784 #define BEXTSIGCLKENABLE 0x800 1785 #define BBANDGAP_MBIAS_POWERUP 0x10000 1786 #define BAD11SH_GAIN 0xc0000 1787 #define BAD11NPUT_RANGE 0x700000 1788 #define BAD110P_CURRENT 0x3800000 1789 #define BLPATH_LOOPBACK 0x4000000 1790 #define BQPATH_LOOPBACK 0x8000000 1791 #define BAFE_LOOPBACK 0x10000000 1792 #define BDA10_SWING 0x7e0 1793 #define BDA10_REVERSE 0x800 1794 #define BDA_CLK_SOURCE 0x1000 1795 #define BDA7INPUT_RANGE 0x6000 1796 #define BDA7_GAIN 0x38000 1797 #define BDA7OUTPUT_CM_MODE 0x40000 1798 #define BDA7INPUT_CM_MODE 0x380000 1799 #define BDA7CURRENT 0xc00000 1800 #define BREGULATOR_ADJUST 0x7000000 1801 #define BAD11POWERUP_ATTX 0x1 1802 #define BDA10PS_ATTX 0x10 1803 #define BAD11POWERUP_ATRX 0x100 1804 #define BDA10PS_ATRX 0x1000 1805 #define BCCKRX_AGC_FORMAT 0x200 1806 #define BPSDFFT_SAMPLE_POINT 0xc000 1807 #define BPSD_AVERAGE_NUM 0x3000 1808 #define BIQPATH_CONTROL 0xc00 1809 #define BPSD_FREQ 0x3ff 1810 #define BPSD_ANTENNA_PATH 0x30 1811 #define BPSD_IQ_SWITCH 0x40 1812 #define BPSD_RX_TRIGGER 0x400000 1813 #define BPSD_TX_TRIGGER 0x80000000 1814 #define BPSD_SINE_TONE_SCALE 0x7f000000 1815 #define BPSD_REPORT 0xffff 1816 1817 #define BOFDM_TXSC 0x30000000 1818 #define BCCK_TXON 0x1 1819 #define BOFDM_TXON 0x2 1820 #define BDEBUG_PAGE 0xfff 1821 #define BDEBUG_ITEM 0xff 1822 #define BANTL 0x10 1823 #define BANT_NONHT 0x100 1824 #define BANT_HT1 0x1000 1825 #define BANT_HT2 0x10000 1826 #define BANT_HT1S1 0x100000 1827 #define BANT_NONHTS1 0x1000000 1828 1829 #define BCCK_BBMODE 0x3 1830 #define BCCK_TXPOWERSAVING 0x80 1831 #define BCCK_RXPOWERSAVING 0x40 1832 1833 #define BCCK_SIDEBAND 0x10 1834 1835 #define BCCK_SCRAMBLE 0x8 1836 #define BCCK_ANTDIVERSITY 0x8000 1837 #define BCCK_CARRIER_RECOVERY 0x4000 1838 #define BCCK_TXRATE 0x3000 1839 #define BCCK_DCCANCEL 0x0800 1840 #define BCCK_ISICANCEL 0x0400 1841 #define BCCK_MATCH_FILTER 0x0200 1842 #define BCCK_EQUALIZER 0x0100 1843 #define BCCK_PREAMBLE_DETECT 0x800000 1844 #define BCCK_FAST_FALSECCA 0x400000 1845 #define BCCK_CH_ESTSTART 0x300000 1846 #define BCCK_CCA_COUNT 0x080000 1847 #define BCCK_CS_LIM 0x070000 1848 #define BCCK_BIST_MODE 0x80000000 1849 #define BCCK_CCAMASK 0x40000000 1850 #define BCCK_TX_DAC_PHASE 0x4 1851 #define BCCK_RX_ADC_PHASE 0x20000000 1852 #define BCCKR_CP_MODE 0x0100 1853 #define BCCK_TXDC_OFFSET 0xf0 1854 #define BCCK_RXDC_OFFSET 0xf 1855 #define BCCK_CCA_MODE 0xc000 1856 #define BCCK_FALSECS_LIM 0x3f00 1857 #define BCCK_CS_RATIO 0xc00000 1858 #define BCCK_CORGBIT_SEL 0x300000 1859 #define BCCK_PD_LIM 0x0f0000 1860 #define BCCK_NEWCCA 0x80000000 1861 #define BCCK_RXHP_OF_IG 0x8000 1862 #define BCCK_RXIG 0x7f00 1863 #define BCCK_LNA_POLARITY 0x800000 1864 #define BCCK_RX1ST_BAIN 0x7f0000 1865 #define BCCK_RF_EXTEND 0x20000000 1866 #define BCCK_RXAGC_SATLEVEL 0x1f000000 1867 #define BCCK_RXAGC_SATCOUNT 0xe0 1868 #define BCCKRXRFSETTLE 0x1f 1869 #define BCCK_FIXED_RXAGC 0x8000 1870 #define BCCK_ANTENNA_POLARITY 0x2000 1871 #define BCCK_TXFILTER_TYPE 0x0c00 1872 #define BCCK_RXAGC_REPORTTYPE 0x0300 1873 #define BCCK_RXDAGC_EN 0x80000000 1874 #define BCCK_RXDAGC_PERIOD 0x20000000 1875 #define BCCK_RXDAGC_SATLEVEL 0x1f000000 1876 #define BCCK_TIMING_RECOVERY 0x800000 1877 #define BCCK_TXC0 0x3f0000 1878 #define BCCK_TXC1 0x3f000000 1879 #define BCCK_TXC2 0x3f 1880 #define BCCK_TXC3 0x3f00 1881 #define BCCK_TXC4 0x3f0000 1882 #define BCCK_TXC5 0x3f000000 1883 #define BCCK_TXC6 0x3f 1884 #define BCCK_TXC7 0x3f00 1885 #define BCCK_DEBUGPORT 0xff0000 1886 #define BCCK_DAC_DEBUG 0x0f000000 1887 #define BCCK_FALSEALARM_ENABLE 0x8000 1888 #define BCCK_FALSEALARM_READ 0x4000 1889 #define BCCK_TRSSI 0x7f 1890 #define BCCK_RXAGC_REPORT 0xfe 1891 #define BCCK_RXREPORT_ANTSEL 0x80000000 1892 #define BCCK_RXREPORT_MFOFF 0x40000000 1893 #define BCCK_RXREPORT_SQLOSS 0x20000000 1894 #define BCCK_RXREPORT_PKTLOSS 0x10000000 1895 #define BCCK_RXREPORT_LOCKEDBIT 0x08000000 1896 #define BCCK_RXREPORT_RATEERROR 0x04000000 1897 #define BCCK_RXREPORT_RXRATE 0x03000000 1898 #define BCCK_RXFA_COUNTER_LOWER 0xff 1899 #define BCCK_RXFA_COUNTER_UPPER 0xff000000 1900 #define BCCK_RXHPAGC_START 0xe000 1901 #define BCCK_RXHPAGC_FINAL 0x1c00 1902 #define BCCK_RXFALSEALARM_ENABLE 0x8000 1903 #define BCCK_FACOUNTER_FREEZE 0x4000 1904 #define BCCK_TXPATH_SEL 0x10000000 1905 #define BCCK_DEFAULT_RXPATH 0xc000000 1906 #define BCCK_OPTION_RXPATH 0x3000000 1907 1908 #define BNUM_OFSTF 0x3 1909 #define BSHIFT_L 0xc0 1910 #define BGI_TH 0xc 1911 #define BRXPATH_A 0x1 1912 #define BRXPATH_B 0x2 1913 #define BRXPATH_C 0x4 1914 #define BRXPATH_D 0x8 1915 #define BTXPATH_A 0x1 1916 #define BTXPATH_B 0x2 1917 #define BTXPATH_C 0x4 1918 #define BTXPATH_D 0x8 1919 #define BTRSSI_FREQ 0x200 1920 #define BADC_BACKOFF 0x3000 1921 #define BDFIR_BACKOFF 0xc000 1922 #define BTRSSI_LATCH_PHASE 0x10000 1923 #define BRX_LDC_OFFSET 0xff 1924 #define BRX_QDC_OFFSET 0xff00 1925 #define BRX_DFIR_MODE 0x1800000 1926 #define BRX_DCNF_TYPE 0xe000000 1927 #define BRXIQIMB_A 0x3ff 1928 #define BRXIQIMB_B 0xfc00 1929 #define BRXIQIMB_C 0x3f0000 1930 #define BRXIQIMB_D 0xffc00000 1931 #define BDC_DC_NOTCH 0x60000 1932 #define BRXNB_NOTCH 0x1f000000 1933 #define BPD_TH 0xf 1934 #define BPD_TH_OPT2 0xc000 1935 #define BPWED_TH 0x700 1936 #define BIFMF_WIN_L 0x800 1937 #define BPD_OPTION 0x1000 1938 #define BMF_WIN_L 0xe000 1939 #define BBW_SEARCH_L 0x30000 1940 #define BWIN_ENH_L 0xc0000 1941 #define BBW_TH 0x700000 1942 #define BED_TH2 0x3800000 1943 #define BBW_OPTION 0x4000000 1944 #define BRADIO_TH 0x18000000 1945 #define BWINDOW_L 0xe0000000 1946 #define BSBD_OPTION 0x1 1947 #define BFRAME_TH 0x1c 1948 #define BFS_OPTION 0x60 1949 #define BDC_SLOPE_CHECK 0x80 1950 #define BFGUARD_COUNTER_DC_L 0xe00 1951 #define BFRAME_WEIGHT_SHORT 0x7000 1952 #define BSUB_TUNE 0xe00000 1953 #define BFRAME_DC_LENGTH 0xe000000 1954 #define BSBD_START_OFFSET 0x30000000 1955 #define BFRAME_TH_2 0x7 1956 #define BFRAME_GI2_TH 0x38 1957 #define BGI2_SYNC_EN 0x40 1958 #define BSARCH_SHORT_EARLY 0x300 1959 #define BSARCH_SHORT_LATE 0xc00 1960 #define BSARCH_GI2_LATE 0x70000 1961 #define BCFOANTSUM 0x1 1962 #define BCFOACC 0x2 1963 #define BCFOSTARTOFFSET 0xc 1964 #define BCFOLOOPBACK 0x70 1965 #define BCFOSUMWEIGHT 0x80 1966 #define BDAGCENABLE 0x10000 1967 #define BTXIQIMB_A 0x3ff 1968 #define BTXIQIMB_b 0xfc00 1969 #define BTXIQIMB_C 0x3f0000 1970 #define BTXIQIMB_D 0xffc00000 1971 #define BTXIDCOFFSET 0xff 1972 #define BTXIQDCOFFSET 0xff00 1973 #define BTXDFIRMODE 0x10000 1974 #define BTXPESUDO_NOISEON 0x4000000 1975 #define BTXPESUDO_NOISE_A 0xff 1976 #define BTXPESUDO_NOISE_B 0xff00 1977 #define BTXPESUDO_NOISE_C 0xff0000 1978 #define BTXPESUDO_NOISE_D 0xff000000 1979 #define BCCA_DROPOPTION 0x20000 1980 #define BCCA_DROPTHRES 0xfff00000 1981 #define BEDCCA_H 0xf 1982 #define BEDCCA_L 0xf0 1983 #define BLAMBDA_ED 0x300 1984 #define BRX_INITIALGAIN 0x7f 1985 #define BRX_ANTDIV_EN 0x80 1986 #define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 1987 #define BRX_HIGHPOWER_FLOW 0x8000 1988 #define BRX_AGC_FREEZE_THRES 0xc0000 1989 #define BRX_FREEZESTEP_AGC1 0x300000 1990 #define BRX_FREEZESTEP_AGC2 0xc00000 1991 #define BRX_FREEZESTEP_AGC3 0x3000000 1992 #define BRX_FREEZESTEP_AGC0 0xc000000 1993 #define BRXRSSI_CMP_EN 0x10000000 1994 #define BRXQUICK_AGCEN 0x20000000 1995 #define BRXAGC_FREEZE_THRES_MODE 0x40000000 1996 #define BRX_OVERFLOW_CHECKTYPE 0x80000000 1997 #define BRX_AGCSHIFT 0x7f 1998 #define BTRSW_TRI_ONLY 0x80 1999 #define BPOWER_THRES 0x300 2000 #define BRXAGC_EN 0x1 2001 #define BRXAGC_TOGETHER_EN 0x2 2002 #define BRXAGC_MIN 0x4 2003 #define BRXHP_INI 0x7 2004 #define BRXHP_TRLNA 0x70 2005 #define BRXHP_RSSI 0x700 2006 #define BRXHP_BBP1 0x7000 2007 #define BRXHP_BBP2 0x70000 2008 #define BRXHP_BBP3 0x700000 2009 #define BRSSI_H 0x7f0000 2010 #define BRSSI_GEN 0x7f000000 2011 #define BRXSETTLE_TRSW 0x7 2012 #define BRXSETTLE_LNA 0x38 2013 #define BRXSETTLE_RSSI 0x1c0 2014 #define BRXSETTLE_BBP 0xe00 2015 #define BRXSETTLE_RXHP 0x7000 2016 #define BRXSETTLE_ANTSW_RSSI 0x38000 2017 #define BRXSETTLE_ANTSW 0xc0000 2018 #define BRXPROCESS_TIME_DAGC 0x300000 2019 #define BRXSETTLE_HSSI 0x400000 2020 #define BRXPROCESS_TIME_BBPPW 0x800000 2021 #define BRXANTENNA_POWER_SHIFT 0x3000000 2022 #define BRSSI_TABLE_SELECT 0xc000000 2023 #define BRXHP_FINAL 0x7000000 2024 #define BRXHPSETTLE_BBP 0x7 2025 #define BRXHTSETTLE_HSSI 0x8 2026 #define BRXHTSETTLE_RXHP 0x70 2027 #define BRXHTSETTLE_BBPPW 0x80 2028 #define BRXHTSETTLE_IDLE 0x300 2029 #define BRXHTSETTLE_RESERVED 0x1c00 2030 #define BRXHT_RXHP_EN 0x8000 2031 #define BRXAGC_FREEZE_THRES 0x30000 2032 #define BRXAGC_TOGETHEREN 0x40000 2033 #define BRXHTAGC_MIN 0x80000 2034 #define BRXHTAGC_EN 0x100000 2035 #define BRXHTDAGC_EN 0x200000 2036 #define BRXHT_RXHP_BBP 0x1c00000 2037 #define BRXHT_RXHP_FINAL 0xe0000000 2038 #define BRXPW_RADIO_TH 0x3 2039 #define BRXPW_RADIO_EN 0x4 2040 #define BRXMF_HOLD 0x3800 2041 #define BRXPD_DELAY_TH1 0x38 2042 #define BRXPD_DELAY_TH2 0x1c0 2043 #define BRXPD_DC_COUNT_MAX 0x600 2044 #define BRXPD_DELAY_TH 0x8000 2045 #define BRXPROCESS_DELAY 0xf0000 2046 #define BRXSEARCHRANGE_GI2_EARLY 0x700000 2047 #define BRXFRAME_FUARD_COUNTER_L 0x3800000 2048 #define BRXSGI_GUARD_L 0xc000000 2049 #define BRXSGI_SEARCH_L 0x30000000 2050 #define BRXSGI_TH 0xc0000000 2051 #define BDFSCNT0 0xff 2052 #define BDFSCNT1 0xff00 2053 #define BDFSFLAG 0xf0000 2054 #define BMF_WEIGHT_SUM 0x300000 2055 #define BMINIDX_TH 0x7f000000 2056 #define BDAFORMAT 0x40000 2057 #define BTXCH_EMU_ENABLE 0x01000000 2058 #define BTRSW_ISOLATION_A 0x7f 2059 #define BTRSW_ISOLATION_B 0x7f00 2060 #define BTRSW_ISOLATION_C 0x7f0000 2061 #define BTRSW_ISOLATION_D 0x7f000000 2062 #define BEXT_LNA_GAIN 0x7c00 2063 2064 #define BSTBC_EN 0x4 2065 #define BANTENNA_MAPPING 0x10 2066 #define BNSS 0x20 2067 #define BCFO_ANTSUM_ID 0x200 2068 #define BPHY_COUNTER_RESET 0x8000000 2069 #define BCFO_REPORT_GET 0x4000000 2070 #define BOFDM_CONTINUE_TX 0x10000000 2071 #define BOFDM_SINGLE_CARRIER 0x20000000 2072 #define BOFDM_SINGLE_TONE 0x40000000 2073 #define BHT_DETECT 0x100 2074 #define BCFOEN 0x10000 2075 #define BCFOVALUE 0xfff00000 2076 #define BSIGTONE_RE 0x3f 2077 #define BSIGTONE_IM 0x7f00 2078 #define BCOUNTER_CCA 0xffff 2079 #define BCOUNTER_PARITYFAIL 0xffff0000 2080 #define BCOUNTER_RATEILLEGAL 0xffff 2081 #define BCOUNTER_CRC8FAIL 0xffff0000 2082 #define BCOUNTER_MCSNOSUPPORT 0xffff 2083 #define BCOUNTER_FASTSYNC 0xffff 2084 #define BSHORTCFO 0xfff 2085 #define BSHORTCFOT_LENGTH 12 2086 #define BSHORTCFOF_LENGTH 11 2087 #define BLONGCFO 0x7ff 2088 #define BLONGCFOT_LENGTH 11 2089 #define BLONGCFOF_LENGTH 11 2090 #define BTAILCFO 0x1fff 2091 #define BTAILCFOT_LENGTH 13 2092 #define BTAILCFOF_LENGTH 12 2093 #define BNOISE_EN_PWDB 0xffff 2094 #define BCC_POWER_DB 0xffff0000 2095 #define BMOISE_PWDB 0xffff 2096 #define BPOWERMEAST_LENGTH 10 2097 #define BPOWERMEASF_LENGTH 3 2098 #define BRX_HT_BW 0x1 2099 #define BRXSC 0x6 2100 #define BRX_HT 0x8 2101 #define BNB_INTF_DET_ON 0x1 2102 #define BINTF_WIN_LEN_CFG 0x30 2103 #define BNB_INTF_TH_CFG 0x1c0 2104 #define BRFGAIN 0x3f 2105 #define BTABLESEL 0x40 2106 #define BTRSW 0x80 2107 #define BRXSNR_A 0xff 2108 #define BRXSNR_B 0xff00 2109 #define BRXSNR_C 0xff0000 2110 #define BRXSNR_D 0xff000000 2111 #define BSNR_EVMT_LENGTH 8 2112 #define BSNR_EVMF_LENGTH 1 2113 #define BCSI1ST 0xff 2114 #define BCSI2ND 0xff00 2115 #define BRXEVM1ST 0xff0000 2116 #define BRXEVM2ND 0xff000000 2117 #define BSIGEVM 0xff 2118 #define BPWDB 0xff00 2119 #define BSGIEN 0x10000 2120 2121 #define BSFACTOR_QMA1 0xf 2122 #define BSFACTOR_QMA2 0xf0 2123 #define BSFACTOR_QMA3 0xf00 2124 #define BSFACTOR_QMA4 0xf000 2125 #define BSFACTOR_QMA5 0xf0000 2126 #define BSFACTOR_QMA6 0xf0000 2127 #define BSFACTOR_QMA7 0xf00000 2128 #define BSFACTOR_QMA8 0xf000000 2129 #define BSFACTOR_QMA9 0xf0000000 2130 #define BCSI_SCHEME 0x100000 2131 2132 #define BNOISE_LVL_TOP_SET 0x3 2133 #define BCHSMOOTH 0x4 2134 #define BCHSMOOTH_CFG1 0x38 2135 #define BCHSMOOTH_CFG2 0x1c0 2136 #define BCHSMOOTH_CFG3 0xe00 2137 #define BCHSMOOTH_CFG4 0x7000 2138 #define BMRCMODE 0x800000 2139 #define BTHEVMCFG 0x7000000 2140 2141 #define BLOOP_FIT_TYPE 0x1 2142 #define BUPD_CFO 0x40 2143 #define BUPD_CFO_OFFDATA 0x80 2144 #define BADV_UPD_CFO 0x100 2145 #define BADV_TIME_CTRL 0x800 2146 #define BUPD_CLKO 0x1000 2147 #define BFC 0x6000 2148 #define BTRACKING_MODE 0x8000 2149 #define BPHCMP_ENABLE 0x10000 2150 #define BUPD_CLKO_LTF 0x20000 2151 #define BCOM_CH_CFO 0x40000 2152 #define BCSI_ESTI_MODE 0x80000 2153 #define BADV_UPD_EQZ 0x100000 2154 #define BUCHCFG 0x7000000 2155 #define BUPDEQZ 0x8000000 2156 2157 #define BRX_PESUDO_NOISE_ON 0x20000000 2158 #define BRX_PESUDO_NOISE_A 0xff 2159 #define BRX_PESUDO_NOISE_B 0xff00 2160 #define BRX_PESUDO_NOISE_C 0xff0000 2161 #define BRX_PESUDO_NOISE_D 0xff000000 2162 #define BRX_PESUDO_NOISESTATE_A 0xffff 2163 #define BRX_PESUDO_NOISESTATE_B 0xffff0000 2164 #define BRX_PESUDO_NOISESTATE_C 0xffff 2165 #define BRX_PESUDO_NOISESTATE_D 0xffff0000 2166 2167 #define BZEBRA1_HSSIENABLE 0x8 2168 #define BZEBRA1_TRXCONTROL 0xc00 2169 #define BZEBRA1_TRXGAINSETTING 0x07f 2170 #define BZEBRA1_RXCOUNTER 0xc00 2171 #define BZEBRA1_TXCHANGEPUMP 0x38 2172 #define BZEBRA1_RXCHANGEPUMP 0x7 2173 #define BZEBRA1_CHANNEL_NUM 0xf80 2174 #define BZEBRA1_TXLPFBW 0x400 2175 #define BZEBRA1_RXLPFBW 0x600 2176 2177 #define BRTL8256REG_MODE_CTRL1 0x100 2178 #define BRTL8256REG_MODE_CTRL0 0x40 2179 #define BRTL8256REG_TXLPFBW 0x18 2180 #define BRTL8256REG_RXLPFBW 0x600 2181 2182 #define BRTL8258_TXLPFBW 0xc 2183 #define BRTL8258_RXLPFBW 0xc00 2184 #define BRTL8258_RSSILPFBW 0xc0 2185 2186 #define BBYTE0 0x1 2187 #define BBYTE1 0x2 2188 #define BBYTE2 0x4 2189 #define BBYTE3 0x8 2190 #define BWORD0 0x3 2191 #define BWORD1 0xc 2192 #define BWORD 0xf 2193 2194 #define MASKBYTE0 0xff 2195 #define MASKBYTE1 0xff00 2196 #define MASKBYTE2 0xff0000 2197 #define MASKBYTE3 0xff000000 2198 #define MASKHWORD 0xffff0000 2199 #define MASKLWORD 0x0000ffff 2200 #define MASKDWORD 0xffffffff 2201 #define MASK12BITS 0xfff 2202 #define MASKH4BITS 0xf0000000 2203 #define MASKOFDM_D 0xffc00000 2204 #define MASKCCK 0x3f3f3f3f 2205 2206 #define MASK4BITS 0x0f 2207 #define MASK20BITS 0xfffff 2208 #define RFREG_OFFSET_MASK 0xfffff 2209 2210 #define BENABLE 0x1 2211 #define BDISABLE 0x0 2212 2213 #define LEFT_ANTENNA 0x0 2214 #define RIGHT_ANTENNA 0x1 2215 2216 #define TCHECK_TXSTATUS 500 2217 #define TUPDATE_RXCOUNTER 100 2218 2219 #define REG_UN_used_register 0x01bf 2220 2221 /* WOL bit information */ 2222 #define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0) 2223 #define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1) 2224 #define HAL92C_WOL_DISASSOC_EVENT BIT(2) 2225 #define HAL92C_WOL_DEAUTH_EVENT BIT(3) 2226 #define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4) 2227 2228 #define WOL_REASON_PTK_UPDATE BIT(0) 2229 #define WOL_REASON_GTK_UPDATE BIT(1) 2230 #define WOL_REASON_DISASSOC BIT(2) 2231 #define WOL_REASON_DEAUTH BIT(3) 2232 #define WOL_REASON_FW_DISCONNECT BIT(4) 2233 #endif 2234