1 /******************************************************************************
2  *
3  * Copyright(c) 2009-2014  Realtek Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * The full GNU General Public License is included in this distribution in the
15  * file called LICENSE.
16  *
17  * Contact Information:
18  * wlanfae <wlanfae@realtek.com>
19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20  * Hsinchu 300, Taiwan.
21  *
22  * Larry Finger <Larry.Finger@lwfinger.net>
23  *
24  *****************************************************************************/
25 
26 #ifndef __RTL92E_PHY_H__
27 #define __RTL92E_PHY_H__
28 
29 /* MAX_TX_COUNT must always set to 4, otherwise read efuse table sequence
30  * will be wrong.
31  */
32 #define MAX_TX_COUNT				4
33 #define TX_1S					0
34 #define TX_2S					1
35 #define TX_3S					2
36 #define TX_4S					3
37 
38 #define MAX_POWER_INDEX				0x3f
39 
40 #define MAX_PRECMD_CNT				16
41 #define MAX_RFDEPENDCMD_CNT			16
42 #define MAX_POSTCMD_CNT				16
43 
44 #define MAX_DOZE_WAITING_TIMES_9x		64
45 
46 #define RT_CANNOT_IO(hw)			false
47 #define HIGHPOWER_RADIOA_ARRAYLEN		22
48 
49 #define IQK_ADDA_REG_NUM			16
50 #define IQK_MAC_REG_NUM				4
51 #define IQK_BB_REG_NUM				9
52 #define MAX_TOLERANCE				5
53 #define	IQK_DELAY_TIME				10
54 #define	index_mapping_NUM			15
55 
56 #define	APK_BB_REG_NUM				5
57 #define	APK_AFE_REG_NUM				16
58 #define	APK_CURVE_REG_NUM			4
59 #define	PATH_NUM				2
60 
61 #define LOOP_LIMIT				5
62 #define MAX_STALL_TIME				50
63 #define ANTENNADIVERSITYVALUE			0x80
64 #define MAX_TXPWR_IDX_NMODE_92S			63
65 #define RESET_CNT_LIMIT				3
66 
67 #define RF6052_MAX_PATH				2
68 
69 #define CT_OFFSET_MAC_ADDR			0X16
70 
71 #define CT_OFFSET_CCK_TX_PWR_IDX		0x5A
72 #define CT_OFFSET_HT401S_TX_PWR_IDX		0x60
73 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF	0x66
74 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF		0x69
75 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF		0x6C
76 
77 #define CT_OFFSET_HT40_MAX_PWR_OFFSET		0x6F
78 #define CT_OFFSET_HT20_MAX_PWR_OFFSET		0x72
79 
80 #define CT_OFFSET_CHANNEL_PLAH			0x75
81 #define CT_OFFSET_THERMAL_METER			0x78
82 #define CT_OFFSET_RF_OPTION			0x79
83 #define CT_OFFSET_VERSION			0x7E
84 #define CT_OFFSET_CUSTOMER_ID			0x7F
85 
86 #define RTL92C_MAX_PATH_NUM			2
87 
88 enum swchnlcmd_id {
89 	CMDID_END,
90 	CMDID_SET_TXPOWEROWER_LEVEL,
91 	CMDID_BBREGWRITE10,
92 	CMDID_WRITEPORT_ULONG,
93 	CMDID_WRITEPORT_USHORT,
94 	CMDID_WRITEPORT_UCHAR,
95 	CMDID_RF_WRITEREG,
96 };
97 
98 struct swchnlcmd {
99 	enum swchnlcmd_id cmdid;
100 	u32 para1;
101 	u32 para2;
102 	u32 msdelay;
103 };
104 
105 enum baseband_config_type {
106 	BASEBAND_CONFIG_PHY_REG = 0,
107 	BASEBAND_CONFIG_AGC_TAB = 1,
108 };
109 
110 enum ant_div_type {
111 	NO_ANTDIV = 0xFF,
112 	CG_TRX_HW_ANTDIV = 0x01,
113 	CGCS_RX_HW_ANTDIV = 0x02,
114 	FIXED_HW_ANTDIV = 0x03,
115 	CG_TRX_SMART_ANTDIV = 0x04,
116 	CGCS_RX_SW_ANTDIV = 0x05,
117 };
118 
119 u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw,
120 			     u32 regaddr, u32 bitmask);
121 void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw,
122 			    u32 regaddr, u32 bitmask, u32 data);
123 u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw,
124 			     enum radio_path rfpath, u32 regaddr,
125 			     u32 bitmask);
126 void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw,
127 			    enum radio_path rfpath, u32 regaddr,
128 			    u32 bitmask, u32 data);
129 bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw);
130 bool rtl92ee_phy_bb_config(struct ieee80211_hw *hw);
131 bool rtl92ee_phy_rf_config(struct ieee80211_hw *hw);
132 void rtl92ee_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
133 void rtl92ee_phy_get_txpower_level(struct ieee80211_hw *hw,
134 				   long *powerlevel);
135 void rtl92ee_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
136 void rtl92ee_phy_scan_operation_backup(struct ieee80211_hw *hw,
137 				       u8 operation);
138 void rtl92ee_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
139 void rtl92ee_phy_set_bw_mode(struct ieee80211_hw *hw,
140 			     enum nl80211_channel_type ch_type);
141 void rtl92ee_phy_sw_chnl_callback(struct ieee80211_hw *hw);
142 u8 rtl92ee_phy_sw_chnl(struct ieee80211_hw *hw);
143 void rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
144 void rtl92ee_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta);
145 void rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw);
146 void rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
147 bool rtl92ee_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
148 					   enum radio_path rfpath);
149 bool rtl92ee_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
150 bool rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
151 				    enum rf_pwrstate rfpwr_state);
152 
153 #endif
154