1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2014  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../pci.h"
6 #include "../ps.h"
7 #include "reg.h"
8 #include "def.h"
9 #include "phy.h"
10 #include "rf.h"
11 #include "dm.h"
12 #include "table.h"
13 
14 static u32 _rtl92ee_phy_rf_serial_read(struct ieee80211_hw *hw,
15 				       enum radio_path rfpath, u32 offset);
16 static void _rtl92ee_phy_rf_serial_write(struct ieee80211_hw *hw,
17 					 enum radio_path rfpath, u32 offset,
18 					 u32 data);
19 static u32 _rtl92ee_phy_calculate_bit_shift(u32 bitmask);
20 static bool _rtl92ee_phy_bb8192ee_config_parafile(struct ieee80211_hw *hw);
21 static bool _rtl92ee_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
22 static bool phy_config_bb_with_hdr_file(struct ieee80211_hw *hw,
23 					u8 configtype);
24 static bool phy_config_bb_with_pghdrfile(struct ieee80211_hw *hw,
25 					 u8 configtype);
26 static void phy_init_bb_rf_register_def(struct ieee80211_hw *hw);
27 static bool _rtl92ee_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
28 					      u32 cmdtableidx, u32 cmdtablesz,
29 					      enum swchnlcmd_id cmdid,
30 					      u32 para1, u32 para2,
31 					      u32 msdelay);
32 static bool _rtl92ee_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
33 					      u8 channel, u8 *stage,
34 					      u8 *step, u32 *delay);
35 static long _rtl92ee_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
36 					  enum wireless_mode wirelessmode,
37 					  u8 txpwridx);
38 static void rtl92ee_phy_set_rf_on(struct ieee80211_hw *hw);
39 static void rtl92ee_phy_set_io(struct ieee80211_hw *hw);
40 
41 u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
42 {
43 	struct rtl_priv *rtlpriv = rtl_priv(hw);
44 	u32 returnvalue, originalvalue, bitshift;
45 
46 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
47 		 "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask);
48 	originalvalue = rtl_read_dword(rtlpriv, regaddr);
49 	bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask);
50 	returnvalue = (originalvalue & bitmask) >> bitshift;
51 
52 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
53 		 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
54 		  bitmask, regaddr, originalvalue);
55 
56 	return returnvalue;
57 }
58 
59 void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
60 			    u32 bitmask, u32 data)
61 {
62 	struct rtl_priv *rtlpriv = rtl_priv(hw);
63 	u32 originalvalue, bitshift;
64 
65 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
66 		 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
67 		  regaddr, bitmask, data);
68 
69 	if (bitmask != MASKDWORD) {
70 		originalvalue = rtl_read_dword(rtlpriv, regaddr);
71 		bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask);
72 		data = ((originalvalue & (~bitmask)) | (data << bitshift));
73 	}
74 
75 	rtl_write_dword(rtlpriv, regaddr, data);
76 
77 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
78 		 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
79 		  regaddr, bitmask, data);
80 }
81 
82 u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw,
83 			     enum radio_path rfpath, u32 regaddr, u32 bitmask)
84 {
85 	struct rtl_priv *rtlpriv = rtl_priv(hw);
86 	u32 original_value, readback_value, bitshift;
87 
88 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
89 		 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
90 		  regaddr, rfpath, bitmask);
91 
92 	spin_lock(&rtlpriv->locks.rf_lock);
93 
94 	original_value = _rtl92ee_phy_rf_serial_read(hw , rfpath, regaddr);
95 	bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask);
96 	readback_value = (original_value & bitmask) >> bitshift;
97 
98 	spin_unlock(&rtlpriv->locks.rf_lock);
99 
100 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
101 		 "regaddr(%#x),rfpath(%#x),bitmask(%#x),original_value(%#x)\n",
102 		  regaddr, rfpath, bitmask, original_value);
103 
104 	return readback_value;
105 }
106 
107 void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw,
108 			    enum radio_path rfpath,
109 			    u32 addr, u32 bitmask, u32 data)
110 {
111 	struct rtl_priv *rtlpriv = rtl_priv(hw);
112 	u32 original_value, bitshift;
113 
114 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
115 		 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
116 		  addr, bitmask, data, rfpath);
117 
118 	spin_lock(&rtlpriv->locks.rf_lock);
119 
120 	if (bitmask != RFREG_OFFSET_MASK) {
121 		original_value = _rtl92ee_phy_rf_serial_read(hw, rfpath, addr);
122 		bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask);
123 		data = (original_value & (~bitmask)) | (data << bitshift);
124 	}
125 
126 	_rtl92ee_phy_rf_serial_write(hw, rfpath, addr, data);
127 
128 	spin_unlock(&rtlpriv->locks.rf_lock);
129 
130 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
131 		 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
132 		  addr, bitmask, data, rfpath);
133 }
134 
135 static u32 _rtl92ee_phy_rf_serial_read(struct ieee80211_hw *hw,
136 				       enum radio_path rfpath, u32 offset)
137 {
138 	struct rtl_priv *rtlpriv = rtl_priv(hw);
139 	struct rtl_phy *rtlphy = &rtlpriv->phy;
140 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
141 	u32 newoffset;
142 	u32 tmplong, tmplong2;
143 	u8 rfpi_enable = 0;
144 	u32 retvalue;
145 
146 	offset &= 0xff;
147 	newoffset = offset;
148 	if (RT_CANNOT_IO(hw)) {
149 		pr_err("return all one\n");
150 		return 0xFFFFFFFF;
151 	}
152 	tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
153 	if (rfpath == RF90_PATH_A)
154 		tmplong2 = tmplong;
155 	else
156 		tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
157 	tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
158 		   (newoffset << 23) | BLSSIREADEDGE;
159 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
160 		      tmplong & (~BLSSIREADEDGE));
161 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
162 	udelay(20);
163 	if (rfpath == RF90_PATH_A)
164 		rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
165 						BIT(8));
166 	else if (rfpath == RF90_PATH_B)
167 		rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
168 						BIT(8));
169 	if (rfpi_enable)
170 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
171 					 BLSSIREADBACKDATA);
172 	else
173 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
174 					 BLSSIREADBACKDATA);
175 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
176 		 "RFR-%d Addr[0x%x]=0x%x\n",
177 		  rfpath, pphyreg->rf_rb, retvalue);
178 	return retvalue;
179 }
180 
181 static void _rtl92ee_phy_rf_serial_write(struct ieee80211_hw *hw,
182 					 enum radio_path rfpath, u32 offset,
183 					 u32 data)
184 {
185 	u32 data_and_addr;
186 	u32 newoffset;
187 	struct rtl_priv *rtlpriv = rtl_priv(hw);
188 	struct rtl_phy *rtlphy = &rtlpriv->phy;
189 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
190 
191 	if (RT_CANNOT_IO(hw)) {
192 		pr_err("stop\n");
193 		return;
194 	}
195 	offset &= 0xff;
196 	newoffset = offset;
197 	data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
198 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
199 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
200 		 "RFW-%d Addr[0x%x]=0x%x\n", rfpath,
201 		 pphyreg->rf3wire_offset, data_and_addr);
202 }
203 
204 static u32 _rtl92ee_phy_calculate_bit_shift(u32 bitmask)
205 {
206 	u32 i;
207 
208 	for (i = 0; i <= 31; i++) {
209 		if (((bitmask >> i) & 0x1) == 1)
210 			break;
211 	}
212 	return i;
213 }
214 
215 bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw)
216 {
217 	return _rtl92ee_phy_config_mac_with_headerfile(hw);
218 }
219 
220 bool rtl92ee_phy_bb_config(struct ieee80211_hw *hw)
221 {
222 	struct rtl_priv *rtlpriv = rtl_priv(hw);
223 	bool rtstatus = true;
224 	u16 regval;
225 	u32 tmp;
226 	u8 crystal_cap;
227 
228 	phy_init_bb_rf_register_def(hw);
229 	regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
230 	rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
231 		       regval | BIT(13) | BIT(0) | BIT(1));
232 
233 	rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
234 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
235 		       FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
236 		       FEN_BB_GLB_RSTN | FEN_BBRSTB);
237 
238 	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
239 
240 	tmp = rtl_read_dword(rtlpriv, 0x4c);
241 	rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23));
242 
243 	rtstatus = _rtl92ee_phy_bb8192ee_config_parafile(hw);
244 
245 	crystal_cap = rtlpriv->efuse.eeprom_crystalcap & 0x3F;
246 	rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
247 		      (crystal_cap | (crystal_cap << 6)));
248 	return rtstatus;
249 }
250 
251 bool rtl92ee_phy_rf_config(struct ieee80211_hw *hw)
252 {
253 	return rtl92ee_phy_rf6052_config(hw);
254 }
255 
256 static bool _check_condition(struct ieee80211_hw *hw,
257 			     const u32  condition)
258 {
259 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
260 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
261 	u32 _board = rtlefuse->board_type; /*need efuse define*/
262 	u32 _interface = rtlhal->interface;
263 	u32 _platform = 0x08;/*SupportPlatform */
264 	u32 cond = condition;
265 
266 	if (condition == 0xCDCDCDCD)
267 		return true;
268 
269 	cond = condition & 0xFF;
270 	if ((_board != cond) && (cond != 0xFF))
271 		return false;
272 
273 	cond = condition & 0xFF00;
274 	cond = cond >> 8;
275 	if ((_interface & cond) == 0 && cond != 0x07)
276 		return false;
277 
278 	cond = condition & 0xFF0000;
279 	cond = cond >> 16;
280 	if ((_platform & cond) == 0 && cond != 0x0F)
281 		return false;
282 
283 	return true;
284 }
285 
286 static void _rtl92ee_config_rf_reg(struct ieee80211_hw *hw, u32 addr, u32 data,
287 				   enum radio_path rfpath, u32 regaddr)
288 {
289 	if (addr == 0xfe || addr == 0xffe) {
290 		mdelay(50);
291 	} else {
292 		rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data);
293 		udelay(1);
294 
295 		if (addr == 0xb6) {
296 			u32 getvalue;
297 			u8 count = 0;
298 
299 			getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD);
300 			udelay(1);
301 
302 			while ((getvalue >> 8) != (data >> 8)) {
303 				count++;
304 				rtl_set_rfreg(hw, rfpath, regaddr,
305 					      RFREG_OFFSET_MASK, data);
306 				udelay(1);
307 				getvalue = rtl_get_rfreg(hw, rfpath, addr,
308 							 MASKDWORD);
309 				if (count > 5)
310 					break;
311 			}
312 		}
313 
314 		if (addr == 0xb2) {
315 			u32 getvalue;
316 			u8 count = 0;
317 
318 			getvalue = rtl_get_rfreg(hw, rfpath, addr, MASKDWORD);
319 			udelay(1);
320 
321 			while (getvalue != data) {
322 				count++;
323 				rtl_set_rfreg(hw, rfpath, regaddr,
324 					      RFREG_OFFSET_MASK, data);
325 				udelay(1);
326 				rtl_set_rfreg(hw, rfpath, 0x18,
327 					      RFREG_OFFSET_MASK, 0x0fc07);
328 				udelay(1);
329 				getvalue = rtl_get_rfreg(hw, rfpath, addr,
330 							 MASKDWORD);
331 				if (count > 5)
332 					break;
333 			}
334 		}
335 	}
336 }
337 
338 static void _rtl92ee_config_rf_radio_a(struct ieee80211_hw *hw,
339 				       u32 addr, u32 data)
340 {
341 	u32 content = 0x1000; /*RF Content: radio_a_txt*/
342 	u32 maskforphyset = (u32)(content & 0xE000);
343 
344 	_rtl92ee_config_rf_reg(hw, addr, data, RF90_PATH_A,
345 			       addr | maskforphyset);
346 }
347 
348 static void _rtl92ee_config_rf_radio_b(struct ieee80211_hw *hw,
349 				       u32 addr, u32 data)
350 {
351 	u32 content = 0x1001; /*RF Content: radio_b_txt*/
352 	u32 maskforphyset = (u32)(content & 0xE000);
353 
354 	_rtl92ee_config_rf_reg(hw, addr, data, RF90_PATH_B,
355 			       addr | maskforphyset);
356 }
357 
358 static void _rtl92ee_config_bb_reg(struct ieee80211_hw *hw,
359 				   u32 addr, u32 data)
360 {
361 	if (addr == 0xfe)
362 		mdelay(50);
363 	else if (addr == 0xfd)
364 		mdelay(5);
365 	else if (addr == 0xfc)
366 		mdelay(1);
367 	else if (addr == 0xfb)
368 		udelay(50);
369 	else if (addr == 0xfa)
370 		udelay(5);
371 	else if (addr == 0xf9)
372 		udelay(1);
373 	else
374 		rtl_set_bbreg(hw, addr, MASKDWORD , data);
375 
376 	udelay(1);
377 }
378 
379 static void _rtl92ee_phy_init_tx_power_by_rate(struct ieee80211_hw *hw)
380 {
381 	struct rtl_priv *rtlpriv = rtl_priv(hw);
382 	struct rtl_phy *rtlphy = &rtlpriv->phy;
383 
384 	u8 band = BAND_ON_2_4G, rf = 0, txnum = 0, sec = 0;
385 
386 	for (; band <= BAND_ON_5G; ++band)
387 		for (; rf < TX_PWR_BY_RATE_NUM_RF; ++rf)
388 			for (; txnum < TX_PWR_BY_RATE_NUM_RF; ++txnum)
389 				for (; sec < TX_PWR_BY_RATE_NUM_SECTION; ++sec)
390 					rtlphy->tx_power_by_rate_offset
391 					     [band][rf][txnum][sec] = 0;
392 }
393 
394 static void _rtl92ee_phy_set_txpower_by_rate_base(struct ieee80211_hw *hw,
395 						  u8 band, u8 path,
396 						  u8 rate_section, u8 txnum,
397 						  u8 value)
398 {
399 	struct rtl_priv *rtlpriv = rtl_priv(hw);
400 	struct rtl_phy *rtlphy = &rtlpriv->phy;
401 
402 	if (path > RF90_PATH_D) {
403 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
404 			 "Invalid Rf Path %d\n", path);
405 		return;
406 	}
407 
408 	if (band == BAND_ON_2_4G) {
409 		switch (rate_section) {
410 		case CCK:
411 			rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value;
412 			break;
413 		case OFDM:
414 			rtlphy->txpwr_by_rate_base_24g[path][txnum][1] = value;
415 			break;
416 		case HT_MCS0_MCS7:
417 			rtlphy->txpwr_by_rate_base_24g[path][txnum][2] = value;
418 			break;
419 		case HT_MCS8_MCS15:
420 			rtlphy->txpwr_by_rate_base_24g[path][txnum][3] = value;
421 			break;
422 		default:
423 			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
424 				 "Invalid RateSection %d in 2.4G,Rf %d,%dTx\n",
425 				  rate_section, path, txnum);
426 			break;
427 		}
428 	} else {
429 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
430 			 "Invalid Band %d\n", band);
431 	}
432 }
433 
434 static u8 _rtl92ee_phy_get_txpower_by_rate_base(struct ieee80211_hw *hw,
435 						u8 band, u8 path, u8 txnum,
436 						u8 rate_section)
437 {
438 	struct rtl_priv *rtlpriv = rtl_priv(hw);
439 	struct rtl_phy *rtlphy = &rtlpriv->phy;
440 	u8 value = 0;
441 
442 	if (path > RF90_PATH_D) {
443 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
444 			 "Invalid Rf Path %d\n", path);
445 		return 0;
446 	}
447 
448 	if (band == BAND_ON_2_4G) {
449 		switch (rate_section) {
450 		case CCK:
451 			value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0];
452 			break;
453 		case OFDM:
454 			value = rtlphy->txpwr_by_rate_base_24g[path][txnum][1];
455 			break;
456 		case HT_MCS0_MCS7:
457 			value = rtlphy->txpwr_by_rate_base_24g[path][txnum][2];
458 			break;
459 		case HT_MCS8_MCS15:
460 			value = rtlphy->txpwr_by_rate_base_24g[path][txnum][3];
461 			break;
462 		default:
463 			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
464 				 "Invalid RateSection %d in 2.4G,Rf %d,%dTx\n",
465 				  rate_section, path, txnum);
466 			break;
467 		}
468 	} else {
469 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
470 			 "Invalid Band %d()\n", band);
471 	}
472 	return value;
473 }
474 
475 static void _rtl92ee_phy_store_txpower_by_rate_base(struct ieee80211_hw *hw)
476 {
477 	struct rtl_priv *rtlpriv = rtl_priv(hw);
478 	struct rtl_phy *rtlphy = &rtlpriv->phy;
479 	u16 raw = 0;
480 	u8 base = 0, path = 0;
481 
482 	for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) {
483 		if (path == RF90_PATH_A) {
484 			raw = (u16)(rtlphy->tx_power_by_rate_offset
485 				    [BAND_ON_2_4G][path][RF_1TX][3] >> 24) &
486 				    0xFF;
487 			base = (raw >> 4) * 10 + (raw & 0xF);
488 			_rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
489 							      path, CCK, RF_1TX,
490 							      base);
491 		} else if (path == RF90_PATH_B) {
492 			raw = (u16)(rtlphy->tx_power_by_rate_offset
493 				    [BAND_ON_2_4G][path][RF_1TX][3] >> 0) &
494 				    0xFF;
495 			base = (raw >> 4) * 10 + (raw & 0xF);
496 			_rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G,
497 							      path, CCK, RF_1TX,
498 							      base);
499 		}
500 		raw = (u16)(rtlphy->tx_power_by_rate_offset
501 			    [BAND_ON_2_4G][path][RF_1TX][1] >> 24) & 0xFF;
502 		base = (raw >> 4) * 10 + (raw & 0xF);
503 		_rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path,
504 						      OFDM, RF_1TX, base);
505 
506 		raw = (u16)(rtlphy->tx_power_by_rate_offset
507 			    [BAND_ON_2_4G][path][RF_1TX][5] >> 24) & 0xFF;
508 		base = (raw >> 4) * 10 + (raw & 0xF);
509 		_rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path,
510 						      HT_MCS0_MCS7, RF_1TX,
511 						      base);
512 
513 		raw = (u16)(rtlphy->tx_power_by_rate_offset
514 			    [BAND_ON_2_4G][path][RF_2TX][7] >> 24) & 0xFF;
515 		base = (raw >> 4) * 10 + (raw & 0xF);
516 		_rtl92ee_phy_set_txpower_by_rate_base(hw, BAND_ON_2_4G, path,
517 						      HT_MCS8_MCS15, RF_2TX,
518 						      base);
519 	}
520 }
521 
522 static void _phy_convert_txpower_dbm_to_relative_value(u32 *data, u8 start,
523 						       u8 end, u8 base)
524 {
525 	s8 i = 0;
526 	u8 tmp = 0;
527 	u32 temp_data = 0;
528 
529 	for (i = 3; i >= 0; --i) {
530 		if (i >= start && i <= end) {
531 			/* Get the exact value */
532 			tmp = (u8)(*data >> (i * 8)) & 0xF;
533 			tmp += ((u8)((*data >> (i * 8 + 4)) & 0xF)) * 10;
534 
535 			/* Change the value to a relative value */
536 			tmp = (tmp > base) ? tmp - base : base - tmp;
537 		} else {
538 			tmp = (u8)(*data >> (i * 8)) & 0xFF;
539 		}
540 		temp_data <<= 8;
541 		temp_data |= tmp;
542 	}
543 	*data = temp_data;
544 }
545 
546 static void phy_convert_txpwr_dbm_to_rel_val(struct ieee80211_hw *hw)
547 {
548 	struct rtl_priv *rtlpriv = rtl_priv(hw);
549 	struct rtl_phy *rtlphy = &rtlpriv->phy;
550 	u8 base = 0, rf = 0, band = BAND_ON_2_4G;
551 
552 	for (rf = RF90_PATH_A; rf <= RF90_PATH_B; ++rf) {
553 		if (rf == RF90_PATH_A) {
554 			base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band,
555 								     rf, RF_1TX,
556 								     CCK);
557 			_phy_convert_txpower_dbm_to_relative_value(
558 				&rtlphy->tx_power_by_rate_offset
559 				[band][rf][RF_1TX][2],
560 				1, 1, base);
561 			_phy_convert_txpower_dbm_to_relative_value(
562 				&rtlphy->tx_power_by_rate_offset
563 				[band][rf][RF_1TX][3],
564 				1, 3, base);
565 		} else if (rf == RF90_PATH_B) {
566 			base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band,
567 								     rf, RF_1TX,
568 								     CCK);
569 			_phy_convert_txpower_dbm_to_relative_value(
570 				&rtlphy->tx_power_by_rate_offset
571 				[band][rf][RF_1TX][3],
572 				0, 0, base);
573 			_phy_convert_txpower_dbm_to_relative_value(
574 				&rtlphy->tx_power_by_rate_offset
575 				[band][rf][RF_1TX][2],
576 				1, 3, base);
577 		}
578 		base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf,
579 							     RF_1TX, OFDM);
580 		_phy_convert_txpower_dbm_to_relative_value(
581 			&rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][0],
582 			0, 3, base);
583 		_phy_convert_txpower_dbm_to_relative_value(
584 			&rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][1],
585 			0, 3, base);
586 
587 		base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf,
588 							     RF_1TX,
589 							     HT_MCS0_MCS7);
590 		_phy_convert_txpower_dbm_to_relative_value(
591 			&rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][4],
592 			0, 3, base);
593 		_phy_convert_txpower_dbm_to_relative_value(
594 			&rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][5],
595 			0, 3, base);
596 
597 		base = _rtl92ee_phy_get_txpower_by_rate_base(hw, band, rf,
598 							     RF_2TX,
599 							     HT_MCS8_MCS15);
600 		_phy_convert_txpower_dbm_to_relative_value(
601 			&rtlphy->tx_power_by_rate_offset[band][rf][RF_2TX][6],
602 			0, 3, base);
603 
604 		_phy_convert_txpower_dbm_to_relative_value(
605 			&rtlphy->tx_power_by_rate_offset[band][rf][RF_2TX][7],
606 			0, 3, base);
607 	}
608 
609 	RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
610 		 "<==phy_convert_txpwr_dbm_to_rel_val()\n");
611 }
612 
613 static void _rtl92ee_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw)
614 {
615 	_rtl92ee_phy_store_txpower_by_rate_base(hw);
616 	phy_convert_txpwr_dbm_to_rel_val(hw);
617 }
618 
619 static bool _rtl92ee_phy_bb8192ee_config_parafile(struct ieee80211_hw *hw)
620 {
621 	struct rtl_priv *rtlpriv = rtl_priv(hw);
622 	struct rtl_phy *rtlphy = &rtlpriv->phy;
623 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
624 	bool rtstatus;
625 
626 	rtstatus = phy_config_bb_with_hdr_file(hw, BASEBAND_CONFIG_PHY_REG);
627 	if (!rtstatus) {
628 		pr_err("Write BB Reg Fail!!\n");
629 		return false;
630 	}
631 
632 	_rtl92ee_phy_init_tx_power_by_rate(hw);
633 	if (!rtlefuse->autoload_failflag) {
634 		rtlphy->pwrgroup_cnt = 0;
635 		rtstatus =
636 		  phy_config_bb_with_pghdrfile(hw, BASEBAND_CONFIG_PHY_REG);
637 	}
638 	_rtl92ee_phy_txpower_by_rate_configuration(hw);
639 	if (!rtstatus) {
640 		pr_err("BB_PG Reg Fail!!\n");
641 		return false;
642 	}
643 	rtstatus = phy_config_bb_with_hdr_file(hw, BASEBAND_CONFIG_AGC_TAB);
644 	if (!rtstatus) {
645 		pr_err("AGC Table Fail\n");
646 		return false;
647 	}
648 	rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw,
649 						      RFPGA0_XA_HSSIPARAMETER2,
650 						      0x200));
651 
652 	return true;
653 }
654 
655 static bool _rtl92ee_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
656 {
657 	struct rtl_priv *rtlpriv = rtl_priv(hw);
658 	u32 i;
659 	u32 arraylength;
660 	u32 *ptrarray;
661 
662 	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl8192EMACPHY_Array\n");
663 	arraylength = RTL8192EE_MAC_ARRAY_LEN;
664 	ptrarray = RTL8192EE_MAC_ARRAY;
665 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
666 		 "Img:RTL8192EE_MAC_ARRAY LEN %d\n" , arraylength);
667 	for (i = 0; i < arraylength; i = i + 2)
668 		rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]);
669 	return true;
670 }
671 
672 #define READ_NEXT_PAIR(v1, v2, i) \
673 	do { \
674 		i += 2; \
675 		v1 = array[i]; \
676 		v2 = array[i+1]; \
677 	} while (0)
678 
679 static bool phy_config_bb_with_hdr_file(struct ieee80211_hw *hw,
680 					u8 configtype)
681 {
682 	int i;
683 	u32 *array;
684 	u16 len;
685 	struct rtl_priv *rtlpriv = rtl_priv(hw);
686 	u32 v1 = 0, v2 = 0;
687 
688 	if (configtype == BASEBAND_CONFIG_PHY_REG) {
689 		len = RTL8192EE_PHY_REG_ARRAY_LEN;
690 		array = RTL8192EE_PHY_REG_ARRAY;
691 
692 		for (i = 0; i < len; i = i + 2) {
693 			v1 = array[i];
694 			v2 = array[i+1];
695 			if (v1 < 0xcdcdcdcd) {
696 				_rtl92ee_config_bb_reg(hw, v1, v2);
697 			} else {/*This line is the start line of branch.*/
698 				/* to protect READ_NEXT_PAIR not overrun */
699 				if (i >= len - 2)
700 					break;
701 
702 				if (!_check_condition(hw , array[i])) {
703 					/*Discard the following pairs*/
704 					READ_NEXT_PAIR(v1, v2, i);
705 					while (v2 != 0xDEAD &&
706 					       v2 != 0xCDEF &&
707 					       v2 != 0xCDCD && i < len - 2) {
708 						READ_NEXT_PAIR(v1, v2, i);
709 					}
710 					i -= 2; /* prevent from for-loop += 2*/
711 				} else {
712 					/* Configure matched pairs and
713 					 * skip to end of if-else.
714 					 */
715 					READ_NEXT_PAIR(v1, v2, i);
716 					while (v2 != 0xDEAD &&
717 					       v2 != 0xCDEF &&
718 					       v2 != 0xCDCD && i < len - 2) {
719 						_rtl92ee_config_bb_reg(hw, v1,
720 								       v2);
721 						READ_NEXT_PAIR(v1, v2, i);
722 					}
723 
724 					while (v2 != 0xDEAD && i < len - 2)
725 						READ_NEXT_PAIR(v1, v2, i);
726 				}
727 			}
728 		}
729 	} else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
730 		len = RTL8192EE_AGC_TAB_ARRAY_LEN;
731 		array = RTL8192EE_AGC_TAB_ARRAY;
732 
733 		for (i = 0; i < len; i = i + 2) {
734 			v1 = array[i];
735 			v2 = array[i+1];
736 			if (v1 < 0xCDCDCDCD) {
737 				rtl_set_bbreg(hw, array[i], MASKDWORD,
738 					      array[i + 1]);
739 				udelay(1);
740 				continue;
741 		    } else{/*This line is the start line of branch.*/
742 			  /* to protect READ_NEXT_PAIR not overrun */
743 				if (i >= len - 2)
744 					break;
745 
746 				if (!_check_condition(hw , array[i])) {
747 					/*Discard the following pairs*/
748 					READ_NEXT_PAIR(v1, v2, i);
749 					while (v2 != 0xDEAD &&
750 					       v2 != 0xCDEF &&
751 					       v2 != 0xCDCD &&
752 					       i < len - 2) {
753 						READ_NEXT_PAIR(v1, v2, i);
754 					}
755 					i -= 2; /* prevent from for-loop += 2*/
756 				} else {
757 					/* Configure matched pairs and
758 					 * skip to end of if-else.
759 					 */
760 					READ_NEXT_PAIR(v1, v2, i);
761 					while (v2 != 0xDEAD &&
762 					       v2 != 0xCDEF &&
763 					       v2 != 0xCDCD &&
764 					       i < len - 2) {
765 						rtl_set_bbreg(hw,
766 							      array[i],
767 							      MASKDWORD,
768 							      array[i + 1]);
769 						udelay(1);
770 						READ_NEXT_PAIR(v1 , v2 , i);
771 					}
772 
773 					while (v2 != 0xDEAD &&
774 					       i < len - 2) {
775 						READ_NEXT_PAIR(v1 , v2 , i);
776 					}
777 				}
778 			}
779 			RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
780 				 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n",
781 				 array[i],
782 				 array[i + 1]);
783 		}
784 	}
785 	return true;
786 }
787 
788 static u8 _rtl92ee_get_rate_section_index(u32 regaddr)
789 {
790 	u8 index = 0;
791 
792 	switch (regaddr) {
793 	case RTXAGC_A_RATE18_06:
794 	case RTXAGC_B_RATE18_06:
795 		index = 0;
796 		break;
797 	case RTXAGC_A_RATE54_24:
798 	case RTXAGC_B_RATE54_24:
799 		index = 1;
800 		break;
801 	case RTXAGC_A_CCK1_MCS32:
802 	case RTXAGC_B_CCK1_55_MCS32:
803 		index = 2;
804 		break;
805 	case RTXAGC_B_CCK11_A_CCK2_11:
806 		index = 3;
807 		break;
808 	case RTXAGC_A_MCS03_MCS00:
809 	case RTXAGC_B_MCS03_MCS00:
810 		index = 4;
811 		break;
812 	case RTXAGC_A_MCS07_MCS04:
813 	case RTXAGC_B_MCS07_MCS04:
814 		index = 5;
815 		break;
816 	case RTXAGC_A_MCS11_MCS08:
817 	case RTXAGC_B_MCS11_MCS08:
818 		index = 6;
819 		break;
820 	case RTXAGC_A_MCS15_MCS12:
821 	case RTXAGC_B_MCS15_MCS12:
822 		index = 7;
823 		break;
824 	default:
825 		regaddr &= 0xFFF;
826 		if (regaddr >= 0xC20 && regaddr <= 0xC4C)
827 			index = (u8)((regaddr - 0xC20) / 4);
828 		else if (regaddr >= 0xE20 && regaddr <= 0xE4C)
829 			index = (u8)((regaddr - 0xE20) / 4);
830 		break;
831 	}
832 	return index;
833 }
834 
835 static void _rtl92ee_store_tx_power_by_rate(struct ieee80211_hw *hw,
836 					    enum band_type band,
837 					    enum radio_path rfpath,
838 					    u32 txnum, u32 regaddr,
839 					    u32 bitmask, u32 data)
840 {
841 	struct rtl_priv *rtlpriv = rtl_priv(hw);
842 	struct rtl_phy *rtlphy = &rtlpriv->phy;
843 	u8 section = _rtl92ee_get_rate_section_index(regaddr);
844 
845 	if (band != BAND_ON_2_4G && band != BAND_ON_5G) {
846 		RT_TRACE(rtlpriv, FPHY, PHY_TXPWR, "Invalid Band %d\n", band);
847 		return;
848 	}
849 
850 	if (rfpath > MAX_RF_PATH - 1) {
851 		RT_TRACE(rtlpriv, FPHY, PHY_TXPWR,
852 			 "Invalid RfPath %d\n", rfpath);
853 		return;
854 	}
855 	if (txnum > MAX_RF_PATH - 1) {
856 		RT_TRACE(rtlpriv, FPHY, PHY_TXPWR, "Invalid TxNum %d\n", txnum);
857 		return;
858 	}
859 
860 	rtlphy->tx_power_by_rate_offset[band][rfpath][txnum][section] = data;
861 }
862 
863 static bool phy_config_bb_with_pghdrfile(struct ieee80211_hw *hw,
864 					 u8 configtype)
865 {
866 	struct rtl_priv *rtlpriv = rtl_priv(hw);
867 	int i;
868 	u32 *phy_regarray_table_pg;
869 	u16 phy_regarray_pg_len;
870 	u32 v1 = 0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v6 = 0;
871 
872 	phy_regarray_pg_len = RTL8192EE_PHY_REG_ARRAY_PG_LEN;
873 	phy_regarray_table_pg = RTL8192EE_PHY_REG_ARRAY_PG;
874 
875 	if (configtype == BASEBAND_CONFIG_PHY_REG) {
876 		for (i = 0; i < phy_regarray_pg_len; i = i + 6) {
877 			v1 = phy_regarray_table_pg[i];
878 			v2 = phy_regarray_table_pg[i+1];
879 			v3 = phy_regarray_table_pg[i+2];
880 			v4 = phy_regarray_table_pg[i+3];
881 			v5 = phy_regarray_table_pg[i+4];
882 			v6 = phy_regarray_table_pg[i+5];
883 
884 			if (v1 < 0xcdcdcdcd) {
885 				_rtl92ee_store_tx_power_by_rate(hw, v1, v2, v3,
886 								v4, v5, v6);
887 				continue;
888 			}
889 		}
890 	} else {
891 		RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
892 			 "configtype != BaseBand_Config_PHY_REG\n");
893 	}
894 	return true;
895 }
896 
897 #define READ_NEXT_RF_PAIR(v1, v2, i) \
898 	do { \
899 		i += 2; \
900 		v1 = array[i]; \
901 		v2 = array[i+1]; \
902 	} while (0)
903 
904 bool rtl92ee_phy_config_rf_with_headerfile(struct ieee80211_hw  *hw,
905 					   enum radio_path rfpath)
906 {
907 	struct rtl_priv *rtlpriv = rtl_priv(hw);
908 	int i;
909 	u32 *array;
910 	u16 len;
911 	u32 v1 = 0, v2 = 0;
912 
913 	switch (rfpath) {
914 	case RF90_PATH_A:
915 		len = RTL8192EE_RADIOA_ARRAY_LEN;
916 		array = RTL8192EE_RADIOA_ARRAY;
917 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
918 			 "Radio_A:RTL8192EE_RADIOA_ARRAY %d\n" , len);
919 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
920 		for (i = 0; i < len; i = i + 2) {
921 			v1 = array[i];
922 			v2 = array[i+1];
923 			if (v1 < 0xcdcdcdcd) {
924 				_rtl92ee_config_rf_radio_a(hw, v1, v2);
925 				continue;
926 			} else {/*This line is the start line of branch.*/
927 				/* to protect READ_NEXT_PAIR not overrun */
928 				if (i >= len - 2)
929 					break;
930 
931 				if (!_check_condition(hw , array[i])) {
932 					/*Discard the following pairs*/
933 					READ_NEXT_RF_PAIR(v1, v2, i);
934 					while (v2 != 0xDEAD &&
935 					       v2 != 0xCDEF &&
936 					       v2 != 0xCDCD && i < len - 2) {
937 						READ_NEXT_RF_PAIR(v1, v2, i);
938 					}
939 					i -= 2; /* prevent from for-loop += 2*/
940 				} else {
941 					/* Configure matched pairs and
942 					 * skip to end of if-else.
943 					 */
944 					READ_NEXT_RF_PAIR(v1, v2, i);
945 					while (v2 != 0xDEAD &&
946 					       v2 != 0xCDEF &&
947 					       v2 != 0xCDCD && i < len - 2) {
948 						_rtl92ee_config_rf_radio_a(hw,
949 									   v1,
950 									   v2);
951 						READ_NEXT_RF_PAIR(v1, v2, i);
952 					}
953 
954 					while (v2 != 0xDEAD && i < len - 2)
955 						READ_NEXT_RF_PAIR(v1, v2, i);
956 				}
957 			}
958 		}
959 		break;
960 
961 	case RF90_PATH_B:
962 		len = RTL8192EE_RADIOB_ARRAY_LEN;
963 		array = RTL8192EE_RADIOB_ARRAY;
964 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
965 			 "Radio_A:RTL8192EE_RADIOB_ARRAY %d\n" , len);
966 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
967 		for (i = 0; i < len; i = i + 2) {
968 			v1 = array[i];
969 			v2 = array[i+1];
970 			if (v1 < 0xcdcdcdcd) {
971 				_rtl92ee_config_rf_radio_b(hw, v1, v2);
972 				continue;
973 			} else {/*This line is the start line of branch.*/
974 				/* to protect READ_NEXT_PAIR not overrun */
975 				if (i >= len - 2)
976 					break;
977 
978 				if (!_check_condition(hw , array[i])) {
979 					/*Discard the following pairs*/
980 					READ_NEXT_RF_PAIR(v1, v2, i);
981 					while (v2 != 0xDEAD &&
982 					       v2 != 0xCDEF &&
983 					       v2 != 0xCDCD && i < len - 2) {
984 						READ_NEXT_RF_PAIR(v1, v2, i);
985 					}
986 					i -= 2; /* prevent from for-loop += 2*/
987 				} else {
988 					/* Configure matched pairs and
989 					 * skip to end of if-else.
990 					 */
991 					READ_NEXT_RF_PAIR(v1, v2, i);
992 					while (v2 != 0xDEAD &&
993 					       v2 != 0xCDEF &&
994 					       v2 != 0xCDCD && i < len - 2) {
995 						_rtl92ee_config_rf_radio_b(hw,
996 									   v1,
997 									   v2);
998 						READ_NEXT_RF_PAIR(v1, v2, i);
999 					}
1000 
1001 					while (v2 != 0xDEAD && i < len - 2)
1002 						READ_NEXT_RF_PAIR(v1, v2, i);
1003 				}
1004 			}
1005 		}
1006 		break;
1007 	case RF90_PATH_C:
1008 	case RF90_PATH_D:
1009 		break;
1010 	}
1011 	return true;
1012 }
1013 
1014 void rtl92ee_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1015 {
1016 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1017 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1018 
1019 	rtlphy->default_initialgain[0] =
1020 		(u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
1021 	rtlphy->default_initialgain[1] =
1022 		(u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
1023 	rtlphy->default_initialgain[2] =
1024 		(u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
1025 	rtlphy->default_initialgain[3] =
1026 		(u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
1027 
1028 	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1029 		 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
1030 		  rtlphy->default_initialgain[0],
1031 		  rtlphy->default_initialgain[1],
1032 		  rtlphy->default_initialgain[2],
1033 		  rtlphy->default_initialgain[3]);
1034 
1035 	rtlphy->framesync = (u8)rtl_get_bbreg(hw,
1036 					      ROFDM0_RXDETECTOR3, MASKBYTE0);
1037 	rtlphy->framesync_c34 = rtl_get_bbreg(hw,
1038 					      ROFDM0_RXDETECTOR2, MASKDWORD);
1039 
1040 	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1041 		 "Default framesync (0x%x) = 0x%x\n",
1042 		  ROFDM0_RXDETECTOR3, rtlphy->framesync);
1043 }
1044 
1045 static void phy_init_bb_rf_register_def(struct ieee80211_hw *hw)
1046 {
1047 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1048 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1049 
1050 	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
1051 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
1052 
1053 	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
1054 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
1055 
1056 	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
1057 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
1058 
1059 	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
1060 							RFPGA0_XA_LSSIPARAMETER;
1061 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
1062 							RFPGA0_XB_LSSIPARAMETER;
1063 
1064 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
1065 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
1066 
1067 	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
1068 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
1069 
1070 	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
1071 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
1072 }
1073 
1074 void rtl92ee_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
1075 {
1076 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1077 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1078 	u8 txpwr_level;
1079 	long txpwr_dbm;
1080 
1081 	txpwr_level = rtlphy->cur_cck_txpwridx;
1082 	txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B,
1083 						  txpwr_level);
1084 	txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
1085 	if (_rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, txpwr_level) >
1086 	    txpwr_dbm)
1087 		txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
1088 							  txpwr_level);
1089 	txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
1090 	if (_rtl92ee_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
1091 					  txpwr_level) > txpwr_dbm)
1092 		txpwr_dbm = _rtl92ee_phy_txpwr_idx_to_dbm(hw,
1093 							  WIRELESS_MODE_N_24G,
1094 							  txpwr_level);
1095 	*powerlevel = txpwr_dbm;
1096 }
1097 
1098 static u8 _rtl92ee_phy_get_ratesection_intxpower_byrate(enum radio_path path,
1099 							u8 rate)
1100 {
1101 	u8 rate_section = 0;
1102 
1103 	switch (rate) {
1104 	case DESC92C_RATE1M:
1105 		rate_section = 2;
1106 		break;
1107 	case DESC92C_RATE2M:
1108 	case DESC92C_RATE5_5M:
1109 		if (path == RF90_PATH_A)
1110 			rate_section = 3;
1111 		else if (path == RF90_PATH_B)
1112 			rate_section = 2;
1113 		break;
1114 	case DESC92C_RATE11M:
1115 		rate_section = 3;
1116 		break;
1117 	case DESC92C_RATE6M:
1118 	case DESC92C_RATE9M:
1119 	case DESC92C_RATE12M:
1120 	case DESC92C_RATE18M:
1121 		rate_section = 0;
1122 		break;
1123 	case DESC92C_RATE24M:
1124 	case DESC92C_RATE36M:
1125 	case DESC92C_RATE48M:
1126 	case DESC92C_RATE54M:
1127 		rate_section = 1;
1128 		break;
1129 	case DESC92C_RATEMCS0:
1130 	case DESC92C_RATEMCS1:
1131 	case DESC92C_RATEMCS2:
1132 	case DESC92C_RATEMCS3:
1133 		rate_section = 4;
1134 		break;
1135 	case DESC92C_RATEMCS4:
1136 	case DESC92C_RATEMCS5:
1137 	case DESC92C_RATEMCS6:
1138 	case DESC92C_RATEMCS7:
1139 		rate_section = 5;
1140 		break;
1141 	case DESC92C_RATEMCS8:
1142 	case DESC92C_RATEMCS9:
1143 	case DESC92C_RATEMCS10:
1144 	case DESC92C_RATEMCS11:
1145 		rate_section = 6;
1146 		break;
1147 	case DESC92C_RATEMCS12:
1148 	case DESC92C_RATEMCS13:
1149 	case DESC92C_RATEMCS14:
1150 	case DESC92C_RATEMCS15:
1151 		rate_section = 7;
1152 		break;
1153 	default:
1154 		WARN_ONCE(true, "rtl8192ee: Rate_Section is Illegal\n");
1155 		break;
1156 	}
1157 	return rate_section;
1158 }
1159 
1160 static u8 _rtl92ee_get_txpower_by_rate(struct ieee80211_hw *hw,
1161 				       enum band_type band,
1162 				       enum radio_path rf, u8 rate)
1163 {
1164 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1165 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1166 	u8 shift = 0, sec, tx_num;
1167 	s8 diff = 0;
1168 
1169 	sec = _rtl92ee_phy_get_ratesection_intxpower_byrate(rf, rate);
1170 	tx_num = RF_TX_NUM_NONIMPLEMENT;
1171 
1172 	if (tx_num == RF_TX_NUM_NONIMPLEMENT) {
1173 		if ((rate >= DESC92C_RATEMCS8 && rate <= DESC92C_RATEMCS15))
1174 			tx_num = RF_2TX;
1175 		else
1176 			tx_num = RF_1TX;
1177 	}
1178 
1179 	switch (rate) {
1180 	case DESC92C_RATE1M:
1181 	case DESC92C_RATE6M:
1182 	case DESC92C_RATE24M:
1183 	case DESC92C_RATEMCS0:
1184 	case DESC92C_RATEMCS4:
1185 	case DESC92C_RATEMCS8:
1186 	case DESC92C_RATEMCS12:
1187 		shift = 0;
1188 		break;
1189 	case DESC92C_RATE2M:
1190 	case DESC92C_RATE9M:
1191 	case DESC92C_RATE36M:
1192 	case DESC92C_RATEMCS1:
1193 	case DESC92C_RATEMCS5:
1194 	case DESC92C_RATEMCS9:
1195 	case DESC92C_RATEMCS13:
1196 		shift = 8;
1197 		break;
1198 	case DESC92C_RATE5_5M:
1199 	case DESC92C_RATE12M:
1200 	case DESC92C_RATE48M:
1201 	case DESC92C_RATEMCS2:
1202 	case DESC92C_RATEMCS6:
1203 	case DESC92C_RATEMCS10:
1204 	case DESC92C_RATEMCS14:
1205 		shift = 16;
1206 		break;
1207 	case DESC92C_RATE11M:
1208 	case DESC92C_RATE18M:
1209 	case DESC92C_RATE54M:
1210 	case DESC92C_RATEMCS3:
1211 	case DESC92C_RATEMCS7:
1212 	case DESC92C_RATEMCS11:
1213 	case DESC92C_RATEMCS15:
1214 		shift = 24;
1215 		break;
1216 	default:
1217 		WARN_ONCE(true, "rtl8192ee: Rate_Section is Illegal\n");
1218 		break;
1219 	}
1220 
1221 	diff = (u8)(rtlphy->tx_power_by_rate_offset[band][rf][tx_num][sec] >>
1222 		    shift) & 0xff;
1223 
1224 	return	diff;
1225 }
1226 
1227 static u8 _rtl92ee_get_txpower_index(struct ieee80211_hw *hw,
1228 				     enum radio_path rfpath, u8 rate,
1229 				     u8 bw, u8 channel)
1230 {
1231 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1232 	struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
1233 	u8 index = (channel - 1);
1234 	u8 tx_power = 0;
1235 	u8 diff = 0;
1236 
1237 	if (channel < 1 || channel > 14) {
1238 		index = 0;
1239 		RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_DMESG,
1240 			 "Illegal channel!!\n");
1241 	}
1242 
1243 	if (IS_CCK_RATE((s8)rate))
1244 		tx_power = rtlefuse->txpwrlevel_cck[rfpath][index];
1245 	else if (DESC92C_RATE6M <= rate)
1246 		tx_power = rtlefuse->txpwrlevel_ht40_1s[rfpath][index];
1247 
1248 	/* OFDM-1T*/
1249 	if (DESC92C_RATE6M <= rate && rate <= DESC92C_RATE54M &&
1250 	    !IS_CCK_RATE((s8)rate))
1251 		tx_power += rtlefuse->txpwr_legacyhtdiff[rfpath][TX_1S];
1252 
1253 	/* BW20-1S, BW20-2S */
1254 	if (bw == HT_CHANNEL_WIDTH_20) {
1255 		if (DESC92C_RATEMCS0 <= rate && rate <= DESC92C_RATEMCS15)
1256 			tx_power += rtlefuse->txpwr_ht20diff[rfpath][TX_1S];
1257 		if (DESC92C_RATEMCS8 <= rate && rate <= DESC92C_RATEMCS15)
1258 			tx_power += rtlefuse->txpwr_ht20diff[rfpath][TX_2S];
1259 	} else if (bw == HT_CHANNEL_WIDTH_20_40) {/* BW40-1S, BW40-2S */
1260 		if (DESC92C_RATEMCS0 <= rate && rate <= DESC92C_RATEMCS15)
1261 			tx_power += rtlefuse->txpwr_ht40diff[rfpath][TX_1S];
1262 		if (DESC92C_RATEMCS8 <= rate && rate <= DESC92C_RATEMCS15)
1263 			tx_power += rtlefuse->txpwr_ht40diff[rfpath][TX_2S];
1264 	}
1265 
1266 	if (rtlefuse->eeprom_regulatory != 2)
1267 		diff = _rtl92ee_get_txpower_by_rate(hw, BAND_ON_2_4G,
1268 						    rfpath, rate);
1269 
1270 	tx_power += diff;
1271 
1272 	if (tx_power > MAX_POWER_INDEX)
1273 		tx_power = MAX_POWER_INDEX;
1274 
1275 	return tx_power;
1276 }
1277 
1278 static void _rtl92ee_set_txpower_index(struct ieee80211_hw *hw, u8 pwr_idx,
1279 				       enum radio_path rfpath, u8 rate)
1280 {
1281 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1282 
1283 	if (rfpath == RF90_PATH_A) {
1284 		switch (rate) {
1285 		case DESC92C_RATE1M:
1286 			rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1,
1287 				      pwr_idx);
1288 			break;
1289 		case DESC92C_RATE2M:
1290 			rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE1,
1291 				      pwr_idx);
1292 			break;
1293 		case DESC92C_RATE5_5M:
1294 			rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE2,
1295 				      pwr_idx);
1296 			break;
1297 		case DESC92C_RATE11M:
1298 			rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE3,
1299 				      pwr_idx);
1300 			break;
1301 		case DESC92C_RATE6M:
1302 			rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE0,
1303 				      pwr_idx);
1304 			break;
1305 		case DESC92C_RATE9M:
1306 			rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE1,
1307 				      pwr_idx);
1308 			break;
1309 		case DESC92C_RATE12M:
1310 			rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE2,
1311 				      pwr_idx);
1312 			break;
1313 		case DESC92C_RATE18M:
1314 			rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE3,
1315 				      pwr_idx);
1316 			break;
1317 		case DESC92C_RATE24M:
1318 			rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE0,
1319 				      pwr_idx);
1320 			break;
1321 		case DESC92C_RATE36M:
1322 			rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE1,
1323 				      pwr_idx);
1324 			break;
1325 		case DESC92C_RATE48M:
1326 			rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE2,
1327 				      pwr_idx);
1328 			break;
1329 		case DESC92C_RATE54M:
1330 			rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE3,
1331 				      pwr_idx);
1332 			break;
1333 		case DESC92C_RATEMCS0:
1334 			rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE0,
1335 				      pwr_idx);
1336 			break;
1337 		case DESC92C_RATEMCS1:
1338 			rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE1,
1339 				      pwr_idx);
1340 			break;
1341 		case DESC92C_RATEMCS2:
1342 			rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE2,
1343 				      pwr_idx);
1344 			break;
1345 		case DESC92C_RATEMCS3:
1346 			rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE3,
1347 				      pwr_idx);
1348 			break;
1349 		case DESC92C_RATEMCS4:
1350 			rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE0,
1351 				      pwr_idx);
1352 			break;
1353 		case DESC92C_RATEMCS5:
1354 			rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE1,
1355 				      pwr_idx);
1356 			break;
1357 		case DESC92C_RATEMCS6:
1358 			rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE2,
1359 				      pwr_idx);
1360 			break;
1361 		case DESC92C_RATEMCS7:
1362 			rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE3,
1363 				      pwr_idx);
1364 			break;
1365 		case DESC92C_RATEMCS8:
1366 			rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE0,
1367 				      pwr_idx);
1368 			break;
1369 		case DESC92C_RATEMCS9:
1370 			rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE1,
1371 				      pwr_idx);
1372 			break;
1373 		case DESC92C_RATEMCS10:
1374 			rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE2,
1375 				      pwr_idx);
1376 			break;
1377 		case DESC92C_RATEMCS11:
1378 			rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE3,
1379 				      pwr_idx);
1380 			break;
1381 		case DESC92C_RATEMCS12:
1382 			rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE0,
1383 				      pwr_idx);
1384 			break;
1385 		case DESC92C_RATEMCS13:
1386 			rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE1,
1387 				      pwr_idx);
1388 			break;
1389 		case DESC92C_RATEMCS14:
1390 			rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE2,
1391 				      pwr_idx);
1392 			break;
1393 		case DESC92C_RATEMCS15:
1394 			rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE3,
1395 				      pwr_idx);
1396 			break;
1397 		default:
1398 			RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1399 				 "Invalid Rate!!\n");
1400 			break;
1401 		}
1402 	} else if (rfpath == RF90_PATH_B) {
1403 		switch (rate) {
1404 		case DESC92C_RATE1M:
1405 			rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE1,
1406 				      pwr_idx);
1407 			break;
1408 		case DESC92C_RATE2M:
1409 			rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE2,
1410 				      pwr_idx);
1411 			break;
1412 		case DESC92C_RATE5_5M:
1413 			rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE3,
1414 				      pwr_idx);
1415 			break;
1416 		case DESC92C_RATE11M:
1417 			rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0,
1418 				      pwr_idx);
1419 			break;
1420 		case DESC92C_RATE6M:
1421 			rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE0,
1422 				      pwr_idx);
1423 			break;
1424 		case DESC92C_RATE9M:
1425 			rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE1,
1426 				      pwr_idx);
1427 			break;
1428 		case DESC92C_RATE12M:
1429 			rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE2,
1430 				      pwr_idx);
1431 			break;
1432 		case DESC92C_RATE18M:
1433 			rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE3,
1434 				      pwr_idx);
1435 			break;
1436 		case DESC92C_RATE24M:
1437 			rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE0,
1438 				      pwr_idx);
1439 			break;
1440 		case DESC92C_RATE36M:
1441 			rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE1,
1442 				      pwr_idx);
1443 			break;
1444 		case DESC92C_RATE48M:
1445 			rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE2,
1446 				      pwr_idx);
1447 			break;
1448 		case DESC92C_RATE54M:
1449 			rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE3,
1450 				      pwr_idx);
1451 			break;
1452 		case DESC92C_RATEMCS0:
1453 			rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE0,
1454 				      pwr_idx);
1455 			break;
1456 		case DESC92C_RATEMCS1:
1457 			rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE1,
1458 				      pwr_idx);
1459 			break;
1460 		case DESC92C_RATEMCS2:
1461 			rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE2,
1462 				      pwr_idx);
1463 			break;
1464 		case DESC92C_RATEMCS3:
1465 			rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE3,
1466 				      pwr_idx);
1467 			break;
1468 		case DESC92C_RATEMCS4:
1469 			rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE0,
1470 				      pwr_idx);
1471 			break;
1472 		case DESC92C_RATEMCS5:
1473 			rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE1,
1474 				      pwr_idx);
1475 			break;
1476 		case DESC92C_RATEMCS6:
1477 			rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE2,
1478 				      pwr_idx);
1479 			break;
1480 		case DESC92C_RATEMCS7:
1481 			rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE3,
1482 				      pwr_idx);
1483 			break;
1484 		case DESC92C_RATEMCS8:
1485 			rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE0,
1486 				      pwr_idx);
1487 			break;
1488 		case DESC92C_RATEMCS9:
1489 			rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE1,
1490 				      pwr_idx);
1491 			break;
1492 		case DESC92C_RATEMCS10:
1493 			rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE2,
1494 				      pwr_idx);
1495 			break;
1496 		case DESC92C_RATEMCS11:
1497 			rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE3,
1498 				      pwr_idx);
1499 			break;
1500 		case DESC92C_RATEMCS12:
1501 			rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE0,
1502 				      pwr_idx);
1503 			break;
1504 		case DESC92C_RATEMCS13:
1505 			rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE1,
1506 				      pwr_idx);
1507 			break;
1508 		case DESC92C_RATEMCS14:
1509 			rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE2,
1510 				      pwr_idx);
1511 			break;
1512 		case DESC92C_RATEMCS15:
1513 			rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE3,
1514 				      pwr_idx);
1515 			break;
1516 		default:
1517 			RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1518 				 "Invalid Rate!!\n");
1519 			break;
1520 		}
1521 	} else {
1522 		RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Invalid RFPath!!\n");
1523 	}
1524 }
1525 
1526 static void phy_set_txpower_index_by_rate_array(struct ieee80211_hw *hw,
1527 						enum radio_path rfpath, u8 bw,
1528 						u8 channel, u8 *rates, u8 size)
1529 {
1530 	u8 i;
1531 	u8 power_index;
1532 
1533 	for (i = 0; i < size; i++) {
1534 		power_index = _rtl92ee_get_txpower_index(hw, rfpath, rates[i],
1535 							 bw, channel);
1536 		_rtl92ee_set_txpower_index(hw, power_index, rfpath, rates[i]);
1537 	}
1538 }
1539 
1540 static void phy_set_txpower_index_by_rate_section(struct ieee80211_hw *hw,
1541 						  enum radio_path rfpath,
1542 						  u8 channel,
1543 						  enum rate_section section)
1544 {
1545 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1546 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1547 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1548 
1549 	if (section == CCK) {
1550 		u8 cck_rates[] = {DESC92C_RATE1M, DESC92C_RATE2M,
1551 				  DESC92C_RATE5_5M, DESC92C_RATE11M};
1552 		if (rtlhal->current_bandtype == BAND_ON_2_4G)
1553 			phy_set_txpower_index_by_rate_array(hw, rfpath,
1554 							rtlphy->current_chan_bw,
1555 							channel, cck_rates, 4);
1556 	} else if (section == OFDM) {
1557 		u8 ofdm_rates[] = {DESC92C_RATE6M, DESC92C_RATE9M,
1558 				   DESC92C_RATE12M, DESC92C_RATE18M,
1559 				   DESC92C_RATE24M, DESC92C_RATE36M,
1560 				   DESC92C_RATE48M, DESC92C_RATE54M};
1561 		phy_set_txpower_index_by_rate_array(hw, rfpath,
1562 						    rtlphy->current_chan_bw,
1563 						    channel, ofdm_rates, 8);
1564 	} else if (section == HT_MCS0_MCS7) {
1565 		u8 ht_rates1t[]  = {DESC92C_RATEMCS0, DESC92C_RATEMCS1,
1566 				    DESC92C_RATEMCS2, DESC92C_RATEMCS3,
1567 				    DESC92C_RATEMCS4, DESC92C_RATEMCS5,
1568 				    DESC92C_RATEMCS6, DESC92C_RATEMCS7};
1569 		phy_set_txpower_index_by_rate_array(hw, rfpath,
1570 						    rtlphy->current_chan_bw,
1571 						    channel, ht_rates1t, 8);
1572 	} else if (section == HT_MCS8_MCS15) {
1573 		u8 ht_rates2t[]  = {DESC92C_RATEMCS8, DESC92C_RATEMCS9,
1574 				    DESC92C_RATEMCS10, DESC92C_RATEMCS11,
1575 				    DESC92C_RATEMCS12, DESC92C_RATEMCS13,
1576 				    DESC92C_RATEMCS14, DESC92C_RATEMCS15};
1577 		phy_set_txpower_index_by_rate_array(hw, rfpath,
1578 						    rtlphy->current_chan_bw,
1579 						    channel, ht_rates2t, 8);
1580 	} else
1581 		RT_TRACE(rtlpriv, FPHY, PHY_TXPWR,
1582 			 "Invalid RateSection %d\n", section);
1583 }
1584 
1585 void rtl92ee_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1586 {
1587 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1588 	struct rtl_phy *rtlphy = &rtl_priv(hw)->phy;
1589 	enum radio_path rfpath;
1590 
1591 	if (!rtlefuse->txpwr_fromeprom)
1592 		return;
1593 	for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1594 	     rfpath++) {
1595 		phy_set_txpower_index_by_rate_section(hw, rfpath,
1596 						      channel, CCK);
1597 		phy_set_txpower_index_by_rate_section(hw, rfpath,
1598 						      channel, OFDM);
1599 		phy_set_txpower_index_by_rate_section(hw, rfpath,
1600 						      channel,
1601 						      HT_MCS0_MCS7);
1602 
1603 		if (rtlphy->num_total_rfpath >= 2)
1604 			phy_set_txpower_index_by_rate_section(hw,
1605 							      rfpath, channel,
1606 							      HT_MCS8_MCS15);
1607 	}
1608 }
1609 
1610 static long _rtl92ee_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
1611 					  enum wireless_mode wirelessmode,
1612 					  u8 txpwridx)
1613 {
1614 	long offset;
1615 	long pwrout_dbm;
1616 
1617 	switch (wirelessmode) {
1618 	case WIRELESS_MODE_B:
1619 		offset = -7;
1620 		break;
1621 	case WIRELESS_MODE_G:
1622 	case WIRELESS_MODE_N_24G:
1623 		offset = -8;
1624 		break;
1625 	default:
1626 		offset = -8;
1627 		break;
1628 	}
1629 	pwrout_dbm = txpwridx / 2 + offset;
1630 	return pwrout_dbm;
1631 }
1632 
1633 void rtl92ee_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1634 {
1635 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1636 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1637 	enum io_type iotype;
1638 
1639 	if (!is_hal_stop(rtlhal)) {
1640 		switch (operation) {
1641 		case SCAN_OPT_BACKUP_BAND0:
1642 			iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
1643 			rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1644 						      (u8 *)&iotype);
1645 
1646 			break;
1647 		case SCAN_OPT_RESTORE:
1648 			iotype = IO_CMD_RESUME_DM_BY_SCAN;
1649 			rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1650 						      (u8 *)&iotype);
1651 			break;
1652 		default:
1653 			pr_err("Unknown Scan Backup operation.\n");
1654 			break;
1655 		}
1656 	}
1657 }
1658 
1659 void rtl92ee_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
1660 {
1661 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1662 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1663 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1664 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1665 	u8 reg_bw_opmode;
1666 	u8 reg_prsr_rsc;
1667 
1668 	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1669 		 "Switch to %s bandwidth\n",
1670 		  rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1671 		  "20MHz" : "40MHz");
1672 
1673 	if (is_hal_stop(rtlhal)) {
1674 		rtlphy->set_bwmode_inprogress = false;
1675 		return;
1676 	}
1677 
1678 	reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1679 	reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1680 
1681 	switch (rtlphy->current_chan_bw) {
1682 	case HT_CHANNEL_WIDTH_20:
1683 		reg_bw_opmode |= BW_OPMODE_20MHZ;
1684 		rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1685 		break;
1686 	case HT_CHANNEL_WIDTH_20_40:
1687 		reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1688 		rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1689 		reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
1690 			       (mac->cur_40_prime_sc << 5);
1691 		rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1692 		break;
1693 	default:
1694 		pr_err("unknown bandwidth: %#X\n",
1695 		       rtlphy->current_chan_bw);
1696 		break;
1697 	}
1698 
1699 	switch (rtlphy->current_chan_bw) {
1700 	case HT_CHANNEL_WIDTH_20:
1701 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1702 		rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1703 		rtl_set_bbreg(hw, ROFDM0_TXPSEUDONOISEWGT,
1704 			      (BIT(31) | BIT(30)), 0);
1705 		break;
1706 	case HT_CHANNEL_WIDTH_20_40:
1707 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1708 		rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1709 		rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
1710 			      (mac->cur_40_prime_sc >> 1));
1711 		rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00,
1712 			      mac->cur_40_prime_sc);
1713 
1714 		rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1715 			      (mac->cur_40_prime_sc ==
1716 			       HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1717 		break;
1718 	default:
1719 		pr_err("unknown bandwidth: %#X\n",
1720 		       rtlphy->current_chan_bw);
1721 		break;
1722 	}
1723 	rtl92ee_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1724 	rtlphy->set_bwmode_inprogress = false;
1725 	RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, "\n");
1726 }
1727 
1728 void rtl92ee_phy_set_bw_mode(struct ieee80211_hw *hw,
1729 			     enum nl80211_channel_type ch_type)
1730 {
1731 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1732 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1733 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1734 	u8 tmp_bw = rtlphy->current_chan_bw;
1735 
1736 	if (rtlphy->set_bwmode_inprogress)
1737 		return;
1738 	rtlphy->set_bwmode_inprogress = true;
1739 	if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1740 		rtl92ee_phy_set_bw_mode_callback(hw);
1741 	} else {
1742 		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1743 			 "false driver sleep or unload\n");
1744 		rtlphy->set_bwmode_inprogress = false;
1745 		rtlphy->current_chan_bw = tmp_bw;
1746 	}
1747 }
1748 
1749 void rtl92ee_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1750 {
1751 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1752 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1753 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1754 	u32 delay;
1755 
1756 	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1757 		 "switch to channel%d\n", rtlphy->current_channel);
1758 	if (is_hal_stop(rtlhal))
1759 		return;
1760 	do {
1761 		if (!rtlphy->sw_chnl_inprogress)
1762 			break;
1763 		if (!_rtl92ee_phy_sw_chnl_step_by_step
1764 		    (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
1765 		     &rtlphy->sw_chnl_step, &delay)) {
1766 			if (delay > 0)
1767 				mdelay(delay);
1768 			else
1769 				continue;
1770 		} else {
1771 			rtlphy->sw_chnl_inprogress = false;
1772 		}
1773 		break;
1774 	} while (true);
1775 	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
1776 }
1777 
1778 u8 rtl92ee_phy_sw_chnl(struct ieee80211_hw *hw)
1779 {
1780 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1781 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1782 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1783 
1784 	if (rtlphy->sw_chnl_inprogress)
1785 		return 0;
1786 	if (rtlphy->set_bwmode_inprogress)
1787 		return 0;
1788 	WARN_ONCE((rtlphy->current_channel > 14),
1789 		  "rtl8192ee: WIRELESS_MODE_G but channel>14");
1790 	rtlphy->sw_chnl_inprogress = true;
1791 	rtlphy->sw_chnl_stage = 0;
1792 	rtlphy->sw_chnl_step = 0;
1793 	if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1794 		rtl92ee_phy_sw_chnl_callback(hw);
1795 		RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1796 			 "sw_chnl_inprogress false schedule workitem current channel %d\n",
1797 			 rtlphy->current_channel);
1798 		rtlphy->sw_chnl_inprogress = false;
1799 	} else {
1800 		RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1801 			 "sw_chnl_inprogress false driver sleep or unload\n");
1802 		rtlphy->sw_chnl_inprogress = false;
1803 	}
1804 	return 1;
1805 }
1806 
1807 static bool _rtl92ee_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
1808 					      u8 channel, u8 *stage, u8 *step,
1809 					      u32 *delay)
1810 {
1811 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1812 	struct rtl_phy *rtlphy = &rtlpriv->phy;
1813 	struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
1814 	u32 precommoncmdcnt;
1815 	struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
1816 	u32 postcommoncmdcnt;
1817 	struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
1818 	u32 rfdependcmdcnt;
1819 	struct swchnlcmd *currentcmd = NULL;
1820 	u8 rfpath;
1821 	u8 num_total_rfpath = rtlphy->num_total_rfpath;
1822 
1823 	precommoncmdcnt = 0;
1824 	_rtl92ee_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1825 					  MAX_PRECMD_CNT,
1826 					  CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
1827 	_rtl92ee_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1828 					  MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
1829 
1830 	postcommoncmdcnt = 0;
1831 
1832 	_rtl92ee_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
1833 					  MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
1834 
1835 	rfdependcmdcnt = 0;
1836 
1837 	WARN_ONCE((channel < 1 || channel > 14),
1838 		  "rtl8192ee: illegal channel for Zebra: %d\n", channel);
1839 
1840 	_rtl92ee_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1841 					  MAX_RFDEPENDCMD_CNT,
1842 					  CMDID_RF_WRITEREG,
1843 					  RF_CHNLBW, channel, 10);
1844 
1845 	_rtl92ee_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1846 					  MAX_RFDEPENDCMD_CNT, CMDID_END,
1847 					  0, 0, 0);
1848 
1849 	do {
1850 		switch (*stage) {
1851 		case 0:
1852 			currentcmd = &precommoncmd[*step];
1853 			break;
1854 		case 1:
1855 			currentcmd = &rfdependcmd[*step];
1856 			break;
1857 		case 2:
1858 			currentcmd = &postcommoncmd[*step];
1859 			break;
1860 		default:
1861 			pr_err("Invalid 'stage' = %d, Check it!\n",
1862 			       *stage);
1863 			return true;
1864 		}
1865 
1866 		if (currentcmd->cmdid == CMDID_END) {
1867 			if ((*stage) == 2)
1868 				return true;
1869 			(*stage)++;
1870 			(*step) = 0;
1871 			continue;
1872 		}
1873 
1874 		switch (currentcmd->cmdid) {
1875 		case CMDID_SET_TXPOWEROWER_LEVEL:
1876 			rtl92ee_phy_set_txpower_level(hw, channel);
1877 			break;
1878 		case CMDID_WRITEPORT_ULONG:
1879 			rtl_write_dword(rtlpriv, currentcmd->para1,
1880 					currentcmd->para2);
1881 			break;
1882 		case CMDID_WRITEPORT_USHORT:
1883 			rtl_write_word(rtlpriv, currentcmd->para1,
1884 				       (u16)currentcmd->para2);
1885 			break;
1886 		case CMDID_WRITEPORT_UCHAR:
1887 			rtl_write_byte(rtlpriv, currentcmd->para1,
1888 				       (u8)currentcmd->para2);
1889 			break;
1890 		case CMDID_RF_WRITEREG:
1891 			for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
1892 				rtlphy->rfreg_chnlval[rfpath] =
1893 					((rtlphy->rfreg_chnlval[rfpath] &
1894 					  0xfffff00) | currentcmd->para2);
1895 
1896 				rtl_set_rfreg(hw, (enum radio_path)rfpath,
1897 					      currentcmd->para1,
1898 					      0x3ff,
1899 					      rtlphy->rfreg_chnlval[rfpath]);
1900 			}
1901 			break;
1902 		default:
1903 			RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1904 				 "switch case %#x not processed\n",
1905 				 currentcmd->cmdid);
1906 			break;
1907 		}
1908 
1909 		break;
1910 	} while (true);
1911 
1912 	(*delay) = currentcmd->msdelay;
1913 	(*step)++;
1914 	return false;
1915 }
1916 
1917 static bool _rtl92ee_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
1918 					      u32 cmdtableidx, u32 cmdtablesz,
1919 					      enum swchnlcmd_id cmdid,
1920 					      u32 para1, u32 para2, u32 msdelay)
1921 {
1922 	struct swchnlcmd *pcmd;
1923 
1924 	if (cmdtable == NULL) {
1925 		WARN_ONCE(true, "rtl8192ee: cmdtable cannot be NULL.\n");
1926 		return false;
1927 	}
1928 
1929 	if (cmdtableidx >= cmdtablesz)
1930 		return false;
1931 
1932 	pcmd = cmdtable + cmdtableidx;
1933 	pcmd->cmdid = cmdid;
1934 	pcmd->para1 = para1;
1935 	pcmd->para2 = para2;
1936 	pcmd->msdelay = msdelay;
1937 	return true;
1938 }
1939 
1940 static u8 _rtl92ee_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1941 {
1942 	u32 reg_eac, reg_e94, reg_e9c;
1943 	u8 result = 0x00;
1944 	/* path-A IQK setting */
1945 	/* PA/PAD controlled by 0x0 */
1946 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1947 	rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180);
1948 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1949 
1950 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
1951 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1952 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1953 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1954 
1955 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140303);
1956 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160000);
1957 
1958 	/*LO calibration setting*/
1959 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
1960 
1961 	/*One shot, path A LOK & IQK*/
1962 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1963 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1964 
1965 	mdelay(IQK_DELAY_TIME);
1966 
1967 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1968 	reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1969 	reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1970 
1971 	if (!(reg_eac & BIT(28)) &&
1972 	    (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1973 	    (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1974 		result |= 0x01;
1975 	else
1976 		return result;
1977 
1978 	return result;
1979 }
1980 
1981 static u8 _rtl92ee_phy_path_b_iqk(struct ieee80211_hw *hw)
1982 {
1983 	u32 reg_eac, reg_eb4, reg_ebc;
1984 	u8 result = 0x00;
1985 
1986 	/* PA/PAD controlled by 0x0 */
1987 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1988 	rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180);
1989 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1990 
1991 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1992 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1993 
1994 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1995 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
1996 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c);
1997 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
1998 
1999 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x821403e2);
2000 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160000);
2001 
2002 	/* LO calibration setting */
2003 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911);
2004 
2005 	/*One shot, path B LOK & IQK*/
2006 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
2007 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
2008 
2009 	mdelay(IQK_DELAY_TIME);
2010 
2011 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
2012 	reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
2013 	reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
2014 
2015 	if (!(reg_eac & BIT(31)) &&
2016 	    (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
2017 	    (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
2018 		result |= 0x01;
2019 	else
2020 		return result;
2021 
2022 	return result;
2023 }
2024 
2025 static u8 _rtl92ee_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb)
2026 {
2027 	u32 reg_eac, reg_e94, reg_e9c, reg_ea4 , u32temp;
2028 	u8 result = 0x00;
2029 
2030 	/*Get TXIMR Setting*/
2031 	/*Modify RX IQK mode table*/
2032 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2033 
2034 	rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
2035 	rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
2036 	rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
2037 	rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);
2038 
2039 	/*PA/PAD control by 0x56, and set = 0x0*/
2040 	rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980);
2041 	rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000);
2042 
2043 	/*enter IQK mode*/
2044 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2045 
2046 	/*IQK Setting*/
2047 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
2048 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2049 
2050 	/*path a IQK setting*/
2051 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
2052 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2053 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2054 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2055 
2056 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f);
2057 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160c1f);
2058 
2059 	/*LO calibration Setting*/
2060 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
2061 
2062 	/*one shot,path A LOK & iqk*/
2063 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
2064 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
2065 
2066 	mdelay(IQK_DELAY_TIME);
2067 
2068 	/* Check failed */
2069 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
2070 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
2071 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
2072 
2073 	if (!(reg_eac & BIT(28)) &&
2074 	    (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
2075 	    (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) {
2076 		result |= 0x01;
2077 	} else {
2078 		/*	PA/PAD controlled by 0x0 */
2079 		rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2080 		rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180);
2081 		return result;
2082 	}
2083 
2084 	u32temp = 0x80007C00 | (reg_e94 & 0x3FF0000)  |
2085 		  ((reg_e9c & 0x3FF0000) >> 16);
2086 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);
2087 	/*RX IQK*/
2088 	/*Modify RX IQK mode table*/
2089 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2090 
2091 	rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
2092 
2093 	rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
2094 	rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
2095 	rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);
2096 
2097 	/*PA/PAD control by 0x56, and set = 0x0*/
2098 	rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980);
2099 	rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000);
2100 
2101 	/*enter IQK mode*/
2102 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2103 
2104 	/*IQK Setting*/
2105 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2106 
2107 	/*path a IQK setting*/
2108 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2109 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c);
2110 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2111 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2112 
2113 	rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f);
2114 	rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c1f);
2115 
2116 	/*LO calibration Setting*/
2117 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891);
2118 	/*one shot,path A LOK & iqk*/
2119 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
2120 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
2121 
2122 	mdelay(IQK_DELAY_TIME);
2123 	/*Check failed*/
2124 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
2125 	reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);
2126 
2127 	/*PA/PAD controlled by 0x0*/
2128 	/*leave IQK mode*/
2129 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2130 	rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180);
2131 	/*if Tx is OK, check whether Rx is OK*/
2132 	if (!(reg_eac & BIT(27)) &&
2133 	    (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
2134 	    (((reg_eac & 0x03FF0000) >> 16) != 0x36))
2135 		result |= 0x02;
2136 
2137 	return result;
2138 }
2139 
2140 static u8 _rtl92ee_phy_path_b_rx_iqk(struct ieee80211_hw *hw, bool config_pathb)
2141 {
2142 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2143 	u32 reg_eac, reg_eb4, reg_ebc, reg_ecc, reg_ec4, u32temp;
2144 	u8 result = 0x00;
2145 
2146 	/*Get TXIMR Setting*/
2147 	/*Modify RX IQK mode table*/
2148 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2149 
2150 	rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
2151 	rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
2152 	rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
2153 	rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);
2154 
2155 	/*PA/PAD all off*/
2156 	rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980);
2157 	rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000);
2158 
2159 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2160 
2161 	/*IQK Setting*/
2162 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
2163 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2164 
2165 	/*path a IQK setting*/
2166 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2167 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2168 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c);
2169 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2170 
2171 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f);
2172 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160c1f);
2173 
2174 	/*LO calibration Setting*/
2175 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
2176 
2177 	/*one shot,path A LOK & iqk*/
2178 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
2179 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
2180 
2181 	mdelay(IQK_DELAY_TIME);
2182 
2183 	/* Check failed */
2184 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
2185 	reg_eb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD);
2186 	reg_ebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD);
2187 
2188 	if (!(reg_eac & BIT(31)) &&
2189 	    (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
2190 	    (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) {
2191 		result |= 0x01;
2192 	} else {
2193 		/*	PA/PAD controlled by 0x0 */
2194 		rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2195 		rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180);
2196 		return result;
2197 	}
2198 
2199 	u32temp = 0x80007C00 | (reg_eb4 & 0x3FF0000) |
2200 		  ((reg_ebc & 0x3FF0000) >> 16);
2201 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);
2202 	/*RX IQK*/
2203 	/*Modify RX IQK mode table*/
2204 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2205 	rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
2206 
2207 	rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
2208 	rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
2209 	rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);
2210 
2211 	/*PA/PAD all off*/
2212 	rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980);
2213 	rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000);
2214 
2215 	/*enter IQK mode*/
2216 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2217 
2218 	/*IQK Setting*/
2219 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2220 
2221 	/*path b IQK setting*/
2222 	rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2223 	rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c);
2224 	rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c);
2225 	rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c1c);
2226 
2227 	rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f);
2228 	rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160c1f);
2229 
2230 	/*LO calibration Setting*/
2231 	rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891);
2232 	/*one shot,path A LOK & iqk*/
2233 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000);
2234 	rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
2235 
2236 	mdelay(IQK_DELAY_TIME);
2237 	/*Check failed*/
2238 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
2239 	reg_ec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD);
2240 	reg_ecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD);
2241 	/*PA/PAD controlled by 0x0*/
2242 	/*leave IQK mode*/
2243 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
2244 	rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180);
2245 	/*if Tx is OK, check whether Rx is OK*/
2246 	if (!(reg_eac & BIT(30)) &&
2247 	    (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
2248 	    (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
2249 		result |= 0x02;
2250 	else
2251 		RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "Path B Rx IQK fail!!\n");
2252 
2253 	return result;
2254 }
2255 
2256 static void _rtl92ee_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
2257 						bool b_iqk_ok, long result[][8],
2258 						u8 final_candidate,
2259 						bool btxonly)
2260 {
2261 	u32 oldval_0, x, tx0_a, reg;
2262 	long y, tx0_c;
2263 
2264 	if (final_candidate == 0xFF) {
2265 		return;
2266 	} else if (b_iqk_ok) {
2267 		oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2268 					  MASKDWORD) >> 22) & 0x3FF;
2269 		x = result[final_candidate][0];
2270 		if ((x & 0x00000200) != 0)
2271 			x = x | 0xFFFFFC00;
2272 		tx0_a = (x * oldval_0) >> 8;
2273 		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
2274 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
2275 			      ((x * oldval_0 >> 7) & 0x1));
2276 		y = result[final_candidate][1];
2277 		if ((y & 0x00000200) != 0)
2278 			y = y | 0xFFFFFC00;
2279 		tx0_c = (y * oldval_0) >> 8;
2280 		rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
2281 			      ((tx0_c & 0x3C0) >> 6));
2282 		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
2283 			      (tx0_c & 0x3F));
2284 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
2285 			      ((y * oldval_0 >> 7) & 0x1));
2286 
2287 		if (btxonly)
2288 			return;
2289 
2290 		reg = result[final_candidate][2];
2291 		rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2292 
2293 		reg = result[final_candidate][3] & 0x3F;
2294 		rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2295 
2296 		reg = (result[final_candidate][3] >> 6) & 0xF;
2297 		rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg);
2298 	}
2299 }
2300 
2301 static void _rtl92ee_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
2302 						bool b_iqk_ok, long result[][8],
2303 						u8 final_candidate,
2304 						bool btxonly)
2305 {
2306 	u32 oldval_1, x, tx1_a, reg;
2307 	long y, tx1_c;
2308 
2309 	if (final_candidate == 0xFF) {
2310 		return;
2311 	} else if (b_iqk_ok) {
2312 		oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2313 					  MASKDWORD) >> 22) & 0x3FF;
2314 		x = result[final_candidate][4];
2315 		if ((x & 0x00000200) != 0)
2316 			x = x | 0xFFFFFC00;
2317 		tx1_a = (x * oldval_1) >> 8;
2318 		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx1_a);
2319 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
2320 			      ((x * oldval_1 >> 7) & 0x1));
2321 		y = result[final_candidate][5];
2322 		if ((y & 0x00000200) != 0)
2323 			y = y | 0xFFFFFC00;
2324 		tx1_c = (y * oldval_1) >> 8;
2325 		rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
2326 			      ((tx1_c & 0x3C0) >> 6));
2327 		rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
2328 			      (tx1_c & 0x3F));
2329 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
2330 			      ((y * oldval_1 >> 7) & 0x1));
2331 
2332 		if (btxonly)
2333 			return;
2334 
2335 		reg = result[final_candidate][6];
2336 		rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2337 
2338 		reg = result[final_candidate][7] & 0x3F;
2339 		rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2340 
2341 		reg = (result[final_candidate][7] >> 6) & 0xF;
2342 		rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0xF0000000, reg);
2343 	}
2344 }
2345 
2346 static void _rtl92ee_phy_save_adda_registers(struct ieee80211_hw *hw,
2347 					     u32 *addareg, u32 *addabackup,
2348 					     u32 registernum)
2349 {
2350 	u32 i;
2351 
2352 	for (i = 0; i < registernum; i++)
2353 		addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
2354 }
2355 
2356 static void _rtl92ee_phy_save_mac_registers(struct ieee80211_hw *hw,
2357 					    u32 *macreg, u32 *macbackup)
2358 {
2359 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2360 	u32 i;
2361 
2362 	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
2363 		macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
2364 
2365 	macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
2366 }
2367 
2368 static void _rtl92ee_phy_reload_adda_registers(struct ieee80211_hw *hw,
2369 					       u32 *addareg, u32 *addabackup,
2370 					       u32 regiesternum)
2371 {
2372 	u32 i;
2373 
2374 	for (i = 0; i < regiesternum; i++)
2375 		rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
2376 }
2377 
2378 static void _rtl92ee_phy_reload_mac_registers(struct ieee80211_hw *hw,
2379 					      u32 *macreg, u32 *macbackup)
2380 {
2381 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2382 	u32 i;
2383 
2384 	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
2385 		rtl_write_byte(rtlpriv, macreg[i], (u8)macbackup[i]);
2386 	rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
2387 }
2388 
2389 static void _rtl92ee_phy_path_adda_on(struct ieee80211_hw *hw, u32 *addareg,
2390 				      bool is_patha_on, bool is2t)
2391 {
2392 	u32 i;
2393 
2394 	for (i = 0; i < IQK_ADDA_REG_NUM; i++)
2395 		rtl_set_bbreg(hw, addareg[i], MASKDWORD, 0x0fc01616);
2396 }
2397 
2398 static void _rtl92ee_phy_mac_setting_calibration(struct ieee80211_hw *hw,
2399 						 u32 *macreg, u32 *macbackup)
2400 {
2401 	rtl_set_bbreg(hw, 0x520, 0x00ff0000, 0xff);
2402 }
2403 
2404 static void _rtl92ee_phy_path_a_standby(struct ieee80211_hw *hw)
2405 {
2406 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
2407 	rtl_set_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK, 0x10000);
2408 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
2409 }
2410 
2411 static bool _rtl92ee_phy_simularity_compare(struct ieee80211_hw *hw,
2412 					    long result[][8], u8 c1, u8 c2)
2413 {
2414 	u32 i, j, diff, simularity_bitmap, bound;
2415 
2416 	u8 final_candidate[2] = { 0xFF, 0xFF };
2417 	bool bresult = true/*, is2t = true*/;
2418 	s32 tmp1, tmp2;
2419 
2420 	bound = 8;
2421 
2422 	simularity_bitmap = 0;
2423 
2424 	for (i = 0; i < bound; i++) {
2425 		if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) {
2426 			if ((result[c1][i] & 0x00000200) != 0)
2427 				tmp1 = result[c1][i] | 0xFFFFFC00;
2428 			else
2429 				tmp1 = result[c1][i];
2430 
2431 			if ((result[c2][i] & 0x00000200) != 0)
2432 				tmp2 = result[c2][i] | 0xFFFFFC00;
2433 			else
2434 				tmp2 = result[c2][i];
2435 		} else {
2436 			tmp1 = result[c1][i];
2437 			tmp2 = result[c2][i];
2438 		}
2439 
2440 		diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
2441 
2442 		if (diff > MAX_TOLERANCE) {
2443 			if ((i == 2 || i == 6) && !simularity_bitmap) {
2444 				if (result[c1][i] + result[c1][i + 1] == 0)
2445 					final_candidate[(i / 4)] = c2;
2446 				else if (result[c2][i] + result[c2][i + 1] == 0)
2447 					final_candidate[(i / 4)] = c1;
2448 				else
2449 					simularity_bitmap |= (1 << i);
2450 			} else {
2451 				simularity_bitmap |= (1 << i);
2452 			}
2453 		}
2454 	}
2455 
2456 	if (simularity_bitmap == 0) {
2457 		for (i = 0; i < (bound / 4); i++) {
2458 			if (final_candidate[i] != 0xFF) {
2459 				for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2460 					result[3][j] =
2461 						result[final_candidate[i]][j];
2462 				bresult = false;
2463 			}
2464 		}
2465 		return bresult;
2466 	}
2467 	if (!(simularity_bitmap & 0x03)) {/*path A TX OK*/
2468 		for (i = 0; i < 2; i++)
2469 			result[3][i] = result[c1][i];
2470 	}
2471 	if (!(simularity_bitmap & 0x0c)) {/*path A RX OK*/
2472 		for (i = 2; i < 4; i++)
2473 			result[3][i] = result[c1][i];
2474 	}
2475 	if (!(simularity_bitmap & 0x30)) {/*path B TX OK*/
2476 		for (i = 4; i < 6; i++)
2477 			result[3][i] = result[c1][i];
2478 	}
2479 	if (!(simularity_bitmap & 0xc0)) {/*path B RX OK*/
2480 		for (i = 6; i < 8; i++)
2481 			result[3][i] = result[c1][i];
2482 	}
2483 	return false;
2484 }
2485 
2486 static void _rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw,
2487 				      long result[][8], u8 t, bool is2t)
2488 {
2489 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2490 	struct rtl_phy *rtlphy = &rtlpriv->phy;
2491 	u32 i;
2492 	u8 patha_ok, pathb_ok;
2493 	u8 tmp_0xc50 = (u8)rtl_get_bbreg(hw, 0xc50, MASKBYTE0);
2494 	u8 tmp_0xc58 = (u8)rtl_get_bbreg(hw, 0xc58, MASKBYTE0);
2495 	u32 adda_reg[IQK_ADDA_REG_NUM] = {
2496 		0x85c, 0xe6c, 0xe70, 0xe74,
2497 		0xe78, 0xe7c, 0xe80, 0xe84,
2498 		0xe88, 0xe8c, 0xed0, 0xed4,
2499 		0xed8, 0xedc, 0xee0, 0xeec
2500 	};
2501 	u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
2502 		0x522, 0x550, 0x551, 0x040
2503 	};
2504 	u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2505 		ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR,
2506 		RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c,
2507 		0x870, 0x860,
2508 		0x864, 0x800
2509 	};
2510 	const u32 retrycount = 2;
2511 
2512 	if (t == 0) {
2513 		_rtl92ee_phy_save_adda_registers(hw, adda_reg,
2514 						 rtlphy->adda_backup,
2515 						 IQK_ADDA_REG_NUM);
2516 		_rtl92ee_phy_save_mac_registers(hw, iqk_mac_reg,
2517 						rtlphy->iqk_mac_backup);
2518 		_rtl92ee_phy_save_adda_registers(hw, iqk_bb_reg,
2519 						 rtlphy->iqk_bb_backup,
2520 						 IQK_BB_REG_NUM);
2521 	}
2522 
2523 	_rtl92ee_phy_path_adda_on(hw, adda_reg, true, is2t);
2524 
2525 	/*BB setting*/
2526 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2527 	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
2528 	rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
2529 	rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200);
2530 
2531 	rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(10), 0x01);
2532 	rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(26), 0x01);
2533 	rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 0x01);
2534 	rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 0x01);
2535 
2536 	_rtl92ee_phy_mac_setting_calibration(hw, iqk_mac_reg,
2537 					     rtlphy->iqk_mac_backup);
2538 	/* Page B init*/
2539 	/* IQ calibration setting*/
2540 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2541 	rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
2542 	rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2543 
2544 	for (i = 0 ; i < retrycount ; i++) {
2545 		patha_ok = _rtl92ee_phy_path_a_iqk(hw, is2t);
2546 
2547 		if (patha_ok == 0x01) {
2548 			RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2549 				 "Path A Tx IQK Success!!\n");
2550 			result[t][0] = (rtl_get_bbreg(hw,
2551 						      RTX_POWER_BEFORE_IQK_A,
2552 						      MASKDWORD) & 0x3FF0000)
2553 						      >> 16;
2554 			result[t][1] = (rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A,
2555 						      MASKDWORD) & 0x3FF0000)
2556 						      >> 16;
2557 			break;
2558 		}
2559 		RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2560 			 "Path A Tx IQK Fail!!, ret = 0x%x\n",
2561 			 patha_ok);
2562 	}
2563 
2564 	for (i = 0 ; i < retrycount ; i++) {
2565 		patha_ok = _rtl92ee_phy_path_a_rx_iqk(hw, is2t);
2566 
2567 		if (patha_ok == 0x03) {
2568 			RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2569 				 "Path A Rx IQK Success!!\n");
2570 			result[t][2] = (rtl_get_bbreg(hw,
2571 						      RRX_POWER_BEFORE_IQK_A_2,
2572 						      MASKDWORD) & 0x3FF0000)
2573 						      >> 16;
2574 			result[t][3] = (rtl_get_bbreg(hw,
2575 						      RRX_POWER_AFTER_IQK_A_2,
2576 						      MASKDWORD) & 0x3FF0000)
2577 						      >> 16;
2578 			break;
2579 		}
2580 		RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2581 			 "Path A Rx IQK Fail!!, ret = 0x%x\n",
2582 			  patha_ok);
2583 	}
2584 
2585 	if (0x00 == patha_ok)
2586 		RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2587 			 "Path A IQK failed!!, ret = 0\n");
2588 	if (is2t) {
2589 		_rtl92ee_phy_path_a_standby(hw);
2590 		/* Turn Path B ADDA on */
2591 		_rtl92ee_phy_path_adda_on(hw, adda_reg, false, is2t);
2592 
2593 		/* IQ calibration setting */
2594 		rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
2595 		rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
2596 		rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
2597 
2598 		for (i = 0 ; i < retrycount ; i++) {
2599 			pathb_ok = _rtl92ee_phy_path_b_iqk(hw);
2600 			if (pathb_ok == 0x01) {
2601 				RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2602 					 "Path B Tx IQK Success!!\n");
2603 				result[t][4] = (rtl_get_bbreg(hw,
2604 							RTX_POWER_BEFORE_IQK_B,
2605 							MASKDWORD) & 0x3FF0000)
2606 							>> 16;
2607 				result[t][5] = (rtl_get_bbreg(hw,
2608 							RTX_POWER_AFTER_IQK_B,
2609 							MASKDWORD) & 0x3FF0000)
2610 							>> 16;
2611 				break;
2612 			}
2613 			RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2614 				 "Path B Tx IQK Fail!!, ret = 0x%x\n",
2615 				 pathb_ok);
2616 		}
2617 
2618 		for (i = 0 ; i < retrycount ; i++) {
2619 			pathb_ok = _rtl92ee_phy_path_b_rx_iqk(hw, is2t);
2620 			if (pathb_ok == 0x03) {
2621 				RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2622 					 "Path B Rx IQK Success!!\n");
2623 				result[t][6] = (rtl_get_bbreg(hw,
2624 						       RRX_POWER_BEFORE_IQK_B_2,
2625 						       MASKDWORD) & 0x3FF0000)
2626 						       >> 16;
2627 				result[t][7] = (rtl_get_bbreg(hw,
2628 						       RRX_POWER_AFTER_IQK_B_2,
2629 						       MASKDWORD) & 0x3FF0000)
2630 						       >> 16;
2631 				break;
2632 			}
2633 			RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2634 				 "Path B Rx IQK Fail!!, ret = 0x%x\n",
2635 				 pathb_ok);
2636 		}
2637 
2638 		if (0x00 == pathb_ok)
2639 			RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2640 				 "Path B IQK failed!!, ret = 0\n");
2641 	}
2642 	/* Back to BB mode, load original value */
2643 	RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
2644 		 "IQK:Back to BB mode, load original value!\n");
2645 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0);
2646 
2647 	if (t != 0) {
2648 		/* Reload ADDA power saving parameters */
2649 		_rtl92ee_phy_reload_adda_registers(hw, adda_reg,
2650 						   rtlphy->adda_backup,
2651 						   IQK_ADDA_REG_NUM);
2652 
2653 		/* Reload MAC parameters */
2654 		_rtl92ee_phy_reload_mac_registers(hw, iqk_mac_reg,
2655 						  rtlphy->iqk_mac_backup);
2656 
2657 		_rtl92ee_phy_reload_adda_registers(hw, iqk_bb_reg,
2658 						   rtlphy->iqk_bb_backup,
2659 						   IQK_BB_REG_NUM);
2660 
2661 		/* Restore RX initial gain */
2662 		rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50);
2663 		rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_0xc50);
2664 		if (is2t) {
2665 			rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50);
2666 			rtl_set_bbreg(hw, 0xc58, MASKBYTE0, tmp_0xc58);
2667 		}
2668 
2669 		/* load 0xe30 IQC default value */
2670 		rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00);
2671 		rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00);
2672 	}
2673 }
2674 
2675 static void _rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2676 {
2677 	u8 tmpreg;
2678 	u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
2679 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2680 
2681 	tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2682 
2683 	if ((tmpreg & 0x70) != 0)
2684 		rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2685 	else
2686 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2687 
2688 	if ((tmpreg & 0x70) != 0) {
2689 		rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
2690 
2691 		if (is2t)
2692 			rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
2693 						  MASK12BITS);
2694 
2695 		rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
2696 			      (rf_a_mode & 0x8FFFF) | 0x10000);
2697 
2698 		if (is2t)
2699 			rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
2700 				      (rf_b_mode & 0x8FFFF) | 0x10000);
2701 	}
2702 	lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
2703 
2704 	rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
2705 
2706 	mdelay(100);
2707 
2708 	if ((tmpreg & 0x70) != 0) {
2709 		rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2710 		rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
2711 
2712 		if (is2t)
2713 			rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
2714 				      rf_b_mode);
2715 	} else {
2716 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2717 	}
2718 }
2719 
2720 static void _rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw,
2721 					   bool bmain, bool is2t)
2722 {
2723 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2724 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2725 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2726 
2727 	RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD , "\n");
2728 
2729 	if (is_hal_stop(rtlhal)) {
2730 		u8 u1btmp;
2731 
2732 		u1btmp = rtl_read_byte(rtlpriv, REG_LEDCFG0);
2733 		rtl_write_byte(rtlpriv, REG_LEDCFG0, u1btmp | BIT(7));
2734 		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
2735 	}
2736 	if (is2t) {
2737 		if (bmain)
2738 			rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2739 				      BIT(5) | BIT(6), 0x1);
2740 		else
2741 			rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2742 				      BIT(5) | BIT(6), 0x2);
2743 	} else {
2744 		rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0);
2745 		rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201);
2746 
2747 		/* We use the RF definition of MAIN and AUX,
2748 		 * left antenna and right antenna repectively.
2749 		 * Default output at AUX.
2750 		 */
2751 		if (bmain) {
2752 			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
2753 				      BIT(14) | BIT(13) | BIT(12), 0);
2754 			rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2755 				      BIT(5) | BIT(4) | BIT(3), 0);
2756 			if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
2757 				rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0);
2758 		} else {
2759 			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
2760 				      BIT(14) | BIT(13) | BIT(12), 1);
2761 			rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2762 				      BIT(5) | BIT(4) | BIT(3), 1);
2763 			if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
2764 				rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1);
2765 		}
2766 	}
2767 }
2768 
2769 #undef IQK_ADDA_REG_NUM
2770 #undef IQK_DELAY_TIME
2771 
2772 static u8 rtl92ee_get_rightchnlplace_for_iqk(u8 chnl)
2773 {
2774 	u8 channel_all[59] = {
2775 		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
2776 		36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
2777 		60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
2778 		114, 116, 118, 120, 122, 124, 126, 128,	130,
2779 		132, 134, 136, 138, 140, 149, 151, 153, 155,
2780 		157, 159, 161, 163, 165
2781 	};
2782 	u8 place = chnl;
2783 
2784 	if (chnl > 14) {
2785 		for (place = 14; place < sizeof(channel_all); place++) {
2786 			if (channel_all[place] == chnl)
2787 				return place - 13;
2788 		}
2789 	}
2790 
2791 	return 0;
2792 }
2793 
2794 void rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
2795 {
2796 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2797 	struct rtl_phy *rtlphy = &rtlpriv->phy;
2798 	long result[4][8];
2799 	u8 i, final_candidate;
2800 	bool b_patha_ok, b_pathb_ok;
2801 	long reg_e94, reg_e9c, reg_ea4;
2802 	long reg_eb4, reg_ebc, reg_ec4;
2803 	bool is12simular, is13simular, is23simular;
2804 	u8 idx;
2805 	u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2806 		ROFDM0_XARXIQIMBALANCE,
2807 		ROFDM0_XBRXIQIMBALANCE,
2808 		ROFDM0_ECCATHRESHOLD,
2809 		ROFDM0_AGCRSSITABLE,
2810 		ROFDM0_XATXIQIMBALANCE,
2811 		ROFDM0_XBTXIQIMBALANCE,
2812 		ROFDM0_XCTXAFE,
2813 		ROFDM0_XDTXAFE,
2814 		ROFDM0_RXIQEXTANTA
2815 	};
2816 
2817 	if (b_recovery) {
2818 		_rtl92ee_phy_reload_adda_registers(hw, iqk_bb_reg,
2819 						   rtlphy->iqk_bb_backup, 9);
2820 		return;
2821 	}
2822 
2823 	for (i = 0; i < 8; i++) {
2824 		result[0][i] = 0;
2825 		result[1][i] = 0;
2826 		result[2][i] = 0;
2827 
2828 		if ((i == 0) || (i == 2) || (i == 4)  || (i == 6))
2829 			result[3][i] = 0x100;
2830 		else
2831 			result[3][i] = 0;
2832 	}
2833 	final_candidate = 0xff;
2834 	b_patha_ok = false;
2835 	b_pathb_ok = false;
2836 	is12simular = false;
2837 	is23simular = false;
2838 	is13simular = false;
2839 	for (i = 0; i < 3; i++) {
2840 		_rtl92ee_phy_iq_calibrate(hw, result, i, true);
2841 		if (i == 1) {
2842 			is12simular = _rtl92ee_phy_simularity_compare(hw,
2843 								      result,
2844 								      0, 1);
2845 			if (is12simular) {
2846 				final_candidate = 0;
2847 				break;
2848 			}
2849 		}
2850 
2851 		if (i == 2) {
2852 			is13simular = _rtl92ee_phy_simularity_compare(hw,
2853 								      result,
2854 								      0, 2);
2855 			if (is13simular) {
2856 				final_candidate = 0;
2857 				break;
2858 			}
2859 			is23simular = _rtl92ee_phy_simularity_compare(hw,
2860 								      result,
2861 								      1, 2);
2862 			if (is23simular)
2863 				final_candidate = 1;
2864 			else
2865 				final_candidate = 3;
2866 		}
2867 	}
2868 
2869 	reg_e94 = result[3][0];
2870 	reg_e9c = result[3][1];
2871 	reg_ea4 = result[3][2];
2872 	reg_eb4 = result[3][4];
2873 	reg_ebc = result[3][5];
2874 	reg_ec4 = result[3][6];
2875 
2876 	if (final_candidate != 0xff) {
2877 		reg_e94 = result[final_candidate][0];
2878 		rtlphy->reg_e94 = reg_e94;
2879 		reg_e9c = result[final_candidate][1];
2880 		rtlphy->reg_e9c = reg_e9c;
2881 		reg_ea4 = result[final_candidate][2];
2882 		reg_eb4 = result[final_candidate][4];
2883 		rtlphy->reg_eb4 = reg_eb4;
2884 		reg_ebc = result[final_candidate][5];
2885 		rtlphy->reg_ebc = reg_ebc;
2886 		reg_ec4 = result[final_candidate][6];
2887 		b_patha_ok = true;
2888 		b_pathb_ok = true;
2889 	} else {
2890 		rtlphy->reg_e94 = 0x100;
2891 		rtlphy->reg_eb4 = 0x100;
2892 		rtlphy->reg_e9c = 0x0;
2893 		rtlphy->reg_ebc = 0x0;
2894 	}
2895 
2896 	if (reg_e94 != 0)
2897 		_rtl92ee_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
2898 						    final_candidate,
2899 						    (reg_ea4 == 0));
2900 
2901 	_rtl92ee_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok, result,
2902 					    final_candidate,
2903 					    (reg_ec4 == 0));
2904 
2905 	idx = rtl92ee_get_rightchnlplace_for_iqk(rtlphy->current_channel);
2906 
2907 	/* To Fix BSOD when final_candidate is 0xff */
2908 	if (final_candidate < 4) {
2909 		for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2910 			rtlphy->iqk_matrix[idx].value[0][i] =
2911 				result[final_candidate][i];
2912 
2913 		rtlphy->iqk_matrix[idx].iqk_done = true;
2914 	}
2915 	_rtl92ee_phy_save_adda_registers(hw, iqk_bb_reg,
2916 					 rtlphy->iqk_bb_backup, 9);
2917 }
2918 
2919 void rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw)
2920 {
2921 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2922 	struct rtl_phy *rtlphy = &rtlpriv->phy;
2923 	struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
2924 	u32 timeout = 2000, timecount = 0;
2925 
2926 	while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2927 		udelay(50);
2928 		timecount += 50;
2929 	}
2930 
2931 	rtlphy->lck_inprogress = true;
2932 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
2933 		"LCK:Start!!! currentband %x delay %d ms\n",
2934 		 rtlhal->current_bandtype, timecount);
2935 
2936 	_rtl92ee_phy_lc_calibrate(hw, false);
2937 
2938 	rtlphy->lck_inprogress = false;
2939 }
2940 
2941 void rtl92ee_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
2942 {
2943 }
2944 
2945 void rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
2946 {
2947 	_rtl92ee_phy_set_rfpath_switch(hw, bmain, false);
2948 }
2949 
2950 bool rtl92ee_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2951 {
2952 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2953 	struct rtl_phy *rtlphy = &rtlpriv->phy;
2954 	bool postprocessing = false;
2955 
2956 	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2957 		 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2958 		  iotype, rtlphy->set_io_inprogress);
2959 	do {
2960 		switch (iotype) {
2961 		case IO_CMD_RESUME_DM_BY_SCAN:
2962 			RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2963 				 "[IO CMD] Resume DM after scan.\n");
2964 			postprocessing = true;
2965 			break;
2966 		case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
2967 			RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2968 				 "[IO CMD] Pause DM before scan.\n");
2969 			postprocessing = true;
2970 			break;
2971 		default:
2972 			RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2973 				 "switch case %#x not processed\n", iotype);
2974 			break;
2975 		}
2976 	} while (false);
2977 	if (postprocessing && !rtlphy->set_io_inprogress) {
2978 		rtlphy->set_io_inprogress = true;
2979 		rtlphy->current_io_type = iotype;
2980 	} else {
2981 		return false;
2982 	}
2983 	rtl92ee_phy_set_io(hw);
2984 	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
2985 	return true;
2986 }
2987 
2988 static void rtl92ee_phy_set_io(struct ieee80211_hw *hw)
2989 {
2990 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2991 	struct rtl_phy *rtlphy = &rtlpriv->phy;
2992 	struct dig_t *dm_dig = &rtlpriv->dm_digtable;
2993 
2994 	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2995 		 "--->Cmd(%#x), set_io_inprogress(%d)\n",
2996 		  rtlphy->current_io_type, rtlphy->set_io_inprogress);
2997 	switch (rtlphy->current_io_type) {
2998 	case IO_CMD_RESUME_DM_BY_SCAN:
2999 		rtl92ee_dm_write_dig(hw, rtlphy->initgain_backup.xaagccore1);
3000 		rtl92ee_dm_write_cck_cca_thres(hw, rtlphy->initgain_backup.cca);
3001 		RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE , "no set txpower\n");
3002 		rtl92ee_phy_set_txpower_level(hw, rtlphy->current_channel);
3003 		break;
3004 	case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
3005 		/* 8192eebt */
3006 		rtlphy->initgain_backup.xaagccore1 = dm_dig->cur_igvalue;
3007 		rtl92ee_dm_write_dig(hw, 0x17);
3008 		rtlphy->initgain_backup.cca = dm_dig->cur_cck_cca_thres;
3009 		rtl92ee_dm_write_cck_cca_thres(hw, 0x40);
3010 		break;
3011 	default:
3012 		RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
3013 			 "switch case %#x not processed\n",
3014 			 rtlphy->current_io_type);
3015 		break;
3016 	}
3017 	rtlphy->set_io_inprogress = false;
3018 	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3019 		 "(%#x)\n", rtlphy->current_io_type);
3020 }
3021 
3022 static void rtl92ee_phy_set_rf_on(struct ieee80211_hw *hw)
3023 {
3024 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3025 
3026 	rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
3027 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3028 	/*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);*/
3029 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3030 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3031 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3032 }
3033 
3034 static void _rtl92ee_phy_set_rf_sleep(struct ieee80211_hw *hw)
3035 {
3036 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3037 
3038 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3039 	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3040 
3041 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3042 	rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3043 }
3044 
3045 static bool _rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
3046 					    enum rf_pwrstate rfpwr_state)
3047 {
3048 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3049 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3050 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3051 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3052 	bool bresult = true;
3053 	u8 i, queue_id;
3054 	struct rtl8192_tx_ring *ring = NULL;
3055 
3056 	switch (rfpwr_state) {
3057 	case ERFON:
3058 		if ((ppsc->rfpwr_state == ERFOFF) &&
3059 		    RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3060 			bool rtstatus;
3061 			u32 initializecount = 0;
3062 
3063 			do {
3064 				initializecount++;
3065 				RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3066 					 "IPS Set eRf nic enable\n");
3067 				rtstatus = rtl_ps_enable_nic(hw);
3068 			} while (!rtstatus && (initializecount < 10));
3069 			RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3070 		} else {
3071 			RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3072 				 "Set ERFON sleeping:%d ms\n",
3073 				  jiffies_to_msecs(jiffies -
3074 						   ppsc->last_sleep_jiffies));
3075 			ppsc->last_awake_jiffies = jiffies;
3076 			rtl92ee_phy_set_rf_on(hw);
3077 		}
3078 		if (mac->link_state == MAC80211_LINKED)
3079 			rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK);
3080 		else
3081 			rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK);
3082 		break;
3083 	case ERFOFF:
3084 		for (queue_id = 0, i = 0;
3085 		     queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3086 			ring = &pcipriv->dev.tx_ring[queue_id];
3087 			if (queue_id == BEACON_QUEUE ||
3088 			    skb_queue_len(&ring->queue) == 0) {
3089 				queue_id++;
3090 				continue;
3091 			} else {
3092 				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3093 					 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3094 					 (i + 1), queue_id,
3095 					 skb_queue_len(&ring->queue));
3096 
3097 				udelay(10);
3098 				i++;
3099 			}
3100 			if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3101 				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3102 					 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
3103 					  MAX_DOZE_WAITING_TIMES_9x,
3104 					  queue_id,
3105 					  skb_queue_len(&ring->queue));
3106 				break;
3107 			}
3108 		}
3109 
3110 		if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3111 			RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3112 				 "IPS Set eRf nic disable\n");
3113 			rtl_ps_disable_nic(hw);
3114 			RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3115 		} else {
3116 			if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
3117 				rtlpriv->cfg->ops->led_control(hw,
3118 							LED_CTL_NO_LINK);
3119 			} else {
3120 				rtlpriv->cfg->ops->led_control(hw,
3121 							LED_CTL_POWER_OFF);
3122 			}
3123 		}
3124 		break;
3125 	case ERFSLEEP:
3126 		if (ppsc->rfpwr_state == ERFOFF)
3127 			break;
3128 		for (queue_id = 0, i = 0;
3129 		     queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3130 			ring = &pcipriv->dev.tx_ring[queue_id];
3131 			if (skb_queue_len(&ring->queue) == 0) {
3132 				queue_id++;
3133 				continue;
3134 			} else {
3135 				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3136 					 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3137 					 (i + 1), queue_id,
3138 					 skb_queue_len(&ring->queue));
3139 				udelay(10);
3140 				i++;
3141 			}
3142 			if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3143 				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3144 					 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
3145 					  MAX_DOZE_WAITING_TIMES_9x,
3146 					  queue_id,
3147 					  skb_queue_len(&ring->queue));
3148 				break;
3149 			}
3150 		}
3151 		RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3152 			 "Set ERFSLEEP awaked:%d ms\n",
3153 			  jiffies_to_msecs(jiffies -
3154 					   ppsc->last_awake_jiffies));
3155 		ppsc->last_sleep_jiffies = jiffies;
3156 		_rtl92ee_phy_set_rf_sleep(hw);
3157 		break;
3158 	default:
3159 		RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
3160 			 "switch case %#x not processed\n", rfpwr_state);
3161 		bresult = false;
3162 		break;
3163 	}
3164 	if (bresult)
3165 		ppsc->rfpwr_state = rfpwr_state;
3166 	return bresult;
3167 }
3168 
3169 bool rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
3170 				    enum rf_pwrstate rfpwr_state)
3171 {
3172 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3173 
3174 	bool bresult = false;
3175 
3176 	if (rfpwr_state == ppsc->rfpwr_state)
3177 		return bresult;
3178 	bresult = _rtl92ee_phy_set_rf_power_state(hw, rfpwr_state);
3179 	return bresult;
3180 }
3181