1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2014 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../regd.h" 30 #include "../cam.h" 31 #include "../ps.h" 32 #include "../pci.h" 33 #include "reg.h" 34 #include "def.h" 35 #include "phy.h" 36 #include "dm.h" 37 #include "fw.h" 38 #include "led.h" 39 #include "hw.h" 40 #include "../pwrseqcmd.h" 41 #include "pwrseq.h" 42 43 #define LLT_CONFIG 5 44 45 static void _rtl92ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 46 u8 set_bits, u8 clear_bits) 47 { 48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 49 struct rtl_priv *rtlpriv = rtl_priv(hw); 50 51 rtlpci->reg_bcn_ctrl_val |= set_bits; 52 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 53 54 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 55 } 56 57 static void _rtl92ee_stop_tx_beacon(struct ieee80211_hw *hw) 58 { 59 struct rtl_priv *rtlpriv = rtl_priv(hw); 60 u8 tmp; 61 62 tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 63 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp & (~BIT(6))); 64 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 65 tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 66 tmp &= ~(BIT(0)); 67 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp); 68 } 69 70 static void _rtl92ee_resume_tx_beacon(struct ieee80211_hw *hw) 71 { 72 struct rtl_priv *rtlpriv = rtl_priv(hw); 73 u8 tmp; 74 75 tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 76 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp | BIT(6)); 77 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 78 tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 79 tmp |= BIT(0); 80 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp); 81 } 82 83 static void _rtl92ee_enable_bcn_sub_func(struct ieee80211_hw *hw) 84 { 85 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(1)); 86 } 87 88 static void _rtl92ee_disable_bcn_sub_func(struct ieee80211_hw *hw) 89 { 90 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(1), 0); 91 } 92 93 static void _rtl92ee_set_fw_clock_on(struct ieee80211_hw *hw, 94 u8 rpwm_val, bool b_need_turn_off_ckk) 95 { 96 struct rtl_priv *rtlpriv = rtl_priv(hw); 97 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 98 bool b_support_remote_wake_up; 99 u32 count = 0, isr_regaddr, content; 100 bool b_schedule_timer = b_need_turn_off_ckk; 101 102 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 103 (u8 *)(&b_support_remote_wake_up)); 104 105 if (!rtlhal->fw_ready) 106 return; 107 if (!rtlpriv->psc.fw_current_inpsmode) 108 return; 109 110 while (1) { 111 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 112 if (rtlhal->fw_clk_change_in_progress) { 113 while (rtlhal->fw_clk_change_in_progress) { 114 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 115 count++; 116 udelay(100); 117 if (count > 1000) 118 return; 119 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 120 } 121 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 122 } else { 123 rtlhal->fw_clk_change_in_progress = false; 124 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 125 break; 126 } 127 } 128 129 if (IS_IN_LOW_POWER_STATE_92E(rtlhal->fw_ps_state)) { 130 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, 131 (u8 *)(&rpwm_val)); 132 if (FW_PS_IS_ACK(rpwm_val)) { 133 isr_regaddr = REG_HISR; 134 content = rtl_read_dword(rtlpriv, isr_regaddr); 135 while (!(content & IMR_CPWM) && (count < 500)) { 136 udelay(50); 137 count++; 138 content = rtl_read_dword(rtlpriv, isr_regaddr); 139 } 140 141 if (content & IMR_CPWM) { 142 rtl_write_word(rtlpriv, isr_regaddr, 0x0100); 143 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_92E; 144 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 145 "Receive CPWM INT!!! PSState = %X\n", 146 rtlhal->fw_ps_state); 147 } 148 } 149 150 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 151 rtlhal->fw_clk_change_in_progress = false; 152 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 153 if (b_schedule_timer) { 154 mod_timer(&rtlpriv->works.fw_clockoff_timer, 155 jiffies + MSECS(10)); 156 } 157 } else { 158 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 159 rtlhal->fw_clk_change_in_progress = false; 160 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 161 } 162 } 163 164 static void _rtl92ee_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val) 165 { 166 struct rtl_priv *rtlpriv = rtl_priv(hw); 167 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 168 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 169 struct rtl8192_tx_ring *ring; 170 enum rf_pwrstate rtstate; 171 bool b_schedule_timer = false; 172 u8 queue; 173 174 if (!rtlhal->fw_ready) 175 return; 176 if (!rtlpriv->psc.fw_current_inpsmode) 177 return; 178 if (!rtlhal->allow_sw_to_change_hwclc) 179 return; 180 181 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate)); 182 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF) 183 return; 184 185 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) { 186 ring = &rtlpci->tx_ring[queue]; 187 if (skb_queue_len(&ring->queue)) { 188 b_schedule_timer = true; 189 break; 190 } 191 } 192 193 if (b_schedule_timer) { 194 mod_timer(&rtlpriv->works.fw_clockoff_timer, 195 jiffies + MSECS(10)); 196 return; 197 } 198 199 if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) { 200 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 201 if (!rtlhal->fw_clk_change_in_progress) { 202 rtlhal->fw_clk_change_in_progress = true; 203 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 204 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val); 205 rtl_write_word(rtlpriv, REG_HISR, 0x0100); 206 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 207 (u8 *)(&rpwm_val)); 208 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 209 rtlhal->fw_clk_change_in_progress = false; 210 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 211 } else { 212 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 213 mod_timer(&rtlpriv->works.fw_clockoff_timer, 214 jiffies + MSECS(10)); 215 } 216 } 217 } 218 219 static void _rtl92ee_set_fw_ps_rf_on(struct ieee80211_hw *hw) 220 { 221 u8 rpwm_val = 0; 222 223 rpwm_val |= (FW_PS_STATE_RF_OFF_92E | FW_PS_ACK); 224 _rtl92ee_set_fw_clock_on(hw, rpwm_val, true); 225 } 226 227 static void _rtl92ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw) 228 { 229 u8 rpwm_val = 0; 230 231 rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR; 232 _rtl92ee_set_fw_clock_off(hw, rpwm_val); 233 } 234 235 void rtl92ee_fw_clk_off_timer_callback(unsigned long data) 236 { 237 struct ieee80211_hw *hw = (struct ieee80211_hw *)data; 238 239 _rtl92ee_set_fw_ps_rf_off_low_power(hw); 240 } 241 242 static void _rtl92ee_fwlps_leave(struct ieee80211_hw *hw) 243 { 244 struct rtl_priv *rtlpriv = rtl_priv(hw); 245 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 246 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 247 bool fw_current_inps = false; 248 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE; 249 250 if (ppsc->low_power_enable) { 251 rpwm_val = (FW_PS_STATE_ALL_ON_92E | FW_PS_ACK);/* RF on */ 252 _rtl92ee_set_fw_clock_on(hw, rpwm_val, false); 253 rtlhal->allow_sw_to_change_hwclc = false; 254 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 255 (u8 *)(&fw_pwrmode)); 256 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 257 (u8 *)(&fw_current_inps)); 258 } else { 259 rpwm_val = FW_PS_STATE_ALL_ON_92E; /* RF on */ 260 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 261 (u8 *)(&rpwm_val)); 262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 263 (u8 *)(&fw_pwrmode)); 264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 265 (u8 *)(&fw_current_inps)); 266 } 267 } 268 269 static void _rtl92ee_fwlps_enter(struct ieee80211_hw *hw) 270 { 271 struct rtl_priv *rtlpriv = rtl_priv(hw); 272 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 273 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 274 bool fw_current_inps = true; 275 u8 rpwm_val; 276 277 if (ppsc->low_power_enable) { 278 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR; /* RF off */ 279 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 280 (u8 *)(&fw_current_inps)); 281 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 282 (u8 *)(&ppsc->fwctrl_psmode)); 283 rtlhal->allow_sw_to_change_hwclc = true; 284 _rtl92ee_set_fw_clock_off(hw, rpwm_val); 285 } else { 286 rpwm_val = FW_PS_STATE_RF_OFF_92E; /* RF off */ 287 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 288 (u8 *)(&fw_current_inps)); 289 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 290 (u8 *)(&ppsc->fwctrl_psmode)); 291 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 292 (u8 *)(&rpwm_val)); 293 } 294 } 295 296 void rtl92ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 297 { 298 struct rtl_priv *rtlpriv = rtl_priv(hw); 299 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 300 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 301 302 switch (variable) { 303 case HW_VAR_RCR: 304 *((u32 *)(val)) = rtlpci->receive_config; 305 break; 306 case HW_VAR_RF_STATE: 307 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 308 break; 309 case HW_VAR_FWLPS_RF_ON:{ 310 enum rf_pwrstate rfstate; 311 u32 val_rcr; 312 313 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, 314 (u8 *)(&rfstate)); 315 if (rfstate == ERFOFF) { 316 *((bool *)(val)) = true; 317 } else { 318 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 319 val_rcr &= 0x00070000; 320 if (val_rcr) 321 *((bool *)(val)) = false; 322 else 323 *((bool *)(val)) = true; 324 } 325 } 326 break; 327 case HW_VAR_FW_PSMODE_STATUS: 328 *((bool *)(val)) = ppsc->fw_current_inpsmode; 329 break; 330 case HW_VAR_CORRECT_TSF:{ 331 u64 tsf; 332 u32 *ptsf_low = (u32 *)&tsf; 333 u32 *ptsf_high = ((u32 *)&tsf) + 1; 334 335 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 336 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 337 338 *((u64 *)(val)) = tsf; 339 } 340 break; 341 case HAL_DEF_WOWLAN: 342 break; 343 default: 344 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, 345 "switch case %#x not processed\n", variable); 346 break; 347 } 348 } 349 350 static void _rtl92ee_download_rsvd_page(struct ieee80211_hw *hw) 351 { 352 struct rtl_priv *rtlpriv = rtl_priv(hw); 353 u8 tmp_regcr, tmp_reg422; 354 u8 bcnvalid_reg, txbc_reg; 355 u8 count = 0, dlbcn_count = 0; 356 bool b_recover = false; 357 358 /*Set REG_CR bit 8. DMA beacon by SW.*/ 359 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 360 rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr | BIT(0)); 361 362 /* Disable Hw protection for a time which revserd for Hw sending beacon. 363 * Fix download reserved page packet fail 364 * that access collision with the protection time. 365 * 2010.05.11. Added by tynli. 366 */ 367 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); 368 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0); 369 370 /* Set FWHW_TXQ_CTRL 0x422[6]=0 to 371 * tell Hw the packet is not a real beacon frame. 372 */ 373 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 374 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6))); 375 376 if (tmp_reg422 & BIT(6)) 377 b_recover = true; 378 379 do { 380 /* Clear beacon valid check bit */ 381 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2); 382 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2, 383 bcnvalid_reg | BIT(0)); 384 385 /* download rsvd page */ 386 rtl92ee_set_fw_rsvdpagepkt(hw, false); 387 388 txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3); 389 count = 0; 390 while ((txbc_reg & BIT(4)) && count < 20) { 391 count++; 392 udelay(10); 393 txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3); 394 } 395 rtl_write_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3, 396 txbc_reg | BIT(4)); 397 398 /* check rsvd page download OK. */ 399 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2); 400 count = 0; 401 while (!(bcnvalid_reg & BIT(0)) && count < 20) { 402 count++; 403 udelay(50); 404 bcnvalid_reg = rtl_read_byte(rtlpriv, 405 REG_DWBCN0_CTRL + 2); 406 } 407 408 if (bcnvalid_reg & BIT(0)) 409 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2, BIT(0)); 410 411 dlbcn_count++; 412 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); 413 414 if (!(bcnvalid_reg & BIT(0))) 415 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 416 "Download RSVD page failed!\n"); 417 418 /* Enable Bcn */ 419 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0); 420 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); 421 422 if (b_recover) 423 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422); 424 425 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 426 rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr & (~BIT(0))); 427 } 428 429 void rtl92ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 430 { 431 struct rtl_priv *rtlpriv = rtl_priv(hw); 432 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 433 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 434 struct rtl_efuse *efuse = rtl_efuse(rtl_priv(hw)); 435 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 436 u8 idx; 437 438 switch (variable) { 439 case HW_VAR_ETHER_ADDR: 440 for (idx = 0; idx < ETH_ALEN; idx++) 441 rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]); 442 break; 443 case HW_VAR_BASIC_RATE:{ 444 u16 b_rate_cfg = ((u16 *)val)[0]; 445 446 b_rate_cfg = b_rate_cfg & 0x15f; 447 b_rate_cfg |= 0x01; 448 b_rate_cfg = (b_rate_cfg | 0xd) & (~BIT(1)); 449 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff); 450 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff); 451 break; } 452 case HW_VAR_BSSID: 453 for (idx = 0; idx < ETH_ALEN; idx++) 454 rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]); 455 break; 456 case HW_VAR_SIFS: 457 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 458 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); 459 460 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 461 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 462 463 if (!mac->ht_enable) 464 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e); 465 else 466 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 467 *((u16 *)val)); 468 break; 469 case HW_VAR_SLOT_TIME:{ 470 u8 e_aci; 471 472 RT_TRACE(rtlpriv, COMP_MLME, DBG_TRACE, 473 "HW_VAR_SLOT_TIME %x\n", val[0]); 474 475 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 476 477 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 478 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, 479 (u8 *)(&e_aci)); 480 } 481 break; } 482 case HW_VAR_ACK_PREAMBLE:{ 483 u8 reg_tmp; 484 u8 short_preamble = (bool)(*(u8 *)val); 485 486 reg_tmp = (rtlpriv->mac80211.cur_40_prime_sc) << 5; 487 if (short_preamble) 488 reg_tmp |= 0x80; 489 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 490 rtlpriv->mac80211.short_preamble = short_preamble; 491 } 492 break; 493 case HW_VAR_WPA_CONFIG: 494 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val)); 495 break; 496 case HW_VAR_AMPDU_FACTOR:{ 497 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 }; 498 u8 fac; 499 u8 *reg = NULL; 500 u8 i = 0; 501 502 reg = regtoset_normal; 503 504 fac = *((u8 *)val); 505 if (fac <= 3) { 506 fac = (1 << (fac + 2)); 507 if (fac > 0xf) 508 fac = 0xf; 509 for (i = 0; i < 4; i++) { 510 if ((reg[i] & 0xf0) > (fac << 4)) 511 reg[i] = (reg[i] & 0x0f) | 512 (fac << 4); 513 if ((reg[i] & 0x0f) > fac) 514 reg[i] = (reg[i] & 0xf0) | fac; 515 rtl_write_byte(rtlpriv, 516 (REG_AGGLEN_LMT + i), 517 reg[i]); 518 } 519 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 520 "Set HW_VAR_AMPDU_FACTOR:%#x\n", fac); 521 } 522 } 523 break; 524 case HW_VAR_AC_PARAM:{ 525 u8 e_aci = *((u8 *)val); 526 527 if (rtlpci->acm_method != EACMWAY2_SW) 528 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL, 529 (u8 *)(&e_aci)); 530 } 531 break; 532 case HW_VAR_ACM_CTRL:{ 533 u8 e_aci = *((u8 *)val); 534 union aci_aifsn *aifs = (union aci_aifsn *)(&mac->ac[0].aifs); 535 536 u8 acm = aifs->f.acm; 537 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 538 539 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 540 541 if (acm) { 542 switch (e_aci) { 543 case AC0_BE: 544 acm_ctrl |= ACMHW_BEQEN; 545 break; 546 case AC2_VI: 547 acm_ctrl |= ACMHW_VIQEN; 548 break; 549 case AC3_VO: 550 acm_ctrl |= ACMHW_VOQEN; 551 break; 552 default: 553 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 554 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 555 acm); 556 break; 557 } 558 } else { 559 switch (e_aci) { 560 case AC0_BE: 561 acm_ctrl &= (~ACMHW_BEQEN); 562 break; 563 case AC2_VI: 564 acm_ctrl &= (~ACMHW_VIQEN); 565 break; 566 case AC3_VO: 567 acm_ctrl &= (~ACMHW_VOQEN); 568 break; 569 default: 570 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, 571 "switch case %#x not processed\n", 572 e_aci); 573 break; 574 } 575 } 576 577 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 578 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 579 acm_ctrl); 580 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 581 } 582 break; 583 case HW_VAR_RCR:{ 584 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); 585 rtlpci->receive_config = ((u32 *)(val))[0]; 586 } 587 break; 588 case HW_VAR_RETRY_LIMIT:{ 589 u8 retry_limit = ((u8 *)(val))[0]; 590 591 rtl_write_word(rtlpriv, REG_RETRY_LIMIT, 592 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 593 retry_limit << RETRY_LIMIT_LONG_SHIFT); 594 } 595 break; 596 case HW_VAR_DUAL_TSF_RST: 597 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 598 break; 599 case HW_VAR_EFUSE_BYTES: 600 efuse->efuse_usedbytes = *((u16 *)val); 601 break; 602 case HW_VAR_EFUSE_USAGE: 603 efuse->efuse_usedpercentage = *((u8 *)val); 604 break; 605 case HW_VAR_IO_CMD: 606 rtl92ee_phy_set_io_cmd(hw, (*(enum io_type *)val)); 607 break; 608 case HW_VAR_SET_RPWM:{ 609 u8 rpwm_val; 610 611 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 612 udelay(1); 613 614 if (rpwm_val & BIT(7)) { 615 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val)); 616 } else { 617 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 618 ((*(u8 *)val) | BIT(7))); 619 } 620 } 621 break; 622 case HW_VAR_H2C_FW_PWRMODE: 623 rtl92ee_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); 624 break; 625 case HW_VAR_FW_PSMODE_STATUS: 626 ppsc->fw_current_inpsmode = *((bool *)val); 627 break; 628 case HW_VAR_RESUME_CLK_ON: 629 _rtl92ee_set_fw_ps_rf_on(hw); 630 break; 631 case HW_VAR_FW_LPS_ACTION:{ 632 bool b_enter_fwlps = *((bool *)val); 633 634 if (b_enter_fwlps) 635 _rtl92ee_fwlps_enter(hw); 636 else 637 _rtl92ee_fwlps_leave(hw); 638 } 639 break; 640 case HW_VAR_H2C_FW_JOINBSSRPT:{ 641 u8 mstatus = (*(u8 *)val); 642 643 if (mstatus == RT_MEDIA_CONNECT) { 644 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL); 645 _rtl92ee_download_rsvd_page(hw); 646 } 647 rtl92ee_set_fw_media_status_rpt_cmd(hw, mstatus); 648 } 649 break; 650 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: 651 rtl92ee_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); 652 break; 653 case HW_VAR_AID:{ 654 u16 u2btmp; 655 656 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 657 u2btmp &= 0xC000; 658 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, 659 (u2btmp | mac->assoc_id)); 660 } 661 break; 662 case HW_VAR_CORRECT_TSF:{ 663 u8 btype_ibss = ((u8 *)(val))[0]; 664 665 if (btype_ibss) 666 _rtl92ee_stop_tx_beacon(hw); 667 668 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); 669 670 rtl_write_dword(rtlpriv, REG_TSFTR, 671 (u32)(mac->tsf & 0xffffffff)); 672 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 673 (u32)((mac->tsf >> 32) & 0xffffffff)); 674 675 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0); 676 677 if (btype_ibss) 678 _rtl92ee_resume_tx_beacon(hw); 679 } 680 break; 681 case HW_VAR_KEEP_ALIVE: { 682 u8 array[2]; 683 684 array[0] = 0xff; 685 array[1] = *((u8 *)val); 686 rtl92ee_fill_h2c_cmd(hw, H2C_92E_KEEP_ALIVE_CTRL, 2, array); 687 } 688 break; 689 default: 690 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, 691 "switch case %#x not processed\n", variable); 692 break; 693 } 694 } 695 696 static bool _rtl92ee_llt_table_init(struct ieee80211_hw *hw) 697 { 698 struct rtl_priv *rtlpriv = rtl_priv(hw); 699 u8 txpktbuf_bndy; 700 u8 u8tmp, testcnt = 0; 701 702 txpktbuf_bndy = 0xF7; 703 704 rtl_write_dword(rtlpriv, REG_RQPN, 0x80E60808); 705 706 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy); 707 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x3d00 - 1); 708 709 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 1, txpktbuf_bndy); 710 rtl_write_byte(rtlpriv, REG_DWBCN1_CTRL + 1, txpktbuf_bndy); 711 712 rtl_write_byte(rtlpriv, REG_BCNQ_BDNY, txpktbuf_bndy); 713 rtl_write_byte(rtlpriv, REG_BCNQ1_BDNY, txpktbuf_bndy); 714 715 rtl_write_byte(rtlpriv, REG_MGQ_BDNY, txpktbuf_bndy); 716 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); 717 718 rtl_write_byte(rtlpriv, REG_PBP, 0x31); 719 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 720 721 u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2); 722 rtl_write_byte(rtlpriv, REG_AUTO_LLT + 2, u8tmp | BIT(0)); 723 724 while (u8tmp & BIT(0)) { 725 u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2); 726 udelay(10); 727 testcnt++; 728 if (testcnt > 10) 729 break; 730 } 731 732 return true; 733 } 734 735 static void _rtl92ee_gen_refresh_led_state(struct ieee80211_hw *hw) 736 { 737 struct rtl_priv *rtlpriv = rtl_priv(hw); 738 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 739 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0; 740 741 if (rtlpriv->rtlhal.up_first_time) 742 return; 743 744 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 745 rtl92ee_sw_led_on(hw, pled0); 746 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 747 rtl92ee_sw_led_on(hw, pled0); 748 else 749 rtl92ee_sw_led_off(hw, pled0); 750 } 751 752 static bool _rtl92ee_init_mac(struct ieee80211_hw *hw) 753 { 754 struct rtl_priv *rtlpriv = rtl_priv(hw); 755 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 756 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 757 758 u8 bytetmp; 759 u16 wordtmp; 760 u32 dwordtmp; 761 762 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); 763 764 dwordtmp = rtl_read_dword(rtlpriv, REG_SYS_CFG1); 765 if (dwordtmp & BIT(24)) { 766 rtl_write_byte(rtlpriv, 0x7c, 0xc3); 767 } else { 768 bytetmp = rtl_read_byte(rtlpriv, 0x16); 769 rtl_write_byte(rtlpriv, 0x16, bytetmp | BIT(4) | BIT(6)); 770 rtl_write_byte(rtlpriv, 0x7c, 0x83); 771 } 772 /* 1. 40Mhz crystal source*/ 773 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2); 774 bytetmp &= 0xfb; 775 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp); 776 777 dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4); 778 dwordtmp &= 0xfffffc7f; 779 rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp); 780 781 /* 2. 92E AFE parameter 782 * MP chip then check version 783 */ 784 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2); 785 bytetmp &= 0xbf; 786 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp); 787 788 dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4); 789 dwordtmp &= 0xffdfffff; 790 rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp); 791 792 /* HW Power on sequence */ 793 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 794 PWR_INTF_PCI_MSK, 795 RTL8192E_NIC_ENABLE_FLOW)) { 796 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 797 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n"); 798 return false; 799 } 800 801 /* Release MAC IO register reset */ 802 bytetmp = rtl_read_byte(rtlpriv, REG_CR); 803 bytetmp = 0xff; 804 rtl_write_byte(rtlpriv, REG_CR, bytetmp); 805 mdelay(2); 806 bytetmp = 0x7f; 807 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp); 808 mdelay(2); 809 810 /* Add for wakeup online */ 811 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR); 812 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3)); 813 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1); 814 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4))); 815 /* Release MAC IO register reset */ 816 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 817 818 if (!rtlhal->mac_func_enable) { 819 if (_rtl92ee_llt_table_init(hw) == false) { 820 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 821 "LLT table init fail\n"); 822 return false; 823 } 824 } 825 826 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 827 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff); 828 829 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 830 wordtmp &= 0xf; 831 wordtmp |= 0xF5B1; 832 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 833 /* Reported Tx status from HW for rate adaptive.*/ 834 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 835 836 /* Set RCR register */ 837 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 838 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff); 839 840 /* Set TCR register */ 841 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); 842 843 /* Set TX/RX descriptor physical address -- HI part */ 844 if (!rtlpriv->cfg->mod_params->dma64) 845 goto dma64_end; 846 847 rtl_write_dword(rtlpriv, REG_BCNQ_DESA + 4, 848 ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) >> 849 32); 850 rtl_write_dword(rtlpriv, REG_MGQ_DESA + 4, 851 (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma >> 32); 852 rtl_write_dword(rtlpriv, REG_VOQ_DESA + 4, 853 (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma >> 32); 854 rtl_write_dword(rtlpriv, REG_VIQ_DESA + 4, 855 (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma >> 32); 856 rtl_write_dword(rtlpriv, REG_BEQ_DESA + 4, 857 (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma >> 32); 858 rtl_write_dword(rtlpriv, REG_BKQ_DESA + 4, 859 (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma >> 32); 860 rtl_write_dword(rtlpriv, REG_HQ0_DESA + 4, 861 (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma >> 32); 862 863 rtl_write_dword(rtlpriv, REG_RX_DESA + 4, 864 (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma >> 32); 865 866 dma64_end: 867 868 /* Set TX/RX descriptor physical address(from OS API). */ 869 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 870 ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) & 871 DMA_BIT_MASK(32)); 872 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 873 (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma & 874 DMA_BIT_MASK(32)); 875 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 876 (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma & 877 DMA_BIT_MASK(32)); 878 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 879 (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma & 880 DMA_BIT_MASK(32)); 881 882 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 883 (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma & 884 DMA_BIT_MASK(32)); 885 886 dwordtmp = rtl_read_dword(rtlpriv, REG_BEQ_DESA); 887 888 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 889 (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma & 890 DMA_BIT_MASK(32)); 891 rtl_write_dword(rtlpriv, REG_HQ0_DESA, 892 (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma & 893 DMA_BIT_MASK(32)); 894 895 rtl_write_dword(rtlpriv, REG_RX_DESA, 896 (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma & 897 DMA_BIT_MASK(32)); 898 899 /* if we want to support 64 bit DMA, we should set it here, 900 * but now we do not support 64 bit DMA 901 */ 902 903 rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0x3fffffff); 904 905 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3); 906 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0xF7); 907 908 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 909 910 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); 911 912 rtl_write_word(rtlpriv, REG_MGQ_TXBD_NUM, 913 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 914 rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM, 915 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 916 rtl_write_word(rtlpriv, REG_VIQ_TXBD_NUM, 917 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 918 rtl_write_word(rtlpriv, REG_BEQ_TXBD_NUM, 919 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 920 rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM, 921 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 922 rtl_write_word(rtlpriv, REG_BKQ_TXBD_NUM, 923 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 924 rtl_write_word(rtlpriv, REG_HI0Q_TXBD_NUM, 925 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 926 rtl_write_word(rtlpriv, REG_HI1Q_TXBD_NUM, 927 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 928 rtl_write_word(rtlpriv, REG_HI2Q_TXBD_NUM, 929 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 930 rtl_write_word(rtlpriv, REG_HI3Q_TXBD_NUM, 931 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 932 rtl_write_word(rtlpriv, REG_HI4Q_TXBD_NUM, 933 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 934 rtl_write_word(rtlpriv, REG_HI5Q_TXBD_NUM, 935 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 936 rtl_write_word(rtlpriv, REG_HI6Q_TXBD_NUM, 937 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 938 rtl_write_word(rtlpriv, REG_HI7Q_TXBD_NUM, 939 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 940 /*Rx*/ 941 rtl_write_word(rtlpriv, REG_RX_RXBD_NUM, 942 RX_DESC_NUM_92E | 943 ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x8000); 944 945 rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0XFFFFFFFF); 946 947 _rtl92ee_gen_refresh_led_state(hw); 948 return true; 949 } 950 951 static void _rtl92ee_hw_configure(struct ieee80211_hw *hw) 952 { 953 struct rtl_priv *rtlpriv = rtl_priv(hw); 954 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 955 u32 reg_rrsr; 956 957 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 958 /* Init value for RRSR. */ 959 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr); 960 961 /* ARFB table 9 for 11ac 5G 2SS */ 962 rtl_write_dword(rtlpriv, REG_ARFR0, 0x00000010); 963 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0x3e0ff000); 964 965 /* ARFB table 10 for 11ac 5G 1SS */ 966 rtl_write_dword(rtlpriv, REG_ARFR1, 0x00000010); 967 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x000ff000); 968 969 /* Set SLOT time */ 970 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 971 972 /* CF-End setting. */ 973 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); 974 975 /* Set retry limit */ 976 rtl_write_word(rtlpriv, REG_RETRY_LIMIT, 0x0707); 977 978 /* BAR settings */ 979 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x0201ffff); 980 981 /* Set Data / Response auto rate fallack retry count */ 982 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 983 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 984 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 985 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 986 987 /* Beacon related, for rate adaptive */ 988 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); 989 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); 990 991 rtlpci->reg_bcn_ctrl_val = 0x1d; 992 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 993 994 /* Marked out by Bruce, 2010-09-09. 995 * This register is configured for the 2nd Beacon (multiple BSSID). 996 * We shall disable this register if we only support 1 BSSID. 997 * vivi guess 92d also need this, also 92d now doesnot set this reg 998 */ 999 rtl_write_byte(rtlpriv, REG_BCN_CTRL_1, 0); 1000 1001 /* TBTT prohibit hold time. Suggested by designer TimChen. */ 1002 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */ 1003 1004 rtl_write_byte(rtlpriv, REG_PIFS, 0); 1005 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 1006 1007 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); 1008 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x08ff); 1009 1010 /* For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/ 1011 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); 1012 1013 /* ACKTO for IOT issue. */ 1014 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); 1015 1016 /* Set Spec SIFS (used in NAV) */ 1017 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x100a); 1018 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x100a); 1019 1020 /* Set SIFS for CCK */ 1021 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x100a); 1022 1023 /* Set SIFS for OFDM */ 1024 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x100a); 1025 1026 /* Note Data sheet don't define */ 1027 rtl_write_byte(rtlpriv, 0x4C7, 0x80); 1028 1029 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20); 1030 1031 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1717); 1032 1033 /* Set Multicast Address. 2009.01.07. by tynli. */ 1034 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); 1035 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); 1036 } 1037 1038 static void _rtl92ee_enable_aspm_back_door(struct ieee80211_hw *hw) 1039 { 1040 struct rtl_priv *rtlpriv = rtl_priv(hw); 1041 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1042 u32 tmp32 = 0, count = 0; 1043 u8 tmp8 = 0; 1044 1045 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x78); 1046 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2); 1047 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1048 count = 0; 1049 while (tmp8 && count < 20) { 1050 udelay(10); 1051 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1052 count++; 1053 } 1054 1055 if (0 == tmp8) { 1056 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA); 1057 if ((tmp32 & 0xff00) != 0x2000) { 1058 tmp32 &= 0xffff00ff; 1059 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA, 1060 tmp32 | BIT(13)); 1061 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf078); 1062 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1); 1063 1064 tmp8 = rtl_read_byte(rtlpriv, 1065 REG_BACKDOOR_DBI_DATA + 2); 1066 count = 0; 1067 while (tmp8 && count < 20) { 1068 udelay(10); 1069 tmp8 = rtl_read_byte(rtlpriv, 1070 REG_BACKDOOR_DBI_DATA + 2); 1071 count++; 1072 } 1073 } 1074 } 1075 1076 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x70c); 1077 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2); 1078 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1079 count = 0; 1080 while (tmp8 && count < 20) { 1081 udelay(10); 1082 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1083 count++; 1084 } 1085 if (0 == tmp8) { 1086 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA); 1087 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA, 1088 tmp32 | BIT(31)); 1089 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf70c); 1090 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1); 1091 } 1092 1093 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1094 count = 0; 1095 while (tmp8 && count < 20) { 1096 udelay(10); 1097 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1098 count++; 1099 } 1100 1101 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x718); 1102 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2); 1103 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1104 count = 0; 1105 while (tmp8 && count < 20) { 1106 udelay(10); 1107 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1108 count++; 1109 } 1110 if (ppsc->support_backdoor || (0 == tmp8)) { 1111 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA); 1112 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA, 1113 tmp32 | BIT(11) | BIT(12)); 1114 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf718); 1115 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1); 1116 } 1117 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1118 count = 0; 1119 while (tmp8 && count < 20) { 1120 udelay(10); 1121 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1122 count++; 1123 } 1124 } 1125 1126 void rtl92ee_enable_hw_security_config(struct ieee80211_hw *hw) 1127 { 1128 struct rtl_priv *rtlpriv = rtl_priv(hw); 1129 u8 sec_reg_value; 1130 u8 tmp; 1131 1132 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1133 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 1134 rtlpriv->sec.pairwise_enc_algorithm, 1135 rtlpriv->sec.group_enc_algorithm); 1136 1137 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 1138 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 1139 "not open hw encryption\n"); 1140 return; 1141 } 1142 1143 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE; 1144 1145 if (rtlpriv->sec.use_defaultkey) { 1146 sec_reg_value |= SCR_TXUSEDK; 1147 sec_reg_value |= SCR_RXUSEDK; 1148 } 1149 1150 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 1151 1152 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1153 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1)); 1154 1155 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 1156 "The SECR-value %x\n", sec_reg_value); 1157 1158 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 1159 } 1160 1161 static bool _rtl8192ee_check_pcie_dma_hang(struct rtl_priv *rtlpriv) 1162 { 1163 u8 tmp; 1164 1165 /* write reg 0x350 Bit[26]=1. Enable debug port. */ 1166 tmp = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3); 1167 if (!(tmp & BIT(2))) { 1168 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3, 1169 tmp | BIT(2)); 1170 mdelay(100); /* Suggested by DD Justin_tsai. */ 1171 } 1172 1173 /* read reg 0x350 Bit[25] if 1 : RX hang 1174 * read reg 0x350 Bit[24] if 1 : TX hang 1175 */ 1176 tmp = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3); 1177 if ((tmp & BIT(0)) || (tmp & BIT(1))) { 1178 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1179 "CheckPcieDMAHang8192EE(): true!!\n"); 1180 return true; 1181 } 1182 return false; 1183 } 1184 1185 static void _rtl8192ee_reset_pcie_interface_dma(struct rtl_priv *rtlpriv, 1186 bool mac_power_on) 1187 { 1188 u8 tmp; 1189 bool release_mac_rx_pause; 1190 u8 backup_pcie_dma_pause; 1191 1192 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1193 "ResetPcieInterfaceDMA8192EE()\n"); 1194 1195 /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03" 1196 * released by SD1 Alan. 1197 */ 1198 1199 /* 1. disable register write lock 1200 * write 0x1C bit[1:0] = 2'h0 1201 * write 0xCC bit[2] = 1'b1 1202 */ 1203 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL); 1204 tmp &= ~(BIT(1) | BIT(0)); 1205 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp); 1206 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); 1207 tmp |= BIT(2); 1208 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); 1209 1210 /* 2. Check and pause TRX DMA 1211 * write 0x284 bit[18] = 1'b1 1212 * write 0x301 = 0xFF 1213 */ 1214 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1215 if (tmp & BIT(2)) { 1216 /* Already pause before the function for another reason. */ 1217 release_mac_rx_pause = false; 1218 } else { 1219 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); 1220 release_mac_rx_pause = true; 1221 } 1222 1223 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1); 1224 if (backup_pcie_dma_pause != 0xFF) 1225 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF); 1226 1227 if (mac_power_on) { 1228 /* 3. reset TRX function 1229 * write 0x100 = 0x00 1230 */ 1231 rtl_write_byte(rtlpriv, REG_CR, 0); 1232 } 1233 1234 /* 4. Reset PCIe DMA 1235 * write 0x003 bit[0] = 0 1236 */ 1237 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1238 tmp &= ~(BIT(0)); 1239 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); 1240 1241 /* 5. Enable PCIe DMA 1242 * write 0x003 bit[0] = 1 1243 */ 1244 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1245 tmp |= BIT(0); 1246 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); 1247 1248 if (mac_power_on) { 1249 /* 6. enable TRX function 1250 * write 0x100 = 0xFF 1251 */ 1252 rtl_write_byte(rtlpriv, REG_CR, 0xFF); 1253 1254 /* We should init LLT & RQPN and 1255 * prepare Tx/Rx descrptor address later 1256 * because MAC function is reset. 1257 */ 1258 } 1259 1260 /* 7. Restore PCIe autoload down bit 1261 * write 0xF8 bit[17] = 1'b1 1262 */ 1263 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2); 1264 tmp |= BIT(1); 1265 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp); 1266 1267 /* In MAC power on state, BB and RF maybe in ON state, 1268 * if we release TRx DMA here 1269 * it will cause packets to be started to Tx/Rx, 1270 * so we release Tx/Rx DMA later. 1271 */ 1272 if (!mac_power_on) { 1273 /* 8. release TRX DMA 1274 * write 0x284 bit[18] = 1'b0 1275 * write 0x301 = 0x00 1276 */ 1277 if (release_mac_rx_pause) { 1278 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1279 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 1280 (tmp & (~BIT(2)))); 1281 } 1282 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 1283 backup_pcie_dma_pause); 1284 } 1285 1286 /* 9. lock system register 1287 * write 0xCC bit[2] = 1'b0 1288 */ 1289 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); 1290 tmp &= ~(BIT(2)); 1291 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); 1292 } 1293 1294 int rtl92ee_hw_init(struct ieee80211_hw *hw) 1295 { 1296 struct rtl_priv *rtlpriv = rtl_priv(hw); 1297 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1298 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1299 struct rtl_phy *rtlphy = &rtlpriv->phy; 1300 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1301 bool rtstatus = true; 1302 int err = 0; 1303 u8 tmp_u1b, u1byte; 1304 u32 tmp_u4b; 1305 1306 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, " Rtl8192EE hw init\n"); 1307 rtlpriv->rtlhal.being_init_adapter = true; 1308 rtlpriv->intf_ops->disable_aspm(hw); 1309 1310 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1); 1311 u1byte = rtl_read_byte(rtlpriv, REG_CR); 1312 if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) { 1313 rtlhal->mac_func_enable = true; 1314 } else { 1315 rtlhal->mac_func_enable = false; 1316 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E; 1317 } 1318 1319 if (_rtl8192ee_check_pcie_dma_hang(rtlpriv)) { 1320 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "92ee dma hang!\n"); 1321 _rtl8192ee_reset_pcie_interface_dma(rtlpriv, 1322 rtlhal->mac_func_enable); 1323 rtlhal->mac_func_enable = false; 1324 } 1325 1326 rtstatus = _rtl92ee_init_mac(hw); 1327 1328 rtl_write_byte(rtlpriv, 0x577, 0x03); 1329 1330 /*for Crystal 40 Mhz setting */ 1331 rtl_write_byte(rtlpriv, REG_AFE_CTRL4, 0x2A); 1332 rtl_write_byte(rtlpriv, REG_AFE_CTRL4 + 1, 0x00); 1333 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, 0x83); 1334 1335 /*Forced the antenna b to wifi */ 1336 if (rtlpriv->btcoexist.btc_info.btcoexist == 1) { 1337 rtl_write_byte(rtlpriv, 0x64, 0); 1338 rtl_write_byte(rtlpriv, 0x65, 1); 1339 } 1340 if (!rtstatus) { 1341 pr_err("Init MAC failed\n"); 1342 err = 1; 1343 return err; 1344 } 1345 rtlhal->rx_tag = 0; 1346 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, 0x8000); 1347 err = rtl92ee_download_fw(hw, false); 1348 if (err) { 1349 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1350 "Failed to download FW. Init HW without FW now..\n"); 1351 err = 1; 1352 rtlhal->fw_ready = false; 1353 return err; 1354 } 1355 rtlhal->fw_ready = true; 1356 /*fw related variable initialize */ 1357 ppsc->fw_current_inpsmode = false; 1358 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E; 1359 rtlhal->fw_clk_change_in_progress = false; 1360 rtlhal->allow_sw_to_change_hwclc = false; 1361 rtlhal->last_hmeboxnum = 0; 1362 1363 rtl92ee_phy_mac_config(hw); 1364 1365 rtl92ee_phy_bb_config(hw); 1366 1367 rtl92ee_phy_rf_config(hw); 1368 1369 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, RF90_PATH_A, 1370 RF_CHNLBW, RFREG_OFFSET_MASK); 1371 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, RF90_PATH_B, 1372 RF_CHNLBW, RFREG_OFFSET_MASK); 1373 rtlphy->backup_rf_0x1a = (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1, 1374 RFREG_OFFSET_MASK); 1375 rtlphy->rfreg_chnlval[0] = (rtlphy->rfreg_chnlval[0] & 0xfffff3ff) | 1376 BIT(10) | BIT(11); 1377 1378 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 1379 rtlphy->rfreg_chnlval[0]); 1380 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK, 1381 rtlphy->rfreg_chnlval[0]); 1382 1383 /*---- Set CCK and OFDM Block "ON"----*/ 1384 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1385 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1386 1387 /* Must set this, 1388 * otherwise the rx sensitivity will be very pool. Maddest 1389 */ 1390 rtl_set_rfreg(hw, RF90_PATH_A, 0xB1, RFREG_OFFSET_MASK, 0x54418); 1391 1392 /*Set Hardware(MAC default setting.)*/ 1393 _rtl92ee_hw_configure(hw); 1394 1395 rtlhal->mac_func_enable = true; 1396 1397 rtl_cam_reset_all_entry(hw); 1398 rtl92ee_enable_hw_security_config(hw); 1399 1400 ppsc->rfpwr_state = ERFON; 1401 1402 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1403 _rtl92ee_enable_aspm_back_door(hw); 1404 rtlpriv->intf_ops->enable_aspm(hw); 1405 1406 rtl92ee_bt_hw_init(hw); 1407 1408 rtlpriv->rtlhal.being_init_adapter = false; 1409 1410 if (ppsc->rfpwr_state == ERFON) { 1411 if (rtlphy->iqk_initialized) { 1412 rtl92ee_phy_iq_calibrate(hw, true); 1413 } else { 1414 rtl92ee_phy_iq_calibrate(hw, false); 1415 rtlphy->iqk_initialized = true; 1416 } 1417 } 1418 1419 rtlphy->rfpath_rx_enable[0] = true; 1420 if (rtlphy->rf_type == RF_2T2R) 1421 rtlphy->rfpath_rx_enable[1] = true; 1422 1423 efuse_one_byte_read(hw, 0x1FA, &tmp_u1b); 1424 if (!(tmp_u1b & BIT(0))) { 1425 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); 1426 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n"); 1427 } 1428 1429 if ((!(tmp_u1b & BIT(1))) && (rtlphy->rf_type == RF_2T2R)) { 1430 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05); 1431 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path B\n"); 1432 } 1433 1434 rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128)); 1435 1436 /*Fixed LDPC rx hang issue. */ 1437 tmp_u4b = rtl_read_dword(rtlpriv, REG_SYS_SWR_CTRL1); 1438 rtl_write_byte(rtlpriv, REG_SYS_SWR_CTRL2, 0x75); 1439 tmp_u4b = (tmp_u4b & 0xfff00fff) | (0x7E << 12); 1440 rtl_write_dword(rtlpriv, REG_SYS_SWR_CTRL1, tmp_u4b); 1441 1442 rtl92ee_dm_init(hw); 1443 1444 rtl_write_dword(rtlpriv, 0x4fc, 0); 1445 1446 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1447 "end of Rtl8192EE hw init %x\n", err); 1448 return 0; 1449 } 1450 1451 static enum version_8192e _rtl92ee_read_chip_version(struct ieee80211_hw *hw) 1452 { 1453 struct rtl_priv *rtlpriv = rtl_priv(hw); 1454 struct rtl_phy *rtlphy = &rtlpriv->phy; 1455 enum version_8192e version = VERSION_UNKNOWN; 1456 u32 value32; 1457 1458 rtlphy->rf_type = RF_2T2R; 1459 1460 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1); 1461 if (value32 & TRP_VAUX_EN) 1462 version = (enum version_8192e)VERSION_TEST_CHIP_2T2R_8192E; 1463 else 1464 version = (enum version_8192e)VERSION_NORMAL_CHIP_2T2R_8192E; 1465 1466 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1467 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ? 1468 "RF_2T2R" : "RF_1T1R"); 1469 1470 return version; 1471 } 1472 1473 static int _rtl92ee_set_media_status(struct ieee80211_hw *hw, 1474 enum nl80211_iftype type) 1475 { 1476 struct rtl_priv *rtlpriv = rtl_priv(hw); 1477 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc; 1478 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1479 u8 mode = MSR_NOLINK; 1480 1481 switch (type) { 1482 case NL80211_IFTYPE_UNSPECIFIED: 1483 mode = MSR_NOLINK; 1484 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1485 "Set Network type to NO LINK!\n"); 1486 break; 1487 case NL80211_IFTYPE_ADHOC: 1488 case NL80211_IFTYPE_MESH_POINT: 1489 mode = MSR_ADHOC; 1490 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1491 "Set Network type to Ad Hoc!\n"); 1492 break; 1493 case NL80211_IFTYPE_STATION: 1494 mode = MSR_INFRA; 1495 ledaction = LED_CTL_LINK; 1496 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1497 "Set Network type to STA!\n"); 1498 break; 1499 case NL80211_IFTYPE_AP: 1500 mode = MSR_AP; 1501 ledaction = LED_CTL_LINK; 1502 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1503 "Set Network type to AP!\n"); 1504 break; 1505 default: 1506 pr_err("Network type %d not support!\n", type); 1507 return 1; 1508 } 1509 1510 /* MSR_INFRA == Link in infrastructure network; 1511 * MSR_ADHOC == Link in ad hoc network; 1512 * Therefore, check link state is necessary. 1513 * 1514 * MSR_AP == AP mode; link state is not cared here. 1515 */ 1516 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) { 1517 mode = MSR_NOLINK; 1518 ledaction = LED_CTL_NO_LINK; 1519 } 1520 1521 if (mode == MSR_NOLINK || mode == MSR_INFRA) { 1522 _rtl92ee_stop_tx_beacon(hw); 1523 _rtl92ee_enable_bcn_sub_func(hw); 1524 } else if (mode == MSR_ADHOC || mode == MSR_AP) { 1525 _rtl92ee_resume_tx_beacon(hw); 1526 _rtl92ee_disable_bcn_sub_func(hw); 1527 } else { 1528 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1529 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 1530 mode); 1531 } 1532 1533 rtl_write_byte(rtlpriv, MSR, bt_msr | mode); 1534 rtlpriv->cfg->ops->led_control(hw, ledaction); 1535 if (mode == MSR_AP) 1536 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1537 else 1538 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1539 return 0; 1540 } 1541 1542 void rtl92ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1543 { 1544 struct rtl_priv *rtlpriv = rtl_priv(hw); 1545 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1546 u32 reg_rcr = rtlpci->receive_config; 1547 1548 if (rtlpriv->psc.rfpwr_state != ERFON) 1549 return; 1550 1551 if (check_bssid) { 1552 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1553 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1554 (u8 *)(®_rcr)); 1555 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1556 } else { 1557 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1558 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0); 1559 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1560 (u8 *)(®_rcr)); 1561 } 1562 } 1563 1564 int rtl92ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1565 { 1566 struct rtl_priv *rtlpriv = rtl_priv(hw); 1567 1568 if (_rtl92ee_set_media_status(hw, type)) 1569 return -EOPNOTSUPP; 1570 1571 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1572 if (type != NL80211_IFTYPE_AP && 1573 type != NL80211_IFTYPE_MESH_POINT) 1574 rtl92ee_set_check_bssid(hw, true); 1575 } else { 1576 rtl92ee_set_check_bssid(hw, false); 1577 } 1578 1579 return 0; 1580 } 1581 1582 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ 1583 void rtl92ee_set_qos(struct ieee80211_hw *hw, int aci) 1584 { 1585 struct rtl_priv *rtlpriv = rtl_priv(hw); 1586 1587 rtl92ee_dm_init_edca_turbo(hw); 1588 switch (aci) { 1589 case AC1_BK: 1590 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 1591 break; 1592 case AC0_BE: 1593 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */ 1594 break; 1595 case AC2_VI: 1596 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 1597 break; 1598 case AC3_VO: 1599 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 1600 break; 1601 default: 1602 WARN_ONCE(true, "rtl8192ee: invalid aci: %d !\n", aci); 1603 break; 1604 } 1605 } 1606 1607 void rtl92ee_enable_interrupt(struct ieee80211_hw *hw) 1608 { 1609 struct rtl_priv *rtlpriv = rtl_priv(hw); 1610 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1611 1612 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); 1613 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); 1614 rtlpci->irq_enabled = true; 1615 } 1616 1617 void rtl92ee_disable_interrupt(struct ieee80211_hw *hw) 1618 { 1619 struct rtl_priv *rtlpriv = rtl_priv(hw); 1620 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1621 1622 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED); 1623 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED); 1624 rtlpci->irq_enabled = false; 1625 /*synchronize_irq(rtlpci->pdev->irq);*/ 1626 } 1627 1628 static void _rtl92ee_poweroff_adapter(struct ieee80211_hw *hw) 1629 { 1630 struct rtl_priv *rtlpriv = rtl_priv(hw); 1631 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1632 u8 u1b_tmp; 1633 1634 rtlhal->mac_func_enable = false; 1635 1636 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n"); 1637 1638 /* Run LPS WL RFOFF flow */ 1639 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1640 PWR_INTF_PCI_MSK, RTL8192E_NIC_LPS_ENTER_FLOW); 1641 /* turn off RF */ 1642 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); 1643 1644 /* ==== Reset digital sequence ====== */ 1645 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready) 1646 rtl92ee_firmware_selfreset(hw); 1647 1648 /* Reset MCU */ 1649 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1650 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2)))); 1651 1652 /* reset MCU ready status */ 1653 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1654 1655 /* HW card disable configuration. */ 1656 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1657 PWR_INTF_PCI_MSK, RTL8192E_NIC_DISABLE_FLOW); 1658 1659 /* Reset MCU IO Wrapper */ 1660 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1661 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); 1662 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1663 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0))); 1664 1665 /* lock ISO/CLK/Power control register */ 1666 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E); 1667 } 1668 1669 void rtl92ee_card_disable(struct ieee80211_hw *hw) 1670 { 1671 struct rtl_priv *rtlpriv = rtl_priv(hw); 1672 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1673 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1674 enum nl80211_iftype opmode; 1675 1676 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8192ee card disable\n"); 1677 1678 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1679 1680 mac->link_state = MAC80211_NOLINK; 1681 opmode = NL80211_IFTYPE_UNSPECIFIED; 1682 1683 _rtl92ee_set_media_status(hw, opmode); 1684 1685 if (rtlpriv->rtlhal.driver_is_goingto_unload || 1686 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1687 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1688 1689 _rtl92ee_poweroff_adapter(hw); 1690 1691 /* after power off we should do iqk again */ 1692 if (!rtlpriv->cfg->ops->get_btc_status()) 1693 rtlpriv->phy.iqk_initialized = false; 1694 } 1695 1696 void rtl92ee_interrupt_recognized(struct ieee80211_hw *hw, 1697 struct rtl_int *intvec) 1698 { 1699 struct rtl_priv *rtlpriv = rtl_priv(hw); 1700 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1701 1702 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 1703 rtl_write_dword(rtlpriv, ISR, intvec->inta); 1704 1705 intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; 1706 rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb); 1707 } 1708 1709 void rtl92ee_set_beacon_related_registers(struct ieee80211_hw *hw) 1710 { 1711 struct rtl_priv *rtlpriv = rtl_priv(hw); 1712 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1713 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1714 u16 bcn_interval, atim_window; 1715 1716 bcn_interval = mac->beacon_interval; 1717 atim_window = 2; /*FIX MERGE */ 1718 rtl92ee_disable_interrupt(hw); 1719 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1720 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1721 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 1722 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 1723 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 1724 rtl_write_byte(rtlpriv, 0x606, 0x30); 1725 rtlpci->reg_bcn_ctrl_val |= BIT(3); 1726 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 1727 } 1728 1729 void rtl92ee_set_beacon_interval(struct ieee80211_hw *hw) 1730 { 1731 struct rtl_priv *rtlpriv = rtl_priv(hw); 1732 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1733 u16 bcn_interval = mac->beacon_interval; 1734 1735 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, 1736 "beacon_interval:%d\n", bcn_interval); 1737 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1738 } 1739 1740 void rtl92ee_update_interrupt_mask(struct ieee80211_hw *hw, 1741 u32 add_msr, u32 rm_msr) 1742 { 1743 struct rtl_priv *rtlpriv = rtl_priv(hw); 1744 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1745 1746 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, 1747 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr); 1748 1749 if (add_msr) 1750 rtlpci->irq_mask[0] |= add_msr; 1751 if (rm_msr) 1752 rtlpci->irq_mask[0] &= (~rm_msr); 1753 rtl92ee_disable_interrupt(hw); 1754 rtl92ee_enable_interrupt(hw); 1755 } 1756 1757 static u8 _rtl92ee_get_chnl_group(u8 chnl) 1758 { 1759 u8 group = 0; 1760 1761 if (chnl <= 14) { 1762 if (1 <= chnl && chnl <= 2) 1763 group = 0; 1764 else if (3 <= chnl && chnl <= 5) 1765 group = 1; 1766 else if (6 <= chnl && chnl <= 8) 1767 group = 2; 1768 else if (9 <= chnl && chnl <= 11) 1769 group = 3; 1770 else if (12 <= chnl && chnl <= 14) 1771 group = 4; 1772 } else { 1773 if (36 <= chnl && chnl <= 42) 1774 group = 0; 1775 else if (44 <= chnl && chnl <= 48) 1776 group = 1; 1777 else if (50 <= chnl && chnl <= 58) 1778 group = 2; 1779 else if (60 <= chnl && chnl <= 64) 1780 group = 3; 1781 else if (100 <= chnl && chnl <= 106) 1782 group = 4; 1783 else if (108 <= chnl && chnl <= 114) 1784 group = 5; 1785 else if (116 <= chnl && chnl <= 122) 1786 group = 6; 1787 else if (124 <= chnl && chnl <= 130) 1788 group = 7; 1789 else if (132 <= chnl && chnl <= 138) 1790 group = 8; 1791 else if (140 <= chnl && chnl <= 144) 1792 group = 9; 1793 else if (149 <= chnl && chnl <= 155) 1794 group = 10; 1795 else if (157 <= chnl && chnl <= 161) 1796 group = 11; 1797 else if (165 <= chnl && chnl <= 171) 1798 group = 12; 1799 else if (173 <= chnl && chnl <= 177) 1800 group = 13; 1801 } 1802 return group; 1803 } 1804 1805 static void _rtl8192ee_read_power_value_fromprom(struct ieee80211_hw *hw, 1806 struct txpower_info_2g *pwr2g, 1807 struct txpower_info_5g *pwr5g, 1808 bool autoload_fail, u8 *hwinfo) 1809 { 1810 struct rtl_priv *rtlpriv = rtl_priv(hw); 1811 u32 rf, addr = EEPROM_TX_PWR_INX, group, i = 0; 1812 1813 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1814 "hal_ReadPowerValueFromPROM92E(): PROMContent[0x%x]=0x%x\n", 1815 (addr + 1), hwinfo[addr + 1]); 1816 if (0xFF == hwinfo[addr+1]) /*YJ,add,120316*/ 1817 autoload_fail = true; 1818 1819 if (autoload_fail) { 1820 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1821 "auto load fail : Use Default value!\n"); 1822 for (rf = 0 ; rf < MAX_RF_PATH ; rf++) { 1823 /* 2.4G default value */ 1824 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 1825 pwr2g->index_cck_base[rf][group] = 0x2D; 1826 pwr2g->index_bw40_base[rf][group] = 0x2D; 1827 } 1828 for (i = 0; i < MAX_TX_COUNT; i++) { 1829 if (i == 0) { 1830 pwr2g->bw20_diff[rf][0] = 0x02; 1831 pwr2g->ofdm_diff[rf][0] = 0x04; 1832 } else { 1833 pwr2g->bw20_diff[rf][i] = 0xFE; 1834 pwr2g->bw40_diff[rf][i] = 0xFE; 1835 pwr2g->cck_diff[rf][i] = 0xFE; 1836 pwr2g->ofdm_diff[rf][i] = 0xFE; 1837 } 1838 } 1839 1840 /*5G default value*/ 1841 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) 1842 pwr5g->index_bw40_base[rf][group] = 0x2A; 1843 1844 for (i = 0; i < MAX_TX_COUNT; i++) { 1845 if (i == 0) { 1846 pwr5g->ofdm_diff[rf][0] = 0x04; 1847 pwr5g->bw20_diff[rf][0] = 0x00; 1848 pwr5g->bw80_diff[rf][0] = 0xFE; 1849 pwr5g->bw160_diff[rf][0] = 0xFE; 1850 } else { 1851 pwr5g->ofdm_diff[rf][0] = 0xFE; 1852 pwr5g->bw20_diff[rf][0] = 0xFE; 1853 pwr5g->bw40_diff[rf][0] = 0xFE; 1854 pwr5g->bw80_diff[rf][0] = 0xFE; 1855 pwr5g->bw160_diff[rf][0] = 0xFE; 1856 } 1857 } 1858 } 1859 return; 1860 } 1861 1862 rtl_priv(hw)->efuse.txpwr_fromeprom = true; 1863 1864 for (rf = 0 ; rf < MAX_RF_PATH ; rf++) { 1865 /*2.4G default value*/ 1866 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 1867 pwr2g->index_cck_base[rf][group] = hwinfo[addr++]; 1868 if (pwr2g->index_cck_base[rf][group] == 0xFF) 1869 pwr2g->index_cck_base[rf][group] = 0x2D; 1870 } 1871 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) { 1872 pwr2g->index_bw40_base[rf][group] = hwinfo[addr++]; 1873 if (pwr2g->index_bw40_base[rf][group] == 0xFF) 1874 pwr2g->index_bw40_base[rf][group] = 0x2D; 1875 } 1876 for (i = 0; i < MAX_TX_COUNT; i++) { 1877 if (i == 0) { 1878 pwr2g->bw40_diff[rf][i] = 0; 1879 if (hwinfo[addr] == 0xFF) { 1880 pwr2g->bw20_diff[rf][i] = 0x02; 1881 } else { 1882 pwr2g->bw20_diff[rf][i] = (hwinfo[addr] 1883 & 0xf0) >> 4; 1884 if (pwr2g->bw20_diff[rf][i] & BIT(3)) 1885 pwr2g->bw20_diff[rf][i] |= 0xF0; 1886 } 1887 1888 if (hwinfo[addr] == 0xFF) { 1889 pwr2g->ofdm_diff[rf][i] = 0x04; 1890 } else { 1891 pwr2g->ofdm_diff[rf][i] = (hwinfo[addr] 1892 & 0x0f); 1893 if (pwr2g->ofdm_diff[rf][i] & BIT(3)) 1894 pwr2g->ofdm_diff[rf][i] |= 0xF0; 1895 } 1896 pwr2g->cck_diff[rf][i] = 0; 1897 addr++; 1898 } else { 1899 if (hwinfo[addr] == 0xFF) { 1900 pwr2g->bw40_diff[rf][i] = 0xFE; 1901 } else { 1902 pwr2g->bw40_diff[rf][i] = (hwinfo[addr] 1903 & 0xf0) >> 4; 1904 if (pwr2g->bw40_diff[rf][i] & BIT(3)) 1905 pwr2g->bw40_diff[rf][i] |= 0xF0; 1906 } 1907 1908 if (hwinfo[addr] == 0xFF) { 1909 pwr2g->bw20_diff[rf][i] = 0xFE; 1910 } else { 1911 pwr2g->bw20_diff[rf][i] = (hwinfo[addr] 1912 & 0x0f); 1913 if (pwr2g->bw20_diff[rf][i] & BIT(3)) 1914 pwr2g->bw20_diff[rf][i] |= 0xF0; 1915 } 1916 addr++; 1917 1918 if (hwinfo[addr] == 0xFF) { 1919 pwr2g->ofdm_diff[rf][i] = 0xFE; 1920 } else { 1921 pwr2g->ofdm_diff[rf][i] = (hwinfo[addr] 1922 & 0xf0) >> 4; 1923 if (pwr2g->ofdm_diff[rf][i] & BIT(3)) 1924 pwr2g->ofdm_diff[rf][i] |= 0xF0; 1925 } 1926 1927 if (hwinfo[addr] == 0xFF) { 1928 pwr2g->cck_diff[rf][i] = 0xFE; 1929 } else { 1930 pwr2g->cck_diff[rf][i] = (hwinfo[addr] 1931 & 0x0f); 1932 if (pwr2g->cck_diff[rf][i] & BIT(3)) 1933 pwr2g->cck_diff[rf][i] |= 0xF0; 1934 } 1935 addr++; 1936 } 1937 } 1938 1939 /*5G default value*/ 1940 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) { 1941 pwr5g->index_bw40_base[rf][group] = hwinfo[addr++]; 1942 if (pwr5g->index_bw40_base[rf][group] == 0xFF) 1943 pwr5g->index_bw40_base[rf][group] = 0xFE; 1944 } 1945 1946 for (i = 0; i < MAX_TX_COUNT; i++) { 1947 if (i == 0) { 1948 pwr5g->bw40_diff[rf][i] = 0; 1949 1950 if (hwinfo[addr] == 0xFF) { 1951 pwr5g->bw20_diff[rf][i] = 0; 1952 } else { 1953 pwr5g->bw20_diff[rf][0] = (hwinfo[addr] 1954 & 0xf0) >> 4; 1955 if (pwr5g->bw20_diff[rf][i] & BIT(3)) 1956 pwr5g->bw20_diff[rf][i] |= 0xF0; 1957 } 1958 1959 if (hwinfo[addr] == 0xFF) { 1960 pwr5g->ofdm_diff[rf][i] = 0x04; 1961 } else { 1962 pwr5g->ofdm_diff[rf][0] = (hwinfo[addr] 1963 & 0x0f); 1964 if (pwr5g->ofdm_diff[rf][i] & BIT(3)) 1965 pwr5g->ofdm_diff[rf][i] |= 0xF0; 1966 } 1967 addr++; 1968 } else { 1969 if (hwinfo[addr] == 0xFF) { 1970 pwr5g->bw40_diff[rf][i] = 0xFE; 1971 } else { 1972 pwr5g->bw40_diff[rf][i] = (hwinfo[addr] 1973 & 0xf0) >> 4; 1974 if (pwr5g->bw40_diff[rf][i] & BIT(3)) 1975 pwr5g->bw40_diff[rf][i] |= 0xF0; 1976 } 1977 1978 if (hwinfo[addr] == 0xFF) { 1979 pwr5g->bw20_diff[rf][i] = 0xFE; 1980 } else { 1981 pwr5g->bw20_diff[rf][i] = (hwinfo[addr] 1982 & 0x0f); 1983 if (pwr5g->bw20_diff[rf][i] & BIT(3)) 1984 pwr5g->bw20_diff[rf][i] |= 0xF0; 1985 } 1986 addr++; 1987 } 1988 } 1989 1990 if (hwinfo[addr] == 0xFF) { 1991 pwr5g->ofdm_diff[rf][1] = 0xFE; 1992 pwr5g->ofdm_diff[rf][2] = 0xFE; 1993 } else { 1994 pwr5g->ofdm_diff[rf][1] = (hwinfo[addr] & 0xf0) >> 4; 1995 pwr5g->ofdm_diff[rf][2] = (hwinfo[addr] & 0x0f); 1996 } 1997 addr++; 1998 1999 if (hwinfo[addr] == 0xFF) 2000 pwr5g->ofdm_diff[rf][3] = 0xFE; 2001 else 2002 pwr5g->ofdm_diff[rf][3] = (hwinfo[addr] & 0x0f); 2003 addr++; 2004 2005 for (i = 1; i < MAX_TX_COUNT; i++) { 2006 if (pwr5g->ofdm_diff[rf][i] == 0xFF) 2007 pwr5g->ofdm_diff[rf][i] = 0xFE; 2008 else if (pwr5g->ofdm_diff[rf][i] & BIT(3)) 2009 pwr5g->ofdm_diff[rf][i] |= 0xF0; 2010 } 2011 2012 for (i = 0; i < MAX_TX_COUNT; i++) { 2013 if (hwinfo[addr] == 0xFF) { 2014 pwr5g->bw80_diff[rf][i] = 0xFE; 2015 } else { 2016 pwr5g->bw80_diff[rf][i] = (hwinfo[addr] & 0xf0) 2017 >> 4; 2018 if (pwr5g->bw80_diff[rf][i] & BIT(3)) 2019 pwr5g->bw80_diff[rf][i] |= 0xF0; 2020 } 2021 2022 if (hwinfo[addr] == 0xFF) { 2023 pwr5g->bw160_diff[rf][i] = 0xFE; 2024 } else { 2025 pwr5g->bw160_diff[rf][i] = 2026 (hwinfo[addr] & 0x0f); 2027 if (pwr5g->bw160_diff[rf][i] & BIT(3)) 2028 pwr5g->bw160_diff[rf][i] |= 0xF0; 2029 } 2030 addr++; 2031 } 2032 } 2033 } 2034 2035 static void _rtl92ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 2036 bool autoload_fail, u8 *hwinfo) 2037 { 2038 struct rtl_priv *rtlpriv = rtl_priv(hw); 2039 struct rtl_efuse *efu = rtl_efuse(rtl_priv(hw)); 2040 struct txpower_info_2g pwr2g; 2041 struct txpower_info_5g pwr5g; 2042 u8 rf, idx; 2043 u8 i; 2044 2045 _rtl8192ee_read_power_value_fromprom(hw, &pwr2g, &pwr5g, 2046 autoload_fail, hwinfo); 2047 2048 for (rf = 0; rf < MAX_RF_PATH; rf++) { 2049 for (i = 0; i < 14; i++) { 2050 idx = _rtl92ee_get_chnl_group(i + 1); 2051 2052 if (i == CHANNEL_MAX_NUMBER_2G - 1) { 2053 efu->txpwrlevel_cck[rf][i] = 2054 pwr2g.index_cck_base[rf][5]; 2055 efu->txpwrlevel_ht40_1s[rf][i] = 2056 pwr2g.index_bw40_base[rf][idx]; 2057 } else { 2058 efu->txpwrlevel_cck[rf][i] = 2059 pwr2g.index_cck_base[rf][idx]; 2060 efu->txpwrlevel_ht40_1s[rf][i] = 2061 pwr2g.index_bw40_base[rf][idx]; 2062 } 2063 } 2064 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) { 2065 idx = _rtl92ee_get_chnl_group(channel5g[i]); 2066 efu->txpwr_5g_bw40base[rf][i] = 2067 pwr5g.index_bw40_base[rf][idx]; 2068 } 2069 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) { 2070 u8 upper, lower; 2071 2072 idx = _rtl92ee_get_chnl_group(channel5g_80m[i]); 2073 upper = pwr5g.index_bw40_base[rf][idx]; 2074 lower = pwr5g.index_bw40_base[rf][idx + 1]; 2075 2076 efu->txpwr_5g_bw80base[rf][i] = (upper + lower) / 2; 2077 } 2078 for (i = 0; i < MAX_TX_COUNT; i++) { 2079 efu->txpwr_cckdiff[rf][i] = pwr2g.cck_diff[rf][i]; 2080 efu->txpwr_legacyhtdiff[rf][i] = pwr2g.ofdm_diff[rf][i]; 2081 efu->txpwr_ht20diff[rf][i] = pwr2g.bw20_diff[rf][i]; 2082 efu->txpwr_ht40diff[rf][i] = pwr2g.bw40_diff[rf][i]; 2083 2084 efu->txpwr_5g_ofdmdiff[rf][i] = pwr5g.ofdm_diff[rf][i]; 2085 efu->txpwr_5g_bw20diff[rf][i] = pwr5g.bw20_diff[rf][i]; 2086 efu->txpwr_5g_bw40diff[rf][i] = pwr5g.bw40_diff[rf][i]; 2087 efu->txpwr_5g_bw80diff[rf][i] = pwr5g.bw80_diff[rf][i]; 2088 } 2089 } 2090 2091 if (!autoload_fail) 2092 efu->eeprom_thermalmeter = hwinfo[EEPROM_THERMAL_METER_92E]; 2093 else 2094 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; 2095 2096 if (efu->eeprom_thermalmeter == 0xff || autoload_fail) { 2097 efu->apk_thermalmeterignore = true; 2098 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; 2099 } 2100 2101 efu->thermalmeter[0] = efu->eeprom_thermalmeter; 2102 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 2103 "thermalmeter = 0x%x\n", efu->eeprom_thermalmeter); 2104 2105 if (!autoload_fail) { 2106 efu->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION_92E] 2107 & 0x07; 2108 if (hwinfo[EEPROM_RF_BOARD_OPTION_92E] == 0xFF) 2109 efu->eeprom_regulatory = 0; 2110 } else { 2111 efu->eeprom_regulatory = 0; 2112 } 2113 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 2114 "eeprom_regulatory = 0x%x\n", efu->eeprom_regulatory); 2115 } 2116 2117 static void _rtl92ee_read_adapter_info(struct ieee80211_hw *hw) 2118 { 2119 struct rtl_priv *rtlpriv = rtl_priv(hw); 2120 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2121 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2122 int params[] = {RTL8192E_EEPROM_ID, EEPROM_VID, EEPROM_DID, 2123 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 2124 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 2125 COUNTRY_CODE_WORLD_WIDE_13}; 2126 u8 *hwinfo; 2127 2128 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 2129 if (!hwinfo) 2130 return; 2131 2132 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 2133 goto exit; 2134 2135 if (rtlefuse->eeprom_oemid == 0xFF) 2136 rtlefuse->eeprom_oemid = 0; 2137 2138 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2139 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid); 2140 /* set channel plan from efuse */ 2141 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan; 2142 /*tx power*/ 2143 _rtl92ee_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag, 2144 hwinfo); 2145 2146 rtl92ee_read_bt_coexist_info_from_hwpg(hw, rtlefuse->autoload_failflag, 2147 hwinfo); 2148 2149 /*board type*/ 2150 rtlefuse->board_type = (((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E]) 2151 & 0xE0) >> 5); 2152 if ((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E]) == 0xFF) 2153 rtlefuse->board_type = 0; 2154 2155 if (rtlpriv->btcoexist.btc_info.btcoexist == 1) 2156 rtlefuse->board_type |= BIT(2); /* ODM_BOARD_BT */ 2157 2158 rtlhal->board_type = rtlefuse->board_type; 2159 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2160 "board_type = 0x%x\n", rtlefuse->board_type); 2161 /*parse xtal*/ 2162 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_92E]; 2163 if (hwinfo[EEPROM_XTAL_92E] == 0xFF) 2164 rtlefuse->crystalcap = 0x20; 2165 2166 /*antenna diversity*/ 2167 rtlefuse->antenna_div_type = NO_ANTDIV; 2168 rtlefuse->antenna_div_cfg = 0; 2169 2170 if (rtlhal->oem_id == RT_CID_DEFAULT) { 2171 switch (rtlefuse->eeprom_oemid) { 2172 case EEPROM_CID_DEFAULT: 2173 if (rtlefuse->eeprom_did == 0x818B) { 2174 if ((rtlefuse->eeprom_svid == 0x10EC) && 2175 (rtlefuse->eeprom_smid == 0x001B)) 2176 rtlhal->oem_id = RT_CID_819X_LENOVO; 2177 } else { 2178 rtlhal->oem_id = RT_CID_DEFAULT; 2179 } 2180 break; 2181 default: 2182 rtlhal->oem_id = RT_CID_DEFAULT; 2183 break; 2184 } 2185 } 2186 exit: 2187 kfree(hwinfo); 2188 } 2189 2190 static void _rtl92ee_hal_customized_behavior(struct ieee80211_hw *hw) 2191 { 2192 struct rtl_priv *rtlpriv = rtl_priv(hw); 2193 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2194 2195 rtlpriv->ledctl.led_opendrain = true; 2196 2197 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2198 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 2199 } 2200 2201 void rtl92ee_read_eeprom_info(struct ieee80211_hw *hw) 2202 { 2203 struct rtl_priv *rtlpriv = rtl_priv(hw); 2204 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2205 struct rtl_phy *rtlphy = &rtlpriv->phy; 2206 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2207 u8 tmp_u1b; 2208 2209 rtlhal->version = _rtl92ee_read_chip_version(hw); 2210 if (get_rf_type(rtlphy) == RF_1T1R) { 2211 rtlpriv->dm.rfpath_rxenable[0] = true; 2212 } else { 2213 rtlpriv->dm.rfpath_rxenable[0] = true; 2214 rtlpriv->dm.rfpath_rxenable[1] = true; 2215 } 2216 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 2217 rtlhal->version); 2218 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 2219 if (tmp_u1b & BIT(4)) { 2220 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 2221 rtlefuse->epromtype = EEPROM_93C46; 2222 } else { 2223 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 2224 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 2225 } 2226 if (tmp_u1b & BIT(5)) { 2227 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 2228 rtlefuse->autoload_failflag = false; 2229 _rtl92ee_read_adapter_info(hw); 2230 } else { 2231 pr_err("Autoload ERR!!\n"); 2232 } 2233 _rtl92ee_hal_customized_behavior(hw); 2234 2235 rtlphy->rfpath_rx_enable[0] = true; 2236 if (rtlphy->rf_type == RF_2T2R) 2237 rtlphy->rfpath_rx_enable[1] = true; 2238 } 2239 2240 static u8 _rtl92ee_mrate_idx_to_arfr_id(struct ieee80211_hw *hw, u8 rate_index) 2241 { 2242 u8 ret = 0; 2243 2244 switch (rate_index) { 2245 case RATR_INX_WIRELESS_NGB: 2246 ret = 0; 2247 break; 2248 case RATR_INX_WIRELESS_N: 2249 case RATR_INX_WIRELESS_NG: 2250 ret = 4; 2251 break; 2252 case RATR_INX_WIRELESS_NB: 2253 ret = 2; 2254 break; 2255 case RATR_INX_WIRELESS_GB: 2256 ret = 6; 2257 break; 2258 case RATR_INX_WIRELESS_G: 2259 ret = 7; 2260 break; 2261 case RATR_INX_WIRELESS_B: 2262 ret = 8; 2263 break; 2264 default: 2265 ret = 0; 2266 break; 2267 } 2268 return ret; 2269 } 2270 2271 static void rtl92ee_update_hal_rate_mask(struct ieee80211_hw *hw, 2272 struct ieee80211_sta *sta, 2273 u8 rssi_level, bool update_bw) 2274 { 2275 struct rtl_priv *rtlpriv = rtl_priv(hw); 2276 struct rtl_phy *rtlphy = &rtlpriv->phy; 2277 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2278 struct rtl_sta_info *sta_entry = NULL; 2279 u32 ratr_bitmap; 2280 u8 ratr_index; 2281 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) 2282 ? 1 : 0; 2283 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2284 1 : 0; 2285 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2286 1 : 0; 2287 enum wireless_mode wirelessmode = 0; 2288 bool b_shortgi = false; 2289 u8 rate_mask[7] = {0}; 2290 u8 macid = 0; 2291 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/ 2292 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 2293 wirelessmode = sta_entry->wireless_mode; 2294 if (mac->opmode == NL80211_IFTYPE_STATION || 2295 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2296 curtxbw_40mhz = mac->bw_40; 2297 else if (mac->opmode == NL80211_IFTYPE_AP || 2298 mac->opmode == NL80211_IFTYPE_ADHOC) 2299 macid = sta->aid + 1; 2300 2301 ratr_bitmap = sta->supp_rates[0]; 2302 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2303 ratr_bitmap = 0xfff; 2304 2305 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 2306 sta->ht_cap.mcs.rx_mask[0] << 12); 2307 2308 switch (wirelessmode) { 2309 case WIRELESS_MODE_B: 2310 ratr_index = RATR_INX_WIRELESS_B; 2311 if (ratr_bitmap & 0x0000000c) 2312 ratr_bitmap &= 0x0000000d; 2313 else 2314 ratr_bitmap &= 0x0000000f; 2315 break; 2316 case WIRELESS_MODE_G: 2317 ratr_index = RATR_INX_WIRELESS_GB; 2318 2319 if (rssi_level == 1) 2320 ratr_bitmap &= 0x00000f00; 2321 else if (rssi_level == 2) 2322 ratr_bitmap &= 0x00000ff0; 2323 else 2324 ratr_bitmap &= 0x00000ff5; 2325 break; 2326 case WIRELESS_MODE_N_24G: 2327 if (curtxbw_40mhz) 2328 ratr_index = RATR_INX_WIRELESS_NGB; 2329 else 2330 ratr_index = RATR_INX_WIRELESS_NB; 2331 2332 if (rtlphy->rf_type == RF_1T1R) { 2333 if (curtxbw_40mhz) { 2334 if (rssi_level == 1) 2335 ratr_bitmap &= 0x000f0000; 2336 else if (rssi_level == 2) 2337 ratr_bitmap &= 0x000ff000; 2338 else 2339 ratr_bitmap &= 0x000ff015; 2340 } else { 2341 if (rssi_level == 1) 2342 ratr_bitmap &= 0x000f0000; 2343 else if (rssi_level == 2) 2344 ratr_bitmap &= 0x000ff000; 2345 else 2346 ratr_bitmap &= 0x000ff005; 2347 } 2348 } else { 2349 if (curtxbw_40mhz) { 2350 if (rssi_level == 1) 2351 ratr_bitmap &= 0x0f8f0000; 2352 else if (rssi_level == 2) 2353 ratr_bitmap &= 0x0ffff000; 2354 else 2355 ratr_bitmap &= 0x0ffff015; 2356 } else { 2357 if (rssi_level == 1) 2358 ratr_bitmap &= 0x0f8f0000; 2359 else if (rssi_level == 2) 2360 ratr_bitmap &= 0x0ffff000; 2361 else 2362 ratr_bitmap &= 0x0ffff005; 2363 } 2364 } 2365 2366 if ((curtxbw_40mhz && b_curshortgi_40mhz) || 2367 (!curtxbw_40mhz && b_curshortgi_20mhz)) { 2368 if (macid == 0) 2369 b_shortgi = true; 2370 else if (macid == 1) 2371 b_shortgi = false; 2372 } 2373 break; 2374 default: 2375 ratr_index = RATR_INX_WIRELESS_NGB; 2376 2377 if (rtlphy->rf_type == RF_1T1R) 2378 ratr_bitmap &= 0x000ff0ff; 2379 else 2380 ratr_bitmap &= 0x0f8ff0ff; 2381 break; 2382 } 2383 ratr_index = _rtl92ee_mrate_idx_to_arfr_id(hw, ratr_index); 2384 sta_entry->ratr_index = ratr_index; 2385 2386 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2387 "ratr_bitmap :%x\n", ratr_bitmap); 2388 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 2389 (ratr_index << 28); 2390 rate_mask[0] = macid; 2391 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00); 2392 rate_mask[2] = curtxbw_40mhz | ((!update_bw) << 3); 2393 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff); 2394 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8); 2395 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16); 2396 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24); 2397 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2398 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n", 2399 ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1], 2400 rate_mask[2], rate_mask[3], rate_mask[4], 2401 rate_mask[5], rate_mask[6]); 2402 rtl92ee_fill_h2c_cmd(hw, H2C_92E_RA_MASK, 7, rate_mask); 2403 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0); 2404 } 2405 2406 void rtl92ee_update_hal_rate_tbl(struct ieee80211_hw *hw, 2407 struct ieee80211_sta *sta, u8 rssi_level, 2408 bool update_bw) 2409 { 2410 struct rtl_priv *rtlpriv = rtl_priv(hw); 2411 2412 if (rtlpriv->dm.useramask) 2413 rtl92ee_update_hal_rate_mask(hw, sta, rssi_level, update_bw); 2414 } 2415 2416 void rtl92ee_update_channel_access_setting(struct ieee80211_hw *hw) 2417 { 2418 struct rtl_priv *rtlpriv = rtl_priv(hw); 2419 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2420 u16 sifs_timer; 2421 2422 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2423 (u8 *)&mac->slot_time); 2424 if (!mac->ht_enable) 2425 sifs_timer = 0x0a0a; 2426 else 2427 sifs_timer = 0x0e0e; 2428 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2429 } 2430 2431 bool rtl92ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2432 { 2433 *valid = 1; 2434 return true; 2435 } 2436 2437 void rtl92ee_set_key(struct ieee80211_hw *hw, u32 key_index, 2438 u8 *p_macaddr, bool is_group, u8 enc_algo, 2439 bool is_wepkey, bool clear_all) 2440 { 2441 struct rtl_priv *rtlpriv = rtl_priv(hw); 2442 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2443 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2444 u8 *macaddr = p_macaddr; 2445 u32 entry_id = 0; 2446 bool is_pairwise = false; 2447 2448 static u8 cam_const_addr[4][6] = { 2449 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2450 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2451 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2452 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2453 }; 2454 static u8 cam_const_broad[] = { 2455 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2456 }; 2457 2458 if (clear_all) { 2459 u8 idx = 0; 2460 u8 cam_offset = 0; 2461 u8 clear_number = 5; 2462 2463 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2464 2465 for (idx = 0; idx < clear_number; idx++) { 2466 rtl_cam_mark_invalid(hw, cam_offset + idx); 2467 rtl_cam_empty_entry(hw, cam_offset + idx); 2468 2469 if (idx < 5) { 2470 memset(rtlpriv->sec.key_buf[idx], 0, 2471 MAX_KEY_LEN); 2472 rtlpriv->sec.key_len[idx] = 0; 2473 } 2474 } 2475 2476 } else { 2477 switch (enc_algo) { 2478 case WEP40_ENCRYPTION: 2479 enc_algo = CAM_WEP40; 2480 break; 2481 case WEP104_ENCRYPTION: 2482 enc_algo = CAM_WEP104; 2483 break; 2484 case TKIP_ENCRYPTION: 2485 enc_algo = CAM_TKIP; 2486 break; 2487 case AESCCMP_ENCRYPTION: 2488 enc_algo = CAM_AES; 2489 break; 2490 default: 2491 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, 2492 "switch case %#x not processed\n", enc_algo); 2493 enc_algo = CAM_TKIP; 2494 break; 2495 } 2496 2497 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2498 macaddr = cam_const_addr[key_index]; 2499 entry_id = key_index; 2500 } else { 2501 if (is_group) { 2502 macaddr = cam_const_broad; 2503 entry_id = key_index; 2504 } else { 2505 if (mac->opmode == NL80211_IFTYPE_AP || 2506 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 2507 entry_id = rtl_cam_get_free_entry(hw, 2508 p_macaddr); 2509 if (entry_id >= TOTAL_CAM_ENTRY) { 2510 pr_err("Can not find free hw security cam entry\n"); 2511 return; 2512 } 2513 } else { 2514 entry_id = CAM_PAIRWISE_KEY_POSITION; 2515 } 2516 2517 key_index = PAIRWISE_KEYIDX; 2518 is_pairwise = true; 2519 } 2520 } 2521 2522 if (rtlpriv->sec.key_len[key_index] == 0) { 2523 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2524 "delete one entry, entry_id is %d\n", 2525 entry_id); 2526 if (mac->opmode == NL80211_IFTYPE_AP || 2527 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2528 rtl_cam_del_entry(hw, p_macaddr); 2529 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2530 } else { 2531 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2532 "add one entry\n"); 2533 if (is_pairwise) { 2534 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2535 "set Pairwise key\n"); 2536 2537 rtl_cam_add_one_entry(hw, macaddr, key_index, 2538 entry_id, enc_algo, 2539 CAM_CONFIG_NO_USEDK, 2540 rtlpriv->sec.key_buf[key_index]); 2541 } else { 2542 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2543 "set group key\n"); 2544 2545 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2546 rtl_cam_add_one_entry(hw, 2547 rtlefuse->dev_addr, 2548 PAIRWISE_KEYIDX, 2549 CAM_PAIRWISE_KEY_POSITION, 2550 enc_algo, CAM_CONFIG_NO_USEDK, 2551 rtlpriv->sec.key_buf[entry_id]); 2552 } 2553 2554 rtl_cam_add_one_entry(hw, macaddr, key_index, 2555 entry_id, enc_algo, 2556 CAM_CONFIG_NO_USEDK, 2557 rtlpriv->sec.key_buf[entry_id]); 2558 } 2559 } 2560 } 2561 } 2562 2563 void rtl92ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 2564 bool auto_load_fail, u8 *hwinfo) 2565 { 2566 struct rtl_priv *rtlpriv = rtl_priv(hw); 2567 u8 value; 2568 2569 if (!auto_load_fail) { 2570 value = hwinfo[EEPROM_RF_BOARD_OPTION_92E]; 2571 if (((value & 0xe0) >> 5) == 0x1) 2572 rtlpriv->btcoexist.btc_info.btcoexist = 1; 2573 else 2574 rtlpriv->btcoexist.btc_info.btcoexist = 0; 2575 2576 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E; 2577 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X2; 2578 } else { 2579 rtlpriv->btcoexist.btc_info.btcoexist = 1; 2580 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E; 2581 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X1; 2582 } 2583 } 2584 2585 void rtl92ee_bt_reg_init(struct ieee80211_hw *hw) 2586 { 2587 struct rtl_priv *rtlpriv = rtl_priv(hw); 2588 2589 /* 0:Low, 1:High, 2:From Efuse. */ 2590 rtlpriv->btcoexist.reg_bt_iso = 2; 2591 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 2592 rtlpriv->btcoexist.reg_bt_sco = 3; 2593 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 2594 rtlpriv->btcoexist.reg_bt_sco = 0; 2595 } 2596 2597 void rtl92ee_bt_hw_init(struct ieee80211_hw *hw) 2598 { 2599 struct rtl_priv *rtlpriv = rtl_priv(hw); 2600 2601 if (rtlpriv->cfg->ops->get_btc_status()) 2602 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv); 2603 } 2604 2605 void rtl92ee_suspend(struct ieee80211_hw *hw) 2606 { 2607 } 2608 2609 void rtl92ee_resume(struct ieee80211_hw *hw) 2610 { 2611 } 2612 2613 /* Turn on AAP (RCR:bit 0) for promicuous mode. */ 2614 void rtl92ee_allow_all_destaddr(struct ieee80211_hw *hw, 2615 bool allow_all_da, bool write_into_reg) 2616 { 2617 struct rtl_priv *rtlpriv = rtl_priv(hw); 2618 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2619 2620 if (allow_all_da) /* Set BIT0 */ 2621 rtlpci->receive_config |= RCR_AAP; 2622 else /* Clear BIT0 */ 2623 rtlpci->receive_config &= ~RCR_AAP; 2624 2625 if (write_into_reg) 2626 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 2627 2628 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD, 2629 "receive_config=0x%08X, write_into_reg=%d\n", 2630 rtlpci->receive_config, write_into_reg); 2631 } 2632