1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2014 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../regd.h" 30 #include "../cam.h" 31 #include "../ps.h" 32 #include "../pci.h" 33 #include "reg.h" 34 #include "def.h" 35 #include "phy.h" 36 #include "dm.h" 37 #include "fw.h" 38 #include "led.h" 39 #include "hw.h" 40 #include "../pwrseqcmd.h" 41 #include "pwrseq.h" 42 43 #define LLT_CONFIG 5 44 45 static void _rtl92ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 46 u8 set_bits, u8 clear_bits) 47 { 48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 49 struct rtl_priv *rtlpriv = rtl_priv(hw); 50 51 rtlpci->reg_bcn_ctrl_val |= set_bits; 52 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 53 54 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 55 } 56 57 static void _rtl92ee_stop_tx_beacon(struct ieee80211_hw *hw) 58 { 59 struct rtl_priv *rtlpriv = rtl_priv(hw); 60 u8 tmp; 61 62 tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 63 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp & (~BIT(6))); 64 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 65 tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 66 tmp &= ~(BIT(0)); 67 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp); 68 } 69 70 static void _rtl92ee_resume_tx_beacon(struct ieee80211_hw *hw) 71 { 72 struct rtl_priv *rtlpriv = rtl_priv(hw); 73 u8 tmp; 74 75 tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 76 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp | BIT(6)); 77 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 78 tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 79 tmp |= BIT(0); 80 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp); 81 } 82 83 static void _rtl92ee_enable_bcn_sub_func(struct ieee80211_hw *hw) 84 { 85 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(1)); 86 } 87 88 static void _rtl92ee_disable_bcn_sub_func(struct ieee80211_hw *hw) 89 { 90 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(1), 0); 91 } 92 93 static void _rtl92ee_set_fw_clock_on(struct ieee80211_hw *hw, 94 u8 rpwm_val, bool b_need_turn_off_ckk) 95 { 96 struct rtl_priv *rtlpriv = rtl_priv(hw); 97 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 98 bool b_support_remote_wake_up; 99 u32 count = 0, isr_regaddr, content; 100 bool b_schedule_timer = b_need_turn_off_ckk; 101 102 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, 103 (u8 *)(&b_support_remote_wake_up)); 104 105 if (!rtlhal->fw_ready) 106 return; 107 if (!rtlpriv->psc.fw_current_inpsmode) 108 return; 109 110 while (1) { 111 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 112 if (rtlhal->fw_clk_change_in_progress) { 113 while (rtlhal->fw_clk_change_in_progress) { 114 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 115 count++; 116 udelay(100); 117 if (count > 1000) 118 return; 119 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 120 } 121 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 122 } else { 123 rtlhal->fw_clk_change_in_progress = false; 124 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 125 break; 126 } 127 } 128 129 if (IS_IN_LOW_POWER_STATE_92E(rtlhal->fw_ps_state)) { 130 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, 131 (u8 *)(&rpwm_val)); 132 if (FW_PS_IS_ACK(rpwm_val)) { 133 isr_regaddr = REG_HISR; 134 content = rtl_read_dword(rtlpriv, isr_regaddr); 135 while (!(content & IMR_CPWM) && (count < 500)) { 136 udelay(50); 137 count++; 138 content = rtl_read_dword(rtlpriv, isr_regaddr); 139 } 140 141 if (content & IMR_CPWM) { 142 rtl_write_word(rtlpriv, isr_regaddr, 0x0100); 143 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_92E; 144 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 145 "Receive CPWM INT!!! PSState = %X\n", 146 rtlhal->fw_ps_state); 147 } 148 } 149 150 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 151 rtlhal->fw_clk_change_in_progress = false; 152 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 153 if (b_schedule_timer) { 154 mod_timer(&rtlpriv->works.fw_clockoff_timer, 155 jiffies + MSECS(10)); 156 } 157 } else { 158 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 159 rtlhal->fw_clk_change_in_progress = false; 160 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 161 } 162 } 163 164 static void _rtl92ee_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val) 165 { 166 struct rtl_priv *rtlpriv = rtl_priv(hw); 167 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 168 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 169 struct rtl8192_tx_ring *ring; 170 enum rf_pwrstate rtstate; 171 bool b_schedule_timer = false; 172 u8 queue; 173 174 if (!rtlhal->fw_ready) 175 return; 176 if (!rtlpriv->psc.fw_current_inpsmode) 177 return; 178 if (!rtlhal->allow_sw_to_change_hwclc) 179 return; 180 181 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate)); 182 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF) 183 return; 184 185 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) { 186 ring = &rtlpci->tx_ring[queue]; 187 if (skb_queue_len(&ring->queue)) { 188 b_schedule_timer = true; 189 break; 190 } 191 } 192 193 if (b_schedule_timer) { 194 mod_timer(&rtlpriv->works.fw_clockoff_timer, 195 jiffies + MSECS(10)); 196 return; 197 } 198 199 if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) { 200 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 201 if (!rtlhal->fw_clk_change_in_progress) { 202 rtlhal->fw_clk_change_in_progress = true; 203 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 204 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val); 205 rtl_write_word(rtlpriv, REG_HISR, 0x0100); 206 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 207 (u8 *)(&rpwm_val)); 208 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); 209 rtlhal->fw_clk_change_in_progress = false; 210 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 211 } else { 212 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); 213 mod_timer(&rtlpriv->works.fw_clockoff_timer, 214 jiffies + MSECS(10)); 215 } 216 } 217 } 218 219 static void _rtl92ee_set_fw_ps_rf_on(struct ieee80211_hw *hw) 220 { 221 u8 rpwm_val = 0; 222 223 rpwm_val |= (FW_PS_STATE_RF_OFF_92E | FW_PS_ACK); 224 _rtl92ee_set_fw_clock_on(hw, rpwm_val, true); 225 } 226 227 static void _rtl92ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw) 228 { 229 u8 rpwm_val = 0; 230 231 rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR; 232 _rtl92ee_set_fw_clock_off(hw, rpwm_val); 233 } 234 235 void rtl92ee_fw_clk_off_timer_callback(unsigned long data) 236 { 237 struct ieee80211_hw *hw = (struct ieee80211_hw *)data; 238 239 _rtl92ee_set_fw_ps_rf_off_low_power(hw); 240 } 241 242 static void _rtl92ee_fwlps_leave(struct ieee80211_hw *hw) 243 { 244 struct rtl_priv *rtlpriv = rtl_priv(hw); 245 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 246 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 247 bool fw_current_inps = false; 248 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE; 249 250 if (ppsc->low_power_enable) { 251 rpwm_val = (FW_PS_STATE_ALL_ON_92E | FW_PS_ACK);/* RF on */ 252 _rtl92ee_set_fw_clock_on(hw, rpwm_val, false); 253 rtlhal->allow_sw_to_change_hwclc = false; 254 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 255 (u8 *)(&fw_pwrmode)); 256 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 257 (u8 *)(&fw_current_inps)); 258 } else { 259 rpwm_val = FW_PS_STATE_ALL_ON_92E; /* RF on */ 260 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 261 (u8 *)(&rpwm_val)); 262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 263 (u8 *)(&fw_pwrmode)); 264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 265 (u8 *)(&fw_current_inps)); 266 } 267 } 268 269 static void _rtl92ee_fwlps_enter(struct ieee80211_hw *hw) 270 { 271 struct rtl_priv *rtlpriv = rtl_priv(hw); 272 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 273 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 274 bool fw_current_inps = true; 275 u8 rpwm_val; 276 277 if (ppsc->low_power_enable) { 278 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR; /* RF off */ 279 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 280 (u8 *)(&fw_current_inps)); 281 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 282 (u8 *)(&ppsc->fwctrl_psmode)); 283 rtlhal->allow_sw_to_change_hwclc = true; 284 _rtl92ee_set_fw_clock_off(hw, rpwm_val); 285 } else { 286 rpwm_val = FW_PS_STATE_RF_OFF_92E; /* RF off */ 287 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, 288 (u8 *)(&fw_current_inps)); 289 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, 290 (u8 *)(&ppsc->fwctrl_psmode)); 291 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, 292 (u8 *)(&rpwm_val)); 293 } 294 } 295 296 void rtl92ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 297 { 298 struct rtl_priv *rtlpriv = rtl_priv(hw); 299 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 300 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 301 302 switch (variable) { 303 case HW_VAR_RCR: 304 *((u32 *)(val)) = rtlpci->receive_config; 305 break; 306 case HW_VAR_RF_STATE: 307 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 308 break; 309 case HW_VAR_FWLPS_RF_ON:{ 310 enum rf_pwrstate rfstate; 311 u32 val_rcr; 312 313 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, 314 (u8 *)(&rfstate)); 315 if (rfstate == ERFOFF) { 316 *((bool *)(val)) = true; 317 } else { 318 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 319 val_rcr &= 0x00070000; 320 if (val_rcr) 321 *((bool *)(val)) = false; 322 else 323 *((bool *)(val)) = true; 324 } 325 } 326 break; 327 case HW_VAR_FW_PSMODE_STATUS: 328 *((bool *)(val)) = ppsc->fw_current_inpsmode; 329 break; 330 case HW_VAR_CORRECT_TSF:{ 331 u64 tsf; 332 u32 *ptsf_low = (u32 *)&tsf; 333 u32 *ptsf_high = ((u32 *)&tsf) + 1; 334 335 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 336 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 337 338 *((u64 *)(val)) = tsf; 339 } 340 break; 341 case HAL_DEF_WOWLAN: 342 break; 343 default: 344 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, 345 "switch case %#x not processed\n", variable); 346 break; 347 } 348 } 349 350 static void _rtl92ee_download_rsvd_page(struct ieee80211_hw *hw) 351 { 352 struct rtl_priv *rtlpriv = rtl_priv(hw); 353 u8 tmp_regcr, tmp_reg422; 354 u8 bcnvalid_reg, txbc_reg; 355 u8 count = 0, dlbcn_count = 0; 356 bool b_recover = false; 357 358 /*Set REG_CR bit 8. DMA beacon by SW.*/ 359 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 360 rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr | BIT(0)); 361 362 /* Disable Hw protection for a time which revserd for Hw sending beacon. 363 * Fix download reserved page packet fail 364 * that access collision with the protection time. 365 * 2010.05.11. Added by tynli. 366 */ 367 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); 368 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0); 369 370 /* Set FWHW_TXQ_CTRL 0x422[6]=0 to 371 * tell Hw the packet is not a real beacon frame. 372 */ 373 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 374 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6))); 375 376 if (tmp_reg422 & BIT(6)) 377 b_recover = true; 378 379 do { 380 /* Clear beacon valid check bit */ 381 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2); 382 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2, 383 bcnvalid_reg | BIT(0)); 384 385 /* download rsvd page */ 386 rtl92ee_set_fw_rsvdpagepkt(hw, false); 387 388 txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3); 389 count = 0; 390 while ((txbc_reg & BIT(4)) && count < 20) { 391 count++; 392 udelay(10); 393 txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3); 394 } 395 rtl_write_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3, 396 txbc_reg | BIT(4)); 397 398 /* check rsvd page download OK. */ 399 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2); 400 count = 0; 401 while (!(bcnvalid_reg & BIT(0)) && count < 20) { 402 count++; 403 udelay(50); 404 bcnvalid_reg = rtl_read_byte(rtlpriv, 405 REG_DWBCN0_CTRL + 2); 406 } 407 408 if (bcnvalid_reg & BIT(0)) 409 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2, BIT(0)); 410 411 dlbcn_count++; 412 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5); 413 414 if (!(bcnvalid_reg & BIT(0))) 415 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 416 "Download RSVD page failed!\n"); 417 418 /* Enable Bcn */ 419 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0); 420 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); 421 422 if (b_recover) 423 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422); 424 425 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 426 rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr & (~BIT(0))); 427 } 428 429 void rtl92ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 430 { 431 struct rtl_priv *rtlpriv = rtl_priv(hw); 432 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 433 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 434 struct rtl_efuse *efuse = rtl_efuse(rtl_priv(hw)); 435 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 436 u8 idx; 437 438 switch (variable) { 439 case HW_VAR_ETHER_ADDR: 440 for (idx = 0; idx < ETH_ALEN; idx++) 441 rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]); 442 break; 443 case HW_VAR_BASIC_RATE:{ 444 u16 b_rate_cfg = ((u16 *)val)[0]; 445 446 b_rate_cfg = b_rate_cfg & 0x15f; 447 b_rate_cfg |= 0x01; 448 b_rate_cfg = (b_rate_cfg | 0xd) & (~BIT(1)); 449 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff); 450 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff); 451 break; } 452 case HW_VAR_BSSID: 453 for (idx = 0; idx < ETH_ALEN; idx++) 454 rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]); 455 break; 456 case HW_VAR_SIFS: 457 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 458 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); 459 460 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 461 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 462 463 if (!mac->ht_enable) 464 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e); 465 else 466 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 467 *((u16 *)val)); 468 break; 469 case HW_VAR_SLOT_TIME:{ 470 u8 e_aci; 471 472 RT_TRACE(rtlpriv, COMP_MLME, DBG_TRACE, 473 "HW_VAR_SLOT_TIME %x\n", val[0]); 474 475 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 476 477 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 478 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, 479 (u8 *)(&e_aci)); 480 } 481 break; } 482 case HW_VAR_ACK_PREAMBLE:{ 483 u8 reg_tmp; 484 u8 short_preamble = (bool)(*(u8 *)val); 485 486 reg_tmp = (rtlpriv->mac80211.cur_40_prime_sc) << 5; 487 if (short_preamble) 488 reg_tmp |= 0x80; 489 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 490 rtlpriv->mac80211.short_preamble = short_preamble; 491 } 492 break; 493 case HW_VAR_WPA_CONFIG: 494 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val)); 495 break; 496 case HW_VAR_AMPDU_FACTOR:{ 497 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 }; 498 u8 fac; 499 u8 *reg = NULL; 500 u8 i = 0; 501 502 reg = regtoset_normal; 503 504 fac = *((u8 *)val); 505 if (fac <= 3) { 506 fac = (1 << (fac + 2)); 507 if (fac > 0xf) 508 fac = 0xf; 509 for (i = 0; i < 4; i++) { 510 if ((reg[i] & 0xf0) > (fac << 4)) 511 reg[i] = (reg[i] & 0x0f) | 512 (fac << 4); 513 if ((reg[i] & 0x0f) > fac) 514 reg[i] = (reg[i] & 0xf0) | fac; 515 rtl_write_byte(rtlpriv, 516 (REG_AGGLEN_LMT + i), 517 reg[i]); 518 } 519 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 520 "Set HW_VAR_AMPDU_FACTOR:%#x\n", fac); 521 } 522 } 523 break; 524 case HW_VAR_AC_PARAM:{ 525 u8 e_aci = *((u8 *)val); 526 527 if (rtlpci->acm_method != EACMWAY2_SW) 528 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL, 529 (u8 *)(&e_aci)); 530 } 531 break; 532 case HW_VAR_ACM_CTRL:{ 533 u8 e_aci = *((u8 *)val); 534 union aci_aifsn *aifs = (union aci_aifsn *)(&mac->ac[0].aifs); 535 536 u8 acm = aifs->f.acm; 537 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 538 539 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 540 541 if (acm) { 542 switch (e_aci) { 543 case AC0_BE: 544 acm_ctrl |= ACMHW_BEQEN; 545 break; 546 case AC2_VI: 547 acm_ctrl |= ACMHW_VIQEN; 548 break; 549 case AC3_VO: 550 acm_ctrl |= ACMHW_VOQEN; 551 break; 552 default: 553 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 554 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 555 acm); 556 break; 557 } 558 } else { 559 switch (e_aci) { 560 case AC0_BE: 561 acm_ctrl &= (~ACMHW_BEQEN); 562 break; 563 case AC2_VI: 564 acm_ctrl &= (~ACMHW_VIQEN); 565 break; 566 case AC3_VO: 567 acm_ctrl &= (~ACMHW_VOQEN); 568 break; 569 default: 570 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, 571 "switch case %#x not processed\n", 572 e_aci); 573 break; 574 } 575 } 576 577 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 578 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 579 acm_ctrl); 580 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 581 } 582 break; 583 case HW_VAR_RCR:{ 584 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); 585 rtlpci->receive_config = ((u32 *)(val))[0]; 586 } 587 break; 588 case HW_VAR_RETRY_LIMIT:{ 589 u8 retry_limit = ((u8 *)(val))[0]; 590 591 rtl_write_word(rtlpriv, REG_RETRY_LIMIT, 592 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 593 retry_limit << RETRY_LIMIT_LONG_SHIFT); 594 } 595 break; 596 case HW_VAR_DUAL_TSF_RST: 597 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 598 break; 599 case HW_VAR_EFUSE_BYTES: 600 efuse->efuse_usedbytes = *((u16 *)val); 601 break; 602 case HW_VAR_EFUSE_USAGE: 603 efuse->efuse_usedpercentage = *((u8 *)val); 604 break; 605 case HW_VAR_IO_CMD: 606 rtl92ee_phy_set_io_cmd(hw, (*(enum io_type *)val)); 607 break; 608 case HW_VAR_SET_RPWM:{ 609 u8 rpwm_val; 610 611 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 612 udelay(1); 613 614 if (rpwm_val & BIT(7)) { 615 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val)); 616 } else { 617 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 618 ((*(u8 *)val) | BIT(7))); 619 } 620 } 621 break; 622 case HW_VAR_H2C_FW_PWRMODE: 623 rtl92ee_set_fw_pwrmode_cmd(hw, (*(u8 *)val)); 624 break; 625 case HW_VAR_FW_PSMODE_STATUS: 626 ppsc->fw_current_inpsmode = *((bool *)val); 627 break; 628 case HW_VAR_RESUME_CLK_ON: 629 _rtl92ee_set_fw_ps_rf_on(hw); 630 break; 631 case HW_VAR_FW_LPS_ACTION:{ 632 bool b_enter_fwlps = *((bool *)val); 633 634 if (b_enter_fwlps) 635 _rtl92ee_fwlps_enter(hw); 636 else 637 _rtl92ee_fwlps_leave(hw); 638 } 639 break; 640 case HW_VAR_H2C_FW_JOINBSSRPT:{ 641 u8 mstatus = (*(u8 *)val); 642 643 if (mstatus == RT_MEDIA_CONNECT) { 644 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL); 645 _rtl92ee_download_rsvd_page(hw); 646 } 647 rtl92ee_set_fw_media_status_rpt_cmd(hw, mstatus); 648 } 649 break; 650 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: 651 rtl92ee_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); 652 break; 653 case HW_VAR_AID:{ 654 u16 u2btmp; 655 656 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 657 u2btmp &= 0xC000; 658 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, 659 (u2btmp | mac->assoc_id)); 660 } 661 break; 662 case HW_VAR_CORRECT_TSF:{ 663 u8 btype_ibss = ((u8 *)(val))[0]; 664 665 if (btype_ibss) 666 _rtl92ee_stop_tx_beacon(hw); 667 668 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3)); 669 670 rtl_write_dword(rtlpriv, REG_TSFTR, 671 (u32)(mac->tsf & 0xffffffff)); 672 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 673 (u32)((mac->tsf >> 32) & 0xffffffff)); 674 675 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0); 676 677 if (btype_ibss) 678 _rtl92ee_resume_tx_beacon(hw); 679 } 680 break; 681 case HW_VAR_KEEP_ALIVE: { 682 u8 array[2]; 683 684 array[0] = 0xff; 685 array[1] = *((u8 *)val); 686 rtl92ee_fill_h2c_cmd(hw, H2C_92E_KEEP_ALIVE_CTRL, 2, array); 687 } 688 break; 689 default: 690 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, 691 "switch case %#x not processed\n", variable); 692 break; 693 } 694 } 695 696 static bool _rtl92ee_llt_table_init(struct ieee80211_hw *hw) 697 { 698 struct rtl_priv *rtlpriv = rtl_priv(hw); 699 u8 txpktbuf_bndy; 700 u8 u8tmp, testcnt = 0; 701 702 txpktbuf_bndy = 0xF7; 703 704 rtl_write_dword(rtlpriv, REG_RQPN, 0x80E60808); 705 706 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy); 707 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x3d00 - 1); 708 709 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 1, txpktbuf_bndy); 710 rtl_write_byte(rtlpriv, REG_DWBCN1_CTRL + 1, txpktbuf_bndy); 711 712 rtl_write_byte(rtlpriv, REG_BCNQ_BDNY, txpktbuf_bndy); 713 rtl_write_byte(rtlpriv, REG_BCNQ1_BDNY, txpktbuf_bndy); 714 715 rtl_write_byte(rtlpriv, REG_MGQ_BDNY, txpktbuf_bndy); 716 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); 717 718 rtl_write_byte(rtlpriv, REG_PBP, 0x31); 719 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 720 721 u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2); 722 rtl_write_byte(rtlpriv, REG_AUTO_LLT + 2, u8tmp | BIT(0)); 723 724 while (u8tmp & BIT(0)) { 725 u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2); 726 udelay(10); 727 testcnt++; 728 if (testcnt > 10) 729 break; 730 } 731 732 return true; 733 } 734 735 static void _rtl92ee_gen_refresh_led_state(struct ieee80211_hw *hw) 736 { 737 struct rtl_priv *rtlpriv = rtl_priv(hw); 738 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 739 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0; 740 741 if (rtlpriv->rtlhal.up_first_time) 742 return; 743 744 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 745 rtl92ee_sw_led_on(hw, pled0); 746 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 747 rtl92ee_sw_led_on(hw, pled0); 748 else 749 rtl92ee_sw_led_off(hw, pled0); 750 } 751 752 static bool _rtl92ee_init_mac(struct ieee80211_hw *hw) 753 { 754 struct rtl_priv *rtlpriv = rtl_priv(hw); 755 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 756 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 757 758 u8 bytetmp; 759 u16 wordtmp; 760 u32 dwordtmp; 761 762 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); 763 764 dwordtmp = rtl_read_dword(rtlpriv, REG_SYS_CFG1); 765 if (dwordtmp & BIT(24)) { 766 rtl_write_byte(rtlpriv, 0x7c, 0xc3); 767 } else { 768 bytetmp = rtl_read_byte(rtlpriv, 0x16); 769 rtl_write_byte(rtlpriv, 0x16, bytetmp | BIT(4) | BIT(6)); 770 rtl_write_byte(rtlpriv, 0x7c, 0x83); 771 } 772 /* 1. 40Mhz crystal source*/ 773 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2); 774 bytetmp &= 0xfb; 775 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp); 776 777 dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4); 778 dwordtmp &= 0xfffffc7f; 779 rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp); 780 781 /* 2. 92E AFE parameter 782 * MP chip then check version 783 */ 784 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2); 785 bytetmp &= 0xbf; 786 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp); 787 788 dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4); 789 dwordtmp &= 0xffdfffff; 790 rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp); 791 792 /* HW Power on sequence */ 793 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 794 PWR_INTF_PCI_MSK, 795 RTL8192E_NIC_ENABLE_FLOW)) { 796 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 797 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n"); 798 return false; 799 } 800 801 /* Release MAC IO register reset */ 802 bytetmp = rtl_read_byte(rtlpriv, REG_CR); 803 bytetmp = 0xff; 804 rtl_write_byte(rtlpriv, REG_CR, bytetmp); 805 mdelay(2); 806 bytetmp = 0x7f; 807 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp); 808 mdelay(2); 809 810 /* Add for wakeup online */ 811 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR); 812 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3)); 813 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1); 814 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4))); 815 /* Release MAC IO register reset */ 816 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 817 818 if (!rtlhal->mac_func_enable) { 819 if (_rtl92ee_llt_table_init(hw) == false) { 820 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 821 "LLT table init fail\n"); 822 return false; 823 } 824 } 825 826 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 827 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff); 828 829 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 830 wordtmp &= 0xf; 831 wordtmp |= 0xF5B1; 832 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 833 /* Reported Tx status from HW for rate adaptive.*/ 834 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 835 836 /* Set RCR register */ 837 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 838 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff); 839 840 /* Set TCR register */ 841 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); 842 843 /* Set TX/RX descriptor physical address(from OS API). */ 844 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 845 ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) & 846 DMA_BIT_MASK(32)); 847 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 848 (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma & 849 DMA_BIT_MASK(32)); 850 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 851 (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma & 852 DMA_BIT_MASK(32)); 853 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 854 (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma & 855 DMA_BIT_MASK(32)); 856 857 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 858 (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma & 859 DMA_BIT_MASK(32)); 860 861 dwordtmp = rtl_read_dword(rtlpriv, REG_BEQ_DESA); 862 863 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 864 (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma & 865 DMA_BIT_MASK(32)); 866 rtl_write_dword(rtlpriv, REG_HQ0_DESA, 867 (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma & 868 DMA_BIT_MASK(32)); 869 870 rtl_write_dword(rtlpriv, REG_RX_DESA, 871 (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma & 872 DMA_BIT_MASK(32)); 873 874 /* if we want to support 64 bit DMA, we should set it here, 875 * but now we do not support 64 bit DMA 876 */ 877 878 rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0x3fffffff); 879 880 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3); 881 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0xF7); 882 883 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 884 885 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); 886 887 rtl_write_word(rtlpriv, REG_MGQ_TXBD_NUM, 888 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 889 rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM, 890 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 891 rtl_write_word(rtlpriv, REG_VIQ_TXBD_NUM, 892 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 893 rtl_write_word(rtlpriv, REG_BEQ_TXBD_NUM, 894 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 895 rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM, 896 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 897 rtl_write_word(rtlpriv, REG_BKQ_TXBD_NUM, 898 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 899 rtl_write_word(rtlpriv, REG_HI0Q_TXBD_NUM, 900 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 901 rtl_write_word(rtlpriv, REG_HI1Q_TXBD_NUM, 902 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 903 rtl_write_word(rtlpriv, REG_HI2Q_TXBD_NUM, 904 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 905 rtl_write_word(rtlpriv, REG_HI3Q_TXBD_NUM, 906 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 907 rtl_write_word(rtlpriv, REG_HI4Q_TXBD_NUM, 908 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 909 rtl_write_word(rtlpriv, REG_HI5Q_TXBD_NUM, 910 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 911 rtl_write_word(rtlpriv, REG_HI6Q_TXBD_NUM, 912 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 913 rtl_write_word(rtlpriv, REG_HI7Q_TXBD_NUM, 914 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000)); 915 /*Rx*/ 916 #if (DMA_IS_64BIT == 1) 917 rtl_write_word(rtlpriv, REG_RX_RXBD_NUM, 918 RX_DESC_NUM_92E | 919 ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x8000); 920 #else 921 rtl_write_word(rtlpriv, REG_RX_RXBD_NUM, 922 RX_DESC_NUM_92E | 923 ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x0000); 924 #endif 925 926 rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0XFFFFFFFF); 927 928 _rtl92ee_gen_refresh_led_state(hw); 929 return true; 930 } 931 932 static void _rtl92ee_hw_configure(struct ieee80211_hw *hw) 933 { 934 struct rtl_priv *rtlpriv = rtl_priv(hw); 935 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 936 u32 reg_rrsr; 937 938 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 939 /* Init value for RRSR. */ 940 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr); 941 942 /* ARFB table 9 for 11ac 5G 2SS */ 943 rtl_write_dword(rtlpriv, REG_ARFR0, 0x00000010); 944 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0x3e0ff000); 945 946 /* ARFB table 10 for 11ac 5G 1SS */ 947 rtl_write_dword(rtlpriv, REG_ARFR1, 0x00000010); 948 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x000ff000); 949 950 /* Set SLOT time */ 951 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 952 953 /* CF-End setting. */ 954 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); 955 956 /* Set retry limit */ 957 rtl_write_word(rtlpriv, REG_RETRY_LIMIT, 0x0707); 958 959 /* BAR settings */ 960 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x0201ffff); 961 962 /* Set Data / Response auto rate fallack retry count */ 963 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 964 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 965 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 966 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 967 968 /* Beacon related, for rate adaptive */ 969 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); 970 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); 971 972 rtlpci->reg_bcn_ctrl_val = 0x1d; 973 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 974 975 /* Marked out by Bruce, 2010-09-09. 976 * This register is configured for the 2nd Beacon (multiple BSSID). 977 * We shall disable this register if we only support 1 BSSID. 978 * vivi guess 92d also need this, also 92d now doesnot set this reg 979 */ 980 rtl_write_byte(rtlpriv, REG_BCN_CTRL_1, 0); 981 982 /* TBTT prohibit hold time. Suggested by designer TimChen. */ 983 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */ 984 985 rtl_write_byte(rtlpriv, REG_PIFS, 0); 986 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 987 988 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); 989 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x08ff); 990 991 /* For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/ 992 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); 993 994 /* ACKTO for IOT issue. */ 995 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); 996 997 /* Set Spec SIFS (used in NAV) */ 998 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x100a); 999 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x100a); 1000 1001 /* Set SIFS for CCK */ 1002 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x100a); 1003 1004 /* Set SIFS for OFDM */ 1005 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x100a); 1006 1007 /* Note Data sheet don't define */ 1008 rtl_write_byte(rtlpriv, 0x4C7, 0x80); 1009 1010 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20); 1011 1012 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1717); 1013 1014 /* Set Multicast Address. 2009.01.07. by tynli. */ 1015 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); 1016 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); 1017 } 1018 1019 static void _rtl92ee_enable_aspm_back_door(struct ieee80211_hw *hw) 1020 { 1021 struct rtl_priv *rtlpriv = rtl_priv(hw); 1022 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1023 u32 tmp32 = 0, count = 0; 1024 u8 tmp8 = 0; 1025 1026 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x78); 1027 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2); 1028 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1029 count = 0; 1030 while (tmp8 && count < 20) { 1031 udelay(10); 1032 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1033 count++; 1034 } 1035 1036 if (0 == tmp8) { 1037 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA); 1038 if ((tmp32 & 0xff00) != 0x2000) { 1039 tmp32 &= 0xffff00ff; 1040 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA, 1041 tmp32 | BIT(13)); 1042 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf078); 1043 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1); 1044 1045 tmp8 = rtl_read_byte(rtlpriv, 1046 REG_BACKDOOR_DBI_DATA + 2); 1047 count = 0; 1048 while (tmp8 && count < 20) { 1049 udelay(10); 1050 tmp8 = rtl_read_byte(rtlpriv, 1051 REG_BACKDOOR_DBI_DATA + 2); 1052 count++; 1053 } 1054 } 1055 } 1056 1057 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x70c); 1058 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2); 1059 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1060 count = 0; 1061 while (tmp8 && count < 20) { 1062 udelay(10); 1063 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1064 count++; 1065 } 1066 if (0 == tmp8) { 1067 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA); 1068 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA, 1069 tmp32 | BIT(31)); 1070 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf70c); 1071 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1); 1072 } 1073 1074 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1075 count = 0; 1076 while (tmp8 && count < 20) { 1077 udelay(10); 1078 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1079 count++; 1080 } 1081 1082 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x718); 1083 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2); 1084 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1085 count = 0; 1086 while (tmp8 && count < 20) { 1087 udelay(10); 1088 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1089 count++; 1090 } 1091 if (ppsc->support_backdoor || (0 == tmp8)) { 1092 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA); 1093 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA, 1094 tmp32 | BIT(11) | BIT(12)); 1095 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf718); 1096 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1); 1097 } 1098 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1099 count = 0; 1100 while (tmp8 && count < 20) { 1101 udelay(10); 1102 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); 1103 count++; 1104 } 1105 } 1106 1107 void rtl92ee_enable_hw_security_config(struct ieee80211_hw *hw) 1108 { 1109 struct rtl_priv *rtlpriv = rtl_priv(hw); 1110 u8 sec_reg_value; 1111 u8 tmp; 1112 1113 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1114 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 1115 rtlpriv->sec.pairwise_enc_algorithm, 1116 rtlpriv->sec.group_enc_algorithm); 1117 1118 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 1119 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 1120 "not open hw encryption\n"); 1121 return; 1122 } 1123 1124 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE; 1125 1126 if (rtlpriv->sec.use_defaultkey) { 1127 sec_reg_value |= SCR_TXUSEDK; 1128 sec_reg_value |= SCR_RXUSEDK; 1129 } 1130 1131 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 1132 1133 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); 1134 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1)); 1135 1136 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 1137 "The SECR-value %x\n", sec_reg_value); 1138 1139 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 1140 } 1141 1142 static bool _rtl8192ee_check_pcie_dma_hang(struct rtl_priv *rtlpriv) 1143 { 1144 u8 tmp; 1145 1146 /* write reg 0x350 Bit[26]=1. Enable debug port. */ 1147 tmp = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3); 1148 if (!(tmp & BIT(2))) { 1149 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3, 1150 tmp | BIT(2)); 1151 mdelay(100); /* Suggested by DD Justin_tsai. */ 1152 } 1153 1154 /* read reg 0x350 Bit[25] if 1 : RX hang 1155 * read reg 0x350 Bit[24] if 1 : TX hang 1156 */ 1157 tmp = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3); 1158 if ((tmp & BIT(0)) || (tmp & BIT(1))) { 1159 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1160 "CheckPcieDMAHang8192EE(): true!!\n"); 1161 return true; 1162 } 1163 return false; 1164 } 1165 1166 static void _rtl8192ee_reset_pcie_interface_dma(struct rtl_priv *rtlpriv, 1167 bool mac_power_on) 1168 { 1169 u8 tmp; 1170 bool release_mac_rx_pause; 1171 u8 backup_pcie_dma_pause; 1172 1173 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1174 "ResetPcieInterfaceDMA8192EE()\n"); 1175 1176 /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03" 1177 * released by SD1 Alan. 1178 */ 1179 1180 /* 1. disable register write lock 1181 * write 0x1C bit[1:0] = 2'h0 1182 * write 0xCC bit[2] = 1'b1 1183 */ 1184 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL); 1185 tmp &= ~(BIT(1) | BIT(0)); 1186 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp); 1187 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); 1188 tmp |= BIT(2); 1189 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); 1190 1191 /* 2. Check and pause TRX DMA 1192 * write 0x284 bit[18] = 1'b1 1193 * write 0x301 = 0xFF 1194 */ 1195 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1196 if (tmp & BIT(2)) { 1197 /* Already pause before the function for another reason. */ 1198 release_mac_rx_pause = false; 1199 } else { 1200 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); 1201 release_mac_rx_pause = true; 1202 } 1203 1204 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1); 1205 if (backup_pcie_dma_pause != 0xFF) 1206 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF); 1207 1208 if (mac_power_on) { 1209 /* 3. reset TRX function 1210 * write 0x100 = 0x00 1211 */ 1212 rtl_write_byte(rtlpriv, REG_CR, 0); 1213 } 1214 1215 /* 4. Reset PCIe DMA 1216 * write 0x003 bit[0] = 0 1217 */ 1218 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1219 tmp &= ~(BIT(0)); 1220 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); 1221 1222 /* 5. Enable PCIe DMA 1223 * write 0x003 bit[0] = 1 1224 */ 1225 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1226 tmp |= BIT(0); 1227 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); 1228 1229 if (mac_power_on) { 1230 /* 6. enable TRX function 1231 * write 0x100 = 0xFF 1232 */ 1233 rtl_write_byte(rtlpriv, REG_CR, 0xFF); 1234 1235 /* We should init LLT & RQPN and 1236 * prepare Tx/Rx descrptor address later 1237 * because MAC function is reset. 1238 */ 1239 } 1240 1241 /* 7. Restore PCIe autoload down bit 1242 * write 0xF8 bit[17] = 1'b1 1243 */ 1244 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2); 1245 tmp |= BIT(1); 1246 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp); 1247 1248 /* In MAC power on state, BB and RF maybe in ON state, 1249 * if we release TRx DMA here 1250 * it will cause packets to be started to Tx/Rx, 1251 * so we release Tx/Rx DMA later. 1252 */ 1253 if (!mac_power_on) { 1254 /* 8. release TRX DMA 1255 * write 0x284 bit[18] = 1'b0 1256 * write 0x301 = 0x00 1257 */ 1258 if (release_mac_rx_pause) { 1259 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); 1260 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 1261 (tmp & (~BIT(2)))); 1262 } 1263 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 1264 backup_pcie_dma_pause); 1265 } 1266 1267 /* 9. lock system register 1268 * write 0xCC bit[2] = 1'b0 1269 */ 1270 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); 1271 tmp &= ~(BIT(2)); 1272 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); 1273 } 1274 1275 int rtl92ee_hw_init(struct ieee80211_hw *hw) 1276 { 1277 struct rtl_priv *rtlpriv = rtl_priv(hw); 1278 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1279 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1280 struct rtl_phy *rtlphy = &rtlpriv->phy; 1281 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1282 bool rtstatus = true; 1283 int err = 0; 1284 u8 tmp_u1b, u1byte; 1285 u32 tmp_u4b; 1286 1287 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, " Rtl8192EE hw init\n"); 1288 rtlpriv->rtlhal.being_init_adapter = true; 1289 rtlpriv->intf_ops->disable_aspm(hw); 1290 1291 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1); 1292 u1byte = rtl_read_byte(rtlpriv, REG_CR); 1293 if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) { 1294 rtlhal->mac_func_enable = true; 1295 } else { 1296 rtlhal->mac_func_enable = false; 1297 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E; 1298 } 1299 1300 if (_rtl8192ee_check_pcie_dma_hang(rtlpriv)) { 1301 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "92ee dma hang!\n"); 1302 _rtl8192ee_reset_pcie_interface_dma(rtlpriv, 1303 rtlhal->mac_func_enable); 1304 rtlhal->mac_func_enable = false; 1305 } 1306 1307 rtstatus = _rtl92ee_init_mac(hw); 1308 1309 rtl_write_byte(rtlpriv, 0x577, 0x03); 1310 1311 /*for Crystal 40 Mhz setting */ 1312 rtl_write_byte(rtlpriv, REG_AFE_CTRL4, 0x2A); 1313 rtl_write_byte(rtlpriv, REG_AFE_CTRL4 + 1, 0x00); 1314 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, 0x83); 1315 1316 /*Forced the antenna b to wifi */ 1317 if (rtlpriv->btcoexist.btc_info.btcoexist == 1) { 1318 rtl_write_byte(rtlpriv, 0x64, 0); 1319 rtl_write_byte(rtlpriv, 0x65, 1); 1320 } 1321 if (!rtstatus) { 1322 pr_err("Init MAC failed\n"); 1323 err = 1; 1324 return err; 1325 } 1326 rtlhal->rx_tag = 0; 1327 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, 0x8000); 1328 err = rtl92ee_download_fw(hw, false); 1329 if (err) { 1330 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1331 "Failed to download FW. Init HW without FW now..\n"); 1332 err = 1; 1333 rtlhal->fw_ready = false; 1334 return err; 1335 } 1336 rtlhal->fw_ready = true; 1337 /*fw related variable initialize */ 1338 ppsc->fw_current_inpsmode = false; 1339 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E; 1340 rtlhal->fw_clk_change_in_progress = false; 1341 rtlhal->allow_sw_to_change_hwclc = false; 1342 rtlhal->last_hmeboxnum = 0; 1343 1344 rtl92ee_phy_mac_config(hw); 1345 1346 rtl92ee_phy_bb_config(hw); 1347 1348 rtl92ee_phy_rf_config(hw); 1349 1350 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, RF90_PATH_A, 1351 RF_CHNLBW, RFREG_OFFSET_MASK); 1352 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, RF90_PATH_B, 1353 RF_CHNLBW, RFREG_OFFSET_MASK); 1354 rtlphy->backup_rf_0x1a = (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1, 1355 RFREG_OFFSET_MASK); 1356 rtlphy->rfreg_chnlval[0] = (rtlphy->rfreg_chnlval[0] & 0xfffff3ff) | 1357 BIT(10) | BIT(11); 1358 1359 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 1360 rtlphy->rfreg_chnlval[0]); 1361 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK, 1362 rtlphy->rfreg_chnlval[0]); 1363 1364 /*---- Set CCK and OFDM Block "ON"----*/ 1365 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1366 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1367 1368 /* Must set this, 1369 * otherwise the rx sensitivity will be very pool. Maddest 1370 */ 1371 rtl_set_rfreg(hw, RF90_PATH_A, 0xB1, RFREG_OFFSET_MASK, 0x54418); 1372 1373 /*Set Hardware(MAC default setting.)*/ 1374 _rtl92ee_hw_configure(hw); 1375 1376 rtlhal->mac_func_enable = true; 1377 1378 rtl_cam_reset_all_entry(hw); 1379 rtl92ee_enable_hw_security_config(hw); 1380 1381 ppsc->rfpwr_state = ERFON; 1382 1383 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1384 _rtl92ee_enable_aspm_back_door(hw); 1385 rtlpriv->intf_ops->enable_aspm(hw); 1386 1387 rtl92ee_bt_hw_init(hw); 1388 1389 rtlpriv->rtlhal.being_init_adapter = false; 1390 1391 if (ppsc->rfpwr_state == ERFON) { 1392 if (rtlphy->iqk_initialized) { 1393 rtl92ee_phy_iq_calibrate(hw, true); 1394 } else { 1395 rtl92ee_phy_iq_calibrate(hw, false); 1396 rtlphy->iqk_initialized = true; 1397 } 1398 } 1399 1400 rtlphy->rfpath_rx_enable[0] = true; 1401 if (rtlphy->rf_type == RF_2T2R) 1402 rtlphy->rfpath_rx_enable[1] = true; 1403 1404 efuse_one_byte_read(hw, 0x1FA, &tmp_u1b); 1405 if (!(tmp_u1b & BIT(0))) { 1406 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); 1407 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n"); 1408 } 1409 1410 if ((!(tmp_u1b & BIT(1))) && (rtlphy->rf_type == RF_2T2R)) { 1411 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05); 1412 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path B\n"); 1413 } 1414 1415 rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128)); 1416 1417 /*Fixed LDPC rx hang issue. */ 1418 tmp_u4b = rtl_read_dword(rtlpriv, REG_SYS_SWR_CTRL1); 1419 rtl_write_byte(rtlpriv, REG_SYS_SWR_CTRL2, 0x75); 1420 tmp_u4b = (tmp_u4b & 0xfff00fff) | (0x7E << 12); 1421 rtl_write_dword(rtlpriv, REG_SYS_SWR_CTRL1, tmp_u4b); 1422 1423 rtl92ee_dm_init(hw); 1424 1425 rtl_write_dword(rtlpriv, 0x4fc, 0); 1426 1427 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1428 "end of Rtl8192EE hw init %x\n", err); 1429 return 0; 1430 } 1431 1432 static enum version_8192e _rtl92ee_read_chip_version(struct ieee80211_hw *hw) 1433 { 1434 struct rtl_priv *rtlpriv = rtl_priv(hw); 1435 struct rtl_phy *rtlphy = &rtlpriv->phy; 1436 enum version_8192e version = VERSION_UNKNOWN; 1437 u32 value32; 1438 1439 rtlphy->rf_type = RF_2T2R; 1440 1441 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1); 1442 if (value32 & TRP_VAUX_EN) 1443 version = (enum version_8192e)VERSION_TEST_CHIP_2T2R_8192E; 1444 else 1445 version = (enum version_8192e)VERSION_NORMAL_CHIP_2T2R_8192E; 1446 1447 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1448 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ? 1449 "RF_2T2R" : "RF_1T1R"); 1450 1451 return version; 1452 } 1453 1454 static int _rtl92ee_set_media_status(struct ieee80211_hw *hw, 1455 enum nl80211_iftype type) 1456 { 1457 struct rtl_priv *rtlpriv = rtl_priv(hw); 1458 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc; 1459 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1460 u8 mode = MSR_NOLINK; 1461 1462 switch (type) { 1463 case NL80211_IFTYPE_UNSPECIFIED: 1464 mode = MSR_NOLINK; 1465 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1466 "Set Network type to NO LINK!\n"); 1467 break; 1468 case NL80211_IFTYPE_ADHOC: 1469 case NL80211_IFTYPE_MESH_POINT: 1470 mode = MSR_ADHOC; 1471 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1472 "Set Network type to Ad Hoc!\n"); 1473 break; 1474 case NL80211_IFTYPE_STATION: 1475 mode = MSR_INFRA; 1476 ledaction = LED_CTL_LINK; 1477 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1478 "Set Network type to STA!\n"); 1479 break; 1480 case NL80211_IFTYPE_AP: 1481 mode = MSR_AP; 1482 ledaction = LED_CTL_LINK; 1483 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1484 "Set Network type to AP!\n"); 1485 break; 1486 default: 1487 pr_err("Network type %d not support!\n", type); 1488 return 1; 1489 } 1490 1491 /* MSR_INFRA == Link in infrastructure network; 1492 * MSR_ADHOC == Link in ad hoc network; 1493 * Therefore, check link state is necessary. 1494 * 1495 * MSR_AP == AP mode; link state is not cared here. 1496 */ 1497 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) { 1498 mode = MSR_NOLINK; 1499 ledaction = LED_CTL_NO_LINK; 1500 } 1501 1502 if (mode == MSR_NOLINK || mode == MSR_INFRA) { 1503 _rtl92ee_stop_tx_beacon(hw); 1504 _rtl92ee_enable_bcn_sub_func(hw); 1505 } else if (mode == MSR_ADHOC || mode == MSR_AP) { 1506 _rtl92ee_resume_tx_beacon(hw); 1507 _rtl92ee_disable_bcn_sub_func(hw); 1508 } else { 1509 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1510 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 1511 mode); 1512 } 1513 1514 rtl_write_byte(rtlpriv, MSR, bt_msr | mode); 1515 rtlpriv->cfg->ops->led_control(hw, ledaction); 1516 if (mode == MSR_AP) 1517 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1518 else 1519 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1520 return 0; 1521 } 1522 1523 void rtl92ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1524 { 1525 struct rtl_priv *rtlpriv = rtl_priv(hw); 1526 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1527 u32 reg_rcr = rtlpci->receive_config; 1528 1529 if (rtlpriv->psc.rfpwr_state != ERFON) 1530 return; 1531 1532 if (check_bssid) { 1533 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1534 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1535 (u8 *)(®_rcr)); 1536 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1537 } else { 1538 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1539 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0); 1540 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1541 (u8 *)(®_rcr)); 1542 } 1543 } 1544 1545 int rtl92ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1546 { 1547 struct rtl_priv *rtlpriv = rtl_priv(hw); 1548 1549 if (_rtl92ee_set_media_status(hw, type)) 1550 return -EOPNOTSUPP; 1551 1552 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1553 if (type != NL80211_IFTYPE_AP && 1554 type != NL80211_IFTYPE_MESH_POINT) 1555 rtl92ee_set_check_bssid(hw, true); 1556 } else { 1557 rtl92ee_set_check_bssid(hw, false); 1558 } 1559 1560 return 0; 1561 } 1562 1563 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ 1564 void rtl92ee_set_qos(struct ieee80211_hw *hw, int aci) 1565 { 1566 struct rtl_priv *rtlpriv = rtl_priv(hw); 1567 1568 rtl92ee_dm_init_edca_turbo(hw); 1569 switch (aci) { 1570 case AC1_BK: 1571 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 1572 break; 1573 case AC0_BE: 1574 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */ 1575 break; 1576 case AC2_VI: 1577 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 1578 break; 1579 case AC3_VO: 1580 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 1581 break; 1582 default: 1583 WARN_ONCE(true, "rtl8192ee: invalid aci: %d !\n", aci); 1584 break; 1585 } 1586 } 1587 1588 void rtl92ee_enable_interrupt(struct ieee80211_hw *hw) 1589 { 1590 struct rtl_priv *rtlpriv = rtl_priv(hw); 1591 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1592 1593 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); 1594 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); 1595 rtlpci->irq_enabled = true; 1596 } 1597 1598 void rtl92ee_disable_interrupt(struct ieee80211_hw *hw) 1599 { 1600 struct rtl_priv *rtlpriv = rtl_priv(hw); 1601 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1602 1603 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED); 1604 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED); 1605 rtlpci->irq_enabled = false; 1606 /*synchronize_irq(rtlpci->pdev->irq);*/ 1607 } 1608 1609 static void _rtl92ee_poweroff_adapter(struct ieee80211_hw *hw) 1610 { 1611 struct rtl_priv *rtlpriv = rtl_priv(hw); 1612 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1613 u8 u1b_tmp; 1614 1615 rtlhal->mac_func_enable = false; 1616 1617 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n"); 1618 1619 /* Run LPS WL RFOFF flow */ 1620 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1621 PWR_INTF_PCI_MSK, RTL8192E_NIC_LPS_ENTER_FLOW); 1622 /* turn off RF */ 1623 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); 1624 1625 /* ==== Reset digital sequence ====== */ 1626 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready) 1627 rtl92ee_firmware_selfreset(hw); 1628 1629 /* Reset MCU */ 1630 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 1631 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2)))); 1632 1633 /* reset MCU ready status */ 1634 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1635 1636 /* HW card disable configuration. */ 1637 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, 1638 PWR_INTF_PCI_MSK, RTL8192E_NIC_DISABLE_FLOW); 1639 1640 /* Reset MCU IO Wrapper */ 1641 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1642 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); 1643 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); 1644 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0))); 1645 1646 /* lock ISO/CLK/Power control register */ 1647 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E); 1648 } 1649 1650 void rtl92ee_card_disable(struct ieee80211_hw *hw) 1651 { 1652 struct rtl_priv *rtlpriv = rtl_priv(hw); 1653 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1654 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1655 enum nl80211_iftype opmode; 1656 1657 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8192ee card disable\n"); 1658 1659 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1660 1661 mac->link_state = MAC80211_NOLINK; 1662 opmode = NL80211_IFTYPE_UNSPECIFIED; 1663 1664 _rtl92ee_set_media_status(hw, opmode); 1665 1666 if (rtlpriv->rtlhal.driver_is_goingto_unload || 1667 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1668 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1669 1670 _rtl92ee_poweroff_adapter(hw); 1671 1672 /* after power off we should do iqk again */ 1673 if (!rtlpriv->cfg->ops->get_btc_status()) 1674 rtlpriv->phy.iqk_initialized = false; 1675 } 1676 1677 void rtl92ee_interrupt_recognized(struct ieee80211_hw *hw, 1678 u32 *p_inta, u32 *p_intb) 1679 { 1680 struct rtl_priv *rtlpriv = rtl_priv(hw); 1681 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1682 1683 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 1684 rtl_write_dword(rtlpriv, ISR, *p_inta); 1685 1686 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; 1687 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb); 1688 } 1689 1690 void rtl92ee_set_beacon_related_registers(struct ieee80211_hw *hw) 1691 { 1692 struct rtl_priv *rtlpriv = rtl_priv(hw); 1693 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1694 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1695 u16 bcn_interval, atim_window; 1696 1697 bcn_interval = mac->beacon_interval; 1698 atim_window = 2; /*FIX MERGE */ 1699 rtl92ee_disable_interrupt(hw); 1700 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1701 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1702 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 1703 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 1704 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 1705 rtl_write_byte(rtlpriv, 0x606, 0x30); 1706 rtlpci->reg_bcn_ctrl_val |= BIT(3); 1707 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 1708 } 1709 1710 void rtl92ee_set_beacon_interval(struct ieee80211_hw *hw) 1711 { 1712 struct rtl_priv *rtlpriv = rtl_priv(hw); 1713 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1714 u16 bcn_interval = mac->beacon_interval; 1715 1716 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, 1717 "beacon_interval:%d\n", bcn_interval); 1718 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1719 } 1720 1721 void rtl92ee_update_interrupt_mask(struct ieee80211_hw *hw, 1722 u32 add_msr, u32 rm_msr) 1723 { 1724 struct rtl_priv *rtlpriv = rtl_priv(hw); 1725 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1726 1727 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, 1728 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr); 1729 1730 if (add_msr) 1731 rtlpci->irq_mask[0] |= add_msr; 1732 if (rm_msr) 1733 rtlpci->irq_mask[0] &= (~rm_msr); 1734 rtl92ee_disable_interrupt(hw); 1735 rtl92ee_enable_interrupt(hw); 1736 } 1737 1738 static u8 _rtl92ee_get_chnl_group(u8 chnl) 1739 { 1740 u8 group = 0; 1741 1742 if (chnl <= 14) { 1743 if (1 <= chnl && chnl <= 2) 1744 group = 0; 1745 else if (3 <= chnl && chnl <= 5) 1746 group = 1; 1747 else if (6 <= chnl && chnl <= 8) 1748 group = 2; 1749 else if (9 <= chnl && chnl <= 11) 1750 group = 3; 1751 else if (12 <= chnl && chnl <= 14) 1752 group = 4; 1753 } else { 1754 if (36 <= chnl && chnl <= 42) 1755 group = 0; 1756 else if (44 <= chnl && chnl <= 48) 1757 group = 1; 1758 else if (50 <= chnl && chnl <= 58) 1759 group = 2; 1760 else if (60 <= chnl && chnl <= 64) 1761 group = 3; 1762 else if (100 <= chnl && chnl <= 106) 1763 group = 4; 1764 else if (108 <= chnl && chnl <= 114) 1765 group = 5; 1766 else if (116 <= chnl && chnl <= 122) 1767 group = 6; 1768 else if (124 <= chnl && chnl <= 130) 1769 group = 7; 1770 else if (132 <= chnl && chnl <= 138) 1771 group = 8; 1772 else if (140 <= chnl && chnl <= 144) 1773 group = 9; 1774 else if (149 <= chnl && chnl <= 155) 1775 group = 10; 1776 else if (157 <= chnl && chnl <= 161) 1777 group = 11; 1778 else if (165 <= chnl && chnl <= 171) 1779 group = 12; 1780 else if (173 <= chnl && chnl <= 177) 1781 group = 13; 1782 } 1783 return group; 1784 } 1785 1786 static void _rtl8192ee_read_power_value_fromprom(struct ieee80211_hw *hw, 1787 struct txpower_info_2g *pwr2g, 1788 struct txpower_info_5g *pwr5g, 1789 bool autoload_fail, u8 *hwinfo) 1790 { 1791 struct rtl_priv *rtlpriv = rtl_priv(hw); 1792 u32 rf, addr = EEPROM_TX_PWR_INX, group, i = 0; 1793 1794 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1795 "hal_ReadPowerValueFromPROM92E(): PROMContent[0x%x]=0x%x\n", 1796 (addr + 1), hwinfo[addr + 1]); 1797 if (0xFF == hwinfo[addr+1]) /*YJ,add,120316*/ 1798 autoload_fail = true; 1799 1800 if (autoload_fail) { 1801 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1802 "auto load fail : Use Default value!\n"); 1803 for (rf = 0 ; rf < MAX_RF_PATH ; rf++) { 1804 /* 2.4G default value */ 1805 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 1806 pwr2g->index_cck_base[rf][group] = 0x2D; 1807 pwr2g->index_bw40_base[rf][group] = 0x2D; 1808 } 1809 for (i = 0; i < MAX_TX_COUNT; i++) { 1810 if (i == 0) { 1811 pwr2g->bw20_diff[rf][0] = 0x02; 1812 pwr2g->ofdm_diff[rf][0] = 0x04; 1813 } else { 1814 pwr2g->bw20_diff[rf][i] = 0xFE; 1815 pwr2g->bw40_diff[rf][i] = 0xFE; 1816 pwr2g->cck_diff[rf][i] = 0xFE; 1817 pwr2g->ofdm_diff[rf][i] = 0xFE; 1818 } 1819 } 1820 1821 /*5G default value*/ 1822 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) 1823 pwr5g->index_bw40_base[rf][group] = 0x2A; 1824 1825 for (i = 0; i < MAX_TX_COUNT; i++) { 1826 if (i == 0) { 1827 pwr5g->ofdm_diff[rf][0] = 0x04; 1828 pwr5g->bw20_diff[rf][0] = 0x00; 1829 pwr5g->bw80_diff[rf][0] = 0xFE; 1830 pwr5g->bw160_diff[rf][0] = 0xFE; 1831 } else { 1832 pwr5g->ofdm_diff[rf][0] = 0xFE; 1833 pwr5g->bw20_diff[rf][0] = 0xFE; 1834 pwr5g->bw40_diff[rf][0] = 0xFE; 1835 pwr5g->bw80_diff[rf][0] = 0xFE; 1836 pwr5g->bw160_diff[rf][0] = 0xFE; 1837 } 1838 } 1839 } 1840 return; 1841 } 1842 1843 rtl_priv(hw)->efuse.txpwr_fromeprom = true; 1844 1845 for (rf = 0 ; rf < MAX_RF_PATH ; rf++) { 1846 /*2.4G default value*/ 1847 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) { 1848 pwr2g->index_cck_base[rf][group] = hwinfo[addr++]; 1849 if (pwr2g->index_cck_base[rf][group] == 0xFF) 1850 pwr2g->index_cck_base[rf][group] = 0x2D; 1851 } 1852 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) { 1853 pwr2g->index_bw40_base[rf][group] = hwinfo[addr++]; 1854 if (pwr2g->index_bw40_base[rf][group] == 0xFF) 1855 pwr2g->index_bw40_base[rf][group] = 0x2D; 1856 } 1857 for (i = 0; i < MAX_TX_COUNT; i++) { 1858 if (i == 0) { 1859 pwr2g->bw40_diff[rf][i] = 0; 1860 if (hwinfo[addr] == 0xFF) { 1861 pwr2g->bw20_diff[rf][i] = 0x02; 1862 } else { 1863 pwr2g->bw20_diff[rf][i] = (hwinfo[addr] 1864 & 0xf0) >> 4; 1865 if (pwr2g->bw20_diff[rf][i] & BIT(3)) 1866 pwr2g->bw20_diff[rf][i] |= 0xF0; 1867 } 1868 1869 if (hwinfo[addr] == 0xFF) { 1870 pwr2g->ofdm_diff[rf][i] = 0x04; 1871 } else { 1872 pwr2g->ofdm_diff[rf][i] = (hwinfo[addr] 1873 & 0x0f); 1874 if (pwr2g->ofdm_diff[rf][i] & BIT(3)) 1875 pwr2g->ofdm_diff[rf][i] |= 0xF0; 1876 } 1877 pwr2g->cck_diff[rf][i] = 0; 1878 addr++; 1879 } else { 1880 if (hwinfo[addr] == 0xFF) { 1881 pwr2g->bw40_diff[rf][i] = 0xFE; 1882 } else { 1883 pwr2g->bw40_diff[rf][i] = (hwinfo[addr] 1884 & 0xf0) >> 4; 1885 if (pwr2g->bw40_diff[rf][i] & BIT(3)) 1886 pwr2g->bw40_diff[rf][i] |= 0xF0; 1887 } 1888 1889 if (hwinfo[addr] == 0xFF) { 1890 pwr2g->bw20_diff[rf][i] = 0xFE; 1891 } else { 1892 pwr2g->bw20_diff[rf][i] = (hwinfo[addr] 1893 & 0x0f); 1894 if (pwr2g->bw20_diff[rf][i] & BIT(3)) 1895 pwr2g->bw20_diff[rf][i] |= 0xF0; 1896 } 1897 addr++; 1898 1899 if (hwinfo[addr] == 0xFF) { 1900 pwr2g->ofdm_diff[rf][i] = 0xFE; 1901 } else { 1902 pwr2g->ofdm_diff[rf][i] = (hwinfo[addr] 1903 & 0xf0) >> 4; 1904 if (pwr2g->ofdm_diff[rf][i] & BIT(3)) 1905 pwr2g->ofdm_diff[rf][i] |= 0xF0; 1906 } 1907 1908 if (hwinfo[addr] == 0xFF) { 1909 pwr2g->cck_diff[rf][i] = 0xFE; 1910 } else { 1911 pwr2g->cck_diff[rf][i] = (hwinfo[addr] 1912 & 0x0f); 1913 if (pwr2g->cck_diff[rf][i] & BIT(3)) 1914 pwr2g->cck_diff[rf][i] |= 0xF0; 1915 } 1916 addr++; 1917 } 1918 } 1919 1920 /*5G default value*/ 1921 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) { 1922 pwr5g->index_bw40_base[rf][group] = hwinfo[addr++]; 1923 if (pwr5g->index_bw40_base[rf][group] == 0xFF) 1924 pwr5g->index_bw40_base[rf][group] = 0xFE; 1925 } 1926 1927 for (i = 0; i < MAX_TX_COUNT; i++) { 1928 if (i == 0) { 1929 pwr5g->bw40_diff[rf][i] = 0; 1930 1931 if (hwinfo[addr] == 0xFF) { 1932 pwr5g->bw20_diff[rf][i] = 0; 1933 } else { 1934 pwr5g->bw20_diff[rf][0] = (hwinfo[addr] 1935 & 0xf0) >> 4; 1936 if (pwr5g->bw20_diff[rf][i] & BIT(3)) 1937 pwr5g->bw20_diff[rf][i] |= 0xF0; 1938 } 1939 1940 if (hwinfo[addr] == 0xFF) { 1941 pwr5g->ofdm_diff[rf][i] = 0x04; 1942 } else { 1943 pwr5g->ofdm_diff[rf][0] = (hwinfo[addr] 1944 & 0x0f); 1945 if (pwr5g->ofdm_diff[rf][i] & BIT(3)) 1946 pwr5g->ofdm_diff[rf][i] |= 0xF0; 1947 } 1948 addr++; 1949 } else { 1950 if (hwinfo[addr] == 0xFF) { 1951 pwr5g->bw40_diff[rf][i] = 0xFE; 1952 } else { 1953 pwr5g->bw40_diff[rf][i] = (hwinfo[addr] 1954 & 0xf0) >> 4; 1955 if (pwr5g->bw40_diff[rf][i] & BIT(3)) 1956 pwr5g->bw40_diff[rf][i] |= 0xF0; 1957 } 1958 1959 if (hwinfo[addr] == 0xFF) { 1960 pwr5g->bw20_diff[rf][i] = 0xFE; 1961 } else { 1962 pwr5g->bw20_diff[rf][i] = (hwinfo[addr] 1963 & 0x0f); 1964 if (pwr5g->bw20_diff[rf][i] & BIT(3)) 1965 pwr5g->bw20_diff[rf][i] |= 0xF0; 1966 } 1967 addr++; 1968 } 1969 } 1970 1971 if (hwinfo[addr] == 0xFF) { 1972 pwr5g->ofdm_diff[rf][1] = 0xFE; 1973 pwr5g->ofdm_diff[rf][2] = 0xFE; 1974 } else { 1975 pwr5g->ofdm_diff[rf][1] = (hwinfo[addr] & 0xf0) >> 4; 1976 pwr5g->ofdm_diff[rf][2] = (hwinfo[addr] & 0x0f); 1977 } 1978 addr++; 1979 1980 if (hwinfo[addr] == 0xFF) 1981 pwr5g->ofdm_diff[rf][3] = 0xFE; 1982 else 1983 pwr5g->ofdm_diff[rf][3] = (hwinfo[addr] & 0x0f); 1984 addr++; 1985 1986 for (i = 1; i < MAX_TX_COUNT; i++) { 1987 if (pwr5g->ofdm_diff[rf][i] == 0xFF) 1988 pwr5g->ofdm_diff[rf][i] = 0xFE; 1989 else if (pwr5g->ofdm_diff[rf][i] & BIT(3)) 1990 pwr5g->ofdm_diff[rf][i] |= 0xF0; 1991 } 1992 1993 for (i = 0; i < MAX_TX_COUNT; i++) { 1994 if (hwinfo[addr] == 0xFF) { 1995 pwr5g->bw80_diff[rf][i] = 0xFE; 1996 } else { 1997 pwr5g->bw80_diff[rf][i] = (hwinfo[addr] & 0xf0) 1998 >> 4; 1999 if (pwr5g->bw80_diff[rf][i] & BIT(3)) 2000 pwr5g->bw80_diff[rf][i] |= 0xF0; 2001 } 2002 2003 if (hwinfo[addr] == 0xFF) { 2004 pwr5g->bw160_diff[rf][i] = 0xFE; 2005 } else { 2006 pwr5g->bw160_diff[rf][i] = 2007 (hwinfo[addr] & 0x0f); 2008 if (pwr5g->bw160_diff[rf][i] & BIT(3)) 2009 pwr5g->bw160_diff[rf][i] |= 0xF0; 2010 } 2011 addr++; 2012 } 2013 } 2014 } 2015 2016 static void _rtl92ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 2017 bool autoload_fail, u8 *hwinfo) 2018 { 2019 struct rtl_priv *rtlpriv = rtl_priv(hw); 2020 struct rtl_efuse *efu = rtl_efuse(rtl_priv(hw)); 2021 struct txpower_info_2g pwr2g; 2022 struct txpower_info_5g pwr5g; 2023 u8 rf, idx; 2024 u8 i; 2025 2026 _rtl8192ee_read_power_value_fromprom(hw, &pwr2g, &pwr5g, 2027 autoload_fail, hwinfo); 2028 2029 for (rf = 0; rf < MAX_RF_PATH; rf++) { 2030 for (i = 0; i < 14; i++) { 2031 idx = _rtl92ee_get_chnl_group(i + 1); 2032 2033 if (i == CHANNEL_MAX_NUMBER_2G - 1) { 2034 efu->txpwrlevel_cck[rf][i] = 2035 pwr2g.index_cck_base[rf][5]; 2036 efu->txpwrlevel_ht40_1s[rf][i] = 2037 pwr2g.index_bw40_base[rf][idx]; 2038 } else { 2039 efu->txpwrlevel_cck[rf][i] = 2040 pwr2g.index_cck_base[rf][idx]; 2041 efu->txpwrlevel_ht40_1s[rf][i] = 2042 pwr2g.index_bw40_base[rf][idx]; 2043 } 2044 } 2045 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) { 2046 idx = _rtl92ee_get_chnl_group(channel5g[i]); 2047 efu->txpwr_5g_bw40base[rf][i] = 2048 pwr5g.index_bw40_base[rf][idx]; 2049 } 2050 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) { 2051 u8 upper, lower; 2052 2053 idx = _rtl92ee_get_chnl_group(channel5g_80m[i]); 2054 upper = pwr5g.index_bw40_base[rf][idx]; 2055 lower = pwr5g.index_bw40_base[rf][idx + 1]; 2056 2057 efu->txpwr_5g_bw80base[rf][i] = (upper + lower) / 2; 2058 } 2059 for (i = 0; i < MAX_TX_COUNT; i++) { 2060 efu->txpwr_cckdiff[rf][i] = pwr2g.cck_diff[rf][i]; 2061 efu->txpwr_legacyhtdiff[rf][i] = pwr2g.ofdm_diff[rf][i]; 2062 efu->txpwr_ht20diff[rf][i] = pwr2g.bw20_diff[rf][i]; 2063 efu->txpwr_ht40diff[rf][i] = pwr2g.bw40_diff[rf][i]; 2064 2065 efu->txpwr_5g_ofdmdiff[rf][i] = pwr5g.ofdm_diff[rf][i]; 2066 efu->txpwr_5g_bw20diff[rf][i] = pwr5g.bw20_diff[rf][i]; 2067 efu->txpwr_5g_bw40diff[rf][i] = pwr5g.bw40_diff[rf][i]; 2068 efu->txpwr_5g_bw80diff[rf][i] = pwr5g.bw80_diff[rf][i]; 2069 } 2070 } 2071 2072 if (!autoload_fail) 2073 efu->eeprom_thermalmeter = hwinfo[EEPROM_THERMAL_METER_92E]; 2074 else 2075 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; 2076 2077 if (efu->eeprom_thermalmeter == 0xff || autoload_fail) { 2078 efu->apk_thermalmeterignore = true; 2079 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; 2080 } 2081 2082 efu->thermalmeter[0] = efu->eeprom_thermalmeter; 2083 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 2084 "thermalmeter = 0x%x\n", efu->eeprom_thermalmeter); 2085 2086 if (!autoload_fail) { 2087 efu->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION_92E] 2088 & 0x07; 2089 if (hwinfo[EEPROM_RF_BOARD_OPTION_92E] == 0xFF) 2090 efu->eeprom_regulatory = 0; 2091 } else { 2092 efu->eeprom_regulatory = 0; 2093 } 2094 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 2095 "eeprom_regulatory = 0x%x\n", efu->eeprom_regulatory); 2096 } 2097 2098 static void _rtl92ee_read_adapter_info(struct ieee80211_hw *hw) 2099 { 2100 struct rtl_priv *rtlpriv = rtl_priv(hw); 2101 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2102 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2103 int params[] = {RTL8192E_EEPROM_ID, EEPROM_VID, EEPROM_DID, 2104 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 2105 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 2106 COUNTRY_CODE_WORLD_WIDE_13}; 2107 u8 *hwinfo; 2108 2109 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 2110 if (!hwinfo) 2111 return; 2112 2113 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 2114 goto exit; 2115 2116 if (rtlefuse->eeprom_oemid == 0xFF) 2117 rtlefuse->eeprom_oemid = 0; 2118 2119 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2120 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid); 2121 /* set channel plan from efuse */ 2122 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan; 2123 /*tx power*/ 2124 _rtl92ee_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag, 2125 hwinfo); 2126 2127 rtl92ee_read_bt_coexist_info_from_hwpg(hw, rtlefuse->autoload_failflag, 2128 hwinfo); 2129 2130 /*board type*/ 2131 rtlefuse->board_type = (((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E]) 2132 & 0xE0) >> 5); 2133 if ((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E]) == 0xFF) 2134 rtlefuse->board_type = 0; 2135 2136 rtlhal->board_type = rtlefuse->board_type; 2137 /*parse xtal*/ 2138 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_92E]; 2139 if (hwinfo[EEPROM_XTAL_92E] == 0xFF) 2140 rtlefuse->crystalcap = 0x20; 2141 2142 /*antenna diversity*/ 2143 rtlefuse->antenna_div_type = NO_ANTDIV; 2144 rtlefuse->antenna_div_cfg = 0; 2145 2146 if (rtlhal->oem_id == RT_CID_DEFAULT) { 2147 switch (rtlefuse->eeprom_oemid) { 2148 case EEPROM_CID_DEFAULT: 2149 if (rtlefuse->eeprom_did == 0x818B) { 2150 if ((rtlefuse->eeprom_svid == 0x10EC) && 2151 (rtlefuse->eeprom_smid == 0x001B)) 2152 rtlhal->oem_id = RT_CID_819X_LENOVO; 2153 } else { 2154 rtlhal->oem_id = RT_CID_DEFAULT; 2155 } 2156 break; 2157 default: 2158 rtlhal->oem_id = RT_CID_DEFAULT; 2159 break; 2160 } 2161 } 2162 exit: 2163 kfree(hwinfo); 2164 } 2165 2166 static void _rtl92ee_hal_customized_behavior(struct ieee80211_hw *hw) 2167 { 2168 struct rtl_priv *rtlpriv = rtl_priv(hw); 2169 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2170 2171 rtlpriv->ledctl.led_opendrain = true; 2172 2173 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 2174 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 2175 } 2176 2177 void rtl92ee_read_eeprom_info(struct ieee80211_hw *hw) 2178 { 2179 struct rtl_priv *rtlpriv = rtl_priv(hw); 2180 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2181 struct rtl_phy *rtlphy = &rtlpriv->phy; 2182 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2183 u8 tmp_u1b; 2184 2185 rtlhal->version = _rtl92ee_read_chip_version(hw); 2186 if (get_rf_type(rtlphy) == RF_1T1R) { 2187 rtlpriv->dm.rfpath_rxenable[0] = true; 2188 } else { 2189 rtlpriv->dm.rfpath_rxenable[0] = true; 2190 rtlpriv->dm.rfpath_rxenable[1] = true; 2191 } 2192 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 2193 rtlhal->version); 2194 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 2195 if (tmp_u1b & BIT(4)) { 2196 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 2197 rtlefuse->epromtype = EEPROM_93C46; 2198 } else { 2199 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 2200 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 2201 } 2202 if (tmp_u1b & BIT(5)) { 2203 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 2204 rtlefuse->autoload_failflag = false; 2205 _rtl92ee_read_adapter_info(hw); 2206 } else { 2207 pr_err("Autoload ERR!!\n"); 2208 } 2209 _rtl92ee_hal_customized_behavior(hw); 2210 2211 rtlphy->rfpath_rx_enable[0] = true; 2212 if (rtlphy->rf_type == RF_2T2R) 2213 rtlphy->rfpath_rx_enable[1] = true; 2214 } 2215 2216 static u8 _rtl92ee_mrate_idx_to_arfr_id(struct ieee80211_hw *hw, u8 rate_index) 2217 { 2218 u8 ret = 0; 2219 2220 switch (rate_index) { 2221 case RATR_INX_WIRELESS_NGB: 2222 ret = 0; 2223 break; 2224 case RATR_INX_WIRELESS_N: 2225 case RATR_INX_WIRELESS_NG: 2226 ret = 4; 2227 break; 2228 case RATR_INX_WIRELESS_NB: 2229 ret = 2; 2230 break; 2231 case RATR_INX_WIRELESS_GB: 2232 ret = 6; 2233 break; 2234 case RATR_INX_WIRELESS_G: 2235 ret = 7; 2236 break; 2237 case RATR_INX_WIRELESS_B: 2238 ret = 8; 2239 break; 2240 default: 2241 ret = 0; 2242 break; 2243 } 2244 return ret; 2245 } 2246 2247 static void rtl92ee_update_hal_rate_mask(struct ieee80211_hw *hw, 2248 struct ieee80211_sta *sta, 2249 u8 rssi_level) 2250 { 2251 struct rtl_priv *rtlpriv = rtl_priv(hw); 2252 struct rtl_phy *rtlphy = &rtlpriv->phy; 2253 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2254 struct rtl_sta_info *sta_entry = NULL; 2255 u32 ratr_bitmap; 2256 u8 ratr_index; 2257 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) 2258 ? 1 : 0; 2259 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2260 1 : 0; 2261 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2262 1 : 0; 2263 enum wireless_mode wirelessmode = 0; 2264 bool b_shortgi = false; 2265 u8 rate_mask[7] = {0}; 2266 u8 macid = 0; 2267 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/ 2268 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 2269 wirelessmode = sta_entry->wireless_mode; 2270 if (mac->opmode == NL80211_IFTYPE_STATION || 2271 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2272 curtxbw_40mhz = mac->bw_40; 2273 else if (mac->opmode == NL80211_IFTYPE_AP || 2274 mac->opmode == NL80211_IFTYPE_ADHOC) 2275 macid = sta->aid + 1; 2276 2277 ratr_bitmap = sta->supp_rates[0]; 2278 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2279 ratr_bitmap = 0xfff; 2280 2281 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 2282 sta->ht_cap.mcs.rx_mask[0] << 12); 2283 2284 switch (wirelessmode) { 2285 case WIRELESS_MODE_B: 2286 ratr_index = RATR_INX_WIRELESS_B; 2287 if (ratr_bitmap & 0x0000000c) 2288 ratr_bitmap &= 0x0000000d; 2289 else 2290 ratr_bitmap &= 0x0000000f; 2291 break; 2292 case WIRELESS_MODE_G: 2293 ratr_index = RATR_INX_WIRELESS_GB; 2294 2295 if (rssi_level == 1) 2296 ratr_bitmap &= 0x00000f00; 2297 else if (rssi_level == 2) 2298 ratr_bitmap &= 0x00000ff0; 2299 else 2300 ratr_bitmap &= 0x00000ff5; 2301 break; 2302 case WIRELESS_MODE_N_24G: 2303 if (curtxbw_40mhz) 2304 ratr_index = RATR_INX_WIRELESS_NGB; 2305 else 2306 ratr_index = RATR_INX_WIRELESS_NB; 2307 2308 if (rtlphy->rf_type == RF_1T1R) { 2309 if (curtxbw_40mhz) { 2310 if (rssi_level == 1) 2311 ratr_bitmap &= 0x000f0000; 2312 else if (rssi_level == 2) 2313 ratr_bitmap &= 0x000ff000; 2314 else 2315 ratr_bitmap &= 0x000ff015; 2316 } else { 2317 if (rssi_level == 1) 2318 ratr_bitmap &= 0x000f0000; 2319 else if (rssi_level == 2) 2320 ratr_bitmap &= 0x000ff000; 2321 else 2322 ratr_bitmap &= 0x000ff005; 2323 } 2324 } else { 2325 if (curtxbw_40mhz) { 2326 if (rssi_level == 1) 2327 ratr_bitmap &= 0x0f8f0000; 2328 else if (rssi_level == 2) 2329 ratr_bitmap &= 0x0ffff000; 2330 else 2331 ratr_bitmap &= 0x0ffff015; 2332 } else { 2333 if (rssi_level == 1) 2334 ratr_bitmap &= 0x0f8f0000; 2335 else if (rssi_level == 2) 2336 ratr_bitmap &= 0x0ffff000; 2337 else 2338 ratr_bitmap &= 0x0ffff005; 2339 } 2340 } 2341 2342 if ((curtxbw_40mhz && b_curshortgi_40mhz) || 2343 (!curtxbw_40mhz && b_curshortgi_20mhz)) { 2344 if (macid == 0) 2345 b_shortgi = true; 2346 else if (macid == 1) 2347 b_shortgi = false; 2348 } 2349 break; 2350 default: 2351 ratr_index = RATR_INX_WIRELESS_NGB; 2352 2353 if (rtlphy->rf_type == RF_1T1R) 2354 ratr_bitmap &= 0x000ff0ff; 2355 else 2356 ratr_bitmap &= 0x0f8ff0ff; 2357 break; 2358 } 2359 ratr_index = _rtl92ee_mrate_idx_to_arfr_id(hw, ratr_index); 2360 sta_entry->ratr_index = ratr_index; 2361 2362 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2363 "ratr_bitmap :%x\n", ratr_bitmap); 2364 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 2365 (ratr_index << 28); 2366 rate_mask[0] = macid; 2367 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00); 2368 rate_mask[2] = curtxbw_40mhz; 2369 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff); 2370 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8); 2371 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16); 2372 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24); 2373 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2374 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n", 2375 ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1], 2376 rate_mask[2], rate_mask[3], rate_mask[4], 2377 rate_mask[5], rate_mask[6]); 2378 rtl92ee_fill_h2c_cmd(hw, H2C_92E_RA_MASK, 7, rate_mask); 2379 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0); 2380 } 2381 2382 void rtl92ee_update_hal_rate_tbl(struct ieee80211_hw *hw, 2383 struct ieee80211_sta *sta, u8 rssi_level) 2384 { 2385 struct rtl_priv *rtlpriv = rtl_priv(hw); 2386 2387 if (rtlpriv->dm.useramask) 2388 rtl92ee_update_hal_rate_mask(hw, sta, rssi_level); 2389 } 2390 2391 void rtl92ee_update_channel_access_setting(struct ieee80211_hw *hw) 2392 { 2393 struct rtl_priv *rtlpriv = rtl_priv(hw); 2394 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2395 u16 sifs_timer; 2396 2397 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2398 (u8 *)&mac->slot_time); 2399 if (!mac->ht_enable) 2400 sifs_timer = 0x0a0a; 2401 else 2402 sifs_timer = 0x0e0e; 2403 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2404 } 2405 2406 bool rtl92ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2407 { 2408 *valid = 1; 2409 return true; 2410 } 2411 2412 void rtl92ee_set_key(struct ieee80211_hw *hw, u32 key_index, 2413 u8 *p_macaddr, bool is_group, u8 enc_algo, 2414 bool is_wepkey, bool clear_all) 2415 { 2416 struct rtl_priv *rtlpriv = rtl_priv(hw); 2417 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2418 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2419 u8 *macaddr = p_macaddr; 2420 u32 entry_id = 0; 2421 bool is_pairwise = false; 2422 2423 static u8 cam_const_addr[4][6] = { 2424 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2425 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2426 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2427 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2428 }; 2429 static u8 cam_const_broad[] = { 2430 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2431 }; 2432 2433 if (clear_all) { 2434 u8 idx = 0; 2435 u8 cam_offset = 0; 2436 u8 clear_number = 5; 2437 2438 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2439 2440 for (idx = 0; idx < clear_number; idx++) { 2441 rtl_cam_mark_invalid(hw, cam_offset + idx); 2442 rtl_cam_empty_entry(hw, cam_offset + idx); 2443 2444 if (idx < 5) { 2445 memset(rtlpriv->sec.key_buf[idx], 0, 2446 MAX_KEY_LEN); 2447 rtlpriv->sec.key_len[idx] = 0; 2448 } 2449 } 2450 2451 } else { 2452 switch (enc_algo) { 2453 case WEP40_ENCRYPTION: 2454 enc_algo = CAM_WEP40; 2455 break; 2456 case WEP104_ENCRYPTION: 2457 enc_algo = CAM_WEP104; 2458 break; 2459 case TKIP_ENCRYPTION: 2460 enc_algo = CAM_TKIP; 2461 break; 2462 case AESCCMP_ENCRYPTION: 2463 enc_algo = CAM_AES; 2464 break; 2465 default: 2466 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, 2467 "switch case %#x not processed\n", enc_algo); 2468 enc_algo = CAM_TKIP; 2469 break; 2470 } 2471 2472 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2473 macaddr = cam_const_addr[key_index]; 2474 entry_id = key_index; 2475 } else { 2476 if (is_group) { 2477 macaddr = cam_const_broad; 2478 entry_id = key_index; 2479 } else { 2480 if (mac->opmode == NL80211_IFTYPE_AP || 2481 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 2482 entry_id = rtl_cam_get_free_entry(hw, 2483 p_macaddr); 2484 if (entry_id >= TOTAL_CAM_ENTRY) { 2485 pr_err("Can not find free hw security cam entry\n"); 2486 return; 2487 } 2488 } else { 2489 entry_id = CAM_PAIRWISE_KEY_POSITION; 2490 } 2491 2492 key_index = PAIRWISE_KEYIDX; 2493 is_pairwise = true; 2494 } 2495 } 2496 2497 if (rtlpriv->sec.key_len[key_index] == 0) { 2498 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2499 "delete one entry, entry_id is %d\n", 2500 entry_id); 2501 if (mac->opmode == NL80211_IFTYPE_AP || 2502 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2503 rtl_cam_del_entry(hw, p_macaddr); 2504 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2505 } else { 2506 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2507 "add one entry\n"); 2508 if (is_pairwise) { 2509 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2510 "set Pairwise key\n"); 2511 2512 rtl_cam_add_one_entry(hw, macaddr, key_index, 2513 entry_id, enc_algo, 2514 CAM_CONFIG_NO_USEDK, 2515 rtlpriv->sec.key_buf[key_index]); 2516 } else { 2517 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2518 "set group key\n"); 2519 2520 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2521 rtl_cam_add_one_entry(hw, 2522 rtlefuse->dev_addr, 2523 PAIRWISE_KEYIDX, 2524 CAM_PAIRWISE_KEY_POSITION, 2525 enc_algo, CAM_CONFIG_NO_USEDK, 2526 rtlpriv->sec.key_buf[entry_id]); 2527 } 2528 2529 rtl_cam_add_one_entry(hw, macaddr, key_index, 2530 entry_id, enc_algo, 2531 CAM_CONFIG_NO_USEDK, 2532 rtlpriv->sec.key_buf[entry_id]); 2533 } 2534 } 2535 } 2536 } 2537 2538 void rtl92ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 2539 bool auto_load_fail, u8 *hwinfo) 2540 { 2541 struct rtl_priv *rtlpriv = rtl_priv(hw); 2542 u8 value; 2543 2544 if (!auto_load_fail) { 2545 value = hwinfo[EEPROM_RF_BOARD_OPTION_92E]; 2546 if (((value & 0xe0) >> 5) == 0x1) 2547 rtlpriv->btcoexist.btc_info.btcoexist = 1; 2548 else 2549 rtlpriv->btcoexist.btc_info.btcoexist = 0; 2550 2551 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E; 2552 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X2; 2553 } else { 2554 rtlpriv->btcoexist.btc_info.btcoexist = 1; 2555 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E; 2556 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X1; 2557 } 2558 } 2559 2560 void rtl92ee_bt_reg_init(struct ieee80211_hw *hw) 2561 { 2562 struct rtl_priv *rtlpriv = rtl_priv(hw); 2563 2564 /* 0:Low, 1:High, 2:From Efuse. */ 2565 rtlpriv->btcoexist.reg_bt_iso = 2; 2566 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 2567 rtlpriv->btcoexist.reg_bt_sco = 3; 2568 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 2569 rtlpriv->btcoexist.reg_bt_sco = 0; 2570 } 2571 2572 void rtl92ee_bt_hw_init(struct ieee80211_hw *hw) 2573 { 2574 struct rtl_priv *rtlpriv = rtl_priv(hw); 2575 2576 if (rtlpriv->cfg->ops->get_btc_status()) 2577 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv); 2578 } 2579 2580 void rtl92ee_suspend(struct ieee80211_hw *hw) 2581 { 2582 } 2583 2584 void rtl92ee_resume(struct ieee80211_hw *hw) 2585 { 2586 } 2587 2588 /* Turn on AAP (RCR:bit 0) for promicuous mode. */ 2589 void rtl92ee_allow_all_destaddr(struct ieee80211_hw *hw, 2590 bool allow_all_da, bool write_into_reg) 2591 { 2592 struct rtl_priv *rtlpriv = rtl_priv(hw); 2593 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2594 2595 if (allow_all_da) /* Set BIT0 */ 2596 rtlpci->receive_config |= RCR_AAP; 2597 else /* Clear BIT0 */ 2598 rtlpci->receive_config &= ~RCR_AAP; 2599 2600 if (write_into_reg) 2601 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 2602 2603 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD, 2604 "receive_config=0x%08X, write_into_reg=%d\n", 2605 rtlpci->receive_config, write_into_reg); 2606 } 2607