1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../core.h"
6 #include "../pci.h"
7 #include "../base.h"
8 #include "reg.h"
9 #include "def.h"
10 #include "phy.h"
11 #include "dm.h"
12 #include "hw.h"
13 #include "sw.h"
14 #include "trx.h"
15 #include "led.h"
16 
17 #include <linux/module.h>
18 
19 static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw)
20 {
21 	struct rtl_priv *rtlpriv = rtl_priv(hw);
22 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
23 
24 	/*close ASPM for AMD defaultly */
25 	rtlpci->const_amdpci_aspm = 0;
26 
27 	/*
28 	 * ASPM PS mode.
29 	 * 0 - Disable ASPM,
30 	 * 1 - Enable ASPM without Clock Req,
31 	 * 2 - Enable ASPM with Clock Req,
32 	 * 3 - Alwyas Enable ASPM with Clock Req,
33 	 * 4 - Always Enable ASPM without Clock Req.
34 	 * set defult to RTL8192CE:3 RTL8192E:2
35 	 * */
36 	rtlpci->const_pci_aspm = 3;
37 
38 	/*Setting for PCI-E device */
39 	rtlpci->const_devicepci_aspm_setting = 0x03;
40 
41 	/*Setting for PCI-E bridge */
42 	rtlpci->const_hostpci_aspm_setting = 0x02;
43 
44 	/*
45 	 * In Hw/Sw Radio Off situation.
46 	 * 0 - Default,
47 	 * 1 - From ASPM setting without low Mac Pwr,
48 	 * 2 - From ASPM setting with low Mac Pwr,
49 	 * 3 - Bus D3
50 	 * set default to RTL8192CE:0 RTL8192SE:2
51 	 */
52 	rtlpci->const_hwsw_rfoff_d3 = 0;
53 
54 	/*
55 	 * This setting works for those device with
56 	 * backdoor ASPM setting such as EPHY setting.
57 	 * 0 - Not support ASPM,
58 	 * 1 - Support ASPM,
59 	 * 2 - According to chipset.
60 	 */
61 	rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
62 }
63 
64 static int rtl92d_init_sw_vars(struct ieee80211_hw *hw)
65 {
66 	int err;
67 	u8 tid;
68 	struct rtl_priv *rtlpriv = rtl_priv(hw);
69 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
70 	char *fw_name = "rtlwifi/rtl8192defw.bin";
71 
72 	rtlpriv->dm.dm_initialgain_enable = true;
73 	rtlpriv->dm.dm_flag = 0;
74 	rtlpriv->dm.disable_framebursting = false;
75 	rtlpriv->dm.thermalvalue = 0;
76 	rtlpriv->dm.useramask = true;
77 
78 	/* dual mac */
79 	if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
80 		rtlpriv->phy.current_channel = 36;
81 	else
82 		rtlpriv->phy.current_channel = 1;
83 
84 	if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
85 		rtlpriv->rtlhal.disable_amsdu_8k = true;
86 		/* No long RX - reduce fragmentation */
87 		rtlpci->rxbuffersize = 4096;
88 	}
89 
90 	rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
91 
92 	rtlpci->receive_config = (
93 			RCR_APPFCS
94 			| RCR_AMF
95 			| RCR_ADF
96 			| RCR_APP_MIC
97 			| RCR_APP_ICV
98 			| RCR_AICV
99 			| RCR_ACRC32
100 			| RCR_AB
101 			| RCR_AM
102 			| RCR_APM
103 			| RCR_APP_PHYST_RXFF
104 			| RCR_HTC_LOC_CTRL
105 	);
106 
107 	rtlpci->irq_mask[0] = (u32) (
108 			IMR_ROK
109 			| IMR_VODOK
110 			| IMR_VIDOK
111 			| IMR_BEDOK
112 			| IMR_BKDOK
113 			| IMR_MGNTDOK
114 			| IMR_HIGHDOK
115 			| IMR_BDOK
116 			| IMR_RDU
117 			| IMR_RXFOVW
118 	);
119 
120 	rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD);
121 
122 	/* for LPS & IPS */
123 	rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
124 	rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
125 	rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
126 	if (!rtlpriv->psc.inactiveps)
127 		pr_info("Power Save off (module option)\n");
128 	if (!rtlpriv->psc.fwctrl_lps)
129 		pr_info("FW Power Save off (module option)\n");
130 	rtlpriv->psc.reg_fwctrl_lps = 3;
131 	rtlpriv->psc.reg_max_lps_awakeintvl = 5;
132 	/* for ASPM, you can close aspm through
133 	 * set const_support_pciaspm = 0 */
134 	rtl92d_init_aspm_vars(hw);
135 
136 	if (rtlpriv->psc.reg_fwctrl_lps == 1)
137 		rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
138 	else if (rtlpriv->psc.reg_fwctrl_lps == 2)
139 		rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
140 	else if (rtlpriv->psc.reg_fwctrl_lps == 3)
141 		rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
142 
143 	/* for early mode */
144 	rtlpriv->rtlhal.earlymode_enable = false;
145 	for (tid = 0; tid < 8; tid++)
146 		skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
147 
148 	/* for firmware buf */
149 	rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
150 	if (!rtlpriv->rtlhal.pfirmware) {
151 		pr_err("Can't alloc buffer for fw\n");
152 		return 1;
153 	}
154 
155 	rtlpriv->max_fw_size = 0x8000;
156 	pr_info("Driver for Realtek RTL8192DE WLAN interface\n");
157 	pr_info("Loading firmware file %s\n", fw_name);
158 
159 	/* request fw */
160 	err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
161 				      rtlpriv->io.dev, GFP_KERNEL, hw,
162 				      rtl_fw_cb);
163 	if (err) {
164 		pr_err("Failed to request firmware!\n");
165 		vfree(rtlpriv->rtlhal.pfirmware);
166 		rtlpriv->rtlhal.pfirmware = NULL;
167 		return 1;
168 	}
169 
170 	return 0;
171 }
172 
173 static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw)
174 {
175 	struct rtl_priv *rtlpriv = rtl_priv(hw);
176 	u8 tid;
177 
178 	if (rtlpriv->rtlhal.pfirmware) {
179 		vfree(rtlpriv->rtlhal.pfirmware);
180 		rtlpriv->rtlhal.pfirmware = NULL;
181 	}
182 	for (tid = 0; tid < 8; tid++)
183 		skb_queue_purge(&rtlpriv->mac80211.skb_waitq[tid]);
184 }
185 
186 static struct rtl_hal_ops rtl8192de_hal_ops = {
187 	.init_sw_vars = rtl92d_init_sw_vars,
188 	.deinit_sw_vars = rtl92d_deinit_sw_vars,
189 	.read_eeprom_info = rtl92de_read_eeprom_info,
190 	.interrupt_recognized = rtl92de_interrupt_recognized,
191 	.hw_init = rtl92de_hw_init,
192 	.hw_disable = rtl92de_card_disable,
193 	.hw_suspend = rtl92de_suspend,
194 	.hw_resume = rtl92de_resume,
195 	.enable_interrupt = rtl92de_enable_interrupt,
196 	.disable_interrupt = rtl92de_disable_interrupt,
197 	.set_network_type = rtl92de_set_network_type,
198 	.set_chk_bssid = rtl92de_set_check_bssid,
199 	.set_qos = rtl92de_set_qos,
200 	.set_bcn_reg = rtl92de_set_beacon_related_registers,
201 	.set_bcn_intv = rtl92de_set_beacon_interval,
202 	.update_interrupt_mask = rtl92de_update_interrupt_mask,
203 	.get_hw_reg = rtl92de_get_hw_reg,
204 	.set_hw_reg = rtl92de_set_hw_reg,
205 	.update_rate_tbl = rtl92de_update_hal_rate_tbl,
206 	.fill_tx_desc = rtl92de_tx_fill_desc,
207 	.fill_tx_cmddesc = rtl92de_tx_fill_cmddesc,
208 	.query_rx_desc = rtl92de_rx_query_desc,
209 	.set_channel_access = rtl92de_update_channel_access_setting,
210 	.radio_onoff_checking = rtl92de_gpio_radio_on_off_checking,
211 	.set_bw_mode = rtl92d_phy_set_bw_mode,
212 	.switch_channel = rtl92d_phy_sw_chnl,
213 	.dm_watchdog = rtl92d_dm_watchdog,
214 	.scan_operation_backup = rtl_phy_scan_operation_backup,
215 	.set_rf_power_state = rtl92d_phy_set_rf_power_state,
216 	.led_control = rtl92de_led_control,
217 	.set_desc = rtl92de_set_desc,
218 	.get_desc = rtl92de_get_desc,
219 	.is_tx_desc_closed = rtl92de_is_tx_desc_closed,
220 	.tx_polling = rtl92de_tx_polling,
221 	.enable_hw_sec = rtl92de_enable_hw_security_config,
222 	.set_key = rtl92de_set_key,
223 	.init_sw_leds = rtl92de_init_sw_leds,
224 	.get_bbreg = rtl92d_phy_query_bb_reg,
225 	.set_bbreg = rtl92d_phy_set_bb_reg,
226 	.get_rfreg = rtl92d_phy_query_rf_reg,
227 	.set_rfreg = rtl92d_phy_set_rf_reg,
228 	.linked_set_reg = rtl92d_linked_set_reg,
229 	.get_btc_status = rtl_btc_status_false,
230 };
231 
232 static struct rtl_mod_params rtl92de_mod_params = {
233 	.sw_crypto = false,
234 	.inactiveps = true,
235 	.swctrl_lps = true,
236 	.fwctrl_lps = false,
237 	.aspm_support = 1,
238 	.debug_level = 0,
239 	.debug_mask = 0,
240 };
241 
242 static const struct rtl_hal_cfg rtl92de_hal_cfg = {
243 	.bar_id = 2,
244 	.write_readback = true,
245 	.name = "rtl8192de",
246 	.ops = &rtl8192de_hal_ops,
247 	.mod_params = &rtl92de_mod_params,
248 
249 	.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
250 	.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
251 	.maps[SYS_CLK] = REG_SYS_CLKR,
252 	.maps[MAC_RCR_AM] = RCR_AM,
253 	.maps[MAC_RCR_AB] = RCR_AB,
254 	.maps[MAC_RCR_ACRC32] = RCR_ACRC32,
255 	.maps[MAC_RCR_ACF] = RCR_ACF,
256 	.maps[MAC_RCR_AAP] = RCR_AAP,
257 
258 	.maps[EFUSE_TEST] = REG_EFUSE_TEST,
259 	.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
260 	.maps[EFUSE_CLK] = 0,	/* just for 92se */
261 	.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
262 	.maps[EFUSE_PWC_EV12V] = PWC_EV12V,
263 	.maps[EFUSE_FEN_ELDR] = FEN_ELDR,
264 	.maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
265 	.maps[EFUSE_ANA8M] = 0,	/* just for 92se */
266 	.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
267 	.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
268 	.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
269 
270 	.maps[RWCAM] = REG_CAMCMD,
271 	.maps[WCAMI] = REG_CAMWRITE,
272 	.maps[RCAMO] = REG_CAMREAD,
273 	.maps[CAMDBG] = REG_CAMDBG,
274 	.maps[SECR] = REG_SECCFG,
275 	.maps[SEC_CAM_NONE] = CAM_NONE,
276 	.maps[SEC_CAM_WEP40] = CAM_WEP40,
277 	.maps[SEC_CAM_TKIP] = CAM_TKIP,
278 	.maps[SEC_CAM_AES] = CAM_AES,
279 	.maps[SEC_CAM_WEP104] = CAM_WEP104,
280 
281 	.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
282 	.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
283 	.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
284 	.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
285 	.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
286 	.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
287 	.maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
288 	.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
289 	.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
290 	.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
291 	.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
292 	.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
293 	.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
294 	.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
295 	.maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
296 	.maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
297 
298 	.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
299 	.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
300 	.maps[RTL_IMR_BCNINT] = IMR_BCNINT,
301 	.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
302 	.maps[RTL_IMR_RDU] = IMR_RDU,
303 	.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
304 	.maps[RTL_IMR_BDOK] = IMR_BDOK,
305 	.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
306 	.maps[RTL_IMR_TBDER] = IMR_TBDER,
307 	.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
308 	.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
309 	.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
310 	.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
311 	.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
312 	.maps[RTL_IMR_VODOK] = IMR_VODOK,
313 	.maps[RTL_IMR_ROK] = IMR_ROK,
314 	.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
315 
316 	.maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
317 	.maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
318 	.maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
319 	.maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
320 	.maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
321 	.maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
322 	.maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
323 	.maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
324 	.maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
325 	.maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
326 	.maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
327 	.maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
328 
329 	.maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
330 	.maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
331 };
332 
333 static const struct pci_device_id rtl92de_pci_ids[] = {
334 	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8193, rtl92de_hal_cfg)},
335 	{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x002B, rtl92de_hal_cfg)},
336 	{},
337 };
338 
339 MODULE_DEVICE_TABLE(pci, rtl92de_pci_ids);
340 
341 MODULE_AUTHOR("lizhaoming	<chaoming_li@realsil.com.cn>");
342 MODULE_AUTHOR("Realtek WlanFAE	<wlanfae@realtek.com>");
343 MODULE_AUTHOR("Larry Finger	<Larry.Finger@lwfinger.net>");
344 MODULE_LICENSE("GPL");
345 MODULE_DESCRIPTION("Realtek 8192DE 802.11n Dual Mac PCI wireless");
346 MODULE_FIRMWARE("rtlwifi/rtl8192defw.bin");
347 
348 module_param_named(swenc, rtl92de_mod_params.sw_crypto, bool, 0444);
349 module_param_named(debug_level, rtl92de_mod_params.debug_level, int, 0644);
350 module_param_named(ips, rtl92de_mod_params.inactiveps, bool, 0444);
351 module_param_named(swlps, rtl92de_mod_params.swctrl_lps, bool, 0444);
352 module_param_named(fwlps, rtl92de_mod_params.fwctrl_lps, bool, 0444);
353 module_param_named(aspm, rtl92de_mod_params.aspm_support, int, 0444);
354 module_param_named(debug_mask, rtl92de_mod_params.debug_mask, ullong, 0644);
355 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
356 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
357 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n");
358 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 0)\n");
359 MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
360 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
361 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
362 
363 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
364 
365 static struct pci_driver rtl92de_driver = {
366 	.name = KBUILD_MODNAME,
367 	.id_table = rtl92de_pci_ids,
368 	.probe = rtl_pci_probe,
369 	.remove = rtl_pci_disconnect,
370 	.driver.pm = &rtlwifi_pm_ops,
371 };
372 
373 /* add global spin lock to solve the problem that
374  * Dul mac register operation on the same time */
375 DEFINE_SPINLOCK(globalmutex_power);
376 DEFINE_SPINLOCK(globalmutex_for_fwdownload);
377 DEFINE_SPINLOCK(globalmutex_for_power_and_efuse);
378 
379 static int __init rtl92de_module_init(void)
380 {
381 	int ret = 0;
382 
383 	ret = pci_register_driver(&rtl92de_driver);
384 	if (ret)
385 		WARN_ONCE(true, "rtl8192de: No device found\n");
386 	return ret;
387 }
388 
389 static void __exit rtl92de_module_exit(void)
390 {
391 	pci_unregister_driver(&rtl92de_driver);
392 }
393 
394 module_init(rtl92de_module_init);
395 module_exit(rtl92de_module_exit);
396