1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../core.h" 28 #include "../pci.h" 29 #include "../base.h" 30 #include "reg.h" 31 #include "def.h" 32 #include "phy.h" 33 #include "dm.h" 34 #include "hw.h" 35 #include "sw.h" 36 #include "trx.h" 37 #include "led.h" 38 39 #include <linux/module.h> 40 41 static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw) 42 { 43 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 44 45 /*close ASPM for AMD defaultly */ 46 rtlpci->const_amdpci_aspm = 0; 47 48 /* 49 * ASPM PS mode. 50 * 0 - Disable ASPM, 51 * 1 - Enable ASPM without Clock Req, 52 * 2 - Enable ASPM with Clock Req, 53 * 3 - Alwyas Enable ASPM with Clock Req, 54 * 4 - Always Enable ASPM without Clock Req. 55 * set defult to RTL8192CE:3 RTL8192E:2 56 * */ 57 rtlpci->const_pci_aspm = 3; 58 59 /*Setting for PCI-E device */ 60 rtlpci->const_devicepci_aspm_setting = 0x03; 61 62 /*Setting for PCI-E bridge */ 63 rtlpci->const_hostpci_aspm_setting = 0x02; 64 65 /* 66 * In Hw/Sw Radio Off situation. 67 * 0 - Default, 68 * 1 - From ASPM setting without low Mac Pwr, 69 * 2 - From ASPM setting with low Mac Pwr, 70 * 3 - Bus D3 71 * set default to RTL8192CE:0 RTL8192SE:2 72 */ 73 rtlpci->const_hwsw_rfoff_d3 = 0; 74 75 /* 76 * This setting works for those device with 77 * backdoor ASPM setting such as EPHY setting. 78 * 0 - Not support ASPM, 79 * 1 - Support ASPM, 80 * 2 - According to chipset. 81 */ 82 rtlpci->const_support_pciaspm = 1; 83 } 84 85 static int rtl92d_init_sw_vars(struct ieee80211_hw *hw) 86 { 87 int err; 88 u8 tid; 89 struct rtl_priv *rtlpriv = rtl_priv(hw); 90 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 91 char *fw_name = "rtlwifi/rtl8192defw.bin"; 92 93 rtlpriv->dm.dm_initialgain_enable = true; 94 rtlpriv->dm.dm_flag = 0; 95 rtlpriv->dm.disable_framebursting = false; 96 rtlpriv->dm.thermalvalue = 0; 97 rtlpriv->dm.useramask = true; 98 99 /* dual mac */ 100 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) 101 rtlpriv->phy.current_channel = 36; 102 else 103 rtlpriv->phy.current_channel = 1; 104 105 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) { 106 rtlpriv->rtlhal.disable_amsdu_8k = true; 107 /* No long RX - reduce fragmentation */ 108 rtlpci->rxbuffersize = 4096; 109 } 110 111 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13); 112 113 rtlpci->receive_config = ( 114 RCR_APPFCS 115 | RCR_AMF 116 | RCR_ADF 117 | RCR_APP_MIC 118 | RCR_APP_ICV 119 | RCR_AICV 120 | RCR_ACRC32 121 | RCR_AB 122 | RCR_AM 123 | RCR_APM 124 | RCR_APP_PHYST_RXFF 125 | RCR_HTC_LOC_CTRL 126 ); 127 128 rtlpci->irq_mask[0] = (u32) ( 129 IMR_ROK 130 | IMR_VODOK 131 | IMR_VIDOK 132 | IMR_BEDOK 133 | IMR_BKDOK 134 | IMR_MGNTDOK 135 | IMR_HIGHDOK 136 | IMR_BDOK 137 | IMR_RDU 138 | IMR_RXFOVW 139 ); 140 141 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD); 142 143 /* for LPS & IPS */ 144 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; 145 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; 146 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; 147 if (!rtlpriv->psc.inactiveps) 148 pr_info("Power Save off (module option)\n"); 149 if (!rtlpriv->psc.fwctrl_lps) 150 pr_info("FW Power Save off (module option)\n"); 151 rtlpriv->psc.reg_fwctrl_lps = 3; 152 rtlpriv->psc.reg_max_lps_awakeintvl = 5; 153 /* for ASPM, you can close aspm through 154 * set const_support_pciaspm = 0 */ 155 rtl92d_init_aspm_vars(hw); 156 157 if (rtlpriv->psc.reg_fwctrl_lps == 1) 158 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE; 159 else if (rtlpriv->psc.reg_fwctrl_lps == 2) 160 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE; 161 else if (rtlpriv->psc.reg_fwctrl_lps == 3) 162 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE; 163 164 /* for early mode */ 165 rtlpriv->rtlhal.earlymode_enable = false; 166 for (tid = 0; tid < 8; tid++) 167 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]); 168 169 /* for firmware buf */ 170 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000); 171 if (!rtlpriv->rtlhal.pfirmware) { 172 pr_err("Can't alloc buffer for fw\n"); 173 return 1; 174 } 175 176 rtlpriv->max_fw_size = 0x8000; 177 pr_info("Driver for Realtek RTL8192DE WLAN interface\n"); 178 pr_info("Loading firmware file %s\n", fw_name); 179 180 /* request fw */ 181 err = request_firmware_nowait(THIS_MODULE, 1, fw_name, 182 rtlpriv->io.dev, GFP_KERNEL, hw, 183 rtl_fw_cb); 184 if (err) { 185 pr_err("Failed to request firmware!\n"); 186 vfree(rtlpriv->rtlhal.pfirmware); 187 rtlpriv->rtlhal.pfirmware = NULL; 188 return 1; 189 } 190 191 return 0; 192 } 193 194 static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw) 195 { 196 struct rtl_priv *rtlpriv = rtl_priv(hw); 197 u8 tid; 198 199 if (rtlpriv->rtlhal.pfirmware) { 200 vfree(rtlpriv->rtlhal.pfirmware); 201 rtlpriv->rtlhal.pfirmware = NULL; 202 } 203 for (tid = 0; tid < 8; tid++) 204 skb_queue_purge(&rtlpriv->mac80211.skb_waitq[tid]); 205 } 206 207 static struct rtl_hal_ops rtl8192de_hal_ops = { 208 .init_sw_vars = rtl92d_init_sw_vars, 209 .deinit_sw_vars = rtl92d_deinit_sw_vars, 210 .read_eeprom_info = rtl92de_read_eeprom_info, 211 .interrupt_recognized = rtl92de_interrupt_recognized, 212 .hw_init = rtl92de_hw_init, 213 .hw_disable = rtl92de_card_disable, 214 .hw_suspend = rtl92de_suspend, 215 .hw_resume = rtl92de_resume, 216 .enable_interrupt = rtl92de_enable_interrupt, 217 .disable_interrupt = rtl92de_disable_interrupt, 218 .set_network_type = rtl92de_set_network_type, 219 .set_chk_bssid = rtl92de_set_check_bssid, 220 .set_qos = rtl92de_set_qos, 221 .set_bcn_reg = rtl92de_set_beacon_related_registers, 222 .set_bcn_intv = rtl92de_set_beacon_interval, 223 .update_interrupt_mask = rtl92de_update_interrupt_mask, 224 .get_hw_reg = rtl92de_get_hw_reg, 225 .set_hw_reg = rtl92de_set_hw_reg, 226 .update_rate_tbl = rtl92de_update_hal_rate_tbl, 227 .fill_tx_desc = rtl92de_tx_fill_desc, 228 .fill_tx_cmddesc = rtl92de_tx_fill_cmddesc, 229 .query_rx_desc = rtl92de_rx_query_desc, 230 .set_channel_access = rtl92de_update_channel_access_setting, 231 .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking, 232 .set_bw_mode = rtl92d_phy_set_bw_mode, 233 .switch_channel = rtl92d_phy_sw_chnl, 234 .dm_watchdog = rtl92d_dm_watchdog, 235 .scan_operation_backup = rtl_phy_scan_operation_backup, 236 .set_rf_power_state = rtl92d_phy_set_rf_power_state, 237 .led_control = rtl92de_led_control, 238 .set_desc = rtl92de_set_desc, 239 .get_desc = rtl92de_get_desc, 240 .tx_polling = rtl92de_tx_polling, 241 .enable_hw_sec = rtl92de_enable_hw_security_config, 242 .set_key = rtl92de_set_key, 243 .init_sw_leds = rtl92de_init_sw_leds, 244 .get_bbreg = rtl92d_phy_query_bb_reg, 245 .set_bbreg = rtl92d_phy_set_bb_reg, 246 .get_rfreg = rtl92d_phy_query_rf_reg, 247 .set_rfreg = rtl92d_phy_set_rf_reg, 248 .linked_set_reg = rtl92d_linked_set_reg, 249 .get_btc_status = rtl_btc_status_false, 250 }; 251 252 static struct rtl_mod_params rtl92de_mod_params = { 253 .sw_crypto = false, 254 .inactiveps = true, 255 .swctrl_lps = true, 256 .fwctrl_lps = false, 257 .debug_level = 0, 258 .debug_mask = 0, 259 }; 260 261 static const struct rtl_hal_cfg rtl92de_hal_cfg = { 262 .bar_id = 2, 263 .write_readback = true, 264 .name = "rtl8192de", 265 .ops = &rtl8192de_hal_ops, 266 .mod_params = &rtl92de_mod_params, 267 268 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, 269 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, 270 .maps[SYS_CLK] = REG_SYS_CLKR, 271 .maps[MAC_RCR_AM] = RCR_AM, 272 .maps[MAC_RCR_AB] = RCR_AB, 273 .maps[MAC_RCR_ACRC32] = RCR_ACRC32, 274 .maps[MAC_RCR_ACF] = RCR_ACF, 275 .maps[MAC_RCR_AAP] = RCR_AAP, 276 277 .maps[EFUSE_TEST] = REG_EFUSE_TEST, 278 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, 279 .maps[EFUSE_CLK] = 0, /* just for 92se */ 280 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, 281 .maps[EFUSE_PWC_EV12V] = PWC_EV12V, 282 .maps[EFUSE_FEN_ELDR] = FEN_ELDR, 283 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN, 284 .maps[EFUSE_ANA8M] = 0, /* just for 92se */ 285 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE, 286 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, 287 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, 288 289 .maps[RWCAM] = REG_CAMCMD, 290 .maps[WCAMI] = REG_CAMWRITE, 291 .maps[RCAMO] = REG_CAMREAD, 292 .maps[CAMDBG] = REG_CAMDBG, 293 .maps[SECR] = REG_SECCFG, 294 .maps[SEC_CAM_NONE] = CAM_NONE, 295 .maps[SEC_CAM_WEP40] = CAM_WEP40, 296 .maps[SEC_CAM_TKIP] = CAM_TKIP, 297 .maps[SEC_CAM_AES] = CAM_AES, 298 .maps[SEC_CAM_WEP104] = CAM_WEP104, 299 300 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, 301 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, 302 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, 303 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, 304 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, 305 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, 306 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, 307 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, 308 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, 309 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, 310 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, 311 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, 312 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, 313 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, 314 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2, 315 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1, 316 317 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, 318 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, 319 .maps[RTL_IMR_BCNINT] = IMR_BCNINT, 320 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, 321 .maps[RTL_IMR_RDU] = IMR_RDU, 322 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, 323 .maps[RTL_IMR_BDOK] = IMR_BDOK, 324 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, 325 .maps[RTL_IMR_TBDER] = IMR_TBDER, 326 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, 327 .maps[RTL_IMR_TBDOK] = IMR_TBDOK, 328 .maps[RTL_IMR_BKDOK] = IMR_BKDOK, 329 .maps[RTL_IMR_BEDOK] = IMR_BEDOK, 330 .maps[RTL_IMR_VIDOK] = IMR_VIDOK, 331 .maps[RTL_IMR_VODOK] = IMR_VODOK, 332 .maps[RTL_IMR_ROK] = IMR_ROK, 333 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER), 334 335 .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M, 336 .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M, 337 .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M, 338 .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M, 339 .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M, 340 .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M, 341 .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M, 342 .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M, 343 .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M, 344 .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M, 345 .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M, 346 .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M, 347 348 .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7, 349 .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15, 350 }; 351 352 static const struct pci_device_id rtl92de_pci_ids[] = { 353 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8193, rtl92de_hal_cfg)}, 354 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x002B, rtl92de_hal_cfg)}, 355 {}, 356 }; 357 358 MODULE_DEVICE_TABLE(pci, rtl92de_pci_ids); 359 360 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 361 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 362 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>"); 363 MODULE_LICENSE("GPL"); 364 MODULE_DESCRIPTION("Realtek 8192DE 802.11n Dual Mac PCI wireless"); 365 MODULE_FIRMWARE("rtlwifi/rtl8192defw.bin"); 366 367 module_param_named(swenc, rtl92de_mod_params.sw_crypto, bool, 0444); 368 module_param_named(debug_level, rtl92de_mod_params.debug_level, int, 0644); 369 module_param_named(ips, rtl92de_mod_params.inactiveps, bool, 0444); 370 module_param_named(swlps, rtl92de_mod_params.swctrl_lps, bool, 0444); 371 module_param_named(fwlps, rtl92de_mod_params.fwctrl_lps, bool, 0444); 372 module_param_named(debug_mask, rtl92de_mod_params.debug_mask, ullong, 0644); 373 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); 374 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n"); 375 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n"); 376 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 0)\n"); 377 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)"); 378 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)"); 379 380 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume); 381 382 static struct pci_driver rtl92de_driver = { 383 .name = KBUILD_MODNAME, 384 .id_table = rtl92de_pci_ids, 385 .probe = rtl_pci_probe, 386 .remove = rtl_pci_disconnect, 387 .driver.pm = &rtlwifi_pm_ops, 388 }; 389 390 /* add global spin lock to solve the problem that 391 * Dul mac register operation on the same time */ 392 spinlock_t globalmutex_power; 393 spinlock_t globalmutex_for_fwdownload; 394 spinlock_t globalmutex_for_power_and_efuse; 395 396 static int __init rtl92de_module_init(void) 397 { 398 int ret = 0; 399 400 spin_lock_init(&globalmutex_power); 401 spin_lock_init(&globalmutex_for_fwdownload); 402 spin_lock_init(&globalmutex_for_power_and_efuse); 403 404 ret = pci_register_driver(&rtl92de_driver); 405 if (ret) 406 WARN_ONCE(true, "rtl8192de: No device found\n"); 407 return ret; 408 } 409 410 static void __exit rtl92de_module_exit(void) 411 { 412 pci_unregister_driver(&rtl92de_driver); 413 } 414 415 module_init(rtl92de_module_init); 416 module_exit(rtl92de_module_exit); 417