1f1d2b4d3SLarry Finger /****************************************************************************** 2f1d2b4d3SLarry Finger * 3f1d2b4d3SLarry Finger * Copyright(c) 2009-2012 Realtek Corporation. 4f1d2b4d3SLarry Finger * 5f1d2b4d3SLarry Finger * This program is free software; you can redistribute it and/or modify it 6f1d2b4d3SLarry Finger * under the terms of version 2 of the GNU General Public License as 7f1d2b4d3SLarry Finger * published by the Free Software Foundation. 8f1d2b4d3SLarry Finger * 9f1d2b4d3SLarry Finger * This program is distributed in the hope that it will be useful, but WITHOUT 10f1d2b4d3SLarry Finger * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11f1d2b4d3SLarry Finger * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12f1d2b4d3SLarry Finger * more details. 13f1d2b4d3SLarry Finger * 14f1d2b4d3SLarry Finger * You should have received a copy of the GNU General Public License along with 15f1d2b4d3SLarry Finger * this program; if not, write to the Free Software Foundation, Inc., 16f1d2b4d3SLarry Finger * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17f1d2b4d3SLarry Finger * 18f1d2b4d3SLarry Finger * The full GNU General Public License is included in this distribution in the 19f1d2b4d3SLarry Finger * file called LICENSE. 20f1d2b4d3SLarry Finger * 21f1d2b4d3SLarry Finger * Contact Information: 22f1d2b4d3SLarry Finger * wlanfae <wlanfae@realtek.com> 23f1d2b4d3SLarry Finger * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24f1d2b4d3SLarry Finger * Hsinchu 300, Taiwan. 25f1d2b4d3SLarry Finger * 26f1d2b4d3SLarry Finger * Larry Finger <Larry.Finger@lwfinger.net> 27f1d2b4d3SLarry Finger * 28f1d2b4d3SLarry Finger *****************************************************************************/ 29f1d2b4d3SLarry Finger 30f1d2b4d3SLarry Finger #ifndef __RTL92D_REG_H__ 31f1d2b4d3SLarry Finger #define __RTL92D_REG_H__ 32f1d2b4d3SLarry Finger 33f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 34f1d2b4d3SLarry Finger /* 0x0000h ~ 0x00FFh System Configuration */ 35f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 36f1d2b4d3SLarry Finger #define REG_SYS_ISO_CTRL 0x0000 37f1d2b4d3SLarry Finger #define REG_SYS_FUNC_EN 0x0002 38f1d2b4d3SLarry Finger #define REG_APS_FSMCO 0x0004 39f1d2b4d3SLarry Finger #define REG_SYS_CLKR 0x0008 40f1d2b4d3SLarry Finger #define REG_9346CR 0x000A 41f1d2b4d3SLarry Finger #define REG_EE_VPD 0x000C 42f1d2b4d3SLarry Finger #define REG_AFE_MISC 0x0010 43f1d2b4d3SLarry Finger #define REG_SPS0_CTRL 0x0011 44f1d2b4d3SLarry Finger #define REG_POWER_OFF_IN_PROCESS 0x0017 45f1d2b4d3SLarry Finger #define REG_SPS_OCP_CFG 0x0018 46f1d2b4d3SLarry Finger #define REG_RSV_CTRL 0x001C 47f1d2b4d3SLarry Finger #define REG_RF_CTRL 0x001F 48f1d2b4d3SLarry Finger #define REG_LDOA15_CTRL 0x0020 49f1d2b4d3SLarry Finger #define REG_LDOV12D_CTRL 0x0021 50f1d2b4d3SLarry Finger #define REG_LDOHCI12_CTRL 0x0022 51f1d2b4d3SLarry Finger #define REG_LPLDO_CTRL 0x0023 52f1d2b4d3SLarry Finger #define REG_AFE_XTAL_CTRL 0x0024 53f1d2b4d3SLarry Finger #define REG_AFE_PLL_CTRL 0x0028 54f1d2b4d3SLarry Finger /* for 92d, DMDP,SMSP,DMSP contrl */ 55f1d2b4d3SLarry Finger #define REG_MAC_PHY_CTRL 0x002c 56f1d2b4d3SLarry Finger #define REG_EFUSE_CTRL 0x0030 57f1d2b4d3SLarry Finger #define REG_EFUSE_TEST 0x0034 58f1d2b4d3SLarry Finger #define REG_PWR_DATA 0x0038 59f1d2b4d3SLarry Finger #define REG_CAL_TIMER 0x003C 60f1d2b4d3SLarry Finger #define REG_ACLK_MON 0x003E 61f1d2b4d3SLarry Finger #define REG_GPIO_MUXCFG 0x0040 62f1d2b4d3SLarry Finger #define REG_GPIO_IO_SEL 0x0042 63f1d2b4d3SLarry Finger #define REG_MAC_PINMUX_CFG 0x0043 64f1d2b4d3SLarry Finger #define REG_GPIO_PIN_CTRL 0x0044 65f1d2b4d3SLarry Finger #define REG_GPIO_INTM 0x0048 66f1d2b4d3SLarry Finger #define REG_LEDCFG0 0x004C 67f1d2b4d3SLarry Finger #define REG_LEDCFG1 0x004D 68f1d2b4d3SLarry Finger #define REG_LEDCFG2 0x004E 69f1d2b4d3SLarry Finger #define REG_LEDCFG3 0x004F 70f1d2b4d3SLarry Finger #define REG_FSIMR 0x0050 71f1d2b4d3SLarry Finger #define REG_FSISR 0x0054 72f1d2b4d3SLarry Finger 73f1d2b4d3SLarry Finger #define REG_MCUFWDL 0x0080 74f1d2b4d3SLarry Finger 75f1d2b4d3SLarry Finger #define REG_HMEBOX_EXT_0 0x0088 76f1d2b4d3SLarry Finger #define REG_HMEBOX_EXT_1 0x008A 77f1d2b4d3SLarry Finger #define REG_HMEBOX_EXT_2 0x008C 78f1d2b4d3SLarry Finger #define REG_HMEBOX_EXT_3 0x008E 79f1d2b4d3SLarry Finger 80f1d2b4d3SLarry Finger #define REG_BIST_SCAN 0x00D0 81f1d2b4d3SLarry Finger #define REG_BIST_RPT 0x00D4 82f1d2b4d3SLarry Finger #define REG_BIST_ROM_RPT 0x00D8 83f1d2b4d3SLarry Finger #define REG_USB_SIE_INTF 0x00E0 84f1d2b4d3SLarry Finger #define REG_PCIE_MIO_INTF 0x00E4 85f1d2b4d3SLarry Finger #define REG_PCIE_MIO_INTD 0x00E8 86f1d2b4d3SLarry Finger #define REG_HPON_FSM 0x00EC 87f1d2b4d3SLarry Finger #define REG_SYS_CFG 0x00F0 88f1d2b4d3SLarry Finger #define REG_MAC_PHY_CTRL_NORMAL 0x00f8 89f1d2b4d3SLarry Finger 90f1d2b4d3SLarry Finger #define REG_MAC0 0x0081 91f1d2b4d3SLarry Finger #define REG_MAC1 0x0053 92f1d2b4d3SLarry Finger #define FW_MAC0_READY 0x18 93f1d2b4d3SLarry Finger #define FW_MAC1_READY 0x1A 94f1d2b4d3SLarry Finger #define MAC0_ON BIT(7) 95f1d2b4d3SLarry Finger #define MAC1_ON BIT(0) 96f1d2b4d3SLarry Finger #define MAC0_READY BIT(0) 97f1d2b4d3SLarry Finger #define MAC1_READY BIT(0) 98f1d2b4d3SLarry Finger 99f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 100f1d2b4d3SLarry Finger /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ 101f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 102f1d2b4d3SLarry Finger #define REG_CR 0x0100 103f1d2b4d3SLarry Finger #define REG_PBP 0x0104 104f1d2b4d3SLarry Finger #define REG_TRXDMA_CTRL 0x010C 105f1d2b4d3SLarry Finger #define REG_TRXFF_BNDY 0x0114 106f1d2b4d3SLarry Finger #define REG_TRXFF_STATUS 0x0118 107f1d2b4d3SLarry Finger #define REG_RXFF_PTR 0x011C 108f1d2b4d3SLarry Finger #define REG_HIMR 0x0120 109f1d2b4d3SLarry Finger #define REG_HISR 0x0124 110f1d2b4d3SLarry Finger #define REG_HIMRE 0x0128 111f1d2b4d3SLarry Finger #define REG_HISRE 0x012C 112f1d2b4d3SLarry Finger #define REG_CPWM 0x012F 113f1d2b4d3SLarry Finger #define REG_FWIMR 0x0130 114f1d2b4d3SLarry Finger #define REG_FWISR 0x0134 115f1d2b4d3SLarry Finger #define REG_PKTBUF_DBG_CTRL 0x0140 116f1d2b4d3SLarry Finger #define REG_PKTBUF_DBG_DATA_L 0x0144 117f1d2b4d3SLarry Finger #define REG_PKTBUF_DBG_DATA_H 0x0148 118f1d2b4d3SLarry Finger 119f1d2b4d3SLarry Finger #define REG_TC0_CTRL 0x0150 120f1d2b4d3SLarry Finger #define REG_TC1_CTRL 0x0154 121f1d2b4d3SLarry Finger #define REG_TC2_CTRL 0x0158 122f1d2b4d3SLarry Finger #define REG_TC3_CTRL 0x015C 123f1d2b4d3SLarry Finger #define REG_TC4_CTRL 0x0160 124f1d2b4d3SLarry Finger #define REG_TCUNIT_BASE 0x0164 125f1d2b4d3SLarry Finger #define REG_MBIST_START 0x0174 126f1d2b4d3SLarry Finger #define REG_MBIST_DONE 0x0178 127f1d2b4d3SLarry Finger #define REG_MBIST_FAIL 0x017C 128f1d2b4d3SLarry Finger #define REG_C2HEVT_MSG_NORMAL 0x01A0 129f1d2b4d3SLarry Finger #define REG_C2HEVT_MSG_TEST 0x01B8 130f1d2b4d3SLarry Finger #define REG_C2HEVT_CLEAR 0x01BF 131f1d2b4d3SLarry Finger #define REG_MCUTST_1 0x01c0 132f1d2b4d3SLarry Finger #define REG_FMETHR 0x01C8 133f1d2b4d3SLarry Finger #define REG_HMETFR 0x01CC 134f1d2b4d3SLarry Finger #define REG_HMEBOX_0 0x01D0 135f1d2b4d3SLarry Finger #define REG_HMEBOX_1 0x01D4 136f1d2b4d3SLarry Finger #define REG_HMEBOX_2 0x01D8 137f1d2b4d3SLarry Finger #define REG_HMEBOX_3 0x01DC 138f1d2b4d3SLarry Finger 139f1d2b4d3SLarry Finger #define REG_LLT_INIT 0x01E0 140f1d2b4d3SLarry Finger #define REG_BB_ACCEESS_CTRL 0x01E8 141f1d2b4d3SLarry Finger #define REG_BB_ACCESS_DATA 0x01EC 142f1d2b4d3SLarry Finger 143f1d2b4d3SLarry Finger 144f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 145f1d2b4d3SLarry Finger /* 0x0200h ~ 0x027Fh TXDMA Configuration */ 146f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 147f1d2b4d3SLarry Finger #define REG_RQPN 0x0200 148f1d2b4d3SLarry Finger #define REG_FIFOPAGE 0x0204 149f1d2b4d3SLarry Finger #define REG_TDECTRL 0x0208 150f1d2b4d3SLarry Finger #define REG_TXDMA_OFFSET_CHK 0x020C 151f1d2b4d3SLarry Finger #define REG_TXDMA_STATUS 0x0210 152f1d2b4d3SLarry Finger #define REG_RQPN_NPQ 0x0214 153f1d2b4d3SLarry Finger 154f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 155f1d2b4d3SLarry Finger /* 0x0280h ~ 0x02FFh RXDMA Configuration */ 156f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 157f1d2b4d3SLarry Finger #define REG_RXDMA_AGG_PG_TH 0x0280 158f1d2b4d3SLarry Finger #define REG_RXPKT_NUM 0x0284 159f1d2b4d3SLarry Finger #define REG_RXDMA_STATUS 0x0288 160f1d2b4d3SLarry Finger 161f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 162f1d2b4d3SLarry Finger /* 0x0300h ~ 0x03FFh PCIe */ 163f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 164f1d2b4d3SLarry Finger #define REG_PCIE_CTRL_REG 0x0300 165f1d2b4d3SLarry Finger #define REG_INT_MIG 0x0304 166f1d2b4d3SLarry Finger #define REG_BCNQ_DESA 0x0308 167f1d2b4d3SLarry Finger #define REG_HQ_DESA 0x0310 168f1d2b4d3SLarry Finger #define REG_MGQ_DESA 0x0318 169f1d2b4d3SLarry Finger #define REG_VOQ_DESA 0x0320 170f1d2b4d3SLarry Finger #define REG_VIQ_DESA 0x0328 171f1d2b4d3SLarry Finger #define REG_BEQ_DESA 0x0330 172f1d2b4d3SLarry Finger #define REG_BKQ_DESA 0x0338 173f1d2b4d3SLarry Finger #define REG_RX_DESA 0x0340 174f1d2b4d3SLarry Finger #define REG_DBI 0x0348 175f1d2b4d3SLarry Finger #define REG_DBI_WDATA 0x0348 176f1d2b4d3SLarry Finger #define REG_DBI_RDATA 0x034C 177f1d2b4d3SLarry Finger #define REG_DBI_CTRL 0x0350 178f1d2b4d3SLarry Finger #define REG_DBI_FLAG 0x0352 179f1d2b4d3SLarry Finger #define REG_MDIO 0x0354 180f1d2b4d3SLarry Finger #define REG_DBG_SEL 0x0360 181f1d2b4d3SLarry Finger #define REG_PCIE_HRPWM 0x0361 182f1d2b4d3SLarry Finger #define REG_PCIE_HCPWM 0x0363 183f1d2b4d3SLarry Finger #define REG_UART_CTRL 0x0364 184f1d2b4d3SLarry Finger #define REG_UART_TX_DESA 0x0370 185f1d2b4d3SLarry Finger #define REG_UART_RX_DESA 0x0378 186f1d2b4d3SLarry Finger 187f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 188f1d2b4d3SLarry Finger /* 0x0400h ~ 0x047Fh Protocol Configuration */ 189f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 190f1d2b4d3SLarry Finger #define REG_VOQ_INFORMATION 0x0400 191f1d2b4d3SLarry Finger #define REG_VIQ_INFORMATION 0x0404 192f1d2b4d3SLarry Finger #define REG_BEQ_INFORMATION 0x0408 193f1d2b4d3SLarry Finger #define REG_BKQ_INFORMATION 0x040C 194f1d2b4d3SLarry Finger #define REG_MGQ_INFORMATION 0x0410 195f1d2b4d3SLarry Finger #define REG_HGQ_INFORMATION 0x0414 196f1d2b4d3SLarry Finger #define REG_BCNQ_INFORMATION 0x0418 197f1d2b4d3SLarry Finger 198f1d2b4d3SLarry Finger 199f1d2b4d3SLarry Finger #define REG_CPU_MGQ_INFORMATION 0x041C 200f1d2b4d3SLarry Finger #define REG_FWHW_TXQ_CTRL 0x0420 201f1d2b4d3SLarry Finger #define REG_HWSEQ_CTRL 0x0423 202f1d2b4d3SLarry Finger #define REG_TXPKTBUF_BCNQ_BDNY 0x0424 203f1d2b4d3SLarry Finger #define REG_TXPKTBUF_MGQ_BDNY 0x0425 204f1d2b4d3SLarry Finger #define REG_MULTI_BCNQ_EN 0x0426 205f1d2b4d3SLarry Finger #define REG_MULTI_BCNQ_OFFSET 0x0427 206f1d2b4d3SLarry Finger #define REG_SPEC_SIFS 0x0428 207f1d2b4d3SLarry Finger #define REG_RL 0x042A 208f1d2b4d3SLarry Finger #define REG_DARFRC 0x0430 209f1d2b4d3SLarry Finger #define REG_RARFRC 0x0438 210f1d2b4d3SLarry Finger #define REG_RRSR 0x0440 211f1d2b4d3SLarry Finger #define REG_ARFR0 0x0444 212f1d2b4d3SLarry Finger #define REG_ARFR1 0x0448 213f1d2b4d3SLarry Finger #define REG_ARFR2 0x044C 214f1d2b4d3SLarry Finger #define REG_ARFR3 0x0450 215f1d2b4d3SLarry Finger #define REG_AGGLEN_LMT 0x0458 216f1d2b4d3SLarry Finger #define REG_AMPDU_MIN_SPACE 0x045C 217f1d2b4d3SLarry Finger #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 218f1d2b4d3SLarry Finger #define REG_FAST_EDCA_CTRL 0x0460 219f1d2b4d3SLarry Finger #define REG_RD_RESP_PKT_TH 0x0463 220f1d2b4d3SLarry Finger #define REG_INIRTS_RATE_SEL 0x0480 221f1d2b4d3SLarry Finger #define REG_INIDATA_RATE_SEL 0x0484 222f1d2b4d3SLarry Finger #define REG_POWER_STATUS 0x04A4 223f1d2b4d3SLarry Finger #define REG_POWER_STAGE1 0x04B4 224f1d2b4d3SLarry Finger #define REG_POWER_STAGE2 0x04B8 225f1d2b4d3SLarry Finger #define REG_PKT_LIFE_TIME 0x04C0 226f1d2b4d3SLarry Finger #define REG_STBC_SETTING 0x04C4 227f1d2b4d3SLarry Finger #define REG_PROT_MODE_CTRL 0x04C8 228f1d2b4d3SLarry Finger #define REG_MAX_AGGR_NUM 0x04CA 229f1d2b4d3SLarry Finger #define REG_RTS_MAX_AGGR_NUM 0x04CB 230f1d2b4d3SLarry Finger #define REG_BAR_MODE_CTRL 0x04CC 231f1d2b4d3SLarry Finger #define REG_RA_TRY_RATE_AGG_LMT 0x04CF 232f1d2b4d3SLarry Finger #define REG_EARLY_MODE_CONTROL 0x4D0 233f1d2b4d3SLarry Finger #define REG_NQOS_SEQ 0x04DC 234f1d2b4d3SLarry Finger #define REG_QOS_SEQ 0x04DE 235f1d2b4d3SLarry Finger #define REG_NEED_CPU_HANDLE 0x04E0 236f1d2b4d3SLarry Finger #define REG_PKT_LOSE_RPT 0x04E1 237f1d2b4d3SLarry Finger #define REG_PTCL_ERR_STATUS 0x04E2 238f1d2b4d3SLarry Finger #define REG_DUMMY 0x04FC 239f1d2b4d3SLarry Finger 240f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 241f1d2b4d3SLarry Finger /* 0x0500h ~ 0x05FFh EDCA Configuration */ 242f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 243f1d2b4d3SLarry Finger #define REG_EDCA_VO_PARAM 0x0500 244f1d2b4d3SLarry Finger #define REG_EDCA_VI_PARAM 0x0504 245f1d2b4d3SLarry Finger #define REG_EDCA_BE_PARAM 0x0508 246f1d2b4d3SLarry Finger #define REG_EDCA_BK_PARAM 0x050C 247f1d2b4d3SLarry Finger #define REG_BCNTCFG 0x0510 248f1d2b4d3SLarry Finger #define REG_PIFS 0x0512 249f1d2b4d3SLarry Finger #define REG_RDG_PIFS 0x0513 250f1d2b4d3SLarry Finger #define REG_SIFS_CTX 0x0514 251f1d2b4d3SLarry Finger #define REG_SIFS_TRX 0x0516 252f1d2b4d3SLarry Finger #define REG_AGGR_BREAK_TIME 0x051A 253f1d2b4d3SLarry Finger #define REG_SLOT 0x051B 254f1d2b4d3SLarry Finger #define REG_TX_PTCL_CTRL 0x0520 255f1d2b4d3SLarry Finger #define REG_TXPAUSE 0x0522 256f1d2b4d3SLarry Finger #define REG_DIS_TXREQ_CLR 0x0523 257f1d2b4d3SLarry Finger #define REG_RD_CTRL 0x0524 258f1d2b4d3SLarry Finger #define REG_TBTT_PROHIBIT 0x0540 259f1d2b4d3SLarry Finger #define REG_RD_NAV_NXT 0x0544 260f1d2b4d3SLarry Finger #define REG_NAV_PROT_LEN 0x0546 261f1d2b4d3SLarry Finger #define REG_BCN_CTRL 0x0550 262f1d2b4d3SLarry Finger #define REG_USTIME_TSF 0x0551 263f1d2b4d3SLarry Finger #define REG_MBID_NUM 0x0552 264f1d2b4d3SLarry Finger #define REG_DUAL_TSF_RST 0x0553 265f1d2b4d3SLarry Finger #define REG_BCN_INTERVAL 0x0554 266f1d2b4d3SLarry Finger #define REG_MBSSID_BCN_SPACE 0x0554 267f1d2b4d3SLarry Finger #define REG_DRVERLYINT 0x0558 268f1d2b4d3SLarry Finger #define REG_BCNDMATIM 0x0559 269f1d2b4d3SLarry Finger #define REG_ATIMWND 0x055A 270f1d2b4d3SLarry Finger #define REG_BCN_MAX_ERR 0x055D 271f1d2b4d3SLarry Finger #define REG_RXTSF_OFFSET_CCK 0x055E 272f1d2b4d3SLarry Finger #define REG_RXTSF_OFFSET_OFDM 0x055F 273f1d2b4d3SLarry Finger #define REG_TSFTR 0x0560 274f1d2b4d3SLarry Finger #define REG_INIT_TSFTR 0x0564 275f1d2b4d3SLarry Finger #define REG_PSTIMER 0x0580 276f1d2b4d3SLarry Finger #define REG_TIMER0 0x0584 277f1d2b4d3SLarry Finger #define REG_TIMER1 0x0588 278f1d2b4d3SLarry Finger #define REG_ACMHWCTRL 0x05C0 279f1d2b4d3SLarry Finger #define REG_ACMRSTCTRL 0x05C1 280f1d2b4d3SLarry Finger #define REG_ACMAVG 0x05C2 281f1d2b4d3SLarry Finger #define REG_VO_ADMTIME 0x05C4 282f1d2b4d3SLarry Finger #define REG_VI_ADMTIME 0x05C6 283f1d2b4d3SLarry Finger #define REG_BE_ADMTIME 0x05C8 284f1d2b4d3SLarry Finger #define REG_EDCA_RANDOM_GEN 0x05CC 285f1d2b4d3SLarry Finger #define REG_SCH_TXCMD 0x05D0 286f1d2b4d3SLarry Finger 287f1d2b4d3SLarry Finger /* Dual MAC Co-Existence Register */ 288f1d2b4d3SLarry Finger #define REG_DMC 0x05F0 289f1d2b4d3SLarry Finger 290f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 291f1d2b4d3SLarry Finger /* 0x0600h ~ 0x07FFh WMAC Configuration */ 292f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 293f1d2b4d3SLarry Finger #define REG_APSD_CTRL 0x0600 294f1d2b4d3SLarry Finger #define REG_BWOPMODE 0x0603 295f1d2b4d3SLarry Finger #define REG_TCR 0x0604 296f1d2b4d3SLarry Finger #define REG_RCR 0x0608 297f1d2b4d3SLarry Finger #define REG_RX_PKT_LIMIT 0x060C 298f1d2b4d3SLarry Finger #define REG_RX_DLK_TIME 0x060D 299f1d2b4d3SLarry Finger #define REG_RX_DRVINFO_SZ 0x060F 300f1d2b4d3SLarry Finger 301f1d2b4d3SLarry Finger #define REG_MACID 0x0610 302f1d2b4d3SLarry Finger #define REG_BSSID 0x0618 303f1d2b4d3SLarry Finger #define REG_MAR 0x0620 304f1d2b4d3SLarry Finger #define REG_MBIDCAMCFG 0x0628 305f1d2b4d3SLarry Finger 306f1d2b4d3SLarry Finger #define REG_USTIME_EDCA 0x0638 307f1d2b4d3SLarry Finger #define REG_MAC_SPEC_SIFS 0x063A 308f1d2b4d3SLarry Finger #define REG_RESP_SIFS_CCK 0x063C 309f1d2b4d3SLarry Finger #define REG_RESP_SIFS_OFDM 0x063E 310f1d2b4d3SLarry Finger #define REG_ACKTO 0x0640 311f1d2b4d3SLarry Finger #define REG_CTS2TO 0x0641 312f1d2b4d3SLarry Finger #define REG_EIFS 0x0642 313f1d2b4d3SLarry Finger 314f1d2b4d3SLarry Finger 315f1d2b4d3SLarry Finger /* WMA, BA, CCX */ 316f1d2b4d3SLarry Finger #define REG_NAV_CTRL 0x0650 317f1d2b4d3SLarry Finger #define REG_BACAMCMD 0x0654 318f1d2b4d3SLarry Finger #define REG_BACAMCONTENT 0x0658 319f1d2b4d3SLarry Finger #define REG_LBDLY 0x0660 320f1d2b4d3SLarry Finger #define REG_FWDLY 0x0661 321f1d2b4d3SLarry Finger #define REG_RXERR_RPT 0x0664 322f1d2b4d3SLarry Finger #define REG_WMAC_TRXPTCL_CTL 0x0668 323f1d2b4d3SLarry Finger 324f1d2b4d3SLarry Finger 325f1d2b4d3SLarry Finger /* Security */ 326f1d2b4d3SLarry Finger #define REG_CAMCMD 0x0670 327f1d2b4d3SLarry Finger #define REG_CAMWRITE 0x0674 328f1d2b4d3SLarry Finger #define REG_CAMREAD 0x0678 329f1d2b4d3SLarry Finger #define REG_CAMDBG 0x067C 330f1d2b4d3SLarry Finger #define REG_SECCFG 0x0680 331f1d2b4d3SLarry Finger 332f1d2b4d3SLarry Finger /* Power */ 333f1d2b4d3SLarry Finger #define REG_WOW_CTRL 0x0690 334f1d2b4d3SLarry Finger #define REG_PSSTATUS 0x0691 335f1d2b4d3SLarry Finger #define REG_PS_RX_INFO 0x0692 336f1d2b4d3SLarry Finger #define REG_LPNAV_CTRL 0x0694 337f1d2b4d3SLarry Finger #define REG_WKFMCAM_CMD 0x0698 338f1d2b4d3SLarry Finger #define REG_WKFMCAM_RWD 0x069C 339f1d2b4d3SLarry Finger #define REG_RXFLTMAP0 0x06A0 340f1d2b4d3SLarry Finger #define REG_RXFLTMAP1 0x06A2 341f1d2b4d3SLarry Finger #define REG_RXFLTMAP2 0x06A4 342f1d2b4d3SLarry Finger #define REG_BCN_PSR_RPT 0x06A8 343f1d2b4d3SLarry Finger #define REG_CALB32K_CTRL 0x06AC 344f1d2b4d3SLarry Finger #define REG_PKT_MON_CTRL 0x06B4 345f1d2b4d3SLarry Finger #define REG_BT_COEX_TABLE 0x06C0 346f1d2b4d3SLarry Finger #define REG_WMAC_RESP_TXINFO 0x06D8 347f1d2b4d3SLarry Finger 348f1d2b4d3SLarry Finger 349f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 350f1d2b4d3SLarry Finger /* Redifine 8192C register definition for compatibility */ 351f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 352f1d2b4d3SLarry Finger #define CR9346 REG_9346CR 353f1d2b4d3SLarry Finger #define MSR (REG_CR + 2) 354f1d2b4d3SLarry Finger #define ISR REG_HISR 355f1d2b4d3SLarry Finger #define TSFR REG_TSFTR 356f1d2b4d3SLarry Finger 357f1d2b4d3SLarry Finger #define MACIDR0 REG_MACID 358f1d2b4d3SLarry Finger #define MACIDR4 (REG_MACID + 4) 359f1d2b4d3SLarry Finger 360f1d2b4d3SLarry Finger #define PBP REG_PBP 361f1d2b4d3SLarry Finger 362f1d2b4d3SLarry Finger #define IDR0 MACIDR0 363f1d2b4d3SLarry Finger #define IDR4 MACIDR4 364f1d2b4d3SLarry Finger 365f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 366f1d2b4d3SLarry Finger /* 8192C (MSR) Media Status Register(Offset 0x4C, 8 bits)*/ 367f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 368f1d2b4d3SLarry Finger #define MSR_NOLINK 0x00 369f1d2b4d3SLarry Finger #define MSR_ADHOC 0x01 370f1d2b4d3SLarry Finger #define MSR_INFRA 0x02 371f1d2b4d3SLarry Finger #define MSR_AP 0x03 372f1d2b4d3SLarry Finger #define MSR_MASK 0x03 373f1d2b4d3SLarry Finger 374f1d2b4d3SLarry Finger /* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */ 375f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 376f1d2b4d3SLarry Finger /* 8192C Response Rate Set Register(offset 0x181, 24bits)*/ 377f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 378f1d2b4d3SLarry Finger #define RRSR_RSC_OFFSET 21 379f1d2b4d3SLarry Finger #define RRSR_SHORT_OFFSET 23 380f1d2b4d3SLarry Finger #define RRSR_RSC_BW_40M 0x600000 381f1d2b4d3SLarry Finger #define RRSR_RSC_UPSUBCHNL 0x400000 382f1d2b4d3SLarry Finger #define RRSR_RSC_LOWSUBCHNL 0x200000 383f1d2b4d3SLarry Finger #define RRSR_SHORT 0x800000 384f1d2b4d3SLarry Finger #define RRSR_1M BIT0 385f1d2b4d3SLarry Finger #define RRSR_2M BIT1 386f1d2b4d3SLarry Finger #define RRSR_5_5M BIT2 387f1d2b4d3SLarry Finger #define RRSR_11M BIT3 388f1d2b4d3SLarry Finger #define RRSR_6M BIT4 389f1d2b4d3SLarry Finger #define RRSR_9M BIT5 390f1d2b4d3SLarry Finger #define RRSR_12M BIT6 391f1d2b4d3SLarry Finger #define RRSR_18M BIT7 392f1d2b4d3SLarry Finger #define RRSR_24M BIT8 393f1d2b4d3SLarry Finger #define RRSR_36M BIT9 394f1d2b4d3SLarry Finger #define RRSR_48M BIT10 395f1d2b4d3SLarry Finger #define RRSR_54M BIT11 396f1d2b4d3SLarry Finger #define RRSR_MCS0 BIT12 397f1d2b4d3SLarry Finger #define RRSR_MCS1 BIT13 398f1d2b4d3SLarry Finger #define RRSR_MCS2 BIT14 399f1d2b4d3SLarry Finger #define RRSR_MCS3 BIT15 400f1d2b4d3SLarry Finger #define RRSR_MCS4 BIT16 401f1d2b4d3SLarry Finger #define RRSR_MCS5 BIT17 402f1d2b4d3SLarry Finger #define RRSR_MCS6 BIT18 403f1d2b4d3SLarry Finger #define RRSR_MCS7 BIT19 404f1d2b4d3SLarry Finger #define BRSR_ACKSHORTPMB BIT23 405f1d2b4d3SLarry Finger 406f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 407f1d2b4d3SLarry Finger /* 8192C Rate Definition */ 408f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 409f1d2b4d3SLarry Finger /* CCK */ 410f1d2b4d3SLarry Finger #define RATR_1M 0x00000001 411f1d2b4d3SLarry Finger #define RATR_2M 0x00000002 412f1d2b4d3SLarry Finger #define RATR_55M 0x00000004 413f1d2b4d3SLarry Finger #define RATR_11M 0x00000008 414f1d2b4d3SLarry Finger /* OFDM */ 415f1d2b4d3SLarry Finger #define RATR_6M 0x00000010 416f1d2b4d3SLarry Finger #define RATR_9M 0x00000020 417f1d2b4d3SLarry Finger #define RATR_12M 0x00000040 418f1d2b4d3SLarry Finger #define RATR_18M 0x00000080 419f1d2b4d3SLarry Finger #define RATR_24M 0x00000100 420f1d2b4d3SLarry Finger #define RATR_36M 0x00000200 421f1d2b4d3SLarry Finger #define RATR_48M 0x00000400 422f1d2b4d3SLarry Finger #define RATR_54M 0x00000800 423f1d2b4d3SLarry Finger /* MCS 1 Spatial Stream */ 424f1d2b4d3SLarry Finger #define RATR_MCS0 0x00001000 425f1d2b4d3SLarry Finger #define RATR_MCS1 0x00002000 426f1d2b4d3SLarry Finger #define RATR_MCS2 0x00004000 427f1d2b4d3SLarry Finger #define RATR_MCS3 0x00008000 428f1d2b4d3SLarry Finger #define RATR_MCS4 0x00010000 429f1d2b4d3SLarry Finger #define RATR_MCS5 0x00020000 430f1d2b4d3SLarry Finger #define RATR_MCS6 0x00040000 431f1d2b4d3SLarry Finger #define RATR_MCS7 0x00080000 432f1d2b4d3SLarry Finger /* MCS 2 Spatial Stream */ 433f1d2b4d3SLarry Finger #define RATR_MCS8 0x00100000 434f1d2b4d3SLarry Finger #define RATR_MCS9 0x00200000 435f1d2b4d3SLarry Finger #define RATR_MCS10 0x00400000 436f1d2b4d3SLarry Finger #define RATR_MCS11 0x00800000 437f1d2b4d3SLarry Finger #define RATR_MCS12 0x01000000 438f1d2b4d3SLarry Finger #define RATR_MCS13 0x02000000 439f1d2b4d3SLarry Finger #define RATR_MCS14 0x04000000 440f1d2b4d3SLarry Finger #define RATR_MCS15 0x08000000 441f1d2b4d3SLarry Finger 442f1d2b4d3SLarry Finger /* CCK */ 443f1d2b4d3SLarry Finger #define RATE_1M BIT(0) 444f1d2b4d3SLarry Finger #define RATE_2M BIT(1) 445f1d2b4d3SLarry Finger #define RATE_5_5M BIT(2) 446f1d2b4d3SLarry Finger #define RATE_11M BIT(3) 447f1d2b4d3SLarry Finger /* OFDM */ 448f1d2b4d3SLarry Finger #define RATE_6M BIT(4) 449f1d2b4d3SLarry Finger #define RATE_9M BIT(5) 450f1d2b4d3SLarry Finger #define RATE_12M BIT(6) 451f1d2b4d3SLarry Finger #define RATE_18M BIT(7) 452f1d2b4d3SLarry Finger #define RATE_24M BIT(8) 453f1d2b4d3SLarry Finger #define RATE_36M BIT(9) 454f1d2b4d3SLarry Finger #define RATE_48M BIT(10) 455f1d2b4d3SLarry Finger #define RATE_54M BIT(11) 456f1d2b4d3SLarry Finger /* MCS 1 Spatial Stream */ 457f1d2b4d3SLarry Finger #define RATE_MCS0 BIT(12) 458f1d2b4d3SLarry Finger #define RATE_MCS1 BIT(13) 459f1d2b4d3SLarry Finger #define RATE_MCS2 BIT(14) 460f1d2b4d3SLarry Finger #define RATE_MCS3 BIT(15) 461f1d2b4d3SLarry Finger #define RATE_MCS4 BIT(16) 462f1d2b4d3SLarry Finger #define RATE_MCS5 BIT(17) 463f1d2b4d3SLarry Finger #define RATE_MCS6 BIT(18) 464f1d2b4d3SLarry Finger #define RATE_MCS7 BIT(19) 465f1d2b4d3SLarry Finger /* MCS 2 Spatial Stream */ 466f1d2b4d3SLarry Finger #define RATE_MCS8 BIT(20) 467f1d2b4d3SLarry Finger #define RATE_MCS9 BIT(21) 468f1d2b4d3SLarry Finger #define RATE_MCS10 BIT(22) 469f1d2b4d3SLarry Finger #define RATE_MCS11 BIT(23) 470f1d2b4d3SLarry Finger #define RATE_MCS12 BIT(24) 471f1d2b4d3SLarry Finger #define RATE_MCS13 BIT(25) 472f1d2b4d3SLarry Finger #define RATE_MCS14 BIT(26) 473f1d2b4d3SLarry Finger #define RATE_MCS15 BIT(27) 474f1d2b4d3SLarry Finger 475f1d2b4d3SLarry Finger /* ALL CCK Rate */ 476f1d2b4d3SLarry Finger #define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | \ 477f1d2b4d3SLarry Finger RATR_11M) 478f1d2b4d3SLarry Finger #define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | \ 479f1d2b4d3SLarry Finger RATR_18M | RATR_24M | \ 480f1d2b4d3SLarry Finger RATR_36M | RATR_48M | RATR_54M) 481f1d2b4d3SLarry Finger #define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \ 482f1d2b4d3SLarry Finger RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \ 483f1d2b4d3SLarry Finger RATR_MCS6 | RATR_MCS7) 484f1d2b4d3SLarry Finger #define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \ 485f1d2b4d3SLarry Finger RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \ 486f1d2b4d3SLarry Finger RATR_MCS14 | RATR_MCS15) 487f1d2b4d3SLarry Finger 488f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 489f1d2b4d3SLarry Finger /* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */ 490f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 491f1d2b4d3SLarry Finger #define BW_OPMODE_20MHZ BIT(2) 492f1d2b4d3SLarry Finger #define BW_OPMODE_5G BIT(1) 493f1d2b4d3SLarry Finger #define BW_OPMODE_11J BIT(0) 494f1d2b4d3SLarry Finger 495f1d2b4d3SLarry Finger 496f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 497f1d2b4d3SLarry Finger /* 8192C CAM Config Setting (offset 0x250, 1 byte) */ 498f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 499f1d2b4d3SLarry Finger #define CAM_VALID BIT(15) 500f1d2b4d3SLarry Finger #define CAM_NOTVALID 0x0000 501f1d2b4d3SLarry Finger #define CAM_USEDK BIT(5) 502f1d2b4d3SLarry Finger 503f1d2b4d3SLarry Finger #define CAM_NONE 0x0 504f1d2b4d3SLarry Finger #define CAM_WEP40 0x01 505f1d2b4d3SLarry Finger #define CAM_TKIP 0x02 506f1d2b4d3SLarry Finger #define CAM_AES 0x04 507f1d2b4d3SLarry Finger #define CAM_WEP104 0x05 508f1d2b4d3SLarry Finger #define CAM_SMS4 0x6 509f1d2b4d3SLarry Finger 510f1d2b4d3SLarry Finger 511f1d2b4d3SLarry Finger #define TOTAL_CAM_ENTRY 32 512f1d2b4d3SLarry Finger #define HALF_CAM_ENTRY 16 513f1d2b4d3SLarry Finger 514f1d2b4d3SLarry Finger #define CAM_WRITE BIT(16) 515f1d2b4d3SLarry Finger #define CAM_READ 0x00000000 516f1d2b4d3SLarry Finger #define CAM_POLLINIG BIT(31) 517f1d2b4d3SLarry Finger 518f1d2b4d3SLarry Finger /* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */ 519f1d2b4d3SLarry Finger #define WOW_PMEN BIT0 /* Power management Enable. */ 520f1d2b4d3SLarry Finger #define WOW_WOMEN BIT1 /* WoW function on or off. */ 521f1d2b4d3SLarry Finger #define WOW_MAGIC BIT2 /* Magic packet */ 522f1d2b4d3SLarry Finger #define WOW_UWF BIT3 /* Unicast Wakeup frame. */ 523f1d2b4d3SLarry Finger 524f1d2b4d3SLarry Finger /* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */ 525f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 526f1d2b4d3SLarry Finger /* 8190 IMR/ISR bits (offset 0xfd, 8bits) */ 527f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 528f1d2b4d3SLarry Finger #define IMR8190_DISABLED 0x0 529f1d2b4d3SLarry Finger #define IMR_BCNDMAINT6 BIT(31) 530f1d2b4d3SLarry Finger #define IMR_BCNDMAINT5 BIT(30) 531f1d2b4d3SLarry Finger #define IMR_BCNDMAINT4 BIT(29) 532f1d2b4d3SLarry Finger #define IMR_BCNDMAINT3 BIT(28) 533f1d2b4d3SLarry Finger #define IMR_BCNDMAINT2 BIT(27) 534f1d2b4d3SLarry Finger #define IMR_BCNDMAINT1 BIT(26) 535f1d2b4d3SLarry Finger #define IMR_BCNDOK8 BIT(25) 536f1d2b4d3SLarry Finger #define IMR_BCNDOK7 BIT(24) 537f1d2b4d3SLarry Finger #define IMR_BCNDOK6 BIT(23) 538f1d2b4d3SLarry Finger #define IMR_BCNDOK5 BIT(22) 539f1d2b4d3SLarry Finger #define IMR_BCNDOK4 BIT(21) 540f1d2b4d3SLarry Finger #define IMR_BCNDOK3 BIT(20) 541f1d2b4d3SLarry Finger #define IMR_BCNDOK2 BIT(19) 542f1d2b4d3SLarry Finger #define IMR_BCNDOK1 BIT(18) 543f1d2b4d3SLarry Finger #define IMR_TIMEOUT2 BIT(17) 544f1d2b4d3SLarry Finger #define IMR_TIMEOUT1 BIT(16) 545f1d2b4d3SLarry Finger #define IMR_TXFOVW BIT(15) 546f1d2b4d3SLarry Finger #define IMR_PSTIMEOUT BIT(14) 547f1d2b4d3SLarry Finger #define IMR_BCNINT BIT(13) 548f1d2b4d3SLarry Finger #define IMR_RXFOVW BIT(12) 549f1d2b4d3SLarry Finger #define IMR_RDU BIT(11) 550f1d2b4d3SLarry Finger #define IMR_ATIMEND BIT(10) 551f1d2b4d3SLarry Finger #define IMR_BDOK BIT(9) 552f1d2b4d3SLarry Finger #define IMR_HIGHDOK BIT(8) 553f1d2b4d3SLarry Finger #define IMR_TBDOK BIT(7) 554f1d2b4d3SLarry Finger #define IMR_MGNTDOK BIT(6) 555f1d2b4d3SLarry Finger #define IMR_TBDER BIT(5) 556f1d2b4d3SLarry Finger #define IMR_BKDOK BIT(4) 557f1d2b4d3SLarry Finger #define IMR_BEDOK BIT(3) 558f1d2b4d3SLarry Finger #define IMR_VIDOK BIT(2) 559f1d2b4d3SLarry Finger #define IMR_VODOK BIT(1) 560f1d2b4d3SLarry Finger #define IMR_ROK BIT(0) 561f1d2b4d3SLarry Finger 562f1d2b4d3SLarry Finger #define IMR_TXERR BIT(11) 563f1d2b4d3SLarry Finger #define IMR_RXERR BIT(10) 564f1d2b4d3SLarry Finger #define IMR_C2HCMD BIT(9) 565f1d2b4d3SLarry Finger #define IMR_CPWM BIT(8) 566f1d2b4d3SLarry Finger #define IMR_OCPINT BIT(1) 567f1d2b4d3SLarry Finger #define IMR_WLANOFF BIT(0) 568f1d2b4d3SLarry Finger 569f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 570f1d2b4d3SLarry Finger /* 8192C EFUSE */ 571f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 572f1d2b4d3SLarry Finger #define HWSET_MAX_SIZE 256 573f1d2b4d3SLarry Finger #define EFUSE_MAX_SECTION 32 574f1d2b4d3SLarry Finger #define EFUSE_REAL_CONTENT_LEN 512 575f1d2b4d3SLarry Finger 576f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 577f1d2b4d3SLarry Finger /* 8192C EEPROM/EFUSE share register definition. */ 578f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 579f1d2b4d3SLarry Finger #define EEPROM_DEFAULT_TSSI 0x0 580f1d2b4d3SLarry Finger #define EEPROM_DEFAULT_CRYSTALCAP 0x0 581f1d2b4d3SLarry Finger #define EEPROM_DEFAULT_THERMALMETER 0x12 582f1d2b4d3SLarry Finger 583f1d2b4d3SLarry Finger #define EEPROM_DEFAULT_TXPOWERLEVEL_2G 0x2C 584f1d2b4d3SLarry Finger #define EEPROM_DEFAULT_TXPOWERLEVEL_5G 0x22 585f1d2b4d3SLarry Finger 586f1d2b4d3SLarry Finger #define EEPROM_DEFAULT_HT40_2SDIFF 0x0 587f1d2b4d3SLarry Finger /* HT20<->40 default Tx Power Index Difference */ 588f1d2b4d3SLarry Finger #define EEPROM_DEFAULT_HT20_DIFF 2 589f1d2b4d3SLarry Finger /* OFDM Tx Power index diff */ 590f1d2b4d3SLarry Finger #define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x4 591f1d2b4d3SLarry Finger #define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 592f1d2b4d3SLarry Finger #define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 593f1d2b4d3SLarry Finger 594f1d2b4d3SLarry Finger #define EEPROM_CHANNEL_PLAN_FCC 0x0 595f1d2b4d3SLarry Finger #define EEPROM_CHANNEL_PLAN_IC 0x1 596f1d2b4d3SLarry Finger #define EEPROM_CHANNEL_PLAN_ETSI 0x2 597f1d2b4d3SLarry Finger #define EEPROM_CHANNEL_PLAN_SPAIN 0x3 598f1d2b4d3SLarry Finger #define EEPROM_CHANNEL_PLAN_FRANCE 0x4 599f1d2b4d3SLarry Finger #define EEPROM_CHANNEL_PLAN_MKK 0x5 600f1d2b4d3SLarry Finger #define EEPROM_CHANNEL_PLAN_MKK1 0x6 601f1d2b4d3SLarry Finger #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 602f1d2b4d3SLarry Finger #define EEPROM_CHANNEL_PLAN_TELEC 0x8 603f1d2b4d3SLarry Finger #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 604f1d2b4d3SLarry Finger #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 605f1d2b4d3SLarry Finger #define EEPROM_CHANNEL_PLAN_NCC 0xB 606f1d2b4d3SLarry Finger #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 607f1d2b4d3SLarry Finger 608f1d2b4d3SLarry Finger #define EEPROM_CID_DEFAULT 0x0 609f1d2b4d3SLarry Finger #define EEPROM_CID_TOSHIBA 0x4 610f1d2b4d3SLarry Finger #define EEPROM_CID_CCX 0x10 611f1d2b4d3SLarry Finger #define EEPROM_CID_QMI 0x0D 612f1d2b4d3SLarry Finger #define EEPROM_CID_WHQL 0xFE 613f1d2b4d3SLarry Finger 614f1d2b4d3SLarry Finger 615f1d2b4d3SLarry Finger #define RTL8192_EEPROM_ID 0x8129 616f1d2b4d3SLarry Finger #define EEPROM_WAPI_SUPPORT 0x78 617f1d2b4d3SLarry Finger 618f1d2b4d3SLarry Finger 619f1d2b4d3SLarry Finger #define RTL8190_EEPROM_ID 0x8129 /* 0-1 */ 620f1d2b4d3SLarry Finger #define EEPROM_HPON 0x02 /* LDO settings.2-5 */ 621f1d2b4d3SLarry Finger #define EEPROM_CLK 0x06 /* Clock settings.6-7 */ 622f1d2b4d3SLarry Finger #define EEPROM_MAC_FUNCTION 0x08 /* SE Test mode.8 */ 623f1d2b4d3SLarry Finger 624f1d2b4d3SLarry Finger #define EEPROM_VID 0x28 /* SE Vendor ID.A-B */ 625f1d2b4d3SLarry Finger #define EEPROM_DID 0x2A /* SE Device ID. C-D */ 626f1d2b4d3SLarry Finger #define EEPROM_SVID 0x2C /* SE Vendor ID.E-F */ 627f1d2b4d3SLarry Finger #define EEPROM_SMID 0x2E /* SE PCI Subsystem ID. 10-11 */ 628f1d2b4d3SLarry Finger 629f1d2b4d3SLarry Finger #define EEPROM_MAC_ADDR 0x16 /* SEMAC Address. 12-17 */ 630f1d2b4d3SLarry Finger #define EEPROM_MAC_ADDR_MAC0_92D 0x55 631f1d2b4d3SLarry Finger #define EEPROM_MAC_ADDR_MAC1_92D 0x5B 632f1d2b4d3SLarry Finger 633f1d2b4d3SLarry Finger /* 2.4G band Tx power index setting */ 634f1d2b4d3SLarry Finger #define EEPROM_CCK_TX_PWR_INX_2G 0x61 635f1d2b4d3SLarry Finger #define EEPROM_HT40_1S_TX_PWR_INX_2G 0x67 636f1d2b4d3SLarry Finger #define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G 0x6D 637f1d2b4d3SLarry Finger #define EEPROM_HT20_TX_PWR_INX_DIFF_2G 0x70 638f1d2b4d3SLarry Finger #define EEPROM_OFDM_TX_PWR_INX_DIFF_2G 0x73 639f1d2b4d3SLarry Finger #define EEPROM_HT40_MAX_PWR_OFFSET_2G 0x76 640f1d2b4d3SLarry Finger #define EEPROM_HT20_MAX_PWR_OFFSET_2G 0x79 641f1d2b4d3SLarry Finger 642f1d2b4d3SLarry Finger /*5GL channel 32-64 */ 643f1d2b4d3SLarry Finger #define EEPROM_HT40_1S_TX_PWR_INX_5GL 0x7C 644f1d2b4d3SLarry Finger #define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL 0x82 645f1d2b4d3SLarry Finger #define EEPROM_HT20_TX_PWR_INX_DIFF_5GL 0x85 646f1d2b4d3SLarry Finger #define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL 0x88 647f1d2b4d3SLarry Finger #define EEPROM_HT40_MAX_PWR_OFFSET_5GL 0x8B 648f1d2b4d3SLarry Finger #define EEPROM_HT20_MAX_PWR_OFFSET_5GL 0x8E 649f1d2b4d3SLarry Finger 650f1d2b4d3SLarry Finger /* 5GM channel 100-140 */ 651f1d2b4d3SLarry Finger #define EEPROM_HT40_1S_TX_PWR_INX_5GM 0x91 652f1d2b4d3SLarry Finger #define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM 0x97 653f1d2b4d3SLarry Finger #define EEPROM_HT20_TX_PWR_INX_DIFF_5GM 0x9A 654f1d2b4d3SLarry Finger #define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM 0x9D 655f1d2b4d3SLarry Finger #define EEPROM_HT40_MAX_PWR_OFFSET_5GM 0xA0 656f1d2b4d3SLarry Finger #define EEPROM_HT20_MAX_PWR_OFFSET_5GM 0xA3 657f1d2b4d3SLarry Finger 658f1d2b4d3SLarry Finger /* 5GH channel 149-165 */ 659f1d2b4d3SLarry Finger #define EEPROM_HT40_1S_TX_PWR_INX_5GH 0xA6 660f1d2b4d3SLarry Finger #define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH 0xAC 661f1d2b4d3SLarry Finger #define EEPROM_HT20_TX_PWR_INX_DIFF_5GH 0xAF 662f1d2b4d3SLarry Finger #define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH 0xB2 663f1d2b4d3SLarry Finger #define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5 664f1d2b4d3SLarry Finger #define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8 665f1d2b4d3SLarry Finger 666f1d2b4d3SLarry Finger /* Map of supported channels. */ 667f1d2b4d3SLarry Finger #define EEPROM_CHANNEL_PLAN 0xBB 668f1d2b4d3SLarry Finger #define EEPROM_IQK_DELTA 0xBC 669f1d2b4d3SLarry Finger #define EEPROM_LCK_DELTA 0xBC 670f1d2b4d3SLarry Finger #define EEPROM_XTAL_K 0xBD /* [7:5] */ 671f1d2b4d3SLarry Finger #define EEPROM_TSSI_A_5G 0xBE 672f1d2b4d3SLarry Finger #define EEPROM_TSSI_B_5G 0xBF 673f1d2b4d3SLarry Finger #define EEPROM_TSSI_AB_5G 0xC0 674f1d2b4d3SLarry Finger #define EEPROM_THERMAL_METER 0xC3 /* [4:0] */ 675f1d2b4d3SLarry Finger #define EEPROM_RF_OPT1 0xC4 676f1d2b4d3SLarry Finger #define EEPROM_RF_OPT2 0xC5 677f1d2b4d3SLarry Finger #define EEPROM_RF_OPT3 0xC6 678f1d2b4d3SLarry Finger #define EEPROM_RF_OPT4 0xC7 679f1d2b4d3SLarry Finger #define EEPROM_RF_OPT5 0xC8 680f1d2b4d3SLarry Finger #define EEPROM_RF_OPT6 0xC9 681f1d2b4d3SLarry Finger #define EEPROM_VERSION 0xCA 682f1d2b4d3SLarry Finger #define EEPROM_CUSTOMER_ID 0xCB 683f1d2b4d3SLarry Finger #define EEPROM_RF_OPT7 0xCC 684f1d2b4d3SLarry Finger 685f1d2b4d3SLarry Finger #define EEPROM_DEF_PART_NO 0x3FD /* Byte */ 686f1d2b4d3SLarry Finger #define EEPROME_CHIP_VERSION_L 0x3FF 687f1d2b4d3SLarry Finger #define EEPROME_CHIP_VERSION_H 0x3FE 688f1d2b4d3SLarry Finger 689f1d2b4d3SLarry Finger /* 690f1d2b4d3SLarry Finger * Current IOREG MAP 691f1d2b4d3SLarry Finger * 0x0000h ~ 0x00FFh System Configuration (256 Bytes) 692f1d2b4d3SLarry Finger * 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) 693f1d2b4d3SLarry Finger * 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) 694f1d2b4d3SLarry Finger * 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) 695f1d2b4d3SLarry Finger * 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) 696f1d2b4d3SLarry Finger * 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) 697f1d2b4d3SLarry Finger * 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) 698f1d2b4d3SLarry Finger * 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) 699f1d2b4d3SLarry Finger * 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) 700f1d2b4d3SLarry Finger */ 701f1d2b4d3SLarry Finger 702f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 703f1d2b4d3SLarry Finger /* 8192C (RCR) (Offset 0x608, 32 bits) */ 704f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 705f1d2b4d3SLarry Finger #define RCR_APPFCS BIT(31) 706f1d2b4d3SLarry Finger #define RCR_APP_MIC BIT(30) 707f1d2b4d3SLarry Finger #define RCR_APP_ICV BIT(29) 708f1d2b4d3SLarry Finger #define RCR_APP_PHYST_RXFF BIT(28) 709f1d2b4d3SLarry Finger #define RCR_APP_BA_SSN BIT(27) 710f1d2b4d3SLarry Finger #define RCR_ENMBID BIT(24) 711f1d2b4d3SLarry Finger #define RCR_LSIGEN BIT(23) 712f1d2b4d3SLarry Finger #define RCR_MFBEN BIT(22) 713f1d2b4d3SLarry Finger #define RCR_HTC_LOC_CTRL BIT(14) 714f1d2b4d3SLarry Finger #define RCR_AMF BIT(13) 715f1d2b4d3SLarry Finger #define RCR_ACF BIT(12) 716f1d2b4d3SLarry Finger #define RCR_ADF BIT(11) 717f1d2b4d3SLarry Finger #define RCR_AICV BIT(9) 718f1d2b4d3SLarry Finger #define RCR_ACRC32 BIT(8) 719f1d2b4d3SLarry Finger #define RCR_CBSSID_BCN BIT(7) 720f1d2b4d3SLarry Finger #define RCR_CBSSID_DATA BIT(6) 721f1d2b4d3SLarry Finger #define RCR_APWRMGT BIT(5) 722f1d2b4d3SLarry Finger #define RCR_ADD3 BIT(4) 723f1d2b4d3SLarry Finger #define RCR_AB BIT(3) 724f1d2b4d3SLarry Finger #define RCR_AM BIT(2) 725f1d2b4d3SLarry Finger #define RCR_APM BIT(1) 726f1d2b4d3SLarry Finger #define RCR_AAP BIT(0) 727f1d2b4d3SLarry Finger #define RCR_MXDMA_OFFSET 8 728f1d2b4d3SLarry Finger #define RCR_FIFO_OFFSET 13 729f1d2b4d3SLarry Finger 730f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 731f1d2b4d3SLarry Finger /* 8192C Regsiter Bit and Content definition */ 732f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 733f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 734f1d2b4d3SLarry Finger /* 0x0000h ~ 0x00FFh System Configuration */ 735f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 736f1d2b4d3SLarry Finger 737f1d2b4d3SLarry Finger /* SPS0_CTRL */ 738f1d2b4d3SLarry Finger #define SW18_FPWM BIT(3) 739f1d2b4d3SLarry Finger 740f1d2b4d3SLarry Finger 741f1d2b4d3SLarry Finger /* SYS_ISO_CTRL */ 742f1d2b4d3SLarry Finger #define ISO_MD2PP BIT(0) 743f1d2b4d3SLarry Finger #define ISO_UA2USB BIT(1) 744f1d2b4d3SLarry Finger #define ISO_UD2CORE BIT(2) 745f1d2b4d3SLarry Finger #define ISO_PA2PCIE BIT(3) 746f1d2b4d3SLarry Finger #define ISO_PD2CORE BIT(4) 747f1d2b4d3SLarry Finger #define ISO_IP2MAC BIT(5) 748f1d2b4d3SLarry Finger #define ISO_DIOP BIT(6) 749f1d2b4d3SLarry Finger #define ISO_DIOE BIT(7) 750f1d2b4d3SLarry Finger #define ISO_EB2CORE BIT(8) 751f1d2b4d3SLarry Finger #define ISO_DIOR BIT(9) 752f1d2b4d3SLarry Finger 753f1d2b4d3SLarry Finger #define PWC_EV25V BIT(14) 754f1d2b4d3SLarry Finger #define PWC_EV12V BIT(15) 755f1d2b4d3SLarry Finger 756f1d2b4d3SLarry Finger 757f1d2b4d3SLarry Finger /* SYS_FUNC_EN */ 758f1d2b4d3SLarry Finger #define FEN_BBRSTB BIT(0) 759f1d2b4d3SLarry Finger #define FEN_BB_GLB_RSTn BIT(1) 760f1d2b4d3SLarry Finger #define FEN_USBA BIT(2) 761f1d2b4d3SLarry Finger #define FEN_UPLL BIT(3) 762f1d2b4d3SLarry Finger #define FEN_USBD BIT(4) 763f1d2b4d3SLarry Finger #define FEN_DIO_PCIE BIT(5) 764f1d2b4d3SLarry Finger #define FEN_PCIEA BIT(6) 765f1d2b4d3SLarry Finger #define FEN_PPLL BIT(7) 766f1d2b4d3SLarry Finger #define FEN_PCIED BIT(8) 767f1d2b4d3SLarry Finger #define FEN_DIOE BIT(9) 768f1d2b4d3SLarry Finger #define FEN_CPUEN BIT(10) 769f1d2b4d3SLarry Finger #define FEN_DCORE BIT(11) 770f1d2b4d3SLarry Finger #define FEN_ELDR BIT(12) 771f1d2b4d3SLarry Finger #define FEN_DIO_RF BIT(13) 772f1d2b4d3SLarry Finger #define FEN_HWPDN BIT(14) 773f1d2b4d3SLarry Finger #define FEN_MREGEN BIT(15) 774f1d2b4d3SLarry Finger 775f1d2b4d3SLarry Finger /* APS_FSMCO */ 776f1d2b4d3SLarry Finger #define PFM_LDALL BIT(0) 777f1d2b4d3SLarry Finger #define PFM_ALDN BIT(1) 778f1d2b4d3SLarry Finger #define PFM_LDKP BIT(2) 779f1d2b4d3SLarry Finger #define PFM_WOWL BIT(3) 780f1d2b4d3SLarry Finger #define EnPDN BIT(4) 781f1d2b4d3SLarry Finger #define PDN_PL BIT(5) 782f1d2b4d3SLarry Finger #define APFM_ONMAC BIT(8) 783f1d2b4d3SLarry Finger #define APFM_OFF BIT(9) 784f1d2b4d3SLarry Finger #define APFM_RSM BIT(10) 785f1d2b4d3SLarry Finger #define AFSM_HSUS BIT(11) 786f1d2b4d3SLarry Finger #define AFSM_PCIE BIT(12) 787f1d2b4d3SLarry Finger #define APDM_MAC BIT(13) 788f1d2b4d3SLarry Finger #define APDM_HOST BIT(14) 789f1d2b4d3SLarry Finger #define APDM_HPDN BIT(15) 790f1d2b4d3SLarry Finger #define RDY_MACON BIT(16) 791f1d2b4d3SLarry Finger #define SUS_HOST BIT(17) 792f1d2b4d3SLarry Finger #define ROP_ALD BIT(20) 793f1d2b4d3SLarry Finger #define ROP_PWR BIT(21) 794f1d2b4d3SLarry Finger #define ROP_SPS BIT(22) 795f1d2b4d3SLarry Finger #define SOP_MRST BIT(25) 796f1d2b4d3SLarry Finger #define SOP_FUSE BIT(26) 797f1d2b4d3SLarry Finger #define SOP_ABG BIT(27) 798f1d2b4d3SLarry Finger #define SOP_AMB BIT(28) 799f1d2b4d3SLarry Finger #define SOP_RCK BIT(29) 800f1d2b4d3SLarry Finger #define SOP_A8M BIT(30) 801f1d2b4d3SLarry Finger #define XOP_BTCK BIT(31) 802f1d2b4d3SLarry Finger 803f1d2b4d3SLarry Finger /* SYS_CLKR */ 804f1d2b4d3SLarry Finger #define ANAD16V_EN BIT(0) 805f1d2b4d3SLarry Finger #define ANA8M BIT(1) 806f1d2b4d3SLarry Finger #define MACSLP BIT(4) 807f1d2b4d3SLarry Finger #define LOADER_CLK_EN BIT(5) 808f1d2b4d3SLarry Finger #define _80M_SSC_DIS BIT(7) 809f1d2b4d3SLarry Finger #define _80M_SSC_EN_HO BIT(8) 810f1d2b4d3SLarry Finger #define PHY_SSC_RSTB BIT(9) 811f1d2b4d3SLarry Finger #define SEC_CLK_EN BIT(10) 812f1d2b4d3SLarry Finger #define MAC_CLK_EN BIT(11) 813f1d2b4d3SLarry Finger #define SYS_CLK_EN BIT(12) 814f1d2b4d3SLarry Finger #define RING_CLK_EN BIT(13) 815f1d2b4d3SLarry Finger 816f1d2b4d3SLarry Finger 817f1d2b4d3SLarry Finger /* 9346CR */ 818f1d2b4d3SLarry Finger #define BOOT_FROM_EEPROM BIT(4) 819f1d2b4d3SLarry Finger #define EEPROM_EN BIT(5) 820f1d2b4d3SLarry Finger 821f1d2b4d3SLarry Finger /* AFE_MISC */ 822f1d2b4d3SLarry Finger #define AFE_BGEN BIT(0) 823f1d2b4d3SLarry Finger #define AFE_MBEN BIT(1) 824f1d2b4d3SLarry Finger #define MAC_ID_EN BIT(7) 825f1d2b4d3SLarry Finger 826f1d2b4d3SLarry Finger /* RSV_CTRL */ 827f1d2b4d3SLarry Finger #define WLOCK_ALL BIT(0) 828f1d2b4d3SLarry Finger #define WLOCK_00 BIT(1) 829f1d2b4d3SLarry Finger #define WLOCK_04 BIT(2) 830f1d2b4d3SLarry Finger #define WLOCK_08 BIT(3) 831f1d2b4d3SLarry Finger #define WLOCK_40 BIT(4) 832f1d2b4d3SLarry Finger #define R_DIS_PRST_0 BIT(5) 833f1d2b4d3SLarry Finger #define R_DIS_PRST_1 BIT(6) 834f1d2b4d3SLarry Finger #define LOCK_ALL_EN BIT(7) 835f1d2b4d3SLarry Finger 836f1d2b4d3SLarry Finger /* RF_CTRL */ 837f1d2b4d3SLarry Finger #define RF_EN BIT(0) 838f1d2b4d3SLarry Finger #define RF_RSTB BIT(1) 839f1d2b4d3SLarry Finger #define RF_SDMRSTB BIT(2) 840f1d2b4d3SLarry Finger 841f1d2b4d3SLarry Finger 842f1d2b4d3SLarry Finger 843f1d2b4d3SLarry Finger /* LDOA15_CTRL */ 844f1d2b4d3SLarry Finger #define LDA15_EN BIT(0) 845f1d2b4d3SLarry Finger #define LDA15_STBY BIT(1) 846f1d2b4d3SLarry Finger #define LDA15_OBUF BIT(2) 847f1d2b4d3SLarry Finger #define LDA15_REG_VOS BIT(3) 848f1d2b4d3SLarry Finger #define _LDA15_VOADJ(x) (((x) & 0x7) << 4) 849f1d2b4d3SLarry Finger 850f1d2b4d3SLarry Finger 851f1d2b4d3SLarry Finger 852f1d2b4d3SLarry Finger /* LDOV12D_CTRL */ 853f1d2b4d3SLarry Finger #define LDV12_EN BIT(0) 854f1d2b4d3SLarry Finger #define LDV12_SDBY BIT(1) 855f1d2b4d3SLarry Finger #define LPLDO_HSM BIT(2) 856f1d2b4d3SLarry Finger #define LPLDO_LSM_DIS BIT(3) 857f1d2b4d3SLarry Finger #define _LDV12_VADJ(x) (((x) & 0xF) << 4) 858f1d2b4d3SLarry Finger 859f1d2b4d3SLarry Finger 860f1d2b4d3SLarry Finger /* AFE_XTAL_CTRL */ 861f1d2b4d3SLarry Finger #define XTAL_EN BIT(0) 862f1d2b4d3SLarry Finger #define XTAL_BSEL BIT(1) 863f1d2b4d3SLarry Finger #define _XTAL_BOSC(x) (((x) & 0x3) << 2) 864f1d2b4d3SLarry Finger #define _XTAL_CADJ(x) (((x) & 0xF) << 4) 865f1d2b4d3SLarry Finger #define XTAL_GATE_USB BIT(8) 866f1d2b4d3SLarry Finger #define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) 867f1d2b4d3SLarry Finger #define XTAL_GATE_AFE BIT(11) 868f1d2b4d3SLarry Finger #define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) 869f1d2b4d3SLarry Finger #define XTAL_RF_GATE BIT(14) 870f1d2b4d3SLarry Finger #define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) 871f1d2b4d3SLarry Finger #define XTAL_GATE_DIG BIT(17) 872f1d2b4d3SLarry Finger #define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) 873f1d2b4d3SLarry Finger #define XTAL_BT_GATE BIT(20) 874f1d2b4d3SLarry Finger #define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) 875f1d2b4d3SLarry Finger #define _XTAL_GPIO(x) (((x) & 0x7) << 23) 876f1d2b4d3SLarry Finger 877f1d2b4d3SLarry Finger 878f1d2b4d3SLarry Finger #define CKDLY_AFE BIT(26) 879f1d2b4d3SLarry Finger #define CKDLY_USB BIT(27) 880f1d2b4d3SLarry Finger #define CKDLY_DIG BIT(28) 881f1d2b4d3SLarry Finger #define CKDLY_BT BIT(29) 882f1d2b4d3SLarry Finger 883f1d2b4d3SLarry Finger 884f1d2b4d3SLarry Finger /* AFE_PLL_CTRL */ 885f1d2b4d3SLarry Finger #define APLL_EN BIT(0) 886f1d2b4d3SLarry Finger #define APLL_320_EN BIT(1) 887f1d2b4d3SLarry Finger #define APLL_FREF_SEL BIT(2) 888f1d2b4d3SLarry Finger #define APLL_EDGE_SEL BIT(3) 889f1d2b4d3SLarry Finger #define APLL_WDOGB BIT(4) 890f1d2b4d3SLarry Finger #define APLL_LPFEN BIT(5) 891f1d2b4d3SLarry Finger 892f1d2b4d3SLarry Finger #define APLL_REF_CLK_13MHZ 0x1 893f1d2b4d3SLarry Finger #define APLL_REF_CLK_19_2MHZ 0x2 894f1d2b4d3SLarry Finger #define APLL_REF_CLK_20MHZ 0x3 895f1d2b4d3SLarry Finger #define APLL_REF_CLK_25MHZ 0x4 896f1d2b4d3SLarry Finger #define APLL_REF_CLK_26MHZ 0x5 897f1d2b4d3SLarry Finger #define APLL_REF_CLK_38_4MHZ 0x6 898f1d2b4d3SLarry Finger #define APLL_REF_CLK_40MHZ 0x7 899f1d2b4d3SLarry Finger 900f1d2b4d3SLarry Finger #define APLL_320EN BIT(14) 901f1d2b4d3SLarry Finger #define APLL_80EN BIT(15) 902f1d2b4d3SLarry Finger #define APLL_1MEN BIT(24) 903f1d2b4d3SLarry Finger 904f1d2b4d3SLarry Finger 905f1d2b4d3SLarry Finger /* EFUSE_CTRL */ 906f1d2b4d3SLarry Finger #define ALD_EN BIT(18) 907f1d2b4d3SLarry Finger #define EF_PD BIT(19) 908f1d2b4d3SLarry Finger #define EF_FLAG BIT(31) 909f1d2b4d3SLarry Finger 910f1d2b4d3SLarry Finger /* EFUSE_TEST */ 911f1d2b4d3SLarry Finger #define EF_TRPT BIT(7) 912f1d2b4d3SLarry Finger #define LDOE25_EN BIT(31) 913f1d2b4d3SLarry Finger 914f1d2b4d3SLarry Finger /* MCUFWDL */ 915f1d2b4d3SLarry Finger #define MCUFWDL_EN BIT(0) 916f1d2b4d3SLarry Finger #define MCUFWDL_RDY BIT(1) 917f1d2b4d3SLarry Finger #define FWDL_ChkSum_rpt BIT(2) 918f1d2b4d3SLarry Finger #define MACINI_RDY BIT(3) 919f1d2b4d3SLarry Finger #define BBINI_RDY BIT(4) 920f1d2b4d3SLarry Finger #define RFINI_RDY BIT(5) 921f1d2b4d3SLarry Finger #define WINTINI_RDY BIT(6) 922f1d2b4d3SLarry Finger #define MAC1_WINTINI_RDY BIT(11) 923f1d2b4d3SLarry Finger #define CPRST BIT(23) 924f1d2b4d3SLarry Finger 925f1d2b4d3SLarry Finger /* REG_SYS_CFG */ 926f1d2b4d3SLarry Finger #define XCLK_VLD BIT(0) 927f1d2b4d3SLarry Finger #define ACLK_VLD BIT(1) 928f1d2b4d3SLarry Finger #define UCLK_VLD BIT(2) 929f1d2b4d3SLarry Finger #define PCLK_VLD BIT(3) 930f1d2b4d3SLarry Finger #define PCIRSTB BIT(4) 931f1d2b4d3SLarry Finger #define V15_VLD BIT(5) 932f1d2b4d3SLarry Finger #define TRP_B15V_EN BIT(7) 933f1d2b4d3SLarry Finger #define SIC_IDLE BIT(8) 934f1d2b4d3SLarry Finger #define BD_MAC2 BIT(9) 935f1d2b4d3SLarry Finger #define BD_MAC1 BIT(10) 936f1d2b4d3SLarry Finger #define IC_MACPHY_MODE BIT(11) 937f1d2b4d3SLarry Finger #define PAD_HWPD_IDN BIT(22) 938f1d2b4d3SLarry Finger #define TRP_VAUX_EN BIT(23) 939f1d2b4d3SLarry Finger #define TRP_BT_EN BIT(24) 940f1d2b4d3SLarry Finger #define BD_PKG_SEL BIT(25) 941f1d2b4d3SLarry Finger #define BD_HCI_SEL BIT(26) 942f1d2b4d3SLarry Finger #define TYPE_ID BIT(27) 943f1d2b4d3SLarry Finger 944f1d2b4d3SLarry Finger /* LLT_INIT */ 945f1d2b4d3SLarry Finger #define _LLT_NO_ACTIVE 0x0 946f1d2b4d3SLarry Finger #define _LLT_WRITE_ACCESS 0x1 947f1d2b4d3SLarry Finger #define _LLT_READ_ACCESS 0x2 948f1d2b4d3SLarry Finger 949f1d2b4d3SLarry Finger #define _LLT_INIT_DATA(x) ((x) & 0xFF) 950f1d2b4d3SLarry Finger #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 951f1d2b4d3SLarry Finger #define _LLT_OP(x) (((x) & 0x3) << 30) 952f1d2b4d3SLarry Finger #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 953f1d2b4d3SLarry Finger 954f1d2b4d3SLarry Finger 955f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 956f1d2b4d3SLarry Finger /* 0x0400h ~ 0x047Fh Protocol Configuration */ 957f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 958f1d2b4d3SLarry Finger #define RETRY_LIMIT_SHORT_SHIFT 8 959f1d2b4d3SLarry Finger #define RETRY_LIMIT_LONG_SHIFT 0 960f1d2b4d3SLarry Finger 961f1d2b4d3SLarry Finger 962f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 963f1d2b4d3SLarry Finger /* 0x0500h ~ 0x05FFh EDCA Configuration */ 964f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 965f1d2b4d3SLarry Finger /* EDCA setting */ 966f1d2b4d3SLarry Finger #define AC_PARAM_TXOP_LIMIT_OFFSET 16 967f1d2b4d3SLarry Finger #define AC_PARAM_ECW_MAX_OFFSET 12 968f1d2b4d3SLarry Finger #define AC_PARAM_ECW_MIN_OFFSET 8 969f1d2b4d3SLarry Finger #define AC_PARAM_AIFS_OFFSET 0 970f1d2b4d3SLarry Finger 971f1d2b4d3SLarry Finger /* ACMHWCTRL */ 972f1d2b4d3SLarry Finger #define ACMHW_HWEN BIT(0) 973f1d2b4d3SLarry Finger #define ACMHW_BEQEN BIT(1) 974f1d2b4d3SLarry Finger #define ACMHW_VIQEN BIT(2) 975f1d2b4d3SLarry Finger #define ACMHW_VOQEN BIT(3) 976f1d2b4d3SLarry Finger 977f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 978f1d2b4d3SLarry Finger /* 0x0600h ~ 0x07FFh WMAC Configuration */ 979f1d2b4d3SLarry Finger /* ----------------------------------------------------- */ 980f1d2b4d3SLarry Finger 981f1d2b4d3SLarry Finger /* TCR */ 982f1d2b4d3SLarry Finger #define TSFRST BIT(0) 983f1d2b4d3SLarry Finger #define DIS_GCLK BIT(1) 984f1d2b4d3SLarry Finger #define PAD_SEL BIT(2) 985f1d2b4d3SLarry Finger #define PWR_ST BIT(6) 986f1d2b4d3SLarry Finger #define PWRBIT_OW_EN BIT(7) 987f1d2b4d3SLarry Finger #define ACRC BIT(8) 988f1d2b4d3SLarry Finger #define CFENDFORM BIT(9) 989f1d2b4d3SLarry Finger #define ICV BIT(10) 990f1d2b4d3SLarry Finger 991f1d2b4d3SLarry Finger /* SECCFG */ 992f1d2b4d3SLarry Finger #define SCR_TXUSEDK BIT(0) 993f1d2b4d3SLarry Finger #define SCR_RXUSEDK BIT(1) 994f1d2b4d3SLarry Finger #define SCR_TXENCENABLE BIT(2) 995f1d2b4d3SLarry Finger #define SCR_RXENCENABLE BIT(3) 996f1d2b4d3SLarry Finger #define SCR_SKBYA2 BIT(4) 997f1d2b4d3SLarry Finger #define SCR_NOSKMC BIT(5) 998f1d2b4d3SLarry Finger #define SCR_TXBCUSEDK BIT(6) 999f1d2b4d3SLarry Finger #define SCR_RXBCUSEDK BIT(7) 1000f1d2b4d3SLarry Finger 1001f1d2b4d3SLarry Finger /* General definitions */ 1002f1d2b4d3SLarry Finger #define LAST_ENTRY_OF_TX_PKT_BUFFER 255 1003f1d2b4d3SLarry Finger #define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127 1004f1d2b4d3SLarry Finger 1005f1d2b4d3SLarry Finger #define POLLING_LLT_THRESHOLD 20 1006f1d2b4d3SLarry Finger #define POLLING_READY_TIMEOUT_COUNT 1000 1007f1d2b4d3SLarry Finger 1008f1d2b4d3SLarry Finger /* Min Spacing related settings. */ 1009f1d2b4d3SLarry Finger #define MAX_MSS_DENSITY_2T 0x13 1010f1d2b4d3SLarry Finger #define MAX_MSS_DENSITY_1T 0x0A 1011f1d2b4d3SLarry Finger 1012f1d2b4d3SLarry Finger 1013f1d2b4d3SLarry Finger /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */ 1014f1d2b4d3SLarry Finger /* 1. PMAC duplicate register due to connection: */ 1015f1d2b4d3SLarry Finger /* RF_Mode, TRxRN, NumOf L-STF */ 1016f1d2b4d3SLarry Finger /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */ 1017f1d2b4d3SLarry Finger /* 3. RF register 0x00-2E */ 1018f1d2b4d3SLarry Finger /* 4. Bit Mask for BB/RF register */ 1019f1d2b4d3SLarry Finger /* 5. Other defintion for BB/RF R/W */ 1020f1d2b4d3SLarry Finger 1021f1d2b4d3SLarry Finger /* 3. Page8(0x800) */ 1022f1d2b4d3SLarry Finger #define RFPGA0_RFMOD 0x800 1023f1d2b4d3SLarry Finger 1024f1d2b4d3SLarry Finger #define RFPGA0_TXINFO 0x804 1025f1d2b4d3SLarry Finger #define RFPGA0_PSDFUNCTION 0x808 1026f1d2b4d3SLarry Finger 1027f1d2b4d3SLarry Finger #define RFPGA0_TXGAINSTAGE 0x80c 1028f1d2b4d3SLarry Finger 1029f1d2b4d3SLarry Finger #define RFPGA0_RFTIMING1 0x810 1030f1d2b4d3SLarry Finger #define RFPGA0_RFTIMING2 0x814 1031f1d2b4d3SLarry Finger 1032f1d2b4d3SLarry Finger #define RFPGA0_XA_HSSIPARAMETER1 0x820 1033f1d2b4d3SLarry Finger #define RFPGA0_XA_HSSIPARAMETER2 0x824 1034f1d2b4d3SLarry Finger #define RFPGA0_XB_HSSIPARAMETER1 0x828 1035f1d2b4d3SLarry Finger #define RFPGA0_XB_HSSIPARAMETER2 0x82c 1036f1d2b4d3SLarry Finger 1037f1d2b4d3SLarry Finger #define RFPGA0_XA_LSSIPARAMETER 0x840 1038f1d2b4d3SLarry Finger #define RFPGA0_XB_LSSIPARAMETER 0x844 1039f1d2b4d3SLarry Finger 1040f1d2b4d3SLarry Finger #define RFPGA0_RFWAkEUPPARAMETER 0x850 1041f1d2b4d3SLarry Finger #define RFPGA0_RFSLEEPUPPARAMETER 0x854 1042f1d2b4d3SLarry Finger 1043f1d2b4d3SLarry Finger #define RFPGA0_XAB_SWITCHCONTROL 0x858 1044f1d2b4d3SLarry Finger #define RFPGA0_XCD_SWITCHCONTROL 0x85c 1045f1d2b4d3SLarry Finger 1046f1d2b4d3SLarry Finger #define RFPGA0_XA_RFINTERFACEOE 0x860 1047f1d2b4d3SLarry Finger #define RFPGA0_XB_RFINTERFACEOE 0x864 1048f1d2b4d3SLarry Finger 1049f1d2b4d3SLarry Finger #define RFPGA0_XAB_RFINTERFACESW 0x870 1050f1d2b4d3SLarry Finger #define RFPGA0_XCD_RFINTERFACESW 0x874 1051f1d2b4d3SLarry Finger 1052f1d2b4d3SLarry Finger #define RFPGA0_XAB_RFPARAMETER 0x878 1053f1d2b4d3SLarry Finger #define RFPGA0_XCD_RFPARAMETER 0x87c 1054f1d2b4d3SLarry Finger 1055f1d2b4d3SLarry Finger #define RFPGA0_ANALOGPARAMETER1 0x880 1056f1d2b4d3SLarry Finger #define RFPGA0_ANALOGPARAMETER2 0x884 1057f1d2b4d3SLarry Finger #define RFPGA0_ANALOGPARAMETER3 0x888 1058f1d2b4d3SLarry Finger #define RFPGA0_ADDALLOCKEN 0x888 1059f1d2b4d3SLarry Finger #define RFPGA0_ANALOGPARAMETER4 0x88c 1060f1d2b4d3SLarry Finger 1061f1d2b4d3SLarry Finger #define RFPGA0_XA_LSSIREADBACK 0x8a0 1062f1d2b4d3SLarry Finger #define RFPGA0_XB_LSSIREADBACK 0x8a4 1063f1d2b4d3SLarry Finger #define RFPGA0_XC_LSSIREADBACK 0x8a8 1064f1d2b4d3SLarry Finger #define RFPGA0_XD_LSSIREADBACK 0x8ac 1065f1d2b4d3SLarry Finger 1066f1d2b4d3SLarry Finger #define RFPGA0_PSDREPORT 0x8b4 1067f1d2b4d3SLarry Finger #define TRANSCEIVERA_HSPI_READBACK 0x8b8 1068f1d2b4d3SLarry Finger #define TRANSCEIVERB_HSPI_READBACK 0x8bc 1069f1d2b4d3SLarry Finger #define RFPGA0_XAB_RFINTERFACERB 0x8e0 1070f1d2b4d3SLarry Finger #define RFPGA0_XCD_RFINTERFACERB 0x8e4 1071f1d2b4d3SLarry Finger 1072f1d2b4d3SLarry Finger /* 4. Page9(0x900) */ 1073f1d2b4d3SLarry Finger #define RFPGA1_RFMOD 0x900 1074f1d2b4d3SLarry Finger 1075f1d2b4d3SLarry Finger #define RFPGA1_TXBLOCK 0x904 1076f1d2b4d3SLarry Finger #define RFPGA1_DEBUGSELECT 0x908 1077f1d2b4d3SLarry Finger #define RFPGA1_TXINFO 0x90c 1078f1d2b4d3SLarry Finger 1079f1d2b4d3SLarry Finger /* 5. PageA(0xA00) */ 1080f1d2b4d3SLarry Finger #define RCCK0_SYSTEM 0xa00 1081f1d2b4d3SLarry Finger 1082f1d2b4d3SLarry Finger #define RCCK0_AFESSTTING 0xa04 1083f1d2b4d3SLarry Finger #define RCCK0_CCA 0xa08 1084f1d2b4d3SLarry Finger 1085f1d2b4d3SLarry Finger #define RCCK0_RXAGC1 0xa0c 1086f1d2b4d3SLarry Finger #define RCCK0_RXAGC2 0xa10 1087f1d2b4d3SLarry Finger 1088f1d2b4d3SLarry Finger #define RCCK0_RXHP 0xa14 1089f1d2b4d3SLarry Finger 1090f1d2b4d3SLarry Finger #define RCCK0_DSPPARAMETER1 0xa18 1091f1d2b4d3SLarry Finger #define RCCK0_DSPPARAMETER2 0xa1c 1092f1d2b4d3SLarry Finger 1093f1d2b4d3SLarry Finger #define RCCK0_TXFILTER1 0xa20 1094f1d2b4d3SLarry Finger #define RCCK0_TXFILTER2 0xa24 1095f1d2b4d3SLarry Finger #define RCCK0_DEBUGPORT 0xa28 1096f1d2b4d3SLarry Finger #define RCCK0_FALSEALARMREPORT 0xa2c 1097f1d2b4d3SLarry Finger #define RCCK0_TRSSIREPORT 0xa50 1098f1d2b4d3SLarry Finger #define RCCK0_RXREPORT 0xa54 1099f1d2b4d3SLarry Finger #define RCCK0_FACOUNTERLOWER 0xa5c 1100f1d2b4d3SLarry Finger #define RCCK0_FACOUNTERUPPER 0xa58 1101f1d2b4d3SLarry Finger 1102f1d2b4d3SLarry Finger /* 6. PageC(0xC00) */ 1103f1d2b4d3SLarry Finger #define ROFDM0_LSTF 0xc00 1104f1d2b4d3SLarry Finger 1105f1d2b4d3SLarry Finger #define ROFDM0_TRXPATHENABLE 0xc04 1106f1d2b4d3SLarry Finger #define ROFDM0_TRMUXPAR 0xc08 1107f1d2b4d3SLarry Finger #define ROFDM0_TRSWISOLATION 0xc0c 1108f1d2b4d3SLarry Finger 1109f1d2b4d3SLarry Finger #define ROFDM0_XARXAFE 0xc10 1110f1d2b4d3SLarry Finger #define ROFDM0_XARXIQIMBALANCE 0xc14 1111f1d2b4d3SLarry Finger #define ROFDM0_XBRXAFE 0xc18 1112f1d2b4d3SLarry Finger #define ROFDM0_XBRXIQIMBALANCE 0xc1c 1113f1d2b4d3SLarry Finger #define ROFDM0_XCRXAFE 0xc20 1114f1d2b4d3SLarry Finger #define ROFDM0_XCRXIQIMBALANCE 0xc24 1115f1d2b4d3SLarry Finger #define ROFDM0_XDRXAFE 0xc28 1116f1d2b4d3SLarry Finger #define ROFDM0_XDRXIQIMBALANCE 0xc2c 1117f1d2b4d3SLarry Finger 1118f1d2b4d3SLarry Finger #define ROFDM0_RXDETECTOR1 0xc30 1119f1d2b4d3SLarry Finger #define ROFDM0_RXDETECTOR2 0xc34 1120f1d2b4d3SLarry Finger #define ROFDM0_RXDETECTOR3 0xc38 1121f1d2b4d3SLarry Finger #define ROFDM0_RXDETECTOR4 0xc3c 1122f1d2b4d3SLarry Finger 1123f1d2b4d3SLarry Finger #define ROFDM0_RXDSP 0xc40 1124f1d2b4d3SLarry Finger #define ROFDM0_CFOANDDAGC 0xc44 1125f1d2b4d3SLarry Finger #define ROFDM0_CCADROPTHRESHOLD 0xc48 1126f1d2b4d3SLarry Finger #define ROFDM0_ECCATHRESHOLD 0xc4c 1127f1d2b4d3SLarry Finger 1128f1d2b4d3SLarry Finger #define ROFDM0_XAAGCCORE1 0xc50 1129f1d2b4d3SLarry Finger #define ROFDM0_XAAGCCORE2 0xc54 1130f1d2b4d3SLarry Finger #define ROFDM0_XBAGCCORE1 0xc58 1131f1d2b4d3SLarry Finger #define ROFDM0_XBAGCCORE2 0xc5c 1132f1d2b4d3SLarry Finger #define ROFDM0_XCAGCCORE1 0xc60 1133f1d2b4d3SLarry Finger #define ROFDM0_XCAGCCORE2 0xc64 1134f1d2b4d3SLarry Finger #define ROFDM0_XDAGCCORE1 0xc68 1135f1d2b4d3SLarry Finger #define ROFDM0_XDAGCCORE2 0xc6c 1136f1d2b4d3SLarry Finger 1137f1d2b4d3SLarry Finger #define ROFDM0_AGCPARAMETER1 0xc70 1138f1d2b4d3SLarry Finger #define ROFDM0_AGCPARAMETER2 0xc74 1139f1d2b4d3SLarry Finger #define ROFDM0_AGCRSSITABLE 0xc78 1140f1d2b4d3SLarry Finger #define ROFDM0_HTSTFAGC 0xc7c 1141f1d2b4d3SLarry Finger 1142f1d2b4d3SLarry Finger #define ROFDM0_XATxIQIMBALANCE 0xc80 1143f1d2b4d3SLarry Finger #define ROFDM0_XATxAFE 0xc84 1144f1d2b4d3SLarry Finger #define ROFDM0_XBTxIQIMBALANCE 0xc88 1145f1d2b4d3SLarry Finger #define ROFDM0_XBTxAFE 0xc8c 1146f1d2b4d3SLarry Finger #define ROFDM0_XCTxIQIMBALANCE 0xc90 1147f1d2b4d3SLarry Finger #define ROFDM0_XCTxAFE 0xc94 1148f1d2b4d3SLarry Finger #define ROFDM0_XDTxIQIMBALANCE 0xc98 1149f1d2b4d3SLarry Finger #define ROFDM0_XDTxAFE 0xc9c 1150f1d2b4d3SLarry Finger 1151f1d2b4d3SLarry Finger #define ROFDM0_RXHPPARAMETER 0xce0 1152f1d2b4d3SLarry Finger #define ROFDM0_TXPSEUDONOISEWGT 0xce4 1153f1d2b4d3SLarry Finger #define ROFDM0_FRAMESYNC 0xcf0 1154f1d2b4d3SLarry Finger #define ROFDM0_DFSREPORT 0xcf4 1155f1d2b4d3SLarry Finger #define ROFDM0_TXCOEFF1 0xca4 1156f1d2b4d3SLarry Finger #define ROFDM0_TXCOEFF2 0xca8 1157f1d2b4d3SLarry Finger #define ROFDM0_TXCOEFF3 0xcac 1158f1d2b4d3SLarry Finger #define ROFDM0_TXCOEFF4 0xcb0 1159f1d2b4d3SLarry Finger #define ROFDM0_TXCOEFF5 0xcb4 1160f1d2b4d3SLarry Finger #define ROFDM0_TXCOEFF6 0xcb8 1161f1d2b4d3SLarry Finger 1162f1d2b4d3SLarry Finger /* 7. PageD(0xD00) */ 1163f1d2b4d3SLarry Finger #define ROFDM1_LSTF 0xd00 1164f1d2b4d3SLarry Finger #define ROFDM1_TRXPATHENABLE 0xd04 1165f1d2b4d3SLarry Finger 1166f1d2b4d3SLarry Finger #define ROFDM1_CFO 0xd08 1167f1d2b4d3SLarry Finger #define ROFDM1_CSI1 0xd10 1168f1d2b4d3SLarry Finger #define ROFDM1_SBD 0xd14 1169f1d2b4d3SLarry Finger #define ROFDM1_CSI2 0xd18 1170f1d2b4d3SLarry Finger #define ROFDM1_CFOTRACKING 0xd2c 1171f1d2b4d3SLarry Finger #define ROFDM1_TRXMESAURE1 0xd34 1172f1d2b4d3SLarry Finger #define ROFDM1_INTFDET 0xd3c 1173f1d2b4d3SLarry Finger #define ROFDM1_PSEUDONOISESTATEAB 0xd50 1174f1d2b4d3SLarry Finger #define ROFDM1_PSEUDONOISESTATECD 0xd54 1175f1d2b4d3SLarry Finger #define ROFDM1_RXPSEUDONOISEWGT 0xd58 1176f1d2b4d3SLarry Finger 1177f1d2b4d3SLarry Finger #define ROFDM_PHYCOUNTER1 0xda0 1178f1d2b4d3SLarry Finger #define ROFDM_PHYCOUNTER2 0xda4 1179f1d2b4d3SLarry Finger #define ROFDM_PHYCOUNTER3 0xda8 1180f1d2b4d3SLarry Finger 1181f1d2b4d3SLarry Finger #define ROFDM_SHORTCFOAB 0xdac 1182f1d2b4d3SLarry Finger #define ROFDM_SHORTCFOCD 0xdb0 1183f1d2b4d3SLarry Finger #define ROFDM_LONGCFOAB 0xdb4 1184f1d2b4d3SLarry Finger #define ROFDM_LONGCFOCD 0xdb8 1185f1d2b4d3SLarry Finger #define ROFDM_TAILCFOAB 0xdbc 1186f1d2b4d3SLarry Finger #define ROFDM_TAILCFOCD 0xdc0 1187f1d2b4d3SLarry Finger #define ROFDM_PWMEASURE1 0xdc4 1188f1d2b4d3SLarry Finger #define ROFDM_PWMEASURE2 0xdc8 1189f1d2b4d3SLarry Finger #define ROFDM_BWREPORT 0xdcc 1190f1d2b4d3SLarry Finger #define ROFDM_AGCREPORT 0xdd0 1191f1d2b4d3SLarry Finger #define ROFDM_RXSNR 0xdd4 1192f1d2b4d3SLarry Finger #define ROFDM_RXEVMCSI 0xdd8 1193f1d2b4d3SLarry Finger #define ROFDM_SIGReport 0xddc 1194f1d2b4d3SLarry Finger 1195f1d2b4d3SLarry Finger /* 8. PageE(0xE00) */ 1196f1d2b4d3SLarry Finger #define RTXAGC_A_RATE18_06 0xe00 1197f1d2b4d3SLarry Finger #define RTXAGC_A_RATE54_24 0xe04 1198f1d2b4d3SLarry Finger #define RTXAGC_A_CCK1_MCS32 0xe08 1199f1d2b4d3SLarry Finger #define RTXAGC_A_MCS03_MCS00 0xe10 1200f1d2b4d3SLarry Finger #define RTXAGC_A_MCS07_MCS04 0xe14 1201f1d2b4d3SLarry Finger #define RTXAGC_A_MCS11_MCS08 0xe18 1202f1d2b4d3SLarry Finger #define RTXAGC_A_MCS15_MCS12 0xe1c 1203f1d2b4d3SLarry Finger 1204f1d2b4d3SLarry Finger #define RTXAGC_B_RATE18_06 0x830 1205f1d2b4d3SLarry Finger #define RTXAGC_B_RATE54_24 0x834 1206f1d2b4d3SLarry Finger #define RTXAGC_B_CCK1_55_MCS32 0x838 1207f1d2b4d3SLarry Finger #define RTXAGC_B_MCS03_MCS00 0x83c 1208f1d2b4d3SLarry Finger #define RTXAGC_B_MCS07_MCS04 0x848 1209f1d2b4d3SLarry Finger #define RTXAGC_B_MCS11_MCS08 0x84c 1210f1d2b4d3SLarry Finger #define RTXAGC_B_MCS15_MCS12 0x868 1211f1d2b4d3SLarry Finger #define RTXAGC_B_CCK11_A_CCK2_11 0x86c 1212f1d2b4d3SLarry Finger 1213f1d2b4d3SLarry Finger /* RL6052 Register definition */ 1214f1d2b4d3SLarry Finger #define RF_AC 0x00 1215f1d2b4d3SLarry Finger 1216f1d2b4d3SLarry Finger #define RF_IQADJ_G1 0x01 1217f1d2b4d3SLarry Finger #define RF_IQADJ_G2 0x02 1218f1d2b4d3SLarry Finger #define RF_POW_TRSW 0x05 1219f1d2b4d3SLarry Finger 1220f1d2b4d3SLarry Finger #define RF_GAIN_RX 0x06 1221f1d2b4d3SLarry Finger #define RF_GAIN_TX 0x07 1222f1d2b4d3SLarry Finger 1223f1d2b4d3SLarry Finger #define RF_TXM_IDAC 0x08 1224f1d2b4d3SLarry Finger #define RF_BS_IQGEN 0x0F 1225f1d2b4d3SLarry Finger 1226f1d2b4d3SLarry Finger #define RF_MODE1 0x10 1227f1d2b4d3SLarry Finger #define RF_MODE2 0x11 1228f1d2b4d3SLarry Finger 1229f1d2b4d3SLarry Finger #define RF_RX_AGC_HP 0x12 1230f1d2b4d3SLarry Finger #define RF_TX_AGC 0x13 1231f1d2b4d3SLarry Finger #define RF_BIAS 0x14 1232f1d2b4d3SLarry Finger #define RF_IPA 0x15 1233f1d2b4d3SLarry Finger #define RF_POW_ABILITY 0x17 1234f1d2b4d3SLarry Finger #define RF_MODE_AG 0x18 1235f1d2b4d3SLarry Finger #define rRfChannel 0x18 1236f1d2b4d3SLarry Finger #define RF_CHNLBW 0x18 1237f1d2b4d3SLarry Finger #define RF_TOP 0x19 1238f1d2b4d3SLarry Finger 1239f1d2b4d3SLarry Finger #define RF_RX_G1 0x1A 1240f1d2b4d3SLarry Finger #define RF_RX_G2 0x1B 1241f1d2b4d3SLarry Finger 1242f1d2b4d3SLarry Finger #define RF_RX_BB2 0x1C 1243f1d2b4d3SLarry Finger #define RF_RX_BB1 0x1D 1244f1d2b4d3SLarry Finger 1245f1d2b4d3SLarry Finger #define RF_RCK1 0x1E 1246f1d2b4d3SLarry Finger #define RF_RCK2 0x1F 1247f1d2b4d3SLarry Finger 1248f1d2b4d3SLarry Finger #define RF_TX_G1 0x20 1249f1d2b4d3SLarry Finger #define RF_TX_G2 0x21 1250f1d2b4d3SLarry Finger #define RF_TX_G3 0x22 1251f1d2b4d3SLarry Finger 1252f1d2b4d3SLarry Finger #define RF_TX_BB1 0x23 1253f1d2b4d3SLarry Finger 1254f1d2b4d3SLarry Finger #define RF_T_METER 0x42 1255f1d2b4d3SLarry Finger 1256f1d2b4d3SLarry Finger #define RF_SYN_G1 0x25 1257f1d2b4d3SLarry Finger #define RF_SYN_G2 0x26 1258f1d2b4d3SLarry Finger #define RF_SYN_G3 0x27 1259f1d2b4d3SLarry Finger #define RF_SYN_G4 0x28 1260f1d2b4d3SLarry Finger #define RF_SYN_G5 0x29 1261f1d2b4d3SLarry Finger #define RF_SYN_G6 0x2A 1262f1d2b4d3SLarry Finger #define RF_SYN_G7 0x2B 1263f1d2b4d3SLarry Finger #define RF_SYN_G8 0x2C 1264f1d2b4d3SLarry Finger 1265f1d2b4d3SLarry Finger #define RF_RCK_OS 0x30 1266f1d2b4d3SLarry Finger 1267f1d2b4d3SLarry Finger #define RF_TXPA_G1 0x31 1268f1d2b4d3SLarry Finger #define RF_TXPA_G2 0x32 1269f1d2b4d3SLarry Finger #define RF_TXPA_G3 0x33 1270f1d2b4d3SLarry Finger 1271f1d2b4d3SLarry Finger /* Bit Mask */ 1272f1d2b4d3SLarry Finger 1273f1d2b4d3SLarry Finger /* 2. Page8(0x800) */ 1274f1d2b4d3SLarry Finger #define BRFMOD 0x1 1275f1d2b4d3SLarry Finger #define BCCKTXSC 0x30 1276f1d2b4d3SLarry Finger #define BCCKEN 0x1000000 1277f1d2b4d3SLarry Finger #define BOFDMEN 0x2000000 1278f1d2b4d3SLarry Finger 1279f1d2b4d3SLarry Finger #define B3WIREDATALENGTH 0x800 1280f1d2b4d3SLarry Finger #define B3WIREADDRESSLENGTH 0x400 1281f1d2b4d3SLarry Finger 1282f1d2b4d3SLarry Finger #define BRFSI_RFENV 0x10 1283f1d2b4d3SLarry Finger 1284f1d2b4d3SLarry Finger #define BLSSIREADADDRESS 0x7f800000 1285f1d2b4d3SLarry Finger #define BLSSIREADEDGE 0x80000000 1286f1d2b4d3SLarry Finger #define BLSSIREADBACKDATA 0xfffff 1287f1d2b4d3SLarry Finger /* 4. PageA(0xA00) */ 1288f1d2b4d3SLarry Finger #define BCCKSIDEBAND 0x10 1289f1d2b4d3SLarry Finger 1290f1d2b4d3SLarry Finger /* Other Definition */ 1291f1d2b4d3SLarry Finger #define BBYTE0 0x1 1292f1d2b4d3SLarry Finger #define BBYTE1 0x2 1293f1d2b4d3SLarry Finger #define BBYTE2 0x4 1294f1d2b4d3SLarry Finger #define BBYTE3 0x8 1295f1d2b4d3SLarry Finger #define BWORD0 0x3 1296f1d2b4d3SLarry Finger #define BWORD1 0xc 1297f1d2b4d3SLarry Finger #define BDWORD 0xf 1298f1d2b4d3SLarry Finger 1299f1d2b4d3SLarry Finger #endif 1300