1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30 #include "../wifi.h" 31 #include "../pci.h" 32 #include "../ps.h" 33 #include "../core.h" 34 #include "reg.h" 35 #include "def.h" 36 #include "phy.h" 37 #include "rf.h" 38 #include "dm.h" 39 #include "table.h" 40 #include "sw.h" 41 #include "hw.h" 42 43 #define MAX_RF_IMR_INDEX 12 44 #define MAX_RF_IMR_INDEX_NORMAL 13 45 #define RF_REG_NUM_FOR_C_CUT_5G 6 46 #define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA 7 47 #define RF_REG_NUM_FOR_C_CUT_2G 5 48 #define RF_CHNL_NUM_5G 19 49 #define RF_CHNL_NUM_5G_40M 17 50 #define TARGET_CHNL_NUM_5G 221 51 #define TARGET_CHNL_NUM_2G 14 52 #define CV_CURVE_CNT 64 53 54 static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = { 55 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0 56 }; 57 58 static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = { 59 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6 60 }; 61 62 static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = { 63 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8 64 }; 65 66 static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = { 67 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E 68 }; 69 70 static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = { 71 BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1), 72 BIT(10) | BIT(9), 73 BIT(18) | BIT(17) | BIT(16) | BIT(1), 74 BIT(2) | BIT(1), 75 BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11) 76 }; 77 78 static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = { 79 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 80 112, 116, 120, 124, 128, 132, 136, 140 81 }; 82 83 static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = { 84 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114, 85 118, 122, 126, 130, 134, 138 86 }; 87 static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = { 88 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04}, 89 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04}, 90 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04}, 91 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04}, 92 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04} 93 }; 94 95 static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = { 96 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}, 97 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840}, 98 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41} 99 }; 100 101 static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF; 102 103 static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = { 104 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12}, 105 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52}, 106 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12} 107 }; 108 109 /* [mode][patha+b][reg] */ 110 static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = { 111 { 112 /* channel 1-14. */ 113 { 114 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0, 115 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff 116 }, 117 /* path 36-64 */ 118 { 119 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000, 120 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090, 121 0x32c9a 122 }, 123 /* 100 -165 */ 124 { 125 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000, 126 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a 127 } 128 } 129 }; 130 131 static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0}; 132 133 static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0}; 134 135 static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = { 136 25141, 25116, 25091, 25066, 25041, 137 25016, 24991, 24966, 24941, 24917, 138 24892, 24867, 24843, 24818, 24794, 139 24770, 24765, 24721, 24697, 24672, 140 24648, 24624, 24600, 24576, 24552, 141 24528, 24504, 24480, 24457, 24433, 142 24409, 24385, 24362, 24338, 24315, 143 24291, 24268, 24245, 24221, 24198, 144 24175, 24151, 24128, 24105, 24082, 145 24059, 24036, 24013, 23990, 23967, 146 23945, 23922, 23899, 23876, 23854, 147 23831, 23809, 23786, 23764, 23741, 148 23719, 23697, 23674, 23652, 23630, 149 23608, 23586, 23564, 23541, 23519, 150 23498, 23476, 23454, 23432, 23410, 151 23388, 23367, 23345, 23323, 23302, 152 23280, 23259, 23237, 23216, 23194, 153 23173, 23152, 23130, 23109, 23088, 154 23067, 23046, 23025, 23003, 22982, 155 22962, 22941, 22920, 22899, 22878, 156 22857, 22837, 22816, 22795, 22775, 157 22754, 22733, 22713, 22692, 22672, 158 22652, 22631, 22611, 22591, 22570, 159 22550, 22530, 22510, 22490, 22469, 160 22449, 22429, 22409, 22390, 22370, 161 22350, 22336, 22310, 22290, 22271, 162 22251, 22231, 22212, 22192, 22173, 163 22153, 22134, 22114, 22095, 22075, 164 22056, 22037, 22017, 21998, 21979, 165 21960, 21941, 21921, 21902, 21883, 166 21864, 21845, 21826, 21807, 21789, 167 21770, 21751, 21732, 21713, 21695, 168 21676, 21657, 21639, 21620, 21602, 169 21583, 21565, 21546, 21528, 21509, 170 21491, 21473, 21454, 21436, 21418, 171 21400, 21381, 21363, 21345, 21327, 172 21309, 21291, 21273, 21255, 21237, 173 21219, 21201, 21183, 21166, 21148, 174 21130, 21112, 21095, 21077, 21059, 175 21042, 21024, 21007, 20989, 20972, 176 25679, 25653, 25627, 25601, 25575, 177 25549, 25523, 25497, 25471, 25446, 178 25420, 25394, 25369, 25343, 25318, 179 25292, 25267, 25242, 25216, 25191, 180 25166 181 }; 182 183 /* channel 1~14 */ 184 static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = { 185 26084, 26030, 25976, 25923, 25869, 25816, 25764, 186 25711, 25658, 25606, 25554, 25502, 25451, 25328 187 }; 188 189 static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask) 190 { 191 u32 i; 192 193 for (i = 0; i <= 31; i++) { 194 if (((bitmask >> i) & 0x1) == 1) 195 break; 196 } 197 198 return i; 199 } 200 201 u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) 202 { 203 struct rtl_priv *rtlpriv = rtl_priv(hw); 204 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 205 u32 returnvalue, originalvalue, bitshift; 206 207 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n", 208 regaddr, bitmask); 209 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) { 210 u8 dbi_direct = 0; 211 212 /* mac1 use phy0 read radio_b. */ 213 /* mac0 use phy1 read radio_b. */ 214 if (rtlhal->during_mac1init_radioa) 215 dbi_direct = BIT(3); 216 else if (rtlhal->during_mac0init_radiob) 217 dbi_direct = BIT(3) | BIT(2); 218 originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr, 219 dbi_direct); 220 } else { 221 originalvalue = rtl_read_dword(rtlpriv, regaddr); 222 } 223 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); 224 returnvalue = (originalvalue & bitmask) >> bitshift; 225 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 226 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", 227 bitmask, regaddr, originalvalue); 228 return returnvalue; 229 } 230 231 void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw, 232 u32 regaddr, u32 bitmask, u32 data) 233 { 234 struct rtl_priv *rtlpriv = rtl_priv(hw); 235 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 236 u8 dbi_direct = 0; 237 u32 originalvalue, bitshift; 238 239 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 240 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 241 regaddr, bitmask, data); 242 if (rtlhal->during_mac1init_radioa) 243 dbi_direct = BIT(3); 244 else if (rtlhal->during_mac0init_radiob) 245 /* mac0 use phy1 write radio_b. */ 246 dbi_direct = BIT(3) | BIT(2); 247 if (bitmask != MASKDWORD) { 248 if (rtlhal->during_mac1init_radioa || 249 rtlhal->during_mac0init_radiob) 250 originalvalue = rtl92de_read_dword_dbi(hw, 251 (u16) regaddr, 252 dbi_direct); 253 else 254 originalvalue = rtl_read_dword(rtlpriv, regaddr); 255 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); 256 data = ((originalvalue & (~bitmask)) | (data << bitshift)); 257 } 258 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) 259 rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct); 260 else 261 rtl_write_dword(rtlpriv, regaddr, data); 262 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 263 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 264 regaddr, bitmask, data); 265 } 266 267 static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw, 268 enum radio_path rfpath, u32 offset) 269 { 270 271 struct rtl_priv *rtlpriv = rtl_priv(hw); 272 struct rtl_phy *rtlphy = &(rtlpriv->phy); 273 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 274 u32 newoffset; 275 u32 tmplong, tmplong2; 276 u8 rfpi_enable = 0; 277 u32 retvalue; 278 279 newoffset = offset; 280 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); 281 if (rfpath == RF90_PATH_A) 282 tmplong2 = tmplong; 283 else 284 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); 285 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | 286 (newoffset << 23) | BLSSIREADEDGE; 287 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 288 tmplong & (~BLSSIREADEDGE)); 289 udelay(10); 290 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); 291 udelay(50); 292 udelay(50); 293 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 294 tmplong | BLSSIREADEDGE); 295 udelay(10); 296 if (rfpath == RF90_PATH_A) 297 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, 298 BIT(8)); 299 else if (rfpath == RF90_PATH_B) 300 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, 301 BIT(8)); 302 if (rfpi_enable) 303 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, 304 BLSSIREADBACKDATA); 305 else 306 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 307 BLSSIREADBACKDATA); 308 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n", 309 rfpath, pphyreg->rf_rb, retvalue); 310 return retvalue; 311 } 312 313 static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw, 314 enum radio_path rfpath, 315 u32 offset, u32 data) 316 { 317 u32 data_and_addr; 318 u32 newoffset; 319 struct rtl_priv *rtlpriv = rtl_priv(hw); 320 struct rtl_phy *rtlphy = &(rtlpriv->phy); 321 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 322 323 newoffset = offset; 324 /* T65 RF */ 325 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 326 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 327 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", 328 rfpath, pphyreg->rf3wire_offset, data_and_addr); 329 } 330 331 u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, 332 enum radio_path rfpath, u32 regaddr, u32 bitmask) 333 { 334 struct rtl_priv *rtlpriv = rtl_priv(hw); 335 u32 original_value, readback_value, bitshift; 336 unsigned long flags; 337 338 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 339 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", 340 regaddr, rfpath, bitmask); 341 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 342 original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr); 343 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); 344 readback_value = (original_value & bitmask) >> bitshift; 345 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 346 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 347 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", 348 regaddr, rfpath, bitmask, original_value); 349 return readback_value; 350 } 351 352 void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, 353 u32 regaddr, u32 bitmask, u32 data) 354 { 355 struct rtl_priv *rtlpriv = rtl_priv(hw); 356 struct rtl_phy *rtlphy = &(rtlpriv->phy); 357 u32 original_value, bitshift; 358 unsigned long flags; 359 360 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 361 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 362 regaddr, bitmask, data, rfpath); 363 if (bitmask == 0) 364 return; 365 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 366 if (rtlphy->rf_mode != RF_OP_BY_FW) { 367 if (bitmask != RFREG_OFFSET_MASK) { 368 original_value = _rtl92d_phy_rf_serial_read(hw, 369 rfpath, regaddr); 370 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); 371 data = ((original_value & (~bitmask)) | 372 (data << bitshift)); 373 } 374 _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data); 375 } 376 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 377 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 378 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 379 regaddr, bitmask, data, rfpath); 380 } 381 382 bool rtl92d_phy_mac_config(struct ieee80211_hw *hw) 383 { 384 struct rtl_priv *rtlpriv = rtl_priv(hw); 385 u32 i; 386 u32 arraylength; 387 u32 *ptrarray; 388 389 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n"); 390 arraylength = MAC_2T_ARRAYLENGTH; 391 ptrarray = rtl8192de_mac_2tarray; 392 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n"); 393 for (i = 0; i < arraylength; i = i + 2) 394 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]); 395 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) { 396 /* improve 2-stream TX EVM */ 397 /* rtl_write_byte(rtlpriv, 0x14,0x71); */ 398 /* AMPDU aggregation number 9 */ 399 /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */ 400 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B); 401 } else { 402 /* 92D need to test to decide the num. */ 403 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07); 404 } 405 return true; 406 } 407 408 static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) 409 { 410 struct rtl_priv *rtlpriv = rtl_priv(hw); 411 struct rtl_phy *rtlphy = &(rtlpriv->phy); 412 413 /* RF Interface Sowrtware Control */ 414 /* 16 LSBs if read 32-bit from 0x870 */ 415 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; 416 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ 417 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; 418 /* 16 LSBs if read 32-bit from 0x874 */ 419 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; 420 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ 421 422 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; 423 /* RF Interface Readback Value */ 424 /* 16 LSBs if read 32-bit from 0x8E0 */ 425 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; 426 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ 427 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; 428 /* 16 LSBs if read 32-bit from 0x8E4 */ 429 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; 430 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ 431 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; 432 433 /* RF Interface Output (and Enable) */ 434 /* 16 LSBs if read 32-bit from 0x860 */ 435 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; 436 /* 16 LSBs if read 32-bit from 0x864 */ 437 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; 438 439 /* RF Interface (Output and) Enable */ 440 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ 441 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; 442 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ 443 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; 444 445 /* Addr of LSSI. Wirte RF register by driver */ 446 /* LSSI Parameter */ 447 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = 448 RFPGA0_XA_LSSIPARAMETER; 449 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = 450 RFPGA0_XB_LSSIPARAMETER; 451 452 /* RF parameter */ 453 /* BB Band Select */ 454 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; 455 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; 456 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; 457 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; 458 459 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ 460 /* Tx gain stage */ 461 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; 462 /* Tx gain stage */ 463 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; 464 /* Tx gain stage */ 465 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; 466 /* Tx gain stage */ 467 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; 468 469 /* Tranceiver A~D HSSI Parameter-1 */ 470 /* wire control parameter1 */ 471 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; 472 /* wire control parameter1 */ 473 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; 474 475 /* Tranceiver A~D HSSI Parameter-2 */ 476 /* wire control parameter2 */ 477 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; 478 /* wire control parameter2 */ 479 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; 480 481 /* RF switch Control */ 482 /* TR/Ant switch control */ 483 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 484 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 485 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 486 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 487 488 /* AGC control 1 */ 489 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; 490 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; 491 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; 492 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; 493 494 /* AGC control 2 */ 495 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; 496 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; 497 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; 498 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; 499 500 /* RX AFE control 1 */ 501 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; 502 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; 503 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE; 504 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; 505 506 /*RX AFE control 1 */ 507 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; 508 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; 509 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; 510 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; 511 512 /* Tx AFE control 1 */ 513 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATxIQIMBALANCE; 514 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTxIQIMBALANCE; 515 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTxIQIMBALANCE; 516 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTxIQIMBALANCE; 517 518 /* Tx AFE control 2 */ 519 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATxAFE; 520 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE; 521 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTxAFE; 522 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE; 523 524 /* Tranceiver LSSI Readback SI mode */ 525 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; 526 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; 527 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; 528 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; 529 530 /* Tranceiver LSSI Readback PI mode */ 531 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK; 532 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK; 533 } 534 535 static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 536 u8 configtype) 537 { 538 int i; 539 u32 *phy_regarray_table; 540 u32 *agctab_array_table = NULL; 541 u32 *agctab_5garray_table; 542 u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen; 543 struct rtl_priv *rtlpriv = rtl_priv(hw); 544 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 545 546 /* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */ 547 if (rtlhal->interfaceindex == 0) { 548 agctab_arraylen = AGCTAB_ARRAYLENGTH; 549 agctab_array_table = rtl8192de_agctab_array; 550 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 551 " ===> phy:MAC0, Rtl819XAGCTAB_Array\n"); 552 } else { 553 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 554 agctab_arraylen = AGCTAB_2G_ARRAYLENGTH; 555 agctab_array_table = rtl8192de_agctab_2garray; 556 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 557 " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n"); 558 } else { 559 agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH; 560 agctab_5garray_table = rtl8192de_agctab_5garray; 561 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 562 " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n"); 563 564 } 565 } 566 phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH; 567 phy_regarray_table = rtl8192de_phy_reg_2tarray; 568 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 569 " ===> phy:Rtl819XPHY_REG_Array_PG\n"); 570 if (configtype == BASEBAND_CONFIG_PHY_REG) { 571 for (i = 0; i < phy_reg_arraylen; i = i + 2) { 572 rtl_addr_delay(phy_regarray_table[i]); 573 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, 574 phy_regarray_table[i + 1]); 575 udelay(1); 576 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 577 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", 578 phy_regarray_table[i], 579 phy_regarray_table[i + 1]); 580 } 581 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 582 if (rtlhal->interfaceindex == 0) { 583 for (i = 0; i < agctab_arraylen; i = i + 2) { 584 rtl_set_bbreg(hw, agctab_array_table[i], 585 MASKDWORD, 586 agctab_array_table[i + 1]); 587 /* Add 1us delay between BB/RF register 588 * setting. */ 589 udelay(1); 590 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 591 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", 592 agctab_array_table[i], 593 agctab_array_table[i + 1]); 594 } 595 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 596 "Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n"); 597 } else { 598 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 599 for (i = 0; i < agctab_arraylen; i = i + 2) { 600 rtl_set_bbreg(hw, agctab_array_table[i], 601 MASKDWORD, 602 agctab_array_table[i + 1]); 603 /* Add 1us delay between BB/RF register 604 * setting. */ 605 udelay(1); 606 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 607 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", 608 agctab_array_table[i], 609 agctab_array_table[i + 1]); 610 } 611 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 612 "Load Rtl819XAGCTAB_2GArray\n"); 613 } else { 614 for (i = 0; i < agctab_5garraylen; i = i + 2) { 615 rtl_set_bbreg(hw, 616 agctab_5garray_table[i], 617 MASKDWORD, 618 agctab_5garray_table[i + 1]); 619 /* Add 1us delay between BB/RF registeri 620 * setting. */ 621 udelay(1); 622 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 623 "The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", 624 agctab_5garray_table[i], 625 agctab_5garray_table[i + 1]); 626 } 627 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 628 "Load Rtl819XAGCTAB_5GArray\n"); 629 } 630 } 631 } 632 return true; 633 } 634 635 static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, 636 u32 regaddr, u32 bitmask, 637 u32 data) 638 { 639 struct rtl_priv *rtlpriv = rtl_priv(hw); 640 struct rtl_phy *rtlphy = &(rtlpriv->phy); 641 int index; 642 643 if (regaddr == RTXAGC_A_RATE18_06) 644 index = 0; 645 else if (regaddr == RTXAGC_A_RATE54_24) 646 index = 1; 647 else if (regaddr == RTXAGC_A_CCK1_MCS32) 648 index = 6; 649 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) 650 index = 7; 651 else if (regaddr == RTXAGC_A_MCS03_MCS00) 652 index = 2; 653 else if (regaddr == RTXAGC_A_MCS07_MCS04) 654 index = 3; 655 else if (regaddr == RTXAGC_A_MCS11_MCS08) 656 index = 4; 657 else if (regaddr == RTXAGC_A_MCS15_MCS12) 658 index = 5; 659 else if (regaddr == RTXAGC_B_RATE18_06) 660 index = 8; 661 else if (regaddr == RTXAGC_B_RATE54_24) 662 index = 9; 663 else if (regaddr == RTXAGC_B_CCK1_55_MCS32) 664 index = 14; 665 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) 666 index = 15; 667 else if (regaddr == RTXAGC_B_MCS03_MCS00) 668 index = 10; 669 else if (regaddr == RTXAGC_B_MCS07_MCS04) 670 index = 11; 671 else if (regaddr == RTXAGC_B_MCS11_MCS08) 672 index = 12; 673 else if (regaddr == RTXAGC_B_MCS15_MCS12) 674 index = 13; 675 else 676 return; 677 678 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; 679 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 680 "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", 681 rtlphy->pwrgroup_cnt, index, 682 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]); 683 if (index == 13) 684 rtlphy->pwrgroup_cnt++; 685 } 686 687 static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, 688 u8 configtype) 689 { 690 struct rtl_priv *rtlpriv = rtl_priv(hw); 691 int i; 692 u32 *phy_regarray_table_pg; 693 u16 phy_regarray_pg_len; 694 695 phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH; 696 phy_regarray_table_pg = rtl8192de_phy_reg_array_pg; 697 if (configtype == BASEBAND_CONFIG_PHY_REG) { 698 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { 699 rtl_addr_delay(phy_regarray_table_pg[i]); 700 _rtl92d_store_pwrindex_diffrate_offset(hw, 701 phy_regarray_table_pg[i], 702 phy_regarray_table_pg[i + 1], 703 phy_regarray_table_pg[i + 2]); 704 } 705 } else { 706 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, 707 "configtype != BaseBand_Config_PHY_REG\n"); 708 } 709 return true; 710 } 711 712 static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw) 713 { 714 struct rtl_priv *rtlpriv = rtl_priv(hw); 715 struct rtl_phy *rtlphy = &(rtlpriv->phy); 716 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 717 bool rtstatus = true; 718 719 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n"); 720 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw, 721 BASEBAND_CONFIG_PHY_REG); 722 if (!rtstatus) { 723 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!\n"); 724 return false; 725 } 726 727 /* if (rtlphy->rf_type == RF_1T2R) { 728 * _rtl92c_phy_bb_config_1t(hw); 729 * RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n"); 730 *} */ 731 732 if (rtlefuse->autoload_failflag == false) { 733 rtlphy->pwrgroup_cnt = 0; 734 rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw, 735 BASEBAND_CONFIG_PHY_REG); 736 } 737 if (!rtstatus) { 738 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!\n"); 739 return false; 740 } 741 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw, 742 BASEBAND_CONFIG_AGC_TAB); 743 if (!rtstatus) { 744 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n"); 745 return false; 746 } 747 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw, 748 RFPGA0_XA_HSSIPARAMETER2, 0x200)); 749 750 return true; 751 } 752 753 bool rtl92d_phy_bb_config(struct ieee80211_hw *hw) 754 { 755 struct rtl_priv *rtlpriv = rtl_priv(hw); 756 u16 regval; 757 u32 regvaldw; 758 u8 value; 759 760 _rtl92d_phy_init_bb_rf_register_definition(hw); 761 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 762 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, 763 regval | BIT(13) | BIT(0) | BIT(1)); 764 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83); 765 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb); 766 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */ 767 value = rtl_read_byte(rtlpriv, REG_RF_CTRL); 768 rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB | 769 RF_SDMRSTB); 770 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA | 771 FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB); 772 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); 773 if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) { 774 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0); 775 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23)); 776 } 777 778 return _rtl92d_phy_bb_config(hw); 779 } 780 781 bool rtl92d_phy_rf_config(struct ieee80211_hw *hw) 782 { 783 return rtl92d_phy_rf6052_config(hw); 784 } 785 786 bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 787 enum rf_content content, 788 enum radio_path rfpath) 789 { 790 int i; 791 u32 *radioa_array_table; 792 u32 *radiob_array_table; 793 u16 radioa_arraylen, radiob_arraylen; 794 struct rtl_priv *rtlpriv = rtl_priv(hw); 795 796 radioa_arraylen = RADIOA_2T_ARRAYLENGTH; 797 radioa_array_table = rtl8192de_radioa_2tarray; 798 radiob_arraylen = RADIOB_2T_ARRAYLENGTH; 799 radiob_array_table = rtl8192de_radiob_2tarray; 800 if (rtlpriv->efuse.internal_pa_5g[0]) { 801 radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH; 802 radioa_array_table = rtl8192de_radioa_2t_int_paarray; 803 } 804 if (rtlpriv->efuse.internal_pa_5g[1]) { 805 radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH; 806 radiob_array_table = rtl8192de_radiob_2t_int_paarray; 807 } 808 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 809 "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n"); 810 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 811 "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n"); 812 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath); 813 814 /* this only happens when DMDP, mac0 start on 2.4G, 815 * mac1 start on 5G, mac 0 has to set phy0&phy1 816 * pathA or mac1 has to set phy0&phy1 pathA */ 817 if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) { 818 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 819 " ===> althougth Path A, we load radiob.txt\n"); 820 radioa_arraylen = radiob_arraylen; 821 radioa_array_table = radiob_array_table; 822 } 823 switch (rfpath) { 824 case RF90_PATH_A: 825 for (i = 0; i < radioa_arraylen; i = i + 2) { 826 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i], 827 RFREG_OFFSET_MASK, 828 radioa_array_table[i + 1]); 829 } 830 break; 831 case RF90_PATH_B: 832 for (i = 0; i < radiob_arraylen; i = i + 2) { 833 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i], 834 RFREG_OFFSET_MASK, 835 radiob_array_table[i + 1]); 836 } 837 break; 838 case RF90_PATH_C: 839 case RF90_PATH_D: 840 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 841 "switch case %#x not processed\n", rfpath); 842 break; 843 } 844 return true; 845 } 846 847 void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 848 { 849 struct rtl_priv *rtlpriv = rtl_priv(hw); 850 struct rtl_phy *rtlphy = &(rtlpriv->phy); 851 852 rtlphy->default_initialgain[0] = 853 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); 854 rtlphy->default_initialgain[1] = 855 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); 856 rtlphy->default_initialgain[2] = 857 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); 858 rtlphy->default_initialgain[3] = 859 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); 860 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 861 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", 862 rtlphy->default_initialgain[0], 863 rtlphy->default_initialgain[1], 864 rtlphy->default_initialgain[2], 865 rtlphy->default_initialgain[3]); 866 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, 867 MASKBYTE0); 868 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, 869 MASKDWORD); 870 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 871 "Default framesync (0x%x) = 0x%x\n", 872 ROFDM0_RXDETECTOR3, rtlphy->framesync); 873 } 874 875 static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel, 876 u8 *cckpowerlevel, u8 *ofdmpowerlevel) 877 { 878 struct rtl_priv *rtlpriv = rtl_priv(hw); 879 struct rtl_phy *rtlphy = &(rtlpriv->phy); 880 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 881 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 882 u8 index = (channel - 1); 883 884 /* 1. CCK */ 885 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 886 /* RF-A */ 887 cckpowerlevel[RF90_PATH_A] = 888 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index]; 889 /* RF-B */ 890 cckpowerlevel[RF90_PATH_B] = 891 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index]; 892 } else { 893 cckpowerlevel[RF90_PATH_A] = 0; 894 cckpowerlevel[RF90_PATH_B] = 0; 895 } 896 /* 2. OFDM for 1S or 2S */ 897 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) { 898 /* Read HT 40 OFDM TX power */ 899 ofdmpowerlevel[RF90_PATH_A] = 900 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index]; 901 ofdmpowerlevel[RF90_PATH_B] = 902 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index]; 903 } else if (rtlphy->rf_type == RF_2T2R) { 904 /* Read HT 40 OFDM TX power */ 905 ofdmpowerlevel[RF90_PATH_A] = 906 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index]; 907 ofdmpowerlevel[RF90_PATH_B] = 908 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index]; 909 } 910 } 911 912 static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw, 913 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel) 914 { 915 struct rtl_priv *rtlpriv = rtl_priv(hw); 916 struct rtl_phy *rtlphy = &(rtlpriv->phy); 917 918 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; 919 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; 920 } 921 922 static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl) 923 { 924 u8 place = chnl; 925 926 if (chnl > 14) { 927 for (place = 14; place < sizeof(channel5g); place++) { 928 if (channel5g[place] == chnl) { 929 place++; 930 break; 931 } 932 } 933 } 934 return place; 935 } 936 937 void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) 938 { 939 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 940 struct rtl_priv *rtlpriv = rtl_priv(hw); 941 u8 cckpowerlevel[2], ofdmpowerlevel[2]; 942 943 if (!rtlefuse->txpwr_fromeprom) 944 return; 945 channel = _rtl92c_phy_get_rightchnlplace(channel); 946 _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0], 947 &ofdmpowerlevel[0]); 948 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) 949 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0], 950 &ofdmpowerlevel[0]); 951 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) 952 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); 953 rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel); 954 } 955 956 void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw, 957 enum nl80211_channel_type ch_type) 958 { 959 struct rtl_priv *rtlpriv = rtl_priv(hw); 960 struct rtl_phy *rtlphy = &(rtlpriv->phy); 961 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 962 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 963 unsigned long flag = 0; 964 u8 reg_prsr_rsc; 965 u8 reg_bw_opmode; 966 967 if (rtlphy->set_bwmode_inprogress) 968 return; 969 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { 970 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 971 "FALSE driver sleep or unload\n"); 972 return; 973 } 974 rtlphy->set_bwmode_inprogress = true; 975 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n", 976 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 977 "20MHz" : "40MHz"); 978 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE); 979 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2); 980 switch (rtlphy->current_chan_bw) { 981 case HT_CHANNEL_WIDTH_20: 982 reg_bw_opmode |= BW_OPMODE_20MHZ; 983 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 984 break; 985 case HT_CHANNEL_WIDTH_20_40: 986 reg_bw_opmode &= ~BW_OPMODE_20MHZ; 987 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 988 989 reg_prsr_rsc = (reg_prsr_rsc & 0x90) | 990 (mac->cur_40_prime_sc << 5); 991 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc); 992 break; 993 default: 994 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 995 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); 996 break; 997 } 998 switch (rtlphy->current_chan_bw) { 999 case HT_CHANNEL_WIDTH_20: 1000 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); 1001 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); 1002 /* SET BIT10 BIT11 for receive cck */ 1003 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | 1004 BIT(11), 3); 1005 break; 1006 case HT_CHANNEL_WIDTH_20_40: 1007 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); 1008 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); 1009 /* Set Control channel to upper or lower. 1010 * These settings are required only for 40MHz */ 1011 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 1012 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 1013 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND, 1014 (mac->cur_40_prime_sc >> 1)); 1015 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 1016 } 1017 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); 1018 /* SET BIT10 BIT11 for receive cck */ 1019 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | 1020 BIT(11), 0); 1021 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), 1022 (mac->cur_40_prime_sc == 1023 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); 1024 break; 1025 default: 1026 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1027 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); 1028 break; 1029 1030 } 1031 rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 1032 rtlphy->set_bwmode_inprogress = false; 1033 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 1034 } 1035 1036 static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw) 1037 { 1038 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0); 1039 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0); 1040 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); 1041 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); 1042 } 1043 1044 static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band) 1045 { 1046 struct rtl_priv *rtlpriv = rtl_priv(hw); 1047 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1048 u8 value8; 1049 1050 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n"); 1051 rtlhal->bandset = band; 1052 rtlhal->current_bandtype = band; 1053 if (IS_92D_SINGLEPHY(rtlhal->version)) 1054 rtlhal->bandset = BAND_ON_BOTH; 1055 /* stop RX/Tx */ 1056 _rtl92d_phy_stop_trx_before_changeband(hw); 1057 /* reconfig BB/RF according to wireless mode */ 1058 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 1059 /* BB & RF Config */ 1060 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n"); 1061 if (rtlhal->interfaceindex == 1) 1062 _rtl92d_phy_config_bb_with_headerfile(hw, 1063 BASEBAND_CONFIG_AGC_TAB); 1064 } else { 1065 /* 5G band */ 1066 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n"); 1067 if (rtlhal->interfaceindex == 1) 1068 _rtl92d_phy_config_bb_with_headerfile(hw, 1069 BASEBAND_CONFIG_AGC_TAB); 1070 } 1071 rtl92d_update_bbrf_configuration(hw); 1072 if (rtlhal->current_bandtype == BAND_ON_2_4G) 1073 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1074 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1075 1076 /* 20M BW. */ 1077 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */ 1078 rtlhal->reloadtxpowerindex = true; 1079 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ 1080 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 1081 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex == 1082 0 ? REG_MAC0 : REG_MAC1)); 1083 value8 |= BIT(1); 1084 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex == 1085 0 ? REG_MAC0 : REG_MAC1), value8); 1086 } else { 1087 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex == 1088 0 ? REG_MAC0 : REG_MAC1)); 1089 value8 &= (~BIT(1)); 1090 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex == 1091 0 ? REG_MAC0 : REG_MAC1), value8); 1092 } 1093 mdelay(1); 1094 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n"); 1095 } 1096 1097 static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw, 1098 u8 channel, u8 rfpath) 1099 { 1100 struct rtl_priv *rtlpriv = rtl_priv(hw); 1101 u32 imr_num = MAX_RF_IMR_INDEX; 1102 u32 rfmask = RFREG_OFFSET_MASK; 1103 u8 group, i; 1104 unsigned long flag = 0; 1105 1106 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath); 1107 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) { 1108 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); 1109 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); 1110 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); 1111 /* fc area 0xd2c */ 1112 if (channel > 99) 1113 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | 1114 BIT(14), 2); 1115 else 1116 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | 1117 BIT(14), 1); 1118 /* leave 0 for channel1-14. */ 1119 group = channel <= 64 ? 1 : 2; 1120 imr_num = MAX_RF_IMR_INDEX_NORMAL; 1121 for (i = 0; i < imr_num; i++) 1122 rtl_set_rfreg(hw, (enum radio_path)rfpath, 1123 rf_reg_for_5g_swchnl_normal[i], rfmask, 1124 rf_imr_param_normal[0][group][i]); 1125 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); 1126 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1); 1127 } else { 1128 /* G band. */ 1129 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, 1130 "Load RF IMR parameters for G band. IMR already setting %d\n", 1131 rtlpriv->rtlhal.load_imrandiqk_setting_for2g); 1132 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); 1133 if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) { 1134 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, 1135 "Load RF IMR parameters for G band. %d\n", 1136 rfpath); 1137 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 1138 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); 1139 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 1140 0x00f00000, 0xf); 1141 imr_num = MAX_RF_IMR_INDEX_NORMAL; 1142 for (i = 0; i < imr_num; i++) { 1143 rtl_set_rfreg(hw, (enum radio_path)rfpath, 1144 rf_reg_for_5g_swchnl_normal[i], 1145 RFREG_OFFSET_MASK, 1146 rf_imr_param_normal[0][0][i]); 1147 } 1148 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 1149 0x00f00000, 0); 1150 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3); 1151 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 1152 } 1153 } 1154 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 1155 } 1156 1157 static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw, 1158 u8 rfpath, u32 *pu4_regval) 1159 { 1160 struct rtl_priv *rtlpriv = rtl_priv(hw); 1161 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1162 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 1163 1164 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "====>\n"); 1165 /*----Store original RFENV control type----*/ 1166 switch (rfpath) { 1167 case RF90_PATH_A: 1168 case RF90_PATH_C: 1169 *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV); 1170 break; 1171 case RF90_PATH_B: 1172 case RF90_PATH_D: 1173 *pu4_regval = 1174 rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16); 1175 break; 1176 } 1177 /*----Set RF_ENV enable----*/ 1178 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); 1179 udelay(1); 1180 /*----Set RF_ENV output high----*/ 1181 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); 1182 udelay(1); 1183 /* Set bit number of Address and Data for RF register */ 1184 /* Set 1 to 4 bits for 8255 */ 1185 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0); 1186 udelay(1); 1187 /*Set 0 to 12 bits for 8255 */ 1188 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); 1189 udelay(1); 1190 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<====\n"); 1191 } 1192 1193 static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath, 1194 u32 *pu4_regval) 1195 { 1196 struct rtl_priv *rtlpriv = rtl_priv(hw); 1197 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1198 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 1199 1200 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n"); 1201 /*----Restore RFENV control type----*/ 1202 switch (rfpath) { 1203 case RF90_PATH_A: 1204 case RF90_PATH_C: 1205 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval); 1206 break; 1207 case RF90_PATH_B: 1208 case RF90_PATH_D: 1209 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16, 1210 *pu4_regval); 1211 break; 1212 } 1213 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n"); 1214 } 1215 1216 static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) 1217 { 1218 struct rtl_priv *rtlpriv = rtl_priv(hw); 1219 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1220 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 1221 u8 path = rtlhal->current_bandtype == 1222 BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B; 1223 u8 index = 0, i = 0, rfpath = RF90_PATH_A; 1224 bool need_pwr_down = false, internal_pa = false; 1225 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2; 1226 1227 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n"); 1228 /* config path A for 5G */ 1229 if (rtlhal->current_bandtype == BAND_ON_5G) { 1230 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); 1231 u4tmp = curveindex_5g[channel - 1]; 1232 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1233 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); 1234 for (i = 0; i < RF_CHNL_NUM_5G; i++) { 1235 if (channel == rf_chnl_5g[i] && channel <= 140) 1236 index = 0; 1237 } 1238 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) { 1239 if (channel == rf_chnl_5g_40m[i] && channel <= 140) 1240 index = 1; 1241 } 1242 if (channel == 149 || channel == 155 || channel == 161) 1243 index = 2; 1244 else if (channel == 151 || channel == 153 || channel == 163 1245 || channel == 165) 1246 index = 3; 1247 else if (channel == 157 || channel == 159) 1248 index = 4; 1249 1250 if (rtlhal->macphymode == DUALMAC_DUALPHY 1251 && rtlhal->interfaceindex == 1) { 1252 need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false); 1253 rtlhal->during_mac1init_radioa = true; 1254 /* asume no this case */ 1255 if (need_pwr_down) 1256 _rtl92d_phy_enable_rf_env(hw, path, 1257 &u4regvalue); 1258 } 1259 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) { 1260 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) { 1261 rtl_set_rfreg(hw, (enum radio_path)path, 1262 rf_reg_for_c_cut_5g[i], 1263 RFREG_OFFSET_MASK, 0xE439D); 1264 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) { 1265 u4tmp2 = (rf_reg_pram_c_5g[index][i] & 1266 0x7FF) | (u4tmp << 11); 1267 if (channel == 36) 1268 u4tmp2 &= ~(BIT(7) | BIT(6)); 1269 rtl_set_rfreg(hw, (enum radio_path)path, 1270 rf_reg_for_c_cut_5g[i], 1271 RFREG_OFFSET_MASK, u4tmp2); 1272 } else { 1273 rtl_set_rfreg(hw, (enum radio_path)path, 1274 rf_reg_for_c_cut_5g[i], 1275 RFREG_OFFSET_MASK, 1276 rf_reg_pram_c_5g[index][i]); 1277 } 1278 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 1279 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n", 1280 rf_reg_for_c_cut_5g[i], 1281 rf_reg_pram_c_5g[index][i], 1282 path, index, 1283 rtl_get_rfreg(hw, (enum radio_path)path, 1284 rf_reg_for_c_cut_5g[i], 1285 RFREG_OFFSET_MASK)); 1286 } 1287 if (need_pwr_down) 1288 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); 1289 if (rtlhal->during_mac1init_radioa) 1290 rtl92d_phy_powerdown_anotherphy(hw, false); 1291 if (channel < 149) 1292 value = 0x07; 1293 else if (channel >= 149) 1294 value = 0x02; 1295 if (channel >= 36 && channel <= 64) 1296 index = 0; 1297 else if (channel >= 100 && channel <= 140) 1298 index = 1; 1299 else 1300 index = 2; 1301 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 1302 rfpath++) { 1303 if (rtlhal->macphymode == DUALMAC_DUALPHY && 1304 rtlhal->interfaceindex == 1) /* MAC 1 5G */ 1305 internal_pa = rtlpriv->efuse.internal_pa_5g[1]; 1306 else 1307 internal_pa = 1308 rtlpriv->efuse.internal_pa_5g[rfpath]; 1309 if (internal_pa) { 1310 for (i = 0; 1311 i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA; 1312 i++) { 1313 rtl_set_rfreg(hw, rfpath, 1314 rf_for_c_cut_5g_internal_pa[i], 1315 RFREG_OFFSET_MASK, 1316 rf_pram_c_5g_int_pa[index][i]); 1317 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, 1318 "offset 0x%x value 0x%x path %d index %d\n", 1319 rf_for_c_cut_5g_internal_pa[i], 1320 rf_pram_c_5g_int_pa[index][i], 1321 rfpath, index); 1322 } 1323 } else { 1324 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, 1325 mask, value); 1326 } 1327 } 1328 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { 1329 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); 1330 u4tmp = curveindex_2g[channel - 1]; 1331 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1332 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); 1333 if (channel == 1 || channel == 2 || channel == 4 || channel == 9 1334 || channel == 10 || channel == 11 || channel == 12) 1335 index = 0; 1336 else if (channel == 3 || channel == 13 || channel == 14) 1337 index = 1; 1338 else if (channel >= 5 && channel <= 8) 1339 index = 2; 1340 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 1341 path = RF90_PATH_A; 1342 if (rtlhal->interfaceindex == 0) { 1343 need_pwr_down = 1344 rtl92d_phy_enable_anotherphy(hw, true); 1345 rtlhal->during_mac0init_radiob = true; 1346 1347 if (need_pwr_down) 1348 _rtl92d_phy_enable_rf_env(hw, path, 1349 &u4regvalue); 1350 } 1351 } 1352 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) { 1353 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7) 1354 rtl_set_rfreg(hw, (enum radio_path)path, 1355 rf_reg_for_c_cut_2g[i], 1356 RFREG_OFFSET_MASK, 1357 (rf_reg_param_for_c_cut_2g[index][i] | 1358 BIT(17))); 1359 else 1360 rtl_set_rfreg(hw, (enum radio_path)path, 1361 rf_reg_for_c_cut_2g[i], 1362 RFREG_OFFSET_MASK, 1363 rf_reg_param_for_c_cut_2g 1364 [index][i]); 1365 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 1366 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n", 1367 rf_reg_for_c_cut_2g[i], 1368 rf_reg_param_for_c_cut_2g[index][i], 1369 rf_reg_mask_for_c_cut_2g[i], path, index, 1370 rtl_get_rfreg(hw, (enum radio_path)path, 1371 rf_reg_for_c_cut_2g[i], 1372 RFREG_OFFSET_MASK)); 1373 } 1374 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1375 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", 1376 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); 1377 1378 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4, 1379 RFREG_OFFSET_MASK, 1380 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); 1381 if (need_pwr_down) 1382 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); 1383 if (rtlhal->during_mac0init_radiob) 1384 rtl92d_phy_powerdown_anotherphy(hw, true); 1385 } 1386 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 1387 } 1388 1389 u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl) 1390 { 1391 u8 channel_all[59] = { 1392 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 1393 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 1394 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 1395 114, 116, 118, 120, 122, 124, 126, 128, 130, 1396 132, 134, 136, 138, 140, 149, 151, 153, 155, 1397 157, 159, 161, 163, 165 1398 }; 1399 u8 place = chnl; 1400 1401 if (chnl > 14) { 1402 for (place = 14; place < sizeof(channel_all); place++) { 1403 if (channel_all[place] == chnl) 1404 return place - 13; 1405 } 1406 } 1407 1408 return 0; 1409 } 1410 1411 #define MAX_TOLERANCE 5 1412 #define IQK_DELAY_TIME 1 /* ms */ 1413 #define MAX_TOLERANCE_92D 3 1414 1415 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1416 static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb) 1417 { 1418 struct rtl_priv *rtlpriv = rtl_priv(hw); 1419 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1420 u32 regeac, rege94, rege9c, regea4; 1421 u8 result = 0; 1422 1423 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n"); 1424 /* path-A IQK setting */ 1425 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1426 if (rtlhal->interfaceindex == 0) { 1427 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); 1428 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); 1429 } else { 1430 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); 1431 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); 1432 } 1433 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); 1434 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); 1435 /* path-B IQK setting */ 1436 if (configpathb) { 1437 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); 1438 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); 1439 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); 1440 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); 1441 } 1442 /* LO calibration setting */ 1443 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1444 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); 1445 /* One shot, path A LOK & IQK */ 1446 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); 1447 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); 1448 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 1449 /* delay x ms */ 1450 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1451 "Delay %d ms for One shot, path A LOK & IQK\n", 1452 IQK_DELAY_TIME); 1453 mdelay(IQK_DELAY_TIME); 1454 /* Check failed */ 1455 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1456 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1457 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); 1458 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); 1459 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); 1460 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); 1461 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); 1462 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); 1463 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) && 1464 (((rege9c & 0x03FF0000) >> 16) != 0x42)) 1465 result |= 0x01; 1466 else /* if Tx not OK, ignore Rx */ 1467 return result; 1468 /* if Tx is OK, check whether Rx is OK */ 1469 if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) && 1470 (((regeac & 0x03FF0000) >> 16) != 0x36)) 1471 result |= 0x02; 1472 else 1473 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A Rx IQK fail!!\n"); 1474 return result; 1475 } 1476 1477 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1478 static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw, 1479 bool configpathb) 1480 { 1481 struct rtl_priv *rtlpriv = rtl_priv(hw); 1482 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1483 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1484 u32 regeac, rege94, rege9c, regea4; 1485 u8 result = 0; 1486 u8 i; 1487 u8 retrycount = 2; 1488 u32 TxOKBit = BIT(28), RxOKBit = BIT(27); 1489 1490 if (rtlhal->interfaceindex == 1) { /* PHY1 */ 1491 TxOKBit = BIT(31); 1492 RxOKBit = BIT(30); 1493 } 1494 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n"); 1495 /* path-A IQK setting */ 1496 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1497 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); 1498 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); 1499 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); 1500 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); 1501 /* path-B IQK setting */ 1502 if (configpathb) { 1503 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); 1504 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); 1505 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); 1506 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); 1507 } 1508 /* LO calibration setting */ 1509 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1510 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); 1511 /* path-A PA on */ 1512 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); 1513 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); 1514 for (i = 0; i < retrycount; i++) { 1515 /* One shot, path A LOK & IQK */ 1516 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1517 "One shot, path A LOK & IQK!\n"); 1518 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); 1519 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 1520 /* delay x ms */ 1521 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1522 "Delay %d ms for One shot, path A LOK & IQK.\n", 1523 IQK_DELAY_TIME); 1524 mdelay(IQK_DELAY_TIME * 10); 1525 /* Check failed */ 1526 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1527 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1528 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); 1529 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); 1530 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); 1531 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); 1532 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); 1533 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); 1534 if (!(regeac & TxOKBit) && 1535 (((rege94 & 0x03FF0000) >> 16) != 0x142)) { 1536 result |= 0x01; 1537 } else { /* if Tx not OK, ignore Rx */ 1538 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1539 "Path A Tx IQK fail!!\n"); 1540 continue; 1541 } 1542 1543 /* if Tx is OK, check whether Rx is OK */ 1544 if (!(regeac & RxOKBit) && 1545 (((regea4 & 0x03FF0000) >> 16) != 0x132)) { 1546 result |= 0x02; 1547 break; 1548 } else { 1549 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1550 "Path A Rx IQK fail!!\n"); 1551 } 1552 } 1553 /* path A PA off */ 1554 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 1555 rtlphy->iqk_bb_backup[0]); 1556 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 1557 rtlphy->iqk_bb_backup[1]); 1558 return result; 1559 } 1560 1561 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1562 static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw) 1563 { 1564 struct rtl_priv *rtlpriv = rtl_priv(hw); 1565 u32 regeac, regeb4, regebc, regec4, regecc; 1566 u8 result = 0; 1567 1568 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n"); 1569 /* One shot, path B LOK & IQK */ 1570 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); 1571 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); 1572 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); 1573 /* delay x ms */ 1574 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1575 "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME); 1576 mdelay(IQK_DELAY_TIME); 1577 /* Check failed */ 1578 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1579 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1580 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); 1581 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); 1582 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); 1583 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); 1584 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); 1585 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); 1586 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); 1587 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); 1588 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) && 1589 (((regebc & 0x03FF0000) >> 16) != 0x42)) 1590 result |= 0x01; 1591 else 1592 return result; 1593 if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) && 1594 (((regecc & 0x03FF0000) >> 16) != 0x36)) 1595 result |= 0x02; 1596 else 1597 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B Rx IQK fail!!\n"); 1598 return result; 1599 } 1600 1601 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1602 static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw) 1603 { 1604 struct rtl_priv *rtlpriv = rtl_priv(hw); 1605 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1606 u32 regeac, regeb4, regebc, regec4, regecc; 1607 u8 result = 0; 1608 u8 i; 1609 u8 retrycount = 2; 1610 1611 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n"); 1612 /* path-A IQK setting */ 1613 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1614 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); 1615 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); 1616 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); 1617 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); 1618 1619 /* path-B IQK setting */ 1620 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); 1621 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); 1622 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); 1623 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); 1624 1625 /* LO calibration setting */ 1626 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1627 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); 1628 1629 /* path-B PA on */ 1630 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); 1631 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); 1632 1633 for (i = 0; i < retrycount; i++) { 1634 /* One shot, path B LOK & IQK */ 1635 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1636 "One shot, path A LOK & IQK!\n"); 1637 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); 1638 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 1639 1640 /* delay x ms */ 1641 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1642 "Delay %d ms for One shot, path B LOK & IQK.\n", 10); 1643 mdelay(IQK_DELAY_TIME * 10); 1644 1645 /* Check failed */ 1646 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1647 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1648 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); 1649 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); 1650 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); 1651 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); 1652 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); 1653 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); 1654 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); 1655 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); 1656 if (!(regeac & BIT(31)) && 1657 (((regeb4 & 0x03FF0000) >> 16) != 0x142)) 1658 result |= 0x01; 1659 else 1660 continue; 1661 if (!(regeac & BIT(30)) && 1662 (((regec4 & 0x03FF0000) >> 16) != 0x132)) { 1663 result |= 0x02; 1664 break; 1665 } else { 1666 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1667 "Path B Rx IQK fail!!\n"); 1668 } 1669 } 1670 1671 /* path B PA off */ 1672 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 1673 rtlphy->iqk_bb_backup[0]); 1674 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 1675 rtlphy->iqk_bb_backup[2]); 1676 return result; 1677 } 1678 1679 static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw, 1680 u32 *adda_reg, u32 *adda_backup, 1681 u32 regnum) 1682 { 1683 struct rtl_priv *rtlpriv = rtl_priv(hw); 1684 u32 i; 1685 1686 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n"); 1687 for (i = 0; i < regnum; i++) 1688 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD); 1689 } 1690 1691 static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw, 1692 u32 *macreg, u32 *macbackup) 1693 { 1694 struct rtl_priv *rtlpriv = rtl_priv(hw); 1695 u32 i; 1696 1697 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save MAC parameters.\n"); 1698 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1699 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]); 1700 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]); 1701 } 1702 1703 static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw, 1704 u32 *adda_reg, u32 *adda_backup, 1705 u32 regnum) 1706 { 1707 struct rtl_priv *rtlpriv = rtl_priv(hw); 1708 u32 i; 1709 1710 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1711 "Reload ADDA power saving parameters !\n"); 1712 for (i = 0; i < regnum; i++) 1713 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); 1714 } 1715 1716 static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw, 1717 u32 *macreg, u32 *macbackup) 1718 { 1719 struct rtl_priv *rtlpriv = rtl_priv(hw); 1720 u32 i; 1721 1722 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Reload MAC parameters !\n"); 1723 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1724 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]); 1725 rtl_write_byte(rtlpriv, macreg[i], macbackup[i]); 1726 } 1727 1728 static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw, 1729 u32 *adda_reg, bool patha_on, bool is2t) 1730 { 1731 struct rtl_priv *rtlpriv = rtl_priv(hw); 1732 u32 pathon; 1733 u32 i; 1734 1735 RTPRINT(rtlpriv, FINIT, INIT_IQK, "ADDA ON.\n"); 1736 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4; 1737 if (patha_on) 1738 pathon = rtlpriv->rtlhal.interfaceindex == 0 ? 1739 0x04db25a4 : 0x0b1b25a4; 1740 for (i = 0; i < IQK_ADDA_REG_NUM; i++) 1741 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon); 1742 } 1743 1744 static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw, 1745 u32 *macreg, u32 *macbackup) 1746 { 1747 struct rtl_priv *rtlpriv = rtl_priv(hw); 1748 u32 i; 1749 1750 RTPRINT(rtlpriv, FINIT, INIT_IQK, "MAC settings for Calibration.\n"); 1751 rtl_write_byte(rtlpriv, macreg[0], 0x3F); 1752 1753 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) 1754 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & 1755 (~BIT(3)))); 1756 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5)))); 1757 } 1758 1759 static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw) 1760 { 1761 struct rtl_priv *rtlpriv = rtl_priv(hw); 1762 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n"); 1763 1764 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); 1765 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); 1766 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1767 } 1768 1769 static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode) 1770 { 1771 struct rtl_priv *rtlpriv = rtl_priv(hw); 1772 u32 mode; 1773 1774 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1775 "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI"); 1776 mode = pi_mode ? 0x01000100 : 0x01000000; 1777 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); 1778 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); 1779 } 1780 1781 static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], 1782 u8 t, bool is2t) 1783 { 1784 struct rtl_priv *rtlpriv = rtl_priv(hw); 1785 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1786 u32 i; 1787 u8 patha_ok, pathb_ok; 1788 static u32 adda_reg[IQK_ADDA_REG_NUM] = { 1789 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, 1790 0xe78, 0xe7c, 0xe80, 0xe84, 1791 0xe88, 0xe8c, 0xed0, 0xed4, 1792 0xed8, 0xedc, 0xee0, 0xeec 1793 }; 1794 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 1795 0x522, 0x550, 0x551, 0x040 1796 }; 1797 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = { 1798 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE, 1799 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR, 1800 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE, 1801 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4, 1802 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1 1803 }; 1804 const u32 retrycount = 2; 1805 u32 bbvalue; 1806 1807 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n"); 1808 if (t == 0) { 1809 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); 1810 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); 1811 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", 1812 is2t ? "2T2R" : "1T1R"); 1813 1814 /* Save ADDA parameters, turn Path A ADDA on */ 1815 _rtl92d_phy_save_adda_registers(hw, adda_reg, 1816 rtlphy->adda_backup, IQK_ADDA_REG_NUM); 1817 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, 1818 rtlphy->iqk_mac_backup); 1819 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, 1820 rtlphy->iqk_bb_backup, IQK_BB_REG_NUM); 1821 } 1822 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); 1823 if (t == 0) 1824 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, 1825 RFPGA0_XA_HSSIPARAMETER1, BIT(8)); 1826 1827 /* Switch BB to PI mode to do IQ Calibration. */ 1828 if (!rtlphy->rfpi_enable) 1829 _rtl92d_phy_pimode_switch(hw, true); 1830 1831 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); 1832 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); 1833 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); 1834 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); 1835 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); 1836 if (is2t) { 1837 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 1838 0x00010000); 1839 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, 1840 0x00010000); 1841 } 1842 /* MAC settings */ 1843 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, 1844 rtlphy->iqk_mac_backup); 1845 /* Page B init */ 1846 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); 1847 if (is2t) 1848 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); 1849 /* IQ calibration setting */ 1850 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); 1851 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1852 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); 1853 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); 1854 for (i = 0; i < retrycount; i++) { 1855 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t); 1856 if (patha_ok == 0x03) { 1857 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1858 "Path A IQK Success!!\n"); 1859 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 1860 0x3FF0000) >> 16; 1861 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 1862 0x3FF0000) >> 16; 1863 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & 1864 0x3FF0000) >> 16; 1865 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & 1866 0x3FF0000) >> 16; 1867 break; 1868 } else if (i == (retrycount - 1) && patha_ok == 0x01) { 1869 /* Tx IQK OK */ 1870 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1871 "Path A IQK Only Tx Success!!\n"); 1872 1873 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 1874 0x3FF0000) >> 16; 1875 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 1876 0x3FF0000) >> 16; 1877 } 1878 } 1879 if (0x00 == patha_ok) 1880 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK failed!!\n"); 1881 if (is2t) { 1882 _rtl92d_phy_patha_standby(hw); 1883 /* Turn Path B ADDA on */ 1884 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); 1885 for (i = 0; i < retrycount; i++) { 1886 pathb_ok = _rtl92d_phy_pathb_iqk(hw); 1887 if (pathb_ok == 0x03) { 1888 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1889 "Path B IQK Success!!\n"); 1890 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, 1891 MASKDWORD) & 0x3FF0000) >> 16; 1892 result[t][5] = (rtl_get_bbreg(hw, 0xebc, 1893 MASKDWORD) & 0x3FF0000) >> 16; 1894 result[t][6] = (rtl_get_bbreg(hw, 0xec4, 1895 MASKDWORD) & 0x3FF0000) >> 16; 1896 result[t][7] = (rtl_get_bbreg(hw, 0xecc, 1897 MASKDWORD) & 0x3FF0000) >> 16; 1898 break; 1899 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { 1900 /* Tx IQK OK */ 1901 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1902 "Path B Only Tx IQK Success!!\n"); 1903 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, 1904 MASKDWORD) & 0x3FF0000) >> 16; 1905 result[t][5] = (rtl_get_bbreg(hw, 0xebc, 1906 MASKDWORD) & 0x3FF0000) >> 16; 1907 } 1908 } 1909 if (0x00 == pathb_ok) 1910 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1911 "Path B IQK failed!!\n"); 1912 } 1913 1914 /* Back to BB mode, load original value */ 1915 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1916 "IQK:Back to BB mode, load original value!\n"); 1917 1918 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); 1919 if (t != 0) { 1920 /* Switch back BB to SI mode after finish IQ Calibration. */ 1921 if (!rtlphy->rfpi_enable) 1922 _rtl92d_phy_pimode_switch(hw, false); 1923 /* Reload ADDA power saving parameters */ 1924 _rtl92d_phy_reload_adda_registers(hw, adda_reg, 1925 rtlphy->adda_backup, IQK_ADDA_REG_NUM); 1926 /* Reload MAC parameters */ 1927 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg, 1928 rtlphy->iqk_mac_backup); 1929 if (is2t) 1930 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 1931 rtlphy->iqk_bb_backup, 1932 IQK_BB_REG_NUM); 1933 else 1934 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 1935 rtlphy->iqk_bb_backup, 1936 IQK_BB_REG_NUM - 1); 1937 /* load 0xe30 IQC default value */ 1938 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); 1939 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); 1940 } 1941 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); 1942 } 1943 1944 static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw, 1945 long result[][8], u8 t) 1946 { 1947 struct rtl_priv *rtlpriv = rtl_priv(hw); 1948 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1949 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 1950 u8 patha_ok, pathb_ok; 1951 static u32 adda_reg[IQK_ADDA_REG_NUM] = { 1952 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, 1953 0xe78, 0xe7c, 0xe80, 0xe84, 1954 0xe88, 0xe8c, 0xed0, 0xed4, 1955 0xed8, 0xedc, 0xee0, 0xeec 1956 }; 1957 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 1958 0x522, 0x550, 0x551, 0x040 1959 }; 1960 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = { 1961 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE, 1962 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR, 1963 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE, 1964 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4, 1965 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1 1966 }; 1967 u32 bbvalue; 1968 bool is2t = IS_92D_SINGLEPHY(rtlhal->version); 1969 1970 /* Note: IQ calibration must be performed after loading 1971 * PHY_REG.txt , and radio_a, radio_b.txt */ 1972 1973 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n"); 1974 mdelay(IQK_DELAY_TIME * 20); 1975 if (t == 0) { 1976 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); 1977 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); 1978 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", 1979 is2t ? "2T2R" : "1T1R"); 1980 /* Save ADDA parameters, turn Path A ADDA on */ 1981 _rtl92d_phy_save_adda_registers(hw, adda_reg, 1982 rtlphy->adda_backup, 1983 IQK_ADDA_REG_NUM); 1984 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, 1985 rtlphy->iqk_mac_backup); 1986 if (is2t) 1987 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, 1988 rtlphy->iqk_bb_backup, 1989 IQK_BB_REG_NUM); 1990 else 1991 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, 1992 rtlphy->iqk_bb_backup, 1993 IQK_BB_REG_NUM - 1); 1994 } 1995 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); 1996 /* MAC settings */ 1997 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, 1998 rtlphy->iqk_mac_backup); 1999 if (t == 0) 2000 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, 2001 RFPGA0_XA_HSSIPARAMETER1, BIT(8)); 2002 /* Switch BB to PI mode to do IQ Calibration. */ 2003 if (!rtlphy->rfpi_enable) 2004 _rtl92d_phy_pimode_switch(hw, true); 2005 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); 2006 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); 2007 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); 2008 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); 2009 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); 2010 2011 /* Page B init */ 2012 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); 2013 if (is2t) 2014 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); 2015 /* IQ calibration setting */ 2016 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); 2017 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 2018 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); 2019 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); 2020 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t); 2021 if (patha_ok == 0x03) { 2022 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n"); 2023 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 2024 0x3FF0000) >> 16; 2025 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 2026 0x3FF0000) >> 16; 2027 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & 2028 0x3FF0000) >> 16; 2029 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & 2030 0x3FF0000) >> 16; 2031 } else if (patha_ok == 0x01) { /* Tx IQK OK */ 2032 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2033 "Path A IQK Only Tx Success!!\n"); 2034 2035 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 2036 0x3FF0000) >> 16; 2037 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 2038 0x3FF0000) >> 16; 2039 } else { 2040 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n"); 2041 } 2042 if (is2t) { 2043 /* _rtl92d_phy_patha_standby(hw); */ 2044 /* Turn Path B ADDA on */ 2045 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); 2046 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw); 2047 if (pathb_ok == 0x03) { 2048 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2049 "Path B IQK Success!!\n"); 2050 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & 2051 0x3FF0000) >> 16; 2052 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 2053 0x3FF0000) >> 16; 2054 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & 2055 0x3FF0000) >> 16; 2056 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & 2057 0x3FF0000) >> 16; 2058 } else if (pathb_ok == 0x01) { /* Tx IQK OK */ 2059 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2060 "Path B Only Tx IQK Success!!\n"); 2061 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & 2062 0x3FF0000) >> 16; 2063 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 2064 0x3FF0000) >> 16; 2065 } else { 2066 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2067 "Path B IQK failed!!\n"); 2068 } 2069 } 2070 2071 /* Back to BB mode, load original value */ 2072 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2073 "IQK:Back to BB mode, load original value!\n"); 2074 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); 2075 if (t != 0) { 2076 if (is2t) 2077 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 2078 rtlphy->iqk_bb_backup, 2079 IQK_BB_REG_NUM); 2080 else 2081 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 2082 rtlphy->iqk_bb_backup, 2083 IQK_BB_REG_NUM - 1); 2084 /* Reload MAC parameters */ 2085 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg, 2086 rtlphy->iqk_mac_backup); 2087 /* Switch back BB to SI mode after finish IQ Calibration. */ 2088 if (!rtlphy->rfpi_enable) 2089 _rtl92d_phy_pimode_switch(hw, false); 2090 /* Reload ADDA power saving parameters */ 2091 _rtl92d_phy_reload_adda_registers(hw, adda_reg, 2092 rtlphy->adda_backup, 2093 IQK_ADDA_REG_NUM); 2094 } 2095 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); 2096 } 2097 2098 static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw, 2099 long result[][8], u8 c1, u8 c2) 2100 { 2101 struct rtl_priv *rtlpriv = rtl_priv(hw); 2102 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2103 u32 i, j, diff, sim_bitmap, bound; 2104 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ 2105 bool bresult = true; 2106 bool is2t = IS_92D_SINGLEPHY(rtlhal->version); 2107 2108 if (is2t) 2109 bound = 8; 2110 else 2111 bound = 4; 2112 sim_bitmap = 0; 2113 for (i = 0; i < bound; i++) { 2114 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - 2115 result[c2][i]) : (result[c2][i] - result[c1][i]); 2116 if (diff > MAX_TOLERANCE_92D) { 2117 if ((i == 2 || i == 6) && !sim_bitmap) { 2118 if (result[c1][i] + result[c1][i + 1] == 0) 2119 final_candidate[(i / 4)] = c2; 2120 else if (result[c2][i] + result[c2][i + 1] == 0) 2121 final_candidate[(i / 4)] = c1; 2122 else 2123 sim_bitmap = sim_bitmap | (1 << i); 2124 } else { 2125 sim_bitmap = sim_bitmap | (1 << i); 2126 } 2127 } 2128 } 2129 if (sim_bitmap == 0) { 2130 for (i = 0; i < (bound / 4); i++) { 2131 if (final_candidate[i] != 0xFF) { 2132 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2133 result[3][j] = 2134 result[final_candidate[i]][j]; 2135 bresult = false; 2136 } 2137 } 2138 return bresult; 2139 } 2140 if (!(sim_bitmap & 0x0F)) { /* path A OK */ 2141 for (i = 0; i < 4; i++) 2142 result[3][i] = result[c1][i]; 2143 } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */ 2144 for (i = 0; i < 2; i++) 2145 result[3][i] = result[c1][i]; 2146 } 2147 if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */ 2148 for (i = 4; i < 8; i++) 2149 result[3][i] = result[c1][i]; 2150 } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */ 2151 for (i = 4; i < 6; i++) 2152 result[3][i] = result[c1][i]; 2153 } 2154 return false; 2155 } 2156 2157 static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw, 2158 bool iqk_ok, long result[][8], 2159 u8 final_candidate, bool txonly) 2160 { 2161 struct rtl_priv *rtlpriv = rtl_priv(hw); 2162 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2163 u32 oldval_0, val_x, tx0_a, reg; 2164 long val_y, tx0_c; 2165 bool is2t = IS_92D_SINGLEPHY(rtlhal->version) || 2166 rtlhal->macphymode == DUALMAC_DUALPHY; 2167 2168 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2169 "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed"); 2170 if (final_candidate == 0xFF) { 2171 return; 2172 } else if (iqk_ok) { 2173 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 2174 MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */ 2175 val_x = result[final_candidate][0]; 2176 if ((val_x & 0x00000200) != 0) 2177 val_x = val_x | 0xFFFFFC00; 2178 tx0_a = (val_x * oldval_0) >> 8; 2179 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2180 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n", 2181 val_x, tx0_a, oldval_0); 2182 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a); 2183 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), 2184 ((val_x * oldval_0 >> 7) & 0x1)); 2185 val_y = result[final_candidate][1]; 2186 if ((val_y & 0x00000200) != 0) 2187 val_y = val_y | 0xFFFFFC00; 2188 /* path B IQK result + 3 */ 2189 if (rtlhal->interfaceindex == 1 && 2190 rtlhal->current_bandtype == BAND_ON_5G) 2191 val_y += 3; 2192 tx0_c = (val_y * oldval_0) >> 8; 2193 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2194 "Y = 0x%lx, tx0_c = 0x%lx\n", 2195 val_y, tx0_c); 2196 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 2197 ((tx0_c & 0x3C0) >> 6)); 2198 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000, 2199 (tx0_c & 0x3F)); 2200 if (is2t) 2201 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), 2202 ((val_y * oldval_0 >> 7) & 0x1)); 2203 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n", 2204 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 2205 MASKDWORD)); 2206 if (txonly) { 2207 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n"); 2208 return; 2209 } 2210 reg = result[final_candidate][2]; 2211 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); 2212 reg = result[final_candidate][3] & 0x3F; 2213 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); 2214 reg = (result[final_candidate][3] >> 6) & 0xF; 2215 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); 2216 } 2217 } 2218 2219 static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw, 2220 bool iqk_ok, long result[][8], u8 final_candidate, bool txonly) 2221 { 2222 struct rtl_priv *rtlpriv = rtl_priv(hw); 2223 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2224 u32 oldval_1, val_x, tx1_a, reg; 2225 long val_y, tx1_c; 2226 2227 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n", 2228 iqk_ok ? "Success" : "Failed"); 2229 if (final_candidate == 0xFF) { 2230 return; 2231 } else if (iqk_ok) { 2232 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 2233 MASKDWORD) >> 22) & 0x3FF; 2234 val_x = result[final_candidate][4]; 2235 if ((val_x & 0x00000200) != 0) 2236 val_x = val_x | 0xFFFFFC00; 2237 tx1_a = (val_x * oldval_1) >> 8; 2238 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n", 2239 val_x, tx1_a); 2240 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a); 2241 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), 2242 ((val_x * oldval_1 >> 7) & 0x1)); 2243 val_y = result[final_candidate][5]; 2244 if ((val_y & 0x00000200) != 0) 2245 val_y = val_y | 0xFFFFFC00; 2246 if (rtlhal->current_bandtype == BAND_ON_5G) 2247 val_y += 3; 2248 tx1_c = (val_y * oldval_1) >> 8; 2249 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n", 2250 val_y, tx1_c); 2251 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 2252 ((tx1_c & 0x3C0) >> 6)); 2253 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000, 2254 (tx1_c & 0x3F)); 2255 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), 2256 ((val_y * oldval_1 >> 7) & 0x1)); 2257 if (txonly) 2258 return; 2259 reg = result[final_candidate][6]; 2260 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); 2261 reg = result[final_candidate][7] & 0x3F; 2262 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); 2263 reg = (result[final_candidate][7] >> 6) & 0xF; 2264 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); 2265 } 2266 } 2267 2268 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw) 2269 { 2270 struct rtl_priv *rtlpriv = rtl_priv(hw); 2271 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2272 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2273 long result[4][8]; 2274 u8 i, final_candidate, indexforchannel; 2275 bool patha_ok, pathb_ok; 2276 long rege94, rege9c, regea4, regeac, regeb4; 2277 long regebc, regec4, regecc, regtmp = 0; 2278 bool is12simular, is13simular, is23simular; 2279 unsigned long flag = 0; 2280 2281 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2282 "IQK:Start!!!channel %d\n", rtlphy->current_channel); 2283 for (i = 0; i < 8; i++) { 2284 result[0][i] = 0; 2285 result[1][i] = 0; 2286 result[2][i] = 0; 2287 result[3][i] = 0; 2288 } 2289 final_candidate = 0xff; 2290 patha_ok = false; 2291 pathb_ok = false; 2292 is12simular = false; 2293 is23simular = false; 2294 is13simular = false; 2295 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2296 "IQK !!!currentband %d\n", rtlhal->current_bandtype); 2297 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 2298 for (i = 0; i < 3; i++) { 2299 if (rtlhal->current_bandtype == BAND_ON_5G) { 2300 _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i); 2301 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { 2302 if (IS_92D_SINGLEPHY(rtlhal->version)) 2303 _rtl92d_phy_iq_calibrate(hw, result, i, true); 2304 else 2305 _rtl92d_phy_iq_calibrate(hw, result, i, false); 2306 } 2307 if (i == 1) { 2308 is12simular = _rtl92d_phy_simularity_compare(hw, result, 2309 0, 1); 2310 if (is12simular) { 2311 final_candidate = 0; 2312 break; 2313 } 2314 } 2315 if (i == 2) { 2316 is13simular = _rtl92d_phy_simularity_compare(hw, result, 2317 0, 2); 2318 if (is13simular) { 2319 final_candidate = 0; 2320 break; 2321 } 2322 is23simular = _rtl92d_phy_simularity_compare(hw, result, 2323 1, 2); 2324 if (is23simular) { 2325 final_candidate = 1; 2326 } else { 2327 for (i = 0; i < 8; i++) 2328 regtmp += result[3][i]; 2329 2330 if (regtmp != 0) 2331 final_candidate = 3; 2332 else 2333 final_candidate = 0xFF; 2334 } 2335 } 2336 } 2337 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 2338 for (i = 0; i < 4; i++) { 2339 rege94 = result[i][0]; 2340 rege9c = result[i][1]; 2341 regea4 = result[i][2]; 2342 regeac = result[i][3]; 2343 regeb4 = result[i][4]; 2344 regebc = result[i][5]; 2345 regec4 = result[i][6]; 2346 regecc = result[i][7]; 2347 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2348 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n", 2349 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, 2350 regecc); 2351 } 2352 if (final_candidate != 0xff) { 2353 rtlphy->reg_e94 = rege94 = result[final_candidate][0]; 2354 rtlphy->reg_e9c = rege9c = result[final_candidate][1]; 2355 regea4 = result[final_candidate][2]; 2356 regeac = result[final_candidate][3]; 2357 rtlphy->reg_eb4 = regeb4 = result[final_candidate][4]; 2358 rtlphy->reg_ebc = regebc = result[final_candidate][5]; 2359 regec4 = result[final_candidate][6]; 2360 regecc = result[final_candidate][7]; 2361 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2362 "IQK: final_candidate is %x\n", final_candidate); 2363 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2364 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n", 2365 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, 2366 regecc); 2367 patha_ok = pathb_ok = true; 2368 } else { 2369 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */ 2370 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; /* Y default value */ 2371 } 2372 if ((rege94 != 0) /*&&(regea4 != 0) */) 2373 _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result, 2374 final_candidate, (regea4 == 0)); 2375 if (IS_92D_SINGLEPHY(rtlhal->version)) { 2376 if ((regeb4 != 0) /*&&(regec4 != 0) */) 2377 _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result, 2378 final_candidate, (regec4 == 0)); 2379 } 2380 if (final_candidate != 0xFF) { 2381 indexforchannel = rtl92d_get_rightchnlplace_for_iqk( 2382 rtlphy->current_channel); 2383 2384 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) 2385 rtlphy->iqk_matrix[indexforchannel]. 2386 value[0][i] = result[final_candidate][i]; 2387 rtlphy->iqk_matrix[indexforchannel].iqk_done = 2388 true; 2389 2390 RT_TRACE(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD, 2391 "IQK OK indexforchannel %d\n", indexforchannel); 2392 } 2393 } 2394 2395 void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel) 2396 { 2397 struct rtl_priv *rtlpriv = rtl_priv(hw); 2398 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2399 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2400 u8 indexforchannel; 2401 2402 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel); 2403 /*------Do IQK for normal chip and test chip 5G band------- */ 2404 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel); 2405 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n", 2406 indexforchannel, 2407 rtlphy->iqk_matrix[indexforchannel].iqk_done); 2408 if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done && 2409 rtlphy->need_iqk) { 2410 /* Re Do IQK. */ 2411 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD, 2412 "Do IQK Matrix reg for channel:%d....\n", channel); 2413 rtl92d_phy_iq_calibrate(hw); 2414 } else { 2415 /* Just load the value. */ 2416 /* 2G band just load once. */ 2417 if (((!rtlhal->load_imrandiqk_setting_for2g) && 2418 indexforchannel == 0) || indexforchannel > 0) { 2419 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, 2420 "Just Read IQK Matrix reg for channel:%d....\n", 2421 channel); 2422 if ((rtlphy->iqk_matrix[indexforchannel]. 2423 value[0] != NULL) 2424 /*&&(regea4 != 0) */) 2425 _rtl92d_phy_patha_fill_iqk_matrix(hw, true, 2426 rtlphy->iqk_matrix[ 2427 indexforchannel].value, 0, 2428 (rtlphy->iqk_matrix[ 2429 indexforchannel].value[0][2] == 0)); 2430 if (IS_92D_SINGLEPHY(rtlhal->version)) { 2431 if ((rtlphy->iqk_matrix[ 2432 indexforchannel].value[0][4] != 0) 2433 /*&&(regec4 != 0) */) 2434 _rtl92d_phy_pathb_fill_iqk_matrix(hw, 2435 true, 2436 rtlphy->iqk_matrix[ 2437 indexforchannel].value, 0, 2438 (rtlphy->iqk_matrix[ 2439 indexforchannel].value[0][6] 2440 == 0)); 2441 } 2442 } 2443 } 2444 rtlphy->need_iqk = false; 2445 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 2446 } 2447 2448 static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2) 2449 { 2450 u32 ret; 2451 2452 if (val1 >= val2) 2453 ret = val1 - val2; 2454 else 2455 ret = val2 - val1; 2456 return ret; 2457 } 2458 2459 static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel) 2460 { 2461 2462 int i; 2463 2464 for (i = 0; i < sizeof(channel5g); i++) 2465 if (channel == channel5g[i]) 2466 return true; 2467 return false; 2468 } 2469 2470 static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw, 2471 u32 *targetchnl, u32 * curvecount_val, 2472 bool is5g, u32 *curveindex) 2473 { 2474 struct rtl_priv *rtlpriv = rtl_priv(hw); 2475 u32 smallest_abs_val = 0xffffffff, u4tmp; 2476 u8 i, j; 2477 u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G; 2478 2479 for (i = 0; i < chnl_num; i++) { 2480 if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1)) 2481 continue; 2482 curveindex[i] = 0; 2483 for (j = 0; j < (CV_CURVE_CNT * 2); j++) { 2484 u4tmp = _rtl92d_phy_get_abs(targetchnl[i], 2485 curvecount_val[j]); 2486 2487 if (u4tmp < smallest_abs_val) { 2488 curveindex[i] = j; 2489 smallest_abs_val = u4tmp; 2490 } 2491 } 2492 smallest_abs_val = 0xffffffff; 2493 RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n", 2494 i, curveindex[i]); 2495 } 2496 } 2497 2498 static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw, 2499 u8 channel) 2500 { 2501 struct rtl_priv *rtlpriv = rtl_priv(hw); 2502 u8 erfpath = rtlpriv->rtlhal.current_bandtype == 2503 BAND_ON_5G ? RF90_PATH_A : 2504 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ? 2505 RF90_PATH_B : RF90_PATH_A; 2506 u32 u4tmp = 0, u4regvalue = 0; 2507 bool bneed_powerdown_radio = false; 2508 2509 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath); 2510 RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n", 2511 rtlpriv->rtlhal.current_bandtype); 2512 RTPRINT(rtlpriv, FINIT, INIT_IQK, "channel = %d\n", channel); 2513 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */ 2514 u4tmp = curveindex_5g[channel-1]; 2515 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2516 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); 2517 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && 2518 rtlpriv->rtlhal.interfaceindex == 1) { 2519 bneed_powerdown_radio = 2520 rtl92d_phy_enable_anotherphy(hw, false); 2521 rtlpriv->rtlhal.during_mac1init_radioa = true; 2522 /* asume no this case */ 2523 if (bneed_powerdown_radio) 2524 _rtl92d_phy_enable_rf_env(hw, erfpath, 2525 &u4regvalue); 2526 } 2527 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); 2528 if (bneed_powerdown_radio) 2529 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); 2530 if (rtlpriv->rtlhal.during_mac1init_radioa) 2531 rtl92d_phy_powerdown_anotherphy(hw, false); 2532 } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) { 2533 u4tmp = curveindex_2g[channel-1]; 2534 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2535 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); 2536 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && 2537 rtlpriv->rtlhal.interfaceindex == 0) { 2538 bneed_powerdown_radio = 2539 rtl92d_phy_enable_anotherphy(hw, true); 2540 rtlpriv->rtlhal.during_mac0init_radiob = true; 2541 if (bneed_powerdown_radio) 2542 _rtl92d_phy_enable_rf_env(hw, erfpath, 2543 &u4regvalue); 2544 } 2545 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); 2546 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2547 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", 2548 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)); 2549 if (bneed_powerdown_radio) 2550 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); 2551 if (rtlpriv->rtlhal.during_mac0init_radiob) 2552 rtl92d_phy_powerdown_anotherphy(hw, true); 2553 } 2554 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 2555 } 2556 2557 static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t) 2558 { 2559 struct rtl_priv *rtlpriv = rtl_priv(hw); 2560 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2561 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2562 u8 tmpreg, index, rf_mode[2]; 2563 u8 path = is2t ? 2 : 1; 2564 u8 i; 2565 u32 u4tmp, offset; 2566 u32 curvecount_val[CV_CURVE_CNT * 2] = {0}; 2567 u16 timeout = 800, timecount = 0; 2568 2569 /* Check continuous TX and Packet TX */ 2570 tmpreg = rtl_read_byte(rtlpriv, 0xd03); 2571 /* if Deal with contisuous TX case, disable all continuous TX */ 2572 /* if Deal with Packet TX case, block all queues */ 2573 if ((tmpreg & 0x70) != 0) 2574 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); 2575 else 2576 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 2577 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); 2578 for (index = 0; index < path; index++) { 2579 /* 1. Read original RF mode */ 2580 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; 2581 rf_mode[index] = rtl_read_byte(rtlpriv, offset); 2582 /* 2. Set RF mode = standby mode */ 2583 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC, 2584 RFREG_OFFSET_MASK, 0x010000); 2585 if (rtlpci->init_ready) { 2586 /* switch CV-curve control by LC-calibration */ 2587 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, 2588 BIT(17), 0x0); 2589 /* 4. Set LC calibration begin */ 2590 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, 2591 0x08000, 0x01); 2592 } 2593 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6, 2594 RFREG_OFFSET_MASK); 2595 while ((!(u4tmp & BIT(11))) && timecount <= timeout) { 2596 mdelay(50); 2597 timecount += 50; 2598 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, 2599 RF_SYN_G6, RFREG_OFFSET_MASK); 2600 } 2601 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2602 "PHY_LCK finish delay for %d ms=2\n", timecount); 2603 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK); 2604 if (index == 0 && rtlhal->interfaceindex == 0) { 2605 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2606 "path-A / 5G LCK\n"); 2607 } else { 2608 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2609 "path-B / 2.4G LCK\n"); 2610 } 2611 memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2); 2612 /* Set LC calibration off */ 2613 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, 2614 0x08000, 0x0); 2615 RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n"); 2616 /* save Curve-counting number */ 2617 for (i = 0; i < CV_CURVE_CNT; i++) { 2618 u32 readval = 0, readval2 = 0; 2619 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F, 2620 0x7f, i); 2621 2622 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D, 2623 RFREG_OFFSET_MASK, 0x0); 2624 readval = rtl_get_rfreg(hw, (enum radio_path)index, 2625 0x4F, RFREG_OFFSET_MASK); 2626 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5; 2627 /* reg 0x4f [4:0] */ 2628 /* reg 0x50 [19:10] */ 2629 readval2 = rtl_get_rfreg(hw, (enum radio_path)index, 2630 0x50, 0xffc00); 2631 curvecount_val[2 * i] = (((readval & 0x1F) << 10) | 2632 readval2); 2633 } 2634 if (index == 0 && rtlhal->interfaceindex == 0) 2635 _rtl92d_phy_calc_curvindex(hw, targetchnl_5g, 2636 curvecount_val, 2637 true, curveindex_5g); 2638 else 2639 _rtl92d_phy_calc_curvindex(hw, targetchnl_2g, 2640 curvecount_val, 2641 false, curveindex_2g); 2642 /* switch CV-curve control mode */ 2643 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, 2644 BIT(17), 0x1); 2645 } 2646 2647 /* Restore original situation */ 2648 for (index = 0; index < path; index++) { 2649 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; 2650 rtl_write_byte(rtlpriv, offset, 0x50); 2651 rtl_write_byte(rtlpriv, offset, rf_mode[index]); 2652 } 2653 if ((tmpreg & 0x70) != 0) 2654 rtl_write_byte(rtlpriv, 0xd03, tmpreg); 2655 else /*Deal with Packet TX case */ 2656 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 2657 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); 2658 _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel); 2659 } 2660 2661 static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) 2662 { 2663 struct rtl_priv *rtlpriv = rtl_priv(hw); 2664 2665 RTPRINT(rtlpriv, FINIT, INIT_IQK, "cosa PHY_LCK ver=2\n"); 2666 _rtl92d_phy_lc_calibrate_sw(hw, is2t); 2667 } 2668 2669 void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw) 2670 { 2671 struct rtl_priv *rtlpriv = rtl_priv(hw); 2672 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2673 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2674 u32 timeout = 2000, timecount = 0; 2675 2676 while (rtlpriv->mac80211.act_scanning && timecount < timeout) { 2677 udelay(50); 2678 timecount += 50; 2679 } 2680 2681 rtlphy->lck_inprogress = true; 2682 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2683 "LCK:Start!!! currentband %x delay %d ms\n", 2684 rtlhal->current_bandtype, timecount); 2685 if (IS_92D_SINGLEPHY(rtlhal->version)) { 2686 _rtl92d_phy_lc_calibrate(hw, true); 2687 } else { 2688 /* For 1T1R */ 2689 _rtl92d_phy_lc_calibrate(hw, false); 2690 } 2691 rtlphy->lck_inprogress = false; 2692 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LCK:Finish!!!\n"); 2693 } 2694 2695 void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta) 2696 { 2697 return; 2698 } 2699 2700 static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, 2701 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid, 2702 u32 para1, u32 para2, u32 msdelay) 2703 { 2704 struct swchnlcmd *pcmd; 2705 2706 if (cmdtable == NULL) { 2707 RT_ASSERT(false, "cmdtable cannot be NULL\n"); 2708 return false; 2709 } 2710 if (cmdtableidx >= cmdtablesz) 2711 return false; 2712 2713 pcmd = cmdtable + cmdtableidx; 2714 pcmd->cmdid = cmdid; 2715 pcmd->para1 = para1; 2716 pcmd->para2 = para2; 2717 pcmd->msdelay = msdelay; 2718 return true; 2719 } 2720 2721 void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw) 2722 { 2723 struct rtl_priv *rtlpriv = rtl_priv(hw); 2724 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2725 u8 i; 2726 2727 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2728 "settings regs %d default regs %d\n", 2729 (int)(sizeof(rtlphy->iqk_matrix) / 2730 sizeof(struct iqk_matrix_regs)), 2731 IQK_MATRIX_REG_NUM); 2732 /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */ 2733 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) { 2734 rtlphy->iqk_matrix[i].value[0][0] = 0x100; 2735 rtlphy->iqk_matrix[i].value[0][2] = 0x100; 2736 rtlphy->iqk_matrix[i].value[0][4] = 0x100; 2737 rtlphy->iqk_matrix[i].value[0][6] = 0x100; 2738 rtlphy->iqk_matrix[i].value[0][1] = 0x0; 2739 rtlphy->iqk_matrix[i].value[0][3] = 0x0; 2740 rtlphy->iqk_matrix[i].value[0][5] = 0x0; 2741 rtlphy->iqk_matrix[i].value[0][7] = 0x0; 2742 rtlphy->iqk_matrix[i].iqk_done = false; 2743 } 2744 } 2745 2746 static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 2747 u8 channel, u8 *stage, u8 *step, 2748 u32 *delay) 2749 { 2750 struct rtl_priv *rtlpriv = rtl_priv(hw); 2751 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2752 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT]; 2753 u32 precommoncmdcnt; 2754 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT]; 2755 u32 postcommoncmdcnt; 2756 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT]; 2757 u32 rfdependcmdcnt; 2758 struct swchnlcmd *currentcmd = NULL; 2759 u8 rfpath; 2760 u8 num_total_rfpath = rtlphy->num_total_rfpath; 2761 2762 precommoncmdcnt = 0; 2763 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 2764 MAX_PRECMD_CNT, 2765 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); 2766 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 2767 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); 2768 postcommoncmdcnt = 0; 2769 _rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, 2770 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); 2771 rfdependcmdcnt = 0; 2772 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 2773 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, 2774 RF_CHNLBW, channel, 0); 2775 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 2776 MAX_RFDEPENDCMD_CNT, CMDID_END, 2777 0, 0, 0); 2778 2779 do { 2780 switch (*stage) { 2781 case 0: 2782 currentcmd = &precommoncmd[*step]; 2783 break; 2784 case 1: 2785 currentcmd = &rfdependcmd[*step]; 2786 break; 2787 case 2: 2788 currentcmd = &postcommoncmd[*step]; 2789 break; 2790 } 2791 if (currentcmd->cmdid == CMDID_END) { 2792 if ((*stage) == 2) { 2793 return true; 2794 } else { 2795 (*stage)++; 2796 (*step) = 0; 2797 continue; 2798 } 2799 } 2800 switch (currentcmd->cmdid) { 2801 case CMDID_SET_TXPOWEROWER_LEVEL: 2802 rtl92d_phy_set_txpower_level(hw, channel); 2803 break; 2804 case CMDID_WRITEPORT_ULONG: 2805 rtl_write_dword(rtlpriv, currentcmd->para1, 2806 currentcmd->para2); 2807 break; 2808 case CMDID_WRITEPORT_USHORT: 2809 rtl_write_word(rtlpriv, currentcmd->para1, 2810 (u16)currentcmd->para2); 2811 break; 2812 case CMDID_WRITEPORT_UCHAR: 2813 rtl_write_byte(rtlpriv, currentcmd->para1, 2814 (u8)currentcmd->para2); 2815 break; 2816 case CMDID_RF_WRITEREG: 2817 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { 2818 rtlphy->rfreg_chnlval[rfpath] = 2819 ((rtlphy->rfreg_chnlval[rfpath] & 2820 0xffffff00) | currentcmd->para2); 2821 if (rtlpriv->rtlhal.current_bandtype == 2822 BAND_ON_5G) { 2823 if (currentcmd->para2 > 99) 2824 rtlphy->rfreg_chnlval[rfpath] = 2825 rtlphy->rfreg_chnlval 2826 [rfpath] | (BIT(18)); 2827 else 2828 rtlphy->rfreg_chnlval[rfpath] = 2829 rtlphy->rfreg_chnlval 2830 [rfpath] & (~BIT(18)); 2831 rtlphy->rfreg_chnlval[rfpath] |= 2832 (BIT(16) | BIT(8)); 2833 } else { 2834 rtlphy->rfreg_chnlval[rfpath] &= 2835 ~(BIT(8) | BIT(16) | BIT(18)); 2836 } 2837 rtl_set_rfreg(hw, (enum radio_path)rfpath, 2838 currentcmd->para1, 2839 RFREG_OFFSET_MASK, 2840 rtlphy->rfreg_chnlval[rfpath]); 2841 _rtl92d_phy_reload_imr_setting(hw, channel, 2842 rfpath); 2843 } 2844 _rtl92d_phy_switch_rf_setting(hw, channel); 2845 /* do IQK when all parameters are ready */ 2846 rtl92d_phy_reload_iqk_setting(hw, channel); 2847 break; 2848 default: 2849 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2850 "switch case %#x not processed\n", 2851 currentcmd->cmdid); 2852 break; 2853 } 2854 break; 2855 } while (true); 2856 (*delay) = currentcmd->msdelay; 2857 (*step)++; 2858 return false; 2859 } 2860 2861 u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw) 2862 { 2863 struct rtl_priv *rtlpriv = rtl_priv(hw); 2864 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2865 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2866 u32 delay; 2867 u32 timeout = 1000, timecount = 0; 2868 u8 channel = rtlphy->current_channel; 2869 u32 ret_value; 2870 2871 if (rtlphy->sw_chnl_inprogress) 2872 return 0; 2873 if (rtlphy->set_bwmode_inprogress) 2874 return 0; 2875 2876 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { 2877 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 2878 "sw_chnl_inprogress false driver sleep or unload\n"); 2879 return 0; 2880 } 2881 while (rtlphy->lck_inprogress && timecount < timeout) { 2882 mdelay(50); 2883 timecount += 50; 2884 } 2885 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY && 2886 rtlhal->bandset == BAND_ON_BOTH) { 2887 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 2888 MASKDWORD); 2889 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0))) 2890 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G); 2891 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0))) 2892 rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G); 2893 } 2894 switch (rtlhal->current_bandtype) { 2895 case BAND_ON_5G: 2896 /* Get first channel error when change between 2897 * 5G and 2.4G band. */ 2898 if (channel <= 14) 2899 return 0; 2900 RT_ASSERT((channel > 14), "5G but channel<=14\n"); 2901 break; 2902 case BAND_ON_2_4G: 2903 /* Get first channel error when change between 2904 * 5G and 2.4G band. */ 2905 if (channel > 14) 2906 return 0; 2907 RT_ASSERT((channel <= 14), "2G but channel>14\n"); 2908 break; 2909 default: 2910 RT_ASSERT(false, "Invalid WirelessMode(%#x)!!\n", 2911 rtlpriv->mac80211.mode); 2912 break; 2913 } 2914 rtlphy->sw_chnl_inprogress = true; 2915 if (channel == 0) 2916 channel = 1; 2917 rtlphy->sw_chnl_stage = 0; 2918 rtlphy->sw_chnl_step = 0; 2919 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, 2920 "switch to channel%d\n", rtlphy->current_channel); 2921 2922 do { 2923 if (!rtlphy->sw_chnl_inprogress) 2924 break; 2925 if (!_rtl92d_phy_sw_chnl_step_by_step(hw, 2926 rtlphy->current_channel, 2927 &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) { 2928 if (delay > 0) 2929 mdelay(delay); 2930 else 2931 continue; 2932 } else { 2933 rtlphy->sw_chnl_inprogress = false; 2934 } 2935 break; 2936 } while (true); 2937 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 2938 rtlphy->sw_chnl_inprogress = false; 2939 return 1; 2940 } 2941 2942 static void rtl92d_phy_set_io(struct ieee80211_hw *hw) 2943 { 2944 struct rtl_priv *rtlpriv = rtl_priv(hw); 2945 struct dig_t *de_digtable = &rtlpriv->dm_digtable; 2946 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2947 2948 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2949 "--->Cmd(%#x), set_io_inprogress(%d)\n", 2950 rtlphy->current_io_type, rtlphy->set_io_inprogress); 2951 switch (rtlphy->current_io_type) { 2952 case IO_CMD_RESUME_DM_BY_SCAN: 2953 de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; 2954 rtl92d_dm_write_dig(hw); 2955 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel); 2956 break; 2957 case IO_CMD_PAUSE_DM_BY_SCAN: 2958 rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue; 2959 de_digtable->cur_igvalue = 0x37; 2960 rtl92d_dm_write_dig(hw); 2961 break; 2962 default: 2963 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2964 "switch case %#x not processed\n", 2965 rtlphy->current_io_type); 2966 break; 2967 } 2968 rtlphy->set_io_inprogress = false; 2969 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n", 2970 rtlphy->current_io_type); 2971 } 2972 2973 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) 2974 { 2975 struct rtl_priv *rtlpriv = rtl_priv(hw); 2976 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2977 bool postprocessing = false; 2978 2979 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2980 "-->IO Cmd(%#x), set_io_inprogress(%d)\n", 2981 iotype, rtlphy->set_io_inprogress); 2982 do { 2983 switch (iotype) { 2984 case IO_CMD_RESUME_DM_BY_SCAN: 2985 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2986 "[IO CMD] Resume DM after scan\n"); 2987 postprocessing = true; 2988 break; 2989 case IO_CMD_PAUSE_DM_BY_SCAN: 2990 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2991 "[IO CMD] Pause DM before scan\n"); 2992 postprocessing = true; 2993 break; 2994 default: 2995 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2996 "switch case %#x not processed\n", iotype); 2997 break; 2998 } 2999 } while (false); 3000 if (postprocessing && !rtlphy->set_io_inprogress) { 3001 rtlphy->set_io_inprogress = true; 3002 rtlphy->current_io_type = iotype; 3003 } else { 3004 return false; 3005 } 3006 rtl92d_phy_set_io(hw); 3007 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype); 3008 return true; 3009 } 3010 3011 static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw) 3012 { 3013 struct rtl_priv *rtlpriv = rtl_priv(hw); 3014 3015 /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */ 3016 /* b. SPS_CTRL 0x11[7:0] = 0x2b */ 3017 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) 3018 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 3019 /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */ 3020 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 3021 /* RF_ON_EXCEP(d~g): */ 3022 /* d. APSD_CTRL 0x600[7:0] = 0x00 */ 3023 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); 3024 /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */ 3025 /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/ 3026 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 3027 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 3028 /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */ 3029 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 3030 } 3031 3032 static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw) 3033 { 3034 struct rtl_priv *rtlpriv = rtl_priv(hw); 3035 u32 u4btmp; 3036 u8 delay = 5; 3037 3038 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ 3039 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 3040 /* b. RF path 0 offset 0x00 = 0x00 disable RF */ 3041 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 3042 /* c. APSD_CTRL 0x600[7:0] = 0x40 */ 3043 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 3044 /* d. APSD_CTRL 0x600[7:0] = 0x00 3045 * APSD_CTRL 0x600[7:0] = 0x00 3046 * RF path 0 offset 0x00 = 0x00 3047 * APSD_CTRL 0x600[7:0] = 0x40 3048 * */ 3049 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); 3050 while (u4btmp != 0 && delay > 0) { 3051 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); 3052 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 3053 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 3054 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); 3055 delay--; 3056 } 3057 if (delay == 0) { 3058 /* Jump out the LPS turn off sequence to RF_ON_EXCEP */ 3059 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); 3060 3061 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 3062 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 3063 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 3064 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 3065 "Fail !!! Switch RF timeout\n"); 3066 return; 3067 } 3068 /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */ 3069 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 3070 /* f. SPS_CTRL 0x11[7:0] = 0x22 */ 3071 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) 3072 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); 3073 /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */ 3074 } 3075 3076 bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw, 3077 enum rf_pwrstate rfpwr_state) 3078 { 3079 3080 bool bresult = true; 3081 struct rtl_priv *rtlpriv = rtl_priv(hw); 3082 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 3083 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3084 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 3085 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 3086 u8 i, queue_id; 3087 struct rtl8192_tx_ring *ring = NULL; 3088 3089 if (rfpwr_state == ppsc->rfpwr_state) 3090 return false; 3091 switch (rfpwr_state) { 3092 case ERFON: 3093 if ((ppsc->rfpwr_state == ERFOFF) && 3094 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 3095 bool rtstatus; 3096 u32 InitializeCount = 0; 3097 do { 3098 InitializeCount++; 3099 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 3100 "IPS Set eRf nic enable\n"); 3101 rtstatus = rtl_ps_enable_nic(hw); 3102 } while (!rtstatus && (InitializeCount < 10)); 3103 3104 RT_CLEAR_PS_LEVEL(ppsc, 3105 RT_RF_OFF_LEVL_HALT_NIC); 3106 } else { 3107 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 3108 "awake, sleeped:%d ms state_inap:%x\n", 3109 jiffies_to_msecs(jiffies - 3110 ppsc->last_sleep_jiffies), 3111 rtlpriv->psc.state_inap); 3112 ppsc->last_awake_jiffies = jiffies; 3113 _rtl92d_phy_set_rfon(hw); 3114 } 3115 3116 if (mac->link_state == MAC80211_LINKED) 3117 rtlpriv->cfg->ops->led_control(hw, 3118 LED_CTL_LINK); 3119 else 3120 rtlpriv->cfg->ops->led_control(hw, 3121 LED_CTL_NO_LINK); 3122 break; 3123 case ERFOFF: 3124 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 3125 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 3126 "IPS Set eRf nic disable\n"); 3127 rtl_ps_disable_nic(hw); 3128 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 3129 } else { 3130 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 3131 rtlpriv->cfg->ops->led_control(hw, 3132 LED_CTL_NO_LINK); 3133 else 3134 rtlpriv->cfg->ops->led_control(hw, 3135 LED_CTL_POWER_OFF); 3136 } 3137 break; 3138 case ERFSLEEP: 3139 if (ppsc->rfpwr_state == ERFOFF) 3140 return false; 3141 3142 for (queue_id = 0, i = 0; 3143 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 3144 ring = &pcipriv->dev.tx_ring[queue_id]; 3145 if (skb_queue_len(&ring->queue) == 0 || 3146 queue_id == BEACON_QUEUE) { 3147 queue_id++; 3148 continue; 3149 } else if (rtlpci->pdev->current_state != PCI_D0) { 3150 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 3151 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", 3152 i + 1, queue_id); 3153 break; 3154 } else { 3155 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 3156 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", 3157 i + 1, queue_id, 3158 skb_queue_len(&ring->queue)); 3159 udelay(10); 3160 i++; 3161 } 3162 3163 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 3164 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 3165 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n", 3166 MAX_DOZE_WAITING_TIMES_9x, queue_id, 3167 skb_queue_len(&ring->queue)); 3168 break; 3169 } 3170 } 3171 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 3172 "Set rfsleep awaked:%d ms\n", 3173 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies)); 3174 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 3175 "sleep awaked:%d ms state_inap:%x\n", 3176 jiffies_to_msecs(jiffies - 3177 ppsc->last_awake_jiffies), 3178 rtlpriv->psc.state_inap); 3179 ppsc->last_sleep_jiffies = jiffies; 3180 _rtl92d_phy_set_rfsleep(hw); 3181 break; 3182 default: 3183 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 3184 "switch case %#x not processed\n", rfpwr_state); 3185 bresult = false; 3186 break; 3187 } 3188 if (bresult) 3189 ppsc->rfpwr_state = rfpwr_state; 3190 return bresult; 3191 } 3192 3193 void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw) 3194 { 3195 struct rtl_priv *rtlpriv = rtl_priv(hw); 3196 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3197 u8 offset = REG_MAC_PHY_CTRL_NORMAL; 3198 3199 switch (rtlhal->macphymode) { 3200 case DUALMAC_DUALPHY: 3201 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3202 "MacPhyMode: DUALMAC_DUALPHY\n"); 3203 rtl_write_byte(rtlpriv, offset, 0xF3); 3204 break; 3205 case SINGLEMAC_SINGLEPHY: 3206 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3207 "MacPhyMode: SINGLEMAC_SINGLEPHY\n"); 3208 rtl_write_byte(rtlpriv, offset, 0xF4); 3209 break; 3210 case DUALMAC_SINGLEPHY: 3211 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3212 "MacPhyMode: DUALMAC_SINGLEPHY\n"); 3213 rtl_write_byte(rtlpriv, offset, 0xF1); 3214 break; 3215 } 3216 } 3217 3218 void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw) 3219 { 3220 struct rtl_priv *rtlpriv = rtl_priv(hw); 3221 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3222 struct rtl_phy *rtlphy = &(rtlpriv->phy); 3223 3224 switch (rtlhal->macphymode) { 3225 case DUALMAC_SINGLEPHY: 3226 rtlphy->rf_type = RF_2T2R; 3227 rtlhal->version |= RF_TYPE_2T2R; 3228 rtlhal->bandset = BAND_ON_BOTH; 3229 rtlhal->current_bandtype = BAND_ON_2_4G; 3230 break; 3231 3232 case SINGLEMAC_SINGLEPHY: 3233 rtlphy->rf_type = RF_2T2R; 3234 rtlhal->version |= RF_TYPE_2T2R; 3235 rtlhal->bandset = BAND_ON_BOTH; 3236 rtlhal->current_bandtype = BAND_ON_2_4G; 3237 break; 3238 3239 case DUALMAC_DUALPHY: 3240 rtlphy->rf_type = RF_1T1R; 3241 rtlhal->version &= RF_TYPE_1T1R; 3242 /* Now we let MAC0 run on 5G band. */ 3243 if (rtlhal->interfaceindex == 0) { 3244 rtlhal->bandset = BAND_ON_5G; 3245 rtlhal->current_bandtype = BAND_ON_5G; 3246 } else { 3247 rtlhal->bandset = BAND_ON_2_4G; 3248 rtlhal->current_bandtype = BAND_ON_2_4G; 3249 } 3250 break; 3251 default: 3252 break; 3253 } 3254 } 3255 3256 u8 rtl92d_get_chnlgroup_fromarray(u8 chnl) 3257 { 3258 u8 group; 3259 u8 channel_info[59] = { 3260 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 3261 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 3262 58, 60, 62, 64, 100, 102, 104, 106, 108, 3263 110, 112, 114, 116, 118, 120, 122, 124, 3264 126, 128, 130, 132, 134, 136, 138, 140, 3265 149, 151, 153, 155, 157, 159, 161, 163, 3266 165 3267 }; 3268 3269 if (channel_info[chnl] <= 3) 3270 group = 0; 3271 else if (channel_info[chnl] <= 9) 3272 group = 1; 3273 else if (channel_info[chnl] <= 14) 3274 group = 2; 3275 else if (channel_info[chnl] <= 44) 3276 group = 3; 3277 else if (channel_info[chnl] <= 54) 3278 group = 4; 3279 else if (channel_info[chnl] <= 64) 3280 group = 5; 3281 else if (channel_info[chnl] <= 112) 3282 group = 6; 3283 else if (channel_info[chnl] <= 126) 3284 group = 7; 3285 else if (channel_info[chnl] <= 140) 3286 group = 8; 3287 else if (channel_info[chnl] <= 153) 3288 group = 9; 3289 else if (channel_info[chnl] <= 159) 3290 group = 10; 3291 else 3292 group = 11; 3293 return group; 3294 } 3295 3296 void rtl92d_phy_set_poweron(struct ieee80211_hw *hw) 3297 { 3298 struct rtl_priv *rtlpriv = rtl_priv(hw); 3299 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3300 unsigned long flags; 3301 u8 value8; 3302 u16 i; 3303 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1); 3304 3305 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ 3306 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 3307 value8 = rtl_read_byte(rtlpriv, mac_reg); 3308 value8 |= BIT(1); 3309 rtl_write_byte(rtlpriv, mac_reg, value8); 3310 } else { 3311 value8 = rtl_read_byte(rtlpriv, mac_reg); 3312 value8 &= (~BIT(1)); 3313 rtl_write_byte(rtlpriv, mac_reg, value8); 3314 } 3315 3316 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { 3317 value8 = rtl_read_byte(rtlpriv, REG_MAC0); 3318 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); 3319 } else { 3320 spin_lock_irqsave(&globalmutex_power, flags); 3321 if (rtlhal->interfaceindex == 0) { 3322 value8 = rtl_read_byte(rtlpriv, REG_MAC0); 3323 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); 3324 } else { 3325 value8 = rtl_read_byte(rtlpriv, REG_MAC1); 3326 rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON); 3327 } 3328 value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); 3329 spin_unlock_irqrestore(&globalmutex_power, flags); 3330 for (i = 0; i < 200; i++) { 3331 if ((value8 & BIT(7)) == 0) { 3332 break; 3333 } else { 3334 udelay(500); 3335 spin_lock_irqsave(&globalmutex_power, flags); 3336 value8 = rtl_read_byte(rtlpriv, 3337 REG_POWER_OFF_IN_PROCESS); 3338 spin_unlock_irqrestore(&globalmutex_power, 3339 flags); 3340 } 3341 } 3342 if (i == 200) 3343 RT_ASSERT(false, "Another mac power off over time\n"); 3344 } 3345 } 3346 3347 void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw) 3348 { 3349 struct rtl_priv *rtlpriv = rtl_priv(hw); 3350 3351 switch (rtlpriv->rtlhal.macphymode) { 3352 case DUALMAC_DUALPHY: 3353 rtl_write_byte(rtlpriv, REG_DMC, 0x0); 3354 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); 3355 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); 3356 break; 3357 case DUALMAC_SINGLEPHY: 3358 rtl_write_byte(rtlpriv, REG_DMC, 0xf8); 3359 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); 3360 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); 3361 break; 3362 case SINGLEMAC_SINGLEPHY: 3363 rtl_write_byte(rtlpriv, REG_DMC, 0x0); 3364 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10); 3365 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); 3366 break; 3367 default: 3368 break; 3369 } 3370 } 3371 3372 void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw) 3373 { 3374 struct rtl_priv *rtlpriv = rtl_priv(hw); 3375 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3376 struct rtl_phy *rtlphy = &(rtlpriv->phy); 3377 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3378 u8 rfpath, i; 3379 3380 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n"); 3381 /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */ 3382 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 3383 /* r_select_5G for path_A/B,0x878 */ 3384 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); 3385 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); 3386 if (rtlhal->macphymode != DUALMAC_DUALPHY) { 3387 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); 3388 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); 3389 } 3390 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */ 3391 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); 3392 /* fc_area 0xd2c */ 3393 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); 3394 /* 5G LAN ON */ 3395 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); 3396 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */ 3397 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, 3398 0x40000100); 3399 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, 3400 0x40000100); 3401 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 3402 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 3403 BIT(10) | BIT(6) | BIT(5), 3404 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | 3405 (rtlefuse->eeprom_c9 & BIT(1)) | 3406 ((rtlefuse->eeprom_cc & BIT(1)) << 4)); 3407 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 3408 BIT(10) | BIT(6) | BIT(5), 3409 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | 3410 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | 3411 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); 3412 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); 3413 } else { 3414 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 3415 BIT(26) | BIT(22) | BIT(21) | BIT(10) | 3416 BIT(6) | BIT(5), 3417 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | 3418 (rtlefuse->eeprom_c9 & BIT(1)) | 3419 ((rtlefuse->eeprom_cc & BIT(1)) << 4) | 3420 ((rtlefuse->eeprom_c9 & BIT(7)) << 9) | 3421 ((rtlefuse->eeprom_c9 & BIT(5)) << 12) | 3422 ((rtlefuse->eeprom_cc & BIT(3)) << 18)); 3423 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 3424 BIT(10) | BIT(6) | BIT(5), 3425 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | 3426 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | 3427 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); 3428 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 3429 BIT(10) | BIT(6) | BIT(5), 3430 ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) | 3431 ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) | 3432 ((rtlefuse->eeprom_cc & BIT(2)) << 3)); 3433 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 3434 BIT(31) | BIT(15), 0); 3435 } 3436 /* 1.5V_LDO */ 3437 } else { 3438 /* r_select_5G for path_A/B */ 3439 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); 3440 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); 3441 if (rtlhal->macphymode != DUALMAC_DUALPHY) { 3442 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); 3443 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); 3444 } 3445 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */ 3446 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); 3447 /* fc_area */ 3448 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); 3449 /* 5G LAN ON */ 3450 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); 3451 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */ 3452 if (rtlefuse->internal_pa_5g[0]) 3453 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, 3454 0x2d4000b5); 3455 else 3456 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, 3457 0x20000080); 3458 if (rtlefuse->internal_pa_5g[1]) 3459 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, 3460 0x2d4000b5); 3461 else 3462 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, 3463 0x20000080); 3464 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 3465 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 3466 BIT(10) | BIT(6) | BIT(5), 3467 (rtlefuse->eeprom_cc & BIT(5))); 3468 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 3469 ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); 3470 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 3471 (rtlefuse->eeprom_cc & BIT(4)) >> 4); 3472 } else { 3473 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 3474 BIT(26) | BIT(22) | BIT(21) | BIT(10) | 3475 BIT(6) | BIT(5), 3476 (rtlefuse->eeprom_cc & BIT(5)) | 3477 ((rtlefuse->eeprom_cc & BIT(7)) << 14)); 3478 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 3479 ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); 3480 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 3481 ((rtlefuse->eeprom_cc & BIT(6)) >> 6)); 3482 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 3483 BIT(31) | BIT(15), 3484 ((rtlefuse->eeprom_cc & BIT(4)) >> 4) | 3485 ((rtlefuse->eeprom_cc & BIT(6)) << 10)); 3486 } 3487 } 3488 /* update IQK related settings */ 3489 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); 3490 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); 3491 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00); 3492 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) | 3493 BIT(26) | BIT(24), 0x00); 3494 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 0x00); 3495 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00); 3496 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); 3497 3498 /* Update RF */ 3499 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 3500 rfpath++) { 3501 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 3502 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ 3503 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) | 3504 BIT(18), 0); 3505 /* RF0x0b[16:14] =3b'111 */ 3506 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, 3507 0x1c000, 0x07); 3508 } else { 3509 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ 3510 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | 3511 BIT(16) | BIT(18), 3512 (BIT(16) | BIT(8)) >> 8); 3513 } 3514 } 3515 /* Update for all band. */ 3516 /* DMDP */ 3517 if (rtlphy->rf_type == RF_1T1R) { 3518 /* Use antenna 0,0xc04,0xd04 */ 3519 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); 3520 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); 3521 3522 /* enable ad/da clock1 for dual-phy reg0x888 */ 3523 if (rtlhal->interfaceindex == 0) { 3524 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | 3525 BIT(13), 0x3); 3526 } else { 3527 rtl92d_phy_enable_anotherphy(hw, false); 3528 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3529 "MAC1 use DBI to update 0x888\n"); 3530 /* 0x888 */ 3531 rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN, 3532 rtl92de_read_dword_dbi(hw, 3533 RFPGA0_ADDALLOCKEN, 3534 BIT(3)) | BIT(12) | BIT(13), 3535 BIT(3)); 3536 rtl92d_phy_powerdown_anotherphy(hw, false); 3537 } 3538 } else { 3539 /* Single PHY */ 3540 /* Use antenna 0 & 1,0xc04,0xd04 */ 3541 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); 3542 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); 3543 /* disable ad/da clock1,0x888 */ 3544 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); 3545 } 3546 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 3547 rfpath++) { 3548 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath, 3549 RF_CHNLBW, RFREG_OFFSET_MASK); 3550 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C, 3551 RFREG_OFFSET_MASK); 3552 } 3553 for (i = 0; i < 2; i++) 3554 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n", 3555 rtlphy->rfreg_chnlval[i]); 3556 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n"); 3557 3558 } 3559 3560 bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw) 3561 { 3562 struct rtl_priv *rtlpriv = rtl_priv(hw); 3563 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3564 u8 u1btmp; 3565 unsigned long flags; 3566 3567 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { 3568 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); 3569 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON)); 3570 return true; 3571 } 3572 spin_lock_irqsave(&globalmutex_power, flags); 3573 if (rtlhal->interfaceindex == 0) { 3574 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); 3575 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON)); 3576 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1); 3577 u1btmp &= MAC1_ON; 3578 } else { 3579 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1); 3580 rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON)); 3581 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); 3582 u1btmp &= MAC0_ON; 3583 } 3584 if (u1btmp) { 3585 spin_unlock_irqrestore(&globalmutex_power, flags); 3586 return false; 3587 } 3588 u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); 3589 u1btmp |= BIT(7); 3590 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp); 3591 spin_unlock_irqrestore(&globalmutex_power, flags); 3592 return true; 3593 } 3594