1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../pci.h"
6 #include "../ps.h"
7 #include "../core.h"
8 #include "reg.h"
9 #include "def.h"
10 #include "phy.h"
11 #include "rf.h"
12 #include "dm.h"
13 #include "table.h"
14 #include "sw.h"
15 #include "hw.h"
16 
17 #define MAX_RF_IMR_INDEX			12
18 #define MAX_RF_IMR_INDEX_NORMAL			13
19 #define RF_REG_NUM_FOR_C_CUT_5G			6
20 #define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA	7
21 #define RF_REG_NUM_FOR_C_CUT_2G			5
22 #define RF_CHNL_NUM_5G				19
23 #define RF_CHNL_NUM_5G_40M			17
24 #define TARGET_CHNL_NUM_5G			221
25 #define TARGET_CHNL_NUM_2G			14
26 #define CV_CURVE_CNT				64
27 
28 static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = {
29 	0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
30 };
31 
32 static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = {
33 	RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6
34 };
35 
36 static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
37 	RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8
38 };
39 
40 static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
41 	0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
42 };
43 
44 static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
45 	BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1),
46 	BIT(10) | BIT(9),
47 	BIT(18) | BIT(17) | BIT(16) | BIT(1),
48 	BIT(2) | BIT(1),
49 	BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11)
50 };
51 
52 static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = {
53 	36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108,
54 	112, 116, 120, 124, 128, 132, 136, 140
55 };
56 
57 static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = {
58 	38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114,
59 	118, 122, 126, 130, 134, 138
60 };
61 static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = {
62 	{0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
63 	{0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
64 	{0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
65 	{0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
66 	{0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
67 };
68 
69 static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = {
70 	{0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
71 	{0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
72 	{0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
73 };
74 
75 static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
76 
77 static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
78 	{0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
79 	{0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
80 	{0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
81 };
82 
83 /* [mode][patha+b][reg] */
84 static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = {
85 	{
86 		/* channel 1-14. */
87 		{
88 			0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
89 			0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
90 		},
91 		/* path 36-64 */
92 		{
93 			0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
94 			0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
95 			0x32c9a
96 		},
97 		/* 100 -165 */
98 		{
99 			0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
100 			0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
101 		}
102 	}
103 };
104 
105 static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
106 
107 static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
108 
109 static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = {
110 	25141, 25116, 25091, 25066, 25041,
111 	25016, 24991, 24966, 24941, 24917,
112 	24892, 24867, 24843, 24818, 24794,
113 	24770, 24765, 24721, 24697, 24672,
114 	24648, 24624, 24600, 24576, 24552,
115 	24528, 24504, 24480, 24457, 24433,
116 	24409, 24385, 24362, 24338, 24315,
117 	24291, 24268, 24245, 24221, 24198,
118 	24175, 24151, 24128, 24105, 24082,
119 	24059, 24036, 24013, 23990, 23967,
120 	23945, 23922, 23899, 23876, 23854,
121 	23831, 23809, 23786, 23764, 23741,
122 	23719, 23697, 23674, 23652, 23630,
123 	23608, 23586, 23564, 23541, 23519,
124 	23498, 23476, 23454, 23432, 23410,
125 	23388, 23367, 23345, 23323, 23302,
126 	23280, 23259, 23237, 23216, 23194,
127 	23173, 23152, 23130, 23109, 23088,
128 	23067, 23046, 23025, 23003, 22982,
129 	22962, 22941, 22920, 22899, 22878,
130 	22857, 22837, 22816, 22795, 22775,
131 	22754, 22733, 22713, 22692, 22672,
132 	22652, 22631, 22611, 22591, 22570,
133 	22550, 22530, 22510, 22490, 22469,
134 	22449, 22429, 22409, 22390, 22370,
135 	22350, 22336, 22310, 22290, 22271,
136 	22251, 22231, 22212, 22192, 22173,
137 	22153, 22134, 22114, 22095, 22075,
138 	22056, 22037, 22017, 21998, 21979,
139 	21960, 21941, 21921, 21902, 21883,
140 	21864, 21845, 21826, 21807, 21789,
141 	21770, 21751, 21732, 21713, 21695,
142 	21676, 21657, 21639, 21620, 21602,
143 	21583, 21565, 21546, 21528, 21509,
144 	21491, 21473, 21454, 21436, 21418,
145 	21400, 21381, 21363, 21345, 21327,
146 	21309, 21291, 21273, 21255, 21237,
147 	21219, 21201, 21183, 21166, 21148,
148 	21130, 21112, 21095, 21077, 21059,
149 	21042, 21024, 21007, 20989, 20972,
150 	25679, 25653, 25627, 25601, 25575,
151 	25549, 25523, 25497, 25471, 25446,
152 	25420, 25394, 25369, 25343, 25318,
153 	25292, 25267, 25242, 25216, 25191,
154 	25166
155 };
156 
157 /* channel 1~14 */
158 static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = {
159 	26084, 26030, 25976, 25923, 25869, 25816, 25764,
160 	25711, 25658, 25606, 25554, 25502, 25451, 25328
161 };
162 
163 static const u8 channel_all[59] = {
164 	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
165 	36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
166 	60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
167 	114, 116, 118, 120, 122, 124, 126, 128,	130,
168 	132, 134, 136, 138, 140, 149, 151, 153, 155,
169 	157, 159, 161, 163, 165
170 };
171 
172 static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask)
173 {
174 	u32 i = ffs(bitmask);
175 
176 	return i ? i - 1 : 32;
177 }
178 
179 u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
180 {
181 	struct rtl_priv *rtlpriv = rtl_priv(hw);
182 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
183 	u32 returnvalue, originalvalue, bitshift;
184 
185 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
186 		regaddr, bitmask);
187 	if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) {
188 		u8 dbi_direct = 0;
189 
190 		/* mac1 use phy0 read radio_b. */
191 		/* mac0 use phy1 read radio_b. */
192 		if (rtlhal->during_mac1init_radioa)
193 			dbi_direct = BIT(3);
194 		else if (rtlhal->during_mac0init_radiob)
195 			dbi_direct = BIT(3) | BIT(2);
196 		originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr,
197 			dbi_direct);
198 	} else {
199 		originalvalue = rtl_read_dword(rtlpriv, regaddr);
200 	}
201 	bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
202 	returnvalue = (originalvalue & bitmask) >> bitshift;
203 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
204 		"BBR MASK=0x%x Addr[0x%x]=0x%x\n",
205 		bitmask, regaddr, originalvalue);
206 	return returnvalue;
207 }
208 
209 void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
210 			   u32 regaddr, u32 bitmask, u32 data)
211 {
212 	struct rtl_priv *rtlpriv = rtl_priv(hw);
213 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
214 	u8 dbi_direct = 0;
215 	u32 originalvalue, bitshift;
216 
217 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
218 		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
219 		regaddr, bitmask, data);
220 	if (rtlhal->during_mac1init_radioa)
221 		dbi_direct = BIT(3);
222 	else if (rtlhal->during_mac0init_radiob)
223 		/* mac0 use phy1 write radio_b. */
224 		dbi_direct = BIT(3) | BIT(2);
225 	if (bitmask != MASKDWORD) {
226 		if (rtlhal->during_mac1init_radioa ||
227 		    rtlhal->during_mac0init_radiob)
228 			originalvalue = rtl92de_read_dword_dbi(hw,
229 					(u16) regaddr,
230 					dbi_direct);
231 		else
232 			originalvalue = rtl_read_dword(rtlpriv, regaddr);
233 		bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
234 		data = ((originalvalue & (~bitmask)) | (data << bitshift));
235 	}
236 	if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob)
237 		rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct);
238 	else
239 		rtl_write_dword(rtlpriv, regaddr, data);
240 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
241 		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
242 		regaddr, bitmask, data);
243 }
244 
245 static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
246 				      enum radio_path rfpath, u32 offset)
247 {
248 
249 	struct rtl_priv *rtlpriv = rtl_priv(hw);
250 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
251 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
252 	u32 newoffset;
253 	u32 tmplong, tmplong2;
254 	u8 rfpi_enable = 0;
255 	u32 retvalue;
256 
257 	newoffset = offset;
258 	tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
259 	if (rfpath == RF90_PATH_A)
260 		tmplong2 = tmplong;
261 	else
262 		tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
263 	tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
264 		(newoffset << 23) | BLSSIREADEDGE;
265 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
266 		tmplong & (~BLSSIREADEDGE));
267 	udelay(10);
268 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
269 	udelay(50);
270 	udelay(50);
271 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
272 		tmplong | BLSSIREADEDGE);
273 	udelay(10);
274 	if (rfpath == RF90_PATH_A)
275 		rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
276 			      BIT(8));
277 	else if (rfpath == RF90_PATH_B)
278 		rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
279 			      BIT(8));
280 	if (rfpi_enable)
281 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
282 			BLSSIREADBACKDATA);
283 	else
284 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
285 			BLSSIREADBACKDATA);
286 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n",
287 		rfpath, pphyreg->rf_rb, retvalue);
288 	return retvalue;
289 }
290 
291 static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
292 					enum radio_path rfpath,
293 					u32 offset, u32 data)
294 {
295 	u32 data_and_addr;
296 	u32 newoffset;
297 	struct rtl_priv *rtlpriv = rtl_priv(hw);
298 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
299 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
300 
301 	newoffset = offset;
302 	/* T65 RF */
303 	data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
304 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
305 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
306 		rfpath, pphyreg->rf3wire_offset, data_and_addr);
307 }
308 
309 u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
310 			    enum radio_path rfpath, u32 regaddr, u32 bitmask)
311 {
312 	struct rtl_priv *rtlpriv = rtl_priv(hw);
313 	u32 original_value, readback_value, bitshift;
314 
315 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
316 		"regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
317 		regaddr, rfpath, bitmask);
318 	spin_lock(&rtlpriv->locks.rf_lock);
319 	original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);
320 	bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
321 	readback_value = (original_value & bitmask) >> bitshift;
322 	spin_unlock(&rtlpriv->locks.rf_lock);
323 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
324 		"regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
325 		regaddr, rfpath, bitmask, original_value);
326 	return readback_value;
327 }
328 
329 void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
330 	u32 regaddr, u32 bitmask, u32 data)
331 {
332 	struct rtl_priv *rtlpriv = rtl_priv(hw);
333 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
334 	u32 original_value, bitshift;
335 
336 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
337 		"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
338 		regaddr, bitmask, data, rfpath);
339 	if (bitmask == 0)
340 		return;
341 	spin_lock(&rtlpriv->locks.rf_lock);
342 	if (rtlphy->rf_mode != RF_OP_BY_FW) {
343 		if (bitmask != RFREG_OFFSET_MASK) {
344 			original_value = _rtl92d_phy_rf_serial_read(hw,
345 				rfpath, regaddr);
346 			bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
347 			data = ((original_value & (~bitmask)) |
348 				(data << bitshift));
349 		}
350 		_rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);
351 	}
352 	spin_unlock(&rtlpriv->locks.rf_lock);
353 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
354 		"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
355 		regaddr, bitmask, data, rfpath);
356 }
357 
358 bool rtl92d_phy_mac_config(struct ieee80211_hw *hw)
359 {
360 	struct rtl_priv *rtlpriv = rtl_priv(hw);
361 	u32 i;
362 	u32 arraylength;
363 	u32 *ptrarray;
364 
365 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
366 	arraylength = MAC_2T_ARRAYLENGTH;
367 	ptrarray = rtl8192de_mac_2tarray;
368 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n");
369 	for (i = 0; i < arraylength; i = i + 2)
370 		rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
371 	if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
372 		/* improve 2-stream TX EVM */
373 		/* rtl_write_byte(rtlpriv, 0x14,0x71); */
374 		/* AMPDU aggregation number 9 */
375 		/* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */
376 		rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B);
377 	} else {
378 		/* 92D need to test to decide the num. */
379 		rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07);
380 	}
381 	return true;
382 }
383 
384 static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
385 {
386 	struct rtl_priv *rtlpriv = rtl_priv(hw);
387 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
388 
389 	/* RF Interface Sowrtware Control */
390 	/* 16 LSBs if read 32-bit from 0x870 */
391 	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
392 	/* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
393 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
394 	/* 16 LSBs if read 32-bit from 0x874 */
395 	rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
396 	/* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
397 
398 	rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
399 	/* RF Interface Readback Value */
400 	/* 16 LSBs if read 32-bit from 0x8E0 */
401 	rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
402 	/* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
403 	rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
404 	/* 16 LSBs if read 32-bit from 0x8E4 */
405 	rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
406 	/* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
407 	rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
408 
409 	/* RF Interface Output (and Enable) */
410 	/* 16 LSBs if read 32-bit from 0x860 */
411 	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
412 	/* 16 LSBs if read 32-bit from 0x864 */
413 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
414 
415 	/* RF Interface (Output and)  Enable */
416 	/* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
417 	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
418 	/* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
419 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
420 
421 	/* Addr of LSSI. Wirte RF register by driver */
422 	/* LSSI Parameter */
423 	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
424 				 RFPGA0_XA_LSSIPARAMETER;
425 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
426 				 RFPGA0_XB_LSSIPARAMETER;
427 
428 	/* RF parameter */
429 	/* BB Band Select */
430 	rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
431 	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
432 	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
433 	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
434 
435 	/* Tx AGC Gain Stage (same for all path. Should we remove this?) */
436 	/* Tx gain stage */
437 	rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
438 	/* Tx gain stage */
439 	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
440 	/* Tx gain stage */
441 	rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
442 	/* Tx gain stage */
443 	rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
444 
445 	/* Tranceiver A~D HSSI Parameter-1 */
446 	/* wire control parameter1 */
447 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
448 	/* wire control parameter1 */
449 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
450 
451 	/* Tranceiver A~D HSSI Parameter-2 */
452 	/* wire control parameter2 */
453 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
454 	/* wire control parameter2 */
455 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
456 
457 	/* RF switch Control */
458 	/* TR/Ant switch control */
459 	rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
460 	rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
461 	rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
462 	rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
463 
464 	/* AGC control 1 */
465 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
466 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
467 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
468 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
469 
470 	/* AGC control 2  */
471 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
472 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
473 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
474 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
475 
476 	/* RX AFE control 1 */
477 	rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
478 	rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
479 	rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
480 	rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
481 
482 	/*RX AFE control 1 */
483 	rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
484 	rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
485 	rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
486 	rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
487 
488 	/* Tx AFE control 1 */
489 	rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
490 	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
491 	rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
492 	rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
493 
494 	/* Tx AFE control 2 */
495 	rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
496 	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
497 	rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
498 	rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
499 
500 	/* Tranceiver LSSI Readback SI mode */
501 	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
502 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
503 	rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
504 	rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
505 
506 	/* Tranceiver LSSI Readback PI mode */
507 	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
508 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
509 }
510 
511 static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
512 	u8 configtype)
513 {
514 	int i;
515 	u32 *phy_regarray_table;
516 	u32 *agctab_array_table = NULL;
517 	u32 *agctab_5garray_table;
518 	u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen;
519 	struct rtl_priv *rtlpriv = rtl_priv(hw);
520 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
521 
522 	/* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */
523 	if (rtlhal->interfaceindex == 0) {
524 		agctab_arraylen = AGCTAB_ARRAYLENGTH;
525 		agctab_array_table = rtl8192de_agctab_array;
526 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
527 			" ===> phy:MAC0, Rtl819XAGCTAB_Array\n");
528 	} else {
529 		if (rtlhal->current_bandtype == BAND_ON_2_4G) {
530 			agctab_arraylen = AGCTAB_2G_ARRAYLENGTH;
531 			agctab_array_table = rtl8192de_agctab_2garray;
532 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
533 				" ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n");
534 		} else {
535 			agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH;
536 			agctab_5garray_table = rtl8192de_agctab_5garray;
537 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
538 				" ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n");
539 
540 		}
541 	}
542 	phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH;
543 	phy_regarray_table = rtl8192de_phy_reg_2tarray;
544 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
545 		" ===> phy:Rtl819XPHY_REG_Array_PG\n");
546 	if (configtype == BASEBAND_CONFIG_PHY_REG) {
547 		for (i = 0; i < phy_reg_arraylen; i = i + 2) {
548 			rtl_addr_delay(phy_regarray_table[i]);
549 			rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
550 				      phy_regarray_table[i + 1]);
551 			udelay(1);
552 			rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
553 				"The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
554 				phy_regarray_table[i],
555 				phy_regarray_table[i + 1]);
556 		}
557 	} else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
558 		if (rtlhal->interfaceindex == 0) {
559 			for (i = 0; i < agctab_arraylen; i = i + 2) {
560 				rtl_set_bbreg(hw, agctab_array_table[i],
561 					MASKDWORD,
562 					agctab_array_table[i + 1]);
563 				/* Add 1us delay between BB/RF register
564 				 * setting. */
565 				udelay(1);
566 				rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
567 					"The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
568 					agctab_array_table[i],
569 					agctab_array_table[i + 1]);
570 			}
571 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
572 				"Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n");
573 		} else {
574 			if (rtlhal->current_bandtype == BAND_ON_2_4G) {
575 				for (i = 0; i < agctab_arraylen; i = i + 2) {
576 					rtl_set_bbreg(hw, agctab_array_table[i],
577 						MASKDWORD,
578 						agctab_array_table[i + 1]);
579 					/* Add 1us delay between BB/RF register
580 					 * setting. */
581 					udelay(1);
582 					rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
583 						"The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
584 						agctab_array_table[i],
585 						agctab_array_table[i + 1]);
586 				}
587 				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
588 					"Load Rtl819XAGCTAB_2GArray\n");
589 			} else {
590 				for (i = 0; i < agctab_5garraylen; i = i + 2) {
591 					rtl_set_bbreg(hw,
592 						agctab_5garray_table[i],
593 						MASKDWORD,
594 						agctab_5garray_table[i + 1]);
595 					/* Add 1us delay between BB/RF registeri
596 					 * setting. */
597 					udelay(1);
598 					rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
599 						"The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
600 						agctab_5garray_table[i],
601 						agctab_5garray_table[i + 1]);
602 				}
603 				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
604 					"Load Rtl819XAGCTAB_5GArray\n");
605 			}
606 		}
607 	}
608 	return true;
609 }
610 
611 static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
612 						   u32 regaddr, u32 bitmask,
613 						   u32 data)
614 {
615 	struct rtl_priv *rtlpriv = rtl_priv(hw);
616 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
617 	int index;
618 
619 	if (regaddr == RTXAGC_A_RATE18_06)
620 		index = 0;
621 	else if (regaddr == RTXAGC_A_RATE54_24)
622 		index = 1;
623 	else if (regaddr == RTXAGC_A_CCK1_MCS32)
624 		index = 6;
625 	else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
626 		index = 7;
627 	else if (regaddr == RTXAGC_A_MCS03_MCS00)
628 		index = 2;
629 	else if (regaddr == RTXAGC_A_MCS07_MCS04)
630 		index = 3;
631 	else if (regaddr == RTXAGC_A_MCS11_MCS08)
632 		index = 4;
633 	else if (regaddr == RTXAGC_A_MCS15_MCS12)
634 		index = 5;
635 	else if (regaddr == RTXAGC_B_RATE18_06)
636 		index = 8;
637 	else if (regaddr == RTXAGC_B_RATE54_24)
638 		index = 9;
639 	else if (regaddr == RTXAGC_B_CCK1_55_MCS32)
640 		index = 14;
641 	else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
642 		index = 15;
643 	else if (regaddr == RTXAGC_B_MCS03_MCS00)
644 		index = 10;
645 	else if (regaddr == RTXAGC_B_MCS07_MCS04)
646 		index = 11;
647 	else if (regaddr == RTXAGC_B_MCS11_MCS08)
648 		index = 12;
649 	else if (regaddr == RTXAGC_B_MCS15_MCS12)
650 		index = 13;
651 	else
652 		return;
653 
654 	rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
655 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
656 		"MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
657 		rtlphy->pwrgroup_cnt, index,
658 		rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]);
659 	if (index == 13)
660 		rtlphy->pwrgroup_cnt++;
661 }
662 
663 static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
664 	u8 configtype)
665 {
666 	struct rtl_priv *rtlpriv = rtl_priv(hw);
667 	int i;
668 	u32 *phy_regarray_table_pg;
669 	u16 phy_regarray_pg_len;
670 
671 	phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH;
672 	phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
673 	if (configtype == BASEBAND_CONFIG_PHY_REG) {
674 		for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
675 			rtl_addr_delay(phy_regarray_table_pg[i]);
676 			_rtl92d_store_pwrindex_diffrate_offset(hw,
677 				phy_regarray_table_pg[i],
678 				phy_regarray_table_pg[i + 1],
679 				phy_regarray_table_pg[i + 2]);
680 		}
681 	} else {
682 		rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,
683 			"configtype != BaseBand_Config_PHY_REG\n");
684 	}
685 	return true;
686 }
687 
688 static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw)
689 {
690 	struct rtl_priv *rtlpriv = rtl_priv(hw);
691 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
692 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
693 	bool rtstatus;
694 
695 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
696 	rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
697 		BASEBAND_CONFIG_PHY_REG);
698 	if (!rtstatus) {
699 		pr_err("Write BB Reg Fail!!\n");
700 		return false;
701 	}
702 
703 	/* if (rtlphy->rf_type == RF_1T2R) {
704 	 *      _rtl92c_phy_bb_config_1t(hw);
705 	 *     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
706 	 *} */
707 
708 	if (rtlefuse->autoload_failflag == false) {
709 		rtlphy->pwrgroup_cnt = 0;
710 		rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw,
711 			BASEBAND_CONFIG_PHY_REG);
712 	}
713 	if (!rtstatus) {
714 		pr_err("BB_PG Reg Fail!!\n");
715 		return false;
716 	}
717 	rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
718 		BASEBAND_CONFIG_AGC_TAB);
719 	if (!rtstatus) {
720 		pr_err("AGC Table Fail\n");
721 		return false;
722 	}
723 	rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
724 		RFPGA0_XA_HSSIPARAMETER2, 0x200));
725 
726 	return true;
727 }
728 
729 bool rtl92d_phy_bb_config(struct ieee80211_hw *hw)
730 {
731 	struct rtl_priv *rtlpriv = rtl_priv(hw);
732 	u16 regval;
733 	u32 regvaldw;
734 	u8 value;
735 
736 	_rtl92d_phy_init_bb_rf_register_definition(hw);
737 	regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
738 	rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
739 		       regval | BIT(13) | BIT(0) | BIT(1));
740 	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
741 	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
742 	/* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */
743 	value = rtl_read_byte(rtlpriv, REG_RF_CTRL);
744 	rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
745 		RF_SDMRSTB);
746 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
747 		FEN_DIO_PCIE | FEN_BB_GLB_RSTN | FEN_BBRSTB);
748 	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
749 	if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
750 		regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
751 		rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
752 	}
753 
754 	return _rtl92d_phy_bb_config(hw);
755 }
756 
757 bool rtl92d_phy_rf_config(struct ieee80211_hw *hw)
758 {
759 	return rtl92d_phy_rf6052_config(hw);
760 }
761 
762 bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
763 					  enum rf_content content,
764 					  enum radio_path rfpath)
765 {
766 	int i;
767 	u32 *radioa_array_table;
768 	u32 *radiob_array_table;
769 	u16 radioa_arraylen, radiob_arraylen;
770 	struct rtl_priv *rtlpriv = rtl_priv(hw);
771 
772 	radioa_arraylen = RADIOA_2T_ARRAYLENGTH;
773 	radioa_array_table = rtl8192de_radioa_2tarray;
774 	radiob_arraylen = RADIOB_2T_ARRAYLENGTH;
775 	radiob_array_table = rtl8192de_radiob_2tarray;
776 	if (rtlpriv->efuse.internal_pa_5g[0]) {
777 		radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH;
778 		radioa_array_table = rtl8192de_radioa_2t_int_paarray;
779 	}
780 	if (rtlpriv->efuse.internal_pa_5g[1]) {
781 		radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH;
782 		radiob_array_table = rtl8192de_radiob_2t_int_paarray;
783 	}
784 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
785 		"PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n");
786 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
787 		"PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n");
788 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
789 
790 	/* this only happens when DMDP, mac0 start on 2.4G,
791 	 * mac1 start on 5G, mac 0 has to set phy0&phy1
792 	 * pathA or mac1 has to set phy0&phy1 pathA */
793 	if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) {
794 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
795 			" ===> althougth Path A, we load radiob.txt\n");
796 		radioa_arraylen = radiob_arraylen;
797 		radioa_array_table = radiob_array_table;
798 	}
799 	switch (rfpath) {
800 	case RF90_PATH_A:
801 		for (i = 0; i < radioa_arraylen; i = i + 2) {
802 			rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
803 					RFREG_OFFSET_MASK,
804 					radioa_array_table[i + 1]);
805 		}
806 		break;
807 	case RF90_PATH_B:
808 		for (i = 0; i < radiob_arraylen; i = i + 2) {
809 			rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
810 					RFREG_OFFSET_MASK,
811 					radiob_array_table[i + 1]);
812 		}
813 		break;
814 	case RF90_PATH_C:
815 	case RF90_PATH_D:
816 		pr_err("switch case %#x not processed\n", rfpath);
817 		break;
818 	}
819 	return true;
820 }
821 
822 void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
823 {
824 	struct rtl_priv *rtlpriv = rtl_priv(hw);
825 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
826 
827 	rtlphy->default_initialgain[0] =
828 	    (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
829 	rtlphy->default_initialgain[1] =
830 	    (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
831 	rtlphy->default_initialgain[2] =
832 	    (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
833 	rtlphy->default_initialgain[3] =
834 	    (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
835 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
836 		"Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
837 		rtlphy->default_initialgain[0],
838 		rtlphy->default_initialgain[1],
839 		rtlphy->default_initialgain[2],
840 		rtlphy->default_initialgain[3]);
841 	rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
842 					      MASKBYTE0);
843 	rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
844 					      MASKDWORD);
845 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
846 		"Default framesync (0x%x) = 0x%x\n",
847 		ROFDM0_RXDETECTOR3, rtlphy->framesync);
848 }
849 
850 static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
851 	u8 *cckpowerlevel, u8 *ofdmpowerlevel)
852 {
853 	struct rtl_priv *rtlpriv = rtl_priv(hw);
854 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
855 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
856 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
857 	u8 index = (channel - 1);
858 
859 	/* 1. CCK */
860 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
861 		/* RF-A */
862 		cckpowerlevel[RF90_PATH_A] =
863 				 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
864 		/* RF-B */
865 		cckpowerlevel[RF90_PATH_B] =
866 				 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
867 	} else {
868 		cckpowerlevel[RF90_PATH_A] = 0;
869 		cckpowerlevel[RF90_PATH_B] = 0;
870 	}
871 	/* 2. OFDM for 1S or 2S */
872 	if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
873 		/*  Read HT 40 OFDM TX power */
874 		ofdmpowerlevel[RF90_PATH_A] =
875 		    rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
876 		ofdmpowerlevel[RF90_PATH_B] =
877 		    rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
878 	} else if (rtlphy->rf_type == RF_2T2R) {
879 		/* Read HT 40 OFDM TX power */
880 		ofdmpowerlevel[RF90_PATH_A] =
881 		    rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
882 		ofdmpowerlevel[RF90_PATH_B] =
883 		    rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
884 	}
885 }
886 
887 static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw,
888 	u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
889 {
890 	struct rtl_priv *rtlpriv = rtl_priv(hw);
891 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
892 
893 	rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
894 	rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
895 }
896 
897 static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl)
898 {
899 	u8 place = chnl;
900 
901 	if (chnl > 14) {
902 		for (place = 14; place < sizeof(channel5g); place++) {
903 			if (channel5g[place] == chnl) {
904 				place++;
905 				break;
906 			}
907 		}
908 	}
909 	return place;
910 }
911 
912 void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
913 {
914 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
915 	struct rtl_priv *rtlpriv = rtl_priv(hw);
916 	u8 cckpowerlevel[2], ofdmpowerlevel[2];
917 
918 	if (!rtlefuse->txpwr_fromeprom)
919 		return;
920 	channel = _rtl92c_phy_get_rightchnlplace(channel);
921 	_rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0],
922 		&ofdmpowerlevel[0]);
923 	if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
924 		_rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
925 				&ofdmpowerlevel[0]);
926 	if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
927 		rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
928 	rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
929 }
930 
931 void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
932 			    enum nl80211_channel_type ch_type)
933 {
934 	struct rtl_priv *rtlpriv = rtl_priv(hw);
935 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
936 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
937 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
938 	unsigned long flag = 0;
939 	u8 reg_prsr_rsc;
940 	u8 reg_bw_opmode;
941 
942 	if (rtlphy->set_bwmode_inprogress)
943 		return;
944 	if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
945 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
946 			"FALSE driver sleep or unload\n");
947 		return;
948 	}
949 	rtlphy->set_bwmode_inprogress = true;
950 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
951 		rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
952 		"20MHz" : "40MHz");
953 	reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
954 	reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
955 	switch (rtlphy->current_chan_bw) {
956 	case HT_CHANNEL_WIDTH_20:
957 		reg_bw_opmode |= BW_OPMODE_20MHZ;
958 		rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
959 		break;
960 	case HT_CHANNEL_WIDTH_20_40:
961 		reg_bw_opmode &= ~BW_OPMODE_20MHZ;
962 		rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
963 
964 		reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
965 			(mac->cur_40_prime_sc << 5);
966 		rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
967 		break;
968 	default:
969 		pr_err("unknown bandwidth: %#X\n",
970 		       rtlphy->current_chan_bw);
971 		break;
972 	}
973 	switch (rtlphy->current_chan_bw) {
974 	case HT_CHANNEL_WIDTH_20:
975 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
976 		rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
977 		/* SET BIT10 BIT11  for receive cck */
978 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
979 			      BIT(11), 3);
980 		break;
981 	case HT_CHANNEL_WIDTH_20_40:
982 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
983 		rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
984 		/* Set Control channel to upper or lower.
985 		 * These settings are required only for 40MHz */
986 		if (rtlhal->current_bandtype == BAND_ON_2_4G) {
987 			rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
988 			rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND,
989 				(mac->cur_40_prime_sc >> 1));
990 			rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
991 		}
992 		rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
993 		/* SET BIT10 BIT11  for receive cck */
994 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
995 			      BIT(11), 0);
996 		rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
997 			(mac->cur_40_prime_sc ==
998 			HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
999 		break;
1000 	default:
1001 		pr_err("unknown bandwidth: %#X\n",
1002 		       rtlphy->current_chan_bw);
1003 		break;
1004 
1005 	}
1006 	rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1007 	rtlphy->set_bwmode_inprogress = false;
1008 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
1009 }
1010 
1011 static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
1012 {
1013 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
1014 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
1015 	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00);
1016 	rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
1017 }
1018 
1019 static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
1020 {
1021 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1022 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1023 	u8 value8;
1024 
1025 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
1026 	rtlhal->bandset = band;
1027 	rtlhal->current_bandtype = band;
1028 	if (IS_92D_SINGLEPHY(rtlhal->version))
1029 		rtlhal->bandset = BAND_ON_BOTH;
1030 	/* stop RX/Tx */
1031 	_rtl92d_phy_stop_trx_before_changeband(hw);
1032 	/* reconfig BB/RF according to wireless mode */
1033 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1034 		/* BB & RF Config */
1035 		rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n");
1036 		if (rtlhal->interfaceindex == 1)
1037 			_rtl92d_phy_config_bb_with_headerfile(hw,
1038 				BASEBAND_CONFIG_AGC_TAB);
1039 	} else {
1040 		/* 5G band */
1041 		rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n");
1042 		if (rtlhal->interfaceindex == 1)
1043 			_rtl92d_phy_config_bb_with_headerfile(hw,
1044 				BASEBAND_CONFIG_AGC_TAB);
1045 	}
1046 	rtl92d_update_bbrf_configuration(hw);
1047 	if (rtlhal->current_bandtype == BAND_ON_2_4G)
1048 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1049 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1050 
1051 	/* 20M BW. */
1052 	/* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */
1053 	rtlhal->reloadtxpowerindex = true;
1054 	/* notice fw know band status  0x81[1]/0x53[1] = 0: 5G, 1: 2G */
1055 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1056 		value8 = rtl_read_byte(rtlpriv,	(rtlhal->interfaceindex ==
1057 			0 ? REG_MAC0 : REG_MAC1));
1058 		value8 |= BIT(1);
1059 		rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1060 			0 ? REG_MAC0 : REG_MAC1), value8);
1061 	} else {
1062 		value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1063 			0 ? REG_MAC0 : REG_MAC1));
1064 		value8 &= (~BIT(1));
1065 		rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1066 			0 ? REG_MAC0 : REG_MAC1), value8);
1067 	}
1068 	mdelay(1);
1069 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n");
1070 }
1071 
1072 static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1073 	u8 channel, u8 rfpath)
1074 {
1075 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1076 	u32 imr_num = MAX_RF_IMR_INDEX;
1077 	u32 rfmask = RFREG_OFFSET_MASK;
1078 	u8 group, i;
1079 	unsigned long flag = 0;
1080 
1081 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath);
1082 	if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
1083 		rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1084 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1085 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1086 		/* fc area 0xd2c */
1087 		if (channel > 99)
1088 			rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1089 				      BIT(14), 2);
1090 		else
1091 			rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1092 				      BIT(14), 1);
1093 		/* leave 0 for channel1-14. */
1094 		group = channel <= 64 ? 1 : 2;
1095 		imr_num = MAX_RF_IMR_INDEX_NORMAL;
1096 		for (i = 0; i < imr_num; i++)
1097 			rtl_set_rfreg(hw, (enum radio_path)rfpath,
1098 				      rf_reg_for_5g_swchnl_normal[i], rfmask,
1099 				      rf_imr_param_normal[0][group][i]);
1100 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
1101 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1);
1102 	} else {
1103 		/* G band. */
1104 		rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
1105 			"Load RF IMR parameters for G band. IMR already setting %d\n",
1106 			rtlpriv->rtlhal.load_imrandiqk_setting_for2g);
1107 		rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1108 		if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) {
1109 			rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
1110 				"Load RF IMR parameters for G band. %d\n",
1111 				rfpath);
1112 			rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1113 			rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1114 			rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1115 				      0x00f00000, 0xf);
1116 			imr_num = MAX_RF_IMR_INDEX_NORMAL;
1117 			for (i = 0; i < imr_num; i++) {
1118 				rtl_set_rfreg(hw, (enum radio_path)rfpath,
1119 					      rf_reg_for_5g_swchnl_normal[i],
1120 					      RFREG_OFFSET_MASK,
1121 					      rf_imr_param_normal[0][0][i]);
1122 			}
1123 			rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1124 				      0x00f00000, 0);
1125 			rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3);
1126 			rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1127 		}
1128 	}
1129 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1130 }
1131 
1132 static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw,
1133 	u8 rfpath, u32 *pu4_regval)
1134 {
1135 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1136 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1137 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1138 
1139 	rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "====>\n");
1140 	/*----Store original RFENV control type----*/
1141 	switch (rfpath) {
1142 	case RF90_PATH_A:
1143 	case RF90_PATH_C:
1144 		*pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV);
1145 		break;
1146 	case RF90_PATH_B:
1147 	case RF90_PATH_D:
1148 		*pu4_regval =
1149 		    rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16);
1150 		break;
1151 	}
1152 	/*----Set RF_ENV enable----*/
1153 	rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
1154 	udelay(1);
1155 	/*----Set RF_ENV output high----*/
1156 	rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
1157 	udelay(1);
1158 	/* Set bit number of Address and Data for RF register */
1159 	/* Set 1 to 4 bits for 8255 */
1160 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0);
1161 	udelay(1);
1162 	/*Set 0 to 12 bits for 8255 */
1163 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
1164 	udelay(1);
1165 	rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<====\n");
1166 }
1167 
1168 static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath,
1169 				       u32 *pu4_regval)
1170 {
1171 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1172 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1173 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1174 
1175 	rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n");
1176 	/*----Restore RFENV control type----*/
1177 	switch (rfpath) {
1178 	case RF90_PATH_A:
1179 	case RF90_PATH_C:
1180 		rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval);
1181 		break;
1182 	case RF90_PATH_B:
1183 	case RF90_PATH_D:
1184 		rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
1185 			      *pu4_regval);
1186 		break;
1187 	}
1188 	rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n");
1189 }
1190 
1191 static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1192 {
1193 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1194 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1195 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1196 	u8 path = rtlhal->current_bandtype ==
1197 	    BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B;
1198 	u8 index = 0, i = 0, rfpath = RF90_PATH_A;
1199 	bool need_pwr_down = false, internal_pa = false;
1200 	u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2;
1201 
1202 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n");
1203 	/* config path A for 5G */
1204 	if (rtlhal->current_bandtype == BAND_ON_5G) {
1205 		rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1206 		u4tmp = curveindex_5g[channel - 1];
1207 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1208 			"ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
1209 		for (i = 0; i < RF_CHNL_NUM_5G; i++) {
1210 			if (channel == rf_chnl_5g[i] && channel <= 140)
1211 				index = 0;
1212 		}
1213 		for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) {
1214 			if (channel == rf_chnl_5g_40m[i] && channel <= 140)
1215 				index = 1;
1216 		}
1217 		if (channel == 149 || channel == 155 || channel == 161)
1218 			index = 2;
1219 		else if (channel == 151 || channel == 153 || channel == 163
1220 			 || channel == 165)
1221 			index = 3;
1222 		else if (channel == 157 || channel == 159)
1223 			index = 4;
1224 
1225 		if (rtlhal->macphymode == DUALMAC_DUALPHY
1226 		    && rtlhal->interfaceindex == 1) {
1227 			need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false);
1228 			rtlhal->during_mac1init_radioa = true;
1229 			/* asume no this case */
1230 			if (need_pwr_down)
1231 				_rtl92d_phy_enable_rf_env(hw, path,
1232 							  &u4regvalue);
1233 		}
1234 		for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) {
1235 			if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
1236 				rtl_set_rfreg(hw, (enum radio_path)path,
1237 					      rf_reg_for_c_cut_5g[i],
1238 					      RFREG_OFFSET_MASK, 0xE439D);
1239 			} else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
1240 				u4tmp2 = (rf_reg_pram_c_5g[index][i] &
1241 				     0x7FF) | (u4tmp << 11);
1242 				if (channel == 36)
1243 					u4tmp2 &= ~(BIT(7) | BIT(6));
1244 				rtl_set_rfreg(hw, (enum radio_path)path,
1245 					      rf_reg_for_c_cut_5g[i],
1246 					      RFREG_OFFSET_MASK, u4tmp2);
1247 			} else {
1248 				rtl_set_rfreg(hw, (enum radio_path)path,
1249 					      rf_reg_for_c_cut_5g[i],
1250 					      RFREG_OFFSET_MASK,
1251 					      rf_reg_pram_c_5g[index][i]);
1252 			}
1253 			rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
1254 				"offset 0x%x value 0x%x path %d index %d readback 0x%x\n",
1255 				rf_reg_for_c_cut_5g[i],
1256 				rf_reg_pram_c_5g[index][i],
1257 				path, index,
1258 				rtl_get_rfreg(hw, (enum radio_path)path,
1259 					      rf_reg_for_c_cut_5g[i],
1260 					      RFREG_OFFSET_MASK));
1261 		}
1262 		if (need_pwr_down)
1263 			_rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1264 		if (rtlhal->during_mac1init_radioa)
1265 			rtl92d_phy_powerdown_anotherphy(hw, false);
1266 		if (channel < 149)
1267 			value = 0x07;
1268 		else if (channel >= 149)
1269 			value = 0x02;
1270 		if (channel >= 36 && channel <= 64)
1271 			index = 0;
1272 		else if (channel >= 100 && channel <= 140)
1273 			index = 1;
1274 		else
1275 			index = 2;
1276 		for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1277 			rfpath++) {
1278 			if (rtlhal->macphymode == DUALMAC_DUALPHY &&
1279 				rtlhal->interfaceindex == 1)	/* MAC 1 5G */
1280 				internal_pa = rtlpriv->efuse.internal_pa_5g[1];
1281 			else
1282 				internal_pa =
1283 					 rtlpriv->efuse.internal_pa_5g[rfpath];
1284 			if (internal_pa) {
1285 				for (i = 0;
1286 				     i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA;
1287 				     i++) {
1288 					rtl_set_rfreg(hw, rfpath,
1289 						rf_for_c_cut_5g_internal_pa[i],
1290 						RFREG_OFFSET_MASK,
1291 						rf_pram_c_5g_int_pa[index][i]);
1292 					rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
1293 						"offset 0x%x value 0x%x path %d index %d\n",
1294 						rf_for_c_cut_5g_internal_pa[i],
1295 						rf_pram_c_5g_int_pa[index][i],
1296 						rfpath, index);
1297 				}
1298 			} else {
1299 				rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
1300 					      mask, value);
1301 			}
1302 		}
1303 	} else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1304 		rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1305 		u4tmp = curveindex_2g[channel - 1];
1306 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1307 			"ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
1308 		if (channel == 1 || channel == 2 || channel == 4 || channel == 9
1309 		    || channel == 10 || channel == 11 || channel == 12)
1310 			index = 0;
1311 		else if (channel == 3 || channel == 13 || channel == 14)
1312 			index = 1;
1313 		else if (channel >= 5 && channel <= 8)
1314 			index = 2;
1315 		if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1316 			path = RF90_PATH_A;
1317 			if (rtlhal->interfaceindex == 0) {
1318 				need_pwr_down =
1319 					 rtl92d_phy_enable_anotherphy(hw, true);
1320 				rtlhal->during_mac0init_radiob = true;
1321 
1322 				if (need_pwr_down)
1323 					_rtl92d_phy_enable_rf_env(hw, path,
1324 								  &u4regvalue);
1325 			}
1326 		}
1327 		for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) {
1328 			if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
1329 				rtl_set_rfreg(hw, (enum radio_path)path,
1330 					rf_reg_for_c_cut_2g[i],
1331 					RFREG_OFFSET_MASK,
1332 					(rf_reg_param_for_c_cut_2g[index][i] |
1333 					BIT(17)));
1334 			else
1335 				rtl_set_rfreg(hw, (enum radio_path)path,
1336 					      rf_reg_for_c_cut_2g[i],
1337 					      RFREG_OFFSET_MASK,
1338 					      rf_reg_param_for_c_cut_2g
1339 					      [index][i]);
1340 			rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
1341 				"offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n",
1342 				rf_reg_for_c_cut_2g[i],
1343 				rf_reg_param_for_c_cut_2g[index][i],
1344 				rf_reg_mask_for_c_cut_2g[i], path, index,
1345 				rtl_get_rfreg(hw, (enum radio_path)path,
1346 					      rf_reg_for_c_cut_2g[i],
1347 					      RFREG_OFFSET_MASK));
1348 		}
1349 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1350 			"cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1351 			rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1352 
1353 		rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1354 			      RFREG_OFFSET_MASK,
1355 			      rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1356 		if (need_pwr_down)
1357 			_rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1358 		if (rtlhal->during_mac0init_radiob)
1359 			rtl92d_phy_powerdown_anotherphy(hw, true);
1360 	}
1361 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1362 }
1363 
1364 u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl)
1365 {
1366 	u8 place;
1367 
1368 	if (chnl > 14) {
1369 		for (place = 14; place < sizeof(channel_all); place++) {
1370 			if (channel_all[place] == chnl)
1371 				return place - 13;
1372 		}
1373 	}
1374 
1375 	return 0;
1376 }
1377 
1378 #define MAX_TOLERANCE		5
1379 #define IQK_DELAY_TIME		1	/* ms */
1380 #define MAX_TOLERANCE_92D	3
1381 
1382 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1383 static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1384 {
1385 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1386 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1387 	u32 regeac, rege94, rege9c, regea4;
1388 	u8 result = 0;
1389 
1390 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK!\n");
1391 	/* path-A IQK setting */
1392 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1393 	if (rtlhal->interfaceindex == 0) {
1394 		rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1395 		rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1396 	} else {
1397 		rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22);
1398 		rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22);
1399 	}
1400 	rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1401 	rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206);
1402 	/* path-B IQK setting */
1403 	if (configpathb) {
1404 		rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1405 		rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1406 		rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1407 		rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206);
1408 	}
1409 	/* LO calibration setting */
1410 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1411 	rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1412 	/* One shot, path A LOK & IQK */
1413 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "One shot, path A LOK & IQK!\n");
1414 	rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1415 	rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1416 	/* delay x ms */
1417 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
1418 		"Delay %d ms for One shot, path A LOK & IQK\n",
1419 		IQK_DELAY_TIME);
1420 	mdelay(IQK_DELAY_TIME);
1421 	/* Check failed */
1422 	regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1423 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1424 	rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1425 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe94 = 0x%x\n", rege94);
1426 	rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1427 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe9c = 0x%x\n", rege9c);
1428 	regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1429 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xea4 = 0x%x\n", regea4);
1430 	if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1431 	    (((rege9c & 0x03FF0000) >> 16) != 0x42))
1432 		result |= 0x01;
1433 	else			/* if Tx not OK, ignore Rx */
1434 		return result;
1435 	/* if Tx is OK, check whether Rx is OK */
1436 	if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) &&
1437 	    (((regeac & 0x03FF0000) >> 16) != 0x36))
1438 		result |= 0x02;
1439 	else
1440 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A Rx IQK fail!!\n");
1441 	return result;
1442 }
1443 
1444 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1445 static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1446 					  bool configpathb)
1447 {
1448 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1449 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1450 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1451 	u32 regeac, rege94, rege9c, regea4;
1452 	u8 result = 0;
1453 	u8 i;
1454 	u8 retrycount = 2;
1455 	u32 TXOKBIT = BIT(28), RXOKBIT = BIT(27);
1456 
1457 	if (rtlhal->interfaceindex == 1) {	/* PHY1 */
1458 		TXOKBIT = BIT(31);
1459 		RXOKBIT = BIT(30);
1460 	}
1461 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK!\n");
1462 	/* path-A IQK setting */
1463 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1464 	rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1465 	rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1466 	rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307);
1467 	rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960);
1468 	/* path-B IQK setting */
1469 	if (configpathb) {
1470 		rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1471 		rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1472 		rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000);
1473 		rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000);
1474 	}
1475 	/* LO calibration setting */
1476 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1477 	rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1478 	/* path-A PA on */
1479 	rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60);
1480 	rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30);
1481 	for (i = 0; i < retrycount; i++) {
1482 		/* One shot, path A LOK & IQK */
1483 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1484 			"One shot, path A LOK & IQK!\n");
1485 		rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1486 		rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1487 		/* delay x ms */
1488 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1489 			"Delay %d ms for One shot, path A LOK & IQK.\n",
1490 			IQK_DELAY_TIME);
1491 		mdelay(IQK_DELAY_TIME * 10);
1492 		/* Check failed */
1493 		regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1494 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1495 		rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1496 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe94 = 0x%x\n", rege94);
1497 		rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1498 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe9c = 0x%x\n", rege9c);
1499 		regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1500 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xea4 = 0x%x\n", regea4);
1501 		if (!(regeac & TXOKBIT) &&
1502 		     (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1503 			result |= 0x01;
1504 		} else { /* if Tx not OK, ignore Rx */
1505 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1506 				"Path A Tx IQK fail!!\n");
1507 			continue;
1508 		}
1509 
1510 		/* if Tx is OK, check whether Rx is OK */
1511 		if (!(regeac & RXOKBIT) &&
1512 		    (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1513 			result |= 0x02;
1514 			break;
1515 		} else {
1516 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1517 				"Path A Rx IQK fail!!\n");
1518 		}
1519 	}
1520 	/* path A PA off */
1521 	rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1522 		      rtlphy->iqk_bb_backup[0]);
1523 	rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD,
1524 		      rtlphy->iqk_bb_backup[1]);
1525 	return result;
1526 }
1527 
1528 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1529 static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1530 {
1531 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1532 	u32 regeac, regeb4, regebc, regec4, regecc;
1533 	u8 result = 0;
1534 
1535 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B IQK!\n");
1536 	/* One shot, path B LOK & IQK */
1537 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "One shot, path A LOK & IQK!\n");
1538 	rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1539 	rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1540 	/* delay x ms  */
1541 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
1542 		"Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME);
1543 	mdelay(IQK_DELAY_TIME);
1544 	/* Check failed */
1545 	regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1546 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1547 	regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1548 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeb4 = 0x%x\n", regeb4);
1549 	regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1550 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xebc = 0x%x\n", regebc);
1551 	regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1552 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xec4 = 0x%x\n", regec4);
1553 	regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1554 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xecc = 0x%x\n", regecc);
1555 	if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1556 	    (((regebc & 0x03FF0000) >> 16) != 0x42))
1557 		result |= 0x01;
1558 	else
1559 		return result;
1560 	if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
1561 	    (((regecc & 0x03FF0000) >> 16) != 0x36))
1562 		result |= 0x02;
1563 	else
1564 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B Rx IQK fail!!\n");
1565 	return result;
1566 }
1567 
1568 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1569 static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1570 {
1571 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1572 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1573 	u32 regeac, regeb4, regebc, regec4, regecc;
1574 	u8 result = 0;
1575 	u8 i;
1576 	u8 retrycount = 2;
1577 
1578 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B IQK!\n");
1579 	/* path-A IQK setting */
1580 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1581 	rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1582 	rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1583 	rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000);
1584 	rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000);
1585 
1586 	/* path-B IQK setting */
1587 	rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1588 	rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1589 	rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307);
1590 	rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960);
1591 
1592 	/* LO calibration setting */
1593 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1594 	rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1595 
1596 	/* path-B PA on */
1597 	rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700);
1598 	rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30);
1599 
1600 	for (i = 0; i < retrycount; i++) {
1601 		/* One shot, path B LOK & IQK */
1602 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1603 			"One shot, path A LOK & IQK!\n");
1604 		rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000);
1605 		rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1606 
1607 		/* delay x ms */
1608 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1609 			"Delay %d ms for One shot, path B LOK & IQK.\n", 10);
1610 		mdelay(IQK_DELAY_TIME * 10);
1611 
1612 		/* Check failed */
1613 		regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1614 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1615 		regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1616 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeb4 = 0x%x\n", regeb4);
1617 		regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1618 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xebc = 0x%x\n", regebc);
1619 		regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1620 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xec4 = 0x%x\n", regec4);
1621 		regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1622 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xecc = 0x%x\n", regecc);
1623 		if (!(regeac & BIT(31)) &&
1624 		    (((regeb4 & 0x03FF0000) >> 16) != 0x142))
1625 			result |= 0x01;
1626 		else
1627 			continue;
1628 		if (!(regeac & BIT(30)) &&
1629 		    (((regec4 & 0x03FF0000) >> 16) != 0x132)) {
1630 			result |= 0x02;
1631 			break;
1632 		} else {
1633 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1634 				"Path B Rx IQK fail!!\n");
1635 		}
1636 	}
1637 
1638 	/* path B PA off */
1639 	rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1640 		      rtlphy->iqk_bb_backup[0]);
1641 	rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD,
1642 		      rtlphy->iqk_bb_backup[2]);
1643 	return result;
1644 }
1645 
1646 static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1647 					    u32 *adda_reg, u32 *adda_backup,
1648 					    u32 regnum)
1649 {
1650 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1651 	u32 i;
1652 
1653 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Save ADDA parameters.\n");
1654 	for (i = 0; i < regnum; i++)
1655 		adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD);
1656 }
1657 
1658 static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
1659 	u32 *macreg, u32 *macbackup)
1660 {
1661 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1662 	u32 i;
1663 
1664 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Save MAC parameters.\n");
1665 	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1666 		macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1667 	macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1668 }
1669 
1670 static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1671 					      u32 *adda_reg, u32 *adda_backup,
1672 					      u32 regnum)
1673 {
1674 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1675 	u32 i;
1676 
1677 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
1678 		"Reload ADDA power saving parameters !\n");
1679 	for (i = 0; i < regnum; i++)
1680 		rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]);
1681 }
1682 
1683 static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
1684 					     u32 *macreg, u32 *macbackup)
1685 {
1686 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1687 	u32 i;
1688 
1689 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Reload MAC parameters !\n");
1690 	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1691 		rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1692 	rtl_write_byte(rtlpriv, macreg[i], macbackup[i]);
1693 }
1694 
1695 static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1696 		u32 *adda_reg, bool patha_on, bool is2t)
1697 {
1698 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1699 	u32 pathon;
1700 	u32 i;
1701 
1702 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "ADDA ON.\n");
1703 	pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;
1704 	if (patha_on)
1705 		pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
1706 		    0x04db25a4 : 0x0b1b25a4;
1707 	for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1708 		rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon);
1709 }
1710 
1711 static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1712 						u32 *macreg, u32 *macbackup)
1713 {
1714 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1715 	u32 i;
1716 
1717 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "MAC settings for Calibration.\n");
1718 	rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1719 
1720 	for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1721 		rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] &
1722 			       (~BIT(3))));
1723 	rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1724 }
1725 
1726 static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1727 {
1728 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1729 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A standby mode!\n");
1730 
1731 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1732 	rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000);
1733 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1734 }
1735 
1736 static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
1737 {
1738 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1739 	u32 mode;
1740 
1741 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
1742 		"BB Switch to %s mode!\n", pi_mode ? "PI" : "SI");
1743 	mode = pi_mode ? 0x01000100 : 0x01000000;
1744 	rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1745 	rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1746 }
1747 
1748 static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1749 				     u8 t, bool is2t)
1750 {
1751 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1752 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1753 	u32 i;
1754 	u8 patha_ok, pathb_ok;
1755 	static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1756 		RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1757 		0xe78, 0xe7c, 0xe80, 0xe84,
1758 		0xe88, 0xe8c, 0xed0, 0xed4,
1759 		0xed8, 0xedc, 0xee0, 0xeec
1760 	};
1761 	static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1762 		0x522, 0x550, 0x551, 0x040
1763 	};
1764 	static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1765 		RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1766 		RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1767 		RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1768 		RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1769 		ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1770 	};
1771 	const u32 retrycount = 2;
1772 	u32 bbvalue;
1773 
1774 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK for 2.4G :Start!!!\n");
1775 	if (t == 0) {
1776 		bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1777 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "==>0x%08x\n", bbvalue);
1778 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1779 			is2t ? "2T2R" : "1T1R");
1780 
1781 		/*  Save ADDA parameters, turn Path A ADDA on */
1782 		_rtl92d_phy_save_adda_registers(hw, adda_reg,
1783 			rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1784 		_rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1785 			rtlphy->iqk_mac_backup);
1786 		_rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1787 			rtlphy->iqk_bb_backup, IQK_BB_REG_NUM);
1788 	}
1789 	_rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1790 	if (t == 0)
1791 		rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1792 				RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1793 
1794 	/*  Switch BB to PI mode to do IQ Calibration. */
1795 	if (!rtlphy->rfpi_enable)
1796 		_rtl92d_phy_pimode_switch(hw, true);
1797 
1798 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1799 	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1800 	rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1801 	rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000);
1802 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1803 	if (is2t) {
1804 		rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD,
1805 			      0x00010000);
1806 		rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD,
1807 			      0x00010000);
1808 	}
1809 	/* MAC settings */
1810 	_rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1811 					    rtlphy->iqk_mac_backup);
1812 	/* Page B init */
1813 	rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1814 	if (is2t)
1815 		rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1816 	/* IQ calibration setting */
1817 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK setting!\n");
1818 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1819 	rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1820 	rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1821 	for (i = 0; i < retrycount; i++) {
1822 		patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
1823 		if (patha_ok == 0x03) {
1824 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1825 				"Path A IQK Success!!\n");
1826 			result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1827 					0x3FF0000) >> 16;
1828 			result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1829 					0x3FF0000) >> 16;
1830 			result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1831 					0x3FF0000) >> 16;
1832 			result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1833 					0x3FF0000) >> 16;
1834 			break;
1835 		} else if (i == (retrycount - 1) && patha_ok == 0x01) {
1836 			/* Tx IQK OK */
1837 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1838 				"Path A IQK Only  Tx Success!!\n");
1839 
1840 			result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1841 					0x3FF0000) >> 16;
1842 			result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1843 					0x3FF0000) >> 16;
1844 		}
1845 	}
1846 	if (0x00 == patha_ok)
1847 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK failed!!\n");
1848 	if (is2t) {
1849 		_rtl92d_phy_patha_standby(hw);
1850 		/* Turn Path B ADDA on */
1851 		_rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
1852 		for (i = 0; i < retrycount; i++) {
1853 			pathb_ok = _rtl92d_phy_pathb_iqk(hw);
1854 			if (pathb_ok == 0x03) {
1855 				RTPRINT(rtlpriv, FINIT, INIT_IQK,
1856 					"Path B IQK Success!!\n");
1857 				result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1858 					       MASKDWORD) & 0x3FF0000) >> 16;
1859 				result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1860 					       MASKDWORD) & 0x3FF0000) >> 16;
1861 				result[t][6] = (rtl_get_bbreg(hw, 0xec4,
1862 					       MASKDWORD) & 0x3FF0000) >> 16;
1863 				result[t][7] = (rtl_get_bbreg(hw, 0xecc,
1864 					       MASKDWORD) & 0x3FF0000) >> 16;
1865 				break;
1866 			} else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1867 				/* Tx IQK OK */
1868 				RTPRINT(rtlpriv, FINIT, INIT_IQK,
1869 					"Path B Only Tx IQK Success!!\n");
1870 				result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1871 					       MASKDWORD) & 0x3FF0000) >> 16;
1872 				result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1873 					       MASKDWORD) & 0x3FF0000) >> 16;
1874 			}
1875 		}
1876 		if (0x00 == pathb_ok)
1877 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1878 				"Path B IQK failed!!\n");
1879 	}
1880 
1881 	/* Back to BB mode, load original value */
1882 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
1883 		"IQK:Back to BB mode, load original value!\n");
1884 
1885 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1886 	if (t != 0) {
1887 		/* Switch back BB to SI mode after finish IQ Calibration. */
1888 		if (!rtlphy->rfpi_enable)
1889 			_rtl92d_phy_pimode_switch(hw, false);
1890 		/* Reload ADDA power saving parameters */
1891 		_rtl92d_phy_reload_adda_registers(hw, adda_reg,
1892 				rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1893 		/* Reload MAC parameters */
1894 		_rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
1895 					rtlphy->iqk_mac_backup);
1896 		if (is2t)
1897 			_rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
1898 							  rtlphy->iqk_bb_backup,
1899 							  IQK_BB_REG_NUM);
1900 		else
1901 			_rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
1902 							  rtlphy->iqk_bb_backup,
1903 							  IQK_BB_REG_NUM - 1);
1904 		/* load 0xe30 IQC default value */
1905 		rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
1906 		rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
1907 	}
1908 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "<==\n");
1909 }
1910 
1911 static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
1912 					       long result[][8], u8 t)
1913 {
1914 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1915 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1916 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1917 	u8 patha_ok, pathb_ok;
1918 	static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1919 		RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1920 		0xe78, 0xe7c, 0xe80, 0xe84,
1921 		0xe88, 0xe8c, 0xed0, 0xed4,
1922 		0xed8, 0xedc, 0xee0, 0xeec
1923 	};
1924 	static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1925 		0x522, 0x550, 0x551, 0x040
1926 	};
1927 	static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1928 		RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1929 		RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1930 		RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1931 		RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1932 		ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1933 	};
1934 	u32 bbvalue;
1935 	bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
1936 
1937 	/* Note: IQ calibration must be performed after loading
1938 	 * PHY_REG.txt , and radio_a, radio_b.txt */
1939 
1940 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK for 5G NORMAL:Start!!!\n");
1941 	mdelay(IQK_DELAY_TIME * 20);
1942 	if (t == 0) {
1943 		bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1944 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "==>0x%08x\n", bbvalue);
1945 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1946 			is2t ? "2T2R" : "1T1R");
1947 		/* Save ADDA parameters, turn Path A ADDA on */
1948 		_rtl92d_phy_save_adda_registers(hw, adda_reg,
1949 						rtlphy->adda_backup,
1950 						IQK_ADDA_REG_NUM);
1951 		_rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1952 					       rtlphy->iqk_mac_backup);
1953 		if (is2t)
1954 			_rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1955 							rtlphy->iqk_bb_backup,
1956 							IQK_BB_REG_NUM);
1957 		else
1958 			_rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1959 							rtlphy->iqk_bb_backup,
1960 							IQK_BB_REG_NUM - 1);
1961 	}
1962 	_rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1963 	/* MAC settings */
1964 	_rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1965 			rtlphy->iqk_mac_backup);
1966 	if (t == 0)
1967 		rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1968 			RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1969 	/*  Switch BB to PI mode to do IQ Calibration. */
1970 	if (!rtlphy->rfpi_enable)
1971 		_rtl92d_phy_pimode_switch(hw, true);
1972 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1973 	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1974 	rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1975 	rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000);
1976 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1977 
1978 	/* Page B init */
1979 	rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1980 	if (is2t)
1981 		rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1982 	/* IQ calibration setting  */
1983 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK setting!\n");
1984 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1985 	rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00);
1986 	rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1987 	patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
1988 	if (patha_ok == 0x03) {
1989 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK Success!!\n");
1990 		result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1991 				0x3FF0000) >> 16;
1992 		result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1993 				0x3FF0000) >> 16;
1994 		result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1995 				0x3FF0000) >> 16;
1996 		result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1997 				0x3FF0000) >> 16;
1998 	} else if (patha_ok == 0x01) {	/* Tx IQK OK */
1999 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2000 			"Path A IQK Only  Tx Success!!\n");
2001 
2002 		result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
2003 				0x3FF0000) >> 16;
2004 		result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
2005 				0x3FF0000) >> 16;
2006 	} else {
2007 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK Fail!!\n");
2008 	}
2009 	if (is2t) {
2010 		/* _rtl92d_phy_patha_standby(hw); */
2011 		/* Turn Path B ADDA on  */
2012 		_rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2013 		pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw);
2014 		if (pathb_ok == 0x03) {
2015 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
2016 				"Path B IQK Success!!\n");
2017 			result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2018 			     0x3FF0000) >> 16;
2019 			result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2020 			     0x3FF0000) >> 16;
2021 			result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
2022 			     0x3FF0000) >> 16;
2023 			result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
2024 			     0x3FF0000) >> 16;
2025 		} else if (pathb_ok == 0x01) { /* Tx IQK OK */
2026 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
2027 				"Path B Only Tx IQK Success!!\n");
2028 			result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2029 			     0x3FF0000) >> 16;
2030 			result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2031 			     0x3FF0000) >> 16;
2032 		} else {
2033 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
2034 				"Path B IQK failed!!\n");
2035 		}
2036 	}
2037 
2038 	/* Back to BB mode, load original value */
2039 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
2040 		"IQK:Back to BB mode, load original value!\n");
2041 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
2042 	if (t != 0) {
2043 		if (is2t)
2044 			_rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2045 							  rtlphy->iqk_bb_backup,
2046 							  IQK_BB_REG_NUM);
2047 		else
2048 			_rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2049 							  rtlphy->iqk_bb_backup,
2050 							  IQK_BB_REG_NUM - 1);
2051 		/* Reload MAC parameters */
2052 		_rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2053 				rtlphy->iqk_mac_backup);
2054 		/*  Switch back BB to SI mode after finish IQ Calibration. */
2055 		if (!rtlphy->rfpi_enable)
2056 			_rtl92d_phy_pimode_switch(hw, false);
2057 		/* Reload ADDA power saving parameters */
2058 		_rtl92d_phy_reload_adda_registers(hw, adda_reg,
2059 						  rtlphy->adda_backup,
2060 						  IQK_ADDA_REG_NUM);
2061 	}
2062 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "<==\n");
2063 }
2064 
2065 static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw,
2066 	long result[][8], u8 c1, u8 c2)
2067 {
2068 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2069 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2070 	u32 i, j, diff, sim_bitmap, bound;
2071 	u8 final_candidate[2] = {0xFF, 0xFF};	/* for path A and path B */
2072 	bool bresult = true;
2073 	bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2074 
2075 	if (is2t)
2076 		bound = 8;
2077 	else
2078 		bound = 4;
2079 	sim_bitmap = 0;
2080 	for (i = 0; i < bound; i++) {
2081 		diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] -
2082 		       result[c2][i]) : (result[c2][i] - result[c1][i]);
2083 		if (diff > MAX_TOLERANCE_92D) {
2084 			if ((i == 2 || i == 6) && !sim_bitmap) {
2085 				if (result[c1][i] + result[c1][i + 1] == 0)
2086 					final_candidate[(i / 4)] = c2;
2087 				else if (result[c2][i] + result[c2][i + 1] == 0)
2088 					final_candidate[(i / 4)] = c1;
2089 				else
2090 					sim_bitmap = sim_bitmap | (1 << i);
2091 			} else {
2092 				sim_bitmap = sim_bitmap | (1 << i);
2093 			}
2094 		}
2095 	}
2096 	if (sim_bitmap == 0) {
2097 		for (i = 0; i < (bound / 4); i++) {
2098 			if (final_candidate[i] != 0xFF) {
2099 				for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2100 					result[3][j] =
2101 						 result[final_candidate[i]][j];
2102 				bresult = false;
2103 			}
2104 		}
2105 		return bresult;
2106 	}
2107 	if (!(sim_bitmap & 0x0F)) { /* path A OK */
2108 		for (i = 0; i < 4; i++)
2109 			result[3][i] = result[c1][i];
2110 	} else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */
2111 		for (i = 0; i < 2; i++)
2112 			result[3][i] = result[c1][i];
2113 	}
2114 	if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */
2115 		for (i = 4; i < 8; i++)
2116 			result[3][i] = result[c1][i];
2117 	} else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */
2118 		for (i = 4; i < 6; i++)
2119 			result[3][i] = result[c1][i];
2120 	}
2121 	return false;
2122 }
2123 
2124 static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2125 					      bool iqk_ok, long result[][8],
2126 					      u8 final_candidate, bool txonly)
2127 {
2128 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2129 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2130 	u32 oldval_0, val_x, tx0_a, reg;
2131 	long val_y, tx0_c;
2132 	bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
2133 	    rtlhal->macphymode == DUALMAC_DUALPHY;
2134 
2135 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
2136 		"Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed");
2137 	if (final_candidate == 0xFF) {
2138 		return;
2139 	} else if (iqk_ok) {
2140 		oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2141 			MASKDWORD) >> 22) & 0x3FF;	/* OFDM0_D */
2142 		val_x = result[final_candidate][0];
2143 		if ((val_x & 0x00000200) != 0)
2144 			val_x = val_x | 0xFFFFFC00;
2145 		tx0_a = (val_x * oldval_0) >> 8;
2146 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2147 			"X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n",
2148 			val_x, tx0_a, oldval_0);
2149 		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
2150 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2151 			      ((val_x * oldval_0 >> 7) & 0x1));
2152 		val_y = result[final_candidate][1];
2153 		if ((val_y & 0x00000200) != 0)
2154 			val_y = val_y | 0xFFFFFC00;
2155 		/* path B IQK result + 3 */
2156 		if (rtlhal->interfaceindex == 1 &&
2157 			rtlhal->current_bandtype == BAND_ON_5G)
2158 			val_y += 3;
2159 		tx0_c = (val_y * oldval_0) >> 8;
2160 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2161 			"Y = 0x%lx, tx0_c = 0x%lx\n",
2162 			val_y, tx0_c);
2163 		rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
2164 			      ((tx0_c & 0x3C0) >> 6));
2165 		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
2166 			      (tx0_c & 0x3F));
2167 		if (is2t)
2168 			rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2169 				      ((val_y * oldval_0 >> 7) & 0x1));
2170 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
2171 			rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2172 				      MASKDWORD));
2173 		if (txonly) {
2174 			RTPRINT(rtlpriv, FINIT, INIT_IQK,  "only Tx OK\n");
2175 			return;
2176 		}
2177 		reg = result[final_candidate][2];
2178 		rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2179 		reg = result[final_candidate][3] & 0x3F;
2180 		rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2181 		reg = (result[final_candidate][3] >> 6) & 0xF;
2182 		rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
2183 	}
2184 }
2185 
2186 static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2187 	bool iqk_ok, long result[][8], u8 final_candidate, bool txonly)
2188 {
2189 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2190 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2191 	u32 oldval_1, val_x, tx1_a, reg;
2192 	long val_y, tx1_c;
2193 
2194 	RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n",
2195 		iqk_ok ? "Success" : "Failed");
2196 	if (final_candidate == 0xFF) {
2197 		return;
2198 	} else if (iqk_ok) {
2199 		oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
2200 					  MASKDWORD) >> 22) & 0x3FF;
2201 		val_x = result[final_candidate][4];
2202 		if ((val_x & 0x00000200) != 0)
2203 			val_x = val_x | 0xFFFFFC00;
2204 		tx1_a = (val_x * oldval_1) >> 8;
2205 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n",
2206 			val_x, tx1_a);
2207 		rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
2208 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2209 			      ((val_x * oldval_1 >> 7) & 0x1));
2210 		val_y = result[final_candidate][5];
2211 		if ((val_y & 0x00000200) != 0)
2212 			val_y = val_y | 0xFFFFFC00;
2213 		if (rtlhal->current_bandtype == BAND_ON_5G)
2214 			val_y += 3;
2215 		tx1_c = (val_y * oldval_1) >> 8;
2216 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n",
2217 			val_y, tx1_c);
2218 		rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
2219 			      ((tx1_c & 0x3C0) >> 6));
2220 		rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
2221 			      (tx1_c & 0x3F));
2222 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
2223 			      ((val_y * oldval_1 >> 7) & 0x1));
2224 		if (txonly)
2225 			return;
2226 		reg = result[final_candidate][6];
2227 		rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2228 		reg = result[final_candidate][7] & 0x3F;
2229 		rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2230 		reg = (result[final_candidate][7] >> 6) & 0xF;
2231 		rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
2232 	}
2233 }
2234 
2235 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2236 {
2237 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2238 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2239 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2240 	long result[4][8];
2241 	u8 i, final_candidate, indexforchannel;
2242 	bool patha_ok, pathb_ok;
2243 	long rege94, rege9c, regea4, regeac, regeb4;
2244 	long regebc, regec4, regecc, regtmp = 0;
2245 	bool is12simular, is13simular, is23simular;
2246 	unsigned long flag = 0;
2247 
2248 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
2249 		"IQK:Start!!!channel %d\n", rtlphy->current_channel);
2250 	for (i = 0; i < 8; i++) {
2251 		result[0][i] = 0;
2252 		result[1][i] = 0;
2253 		result[2][i] = 0;
2254 		result[3][i] = 0;
2255 	}
2256 	final_candidate = 0xff;
2257 	patha_ok = false;
2258 	pathb_ok = false;
2259 	is12simular = false;
2260 	is23simular = false;
2261 	is13simular = false;
2262 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
2263 		"IQK !!!currentband %d\n", rtlhal->current_bandtype);
2264 	rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
2265 	for (i = 0; i < 3; i++) {
2266 		if (rtlhal->current_bandtype == BAND_ON_5G) {
2267 			_rtl92d_phy_iq_calibrate_5g_normal(hw, result, i);
2268 		} else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2269 			if (IS_92D_SINGLEPHY(rtlhal->version))
2270 				_rtl92d_phy_iq_calibrate(hw, result, i, true);
2271 			else
2272 				_rtl92d_phy_iq_calibrate(hw, result, i, false);
2273 		}
2274 		if (i == 1) {
2275 			is12simular = _rtl92d_phy_simularity_compare(hw, result,
2276 								     0, 1);
2277 			if (is12simular) {
2278 				final_candidate = 0;
2279 				break;
2280 			}
2281 		}
2282 		if (i == 2) {
2283 			is13simular = _rtl92d_phy_simularity_compare(hw, result,
2284 								     0, 2);
2285 			if (is13simular) {
2286 				final_candidate = 0;
2287 				break;
2288 			}
2289 			is23simular = _rtl92d_phy_simularity_compare(hw, result,
2290 								     1, 2);
2291 			if (is23simular) {
2292 				final_candidate = 1;
2293 			} else {
2294 				for (i = 0; i < 8; i++)
2295 					regtmp += result[3][i];
2296 
2297 				if (regtmp != 0)
2298 					final_candidate = 3;
2299 				else
2300 					final_candidate = 0xFF;
2301 			}
2302 		}
2303 	}
2304 	rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
2305 	for (i = 0; i < 4; i++) {
2306 		rege94 = result[i][0];
2307 		rege9c = result[i][1];
2308 		regea4 = result[i][2];
2309 		regeac = result[i][3];
2310 		regeb4 = result[i][4];
2311 		regebc = result[i][5];
2312 		regec4 = result[i][6];
2313 		regecc = result[i][7];
2314 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2315 			"IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2316 			rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2317 			regecc);
2318 	}
2319 	if (final_candidate != 0xff) {
2320 		rtlphy->reg_e94 = rege94 = result[final_candidate][0];
2321 		rtlphy->reg_e9c = rege9c = result[final_candidate][1];
2322 		regea4 = result[final_candidate][2];
2323 		regeac = result[final_candidate][3];
2324 		rtlphy->reg_eb4 = regeb4 = result[final_candidate][4];
2325 		rtlphy->reg_ebc = regebc = result[final_candidate][5];
2326 		regec4 = result[final_candidate][6];
2327 		regecc = result[final_candidate][7];
2328 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2329 			"IQK: final_candidate is %x\n", final_candidate);
2330 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2331 			"IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2332 			rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2333 			regecc);
2334 		patha_ok = pathb_ok = true;
2335 	} else {
2336 		rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */
2337 		rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;   /* Y default value */
2338 	}
2339 	if ((rege94 != 0) /*&&(regea4 != 0) */)
2340 		_rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result,
2341 				final_candidate, (regea4 == 0));
2342 	if (IS_92D_SINGLEPHY(rtlhal->version)) {
2343 		if ((regeb4 != 0) /*&&(regec4 != 0) */)
2344 			_rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result,
2345 						final_candidate, (regec4 == 0));
2346 	}
2347 	if (final_candidate != 0xFF) {
2348 		indexforchannel = rtl92d_get_rightchnlplace_for_iqk(
2349 				  rtlphy->current_channel);
2350 
2351 		for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2352 			rtlphy->iqk_matrix[indexforchannel].
2353 				value[0][i] = result[final_candidate][i];
2354 		rtlphy->iqk_matrix[indexforchannel].iqk_done =
2355 			true;
2356 
2357 		rtl_dbg(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD,
2358 			"IQK OK indexforchannel %d\n", indexforchannel);
2359 	}
2360 }
2361 
2362 void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel)
2363 {
2364 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2365 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2366 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2367 	u8 indexforchannel;
2368 
2369 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel);
2370 	/*------Do IQK for normal chip and test chip 5G band------- */
2371 	indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
2372 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n",
2373 		indexforchannel,
2374 		 rtlphy->iqk_matrix[indexforchannel].iqk_done);
2375 	if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done &&
2376 		rtlphy->need_iqk) {
2377 		/* Re Do IQK. */
2378 		rtl_dbg(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD,
2379 			"Do IQK Matrix reg for channel:%d....\n", channel);
2380 		rtl92d_phy_iq_calibrate(hw);
2381 	} else {
2382 		/* Just load the value. */
2383 		/* 2G band just load once. */
2384 		if (((!rtlhal->load_imrandiqk_setting_for2g) &&
2385 		    indexforchannel == 0) || indexforchannel > 0) {
2386 			rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
2387 				"Just Read IQK Matrix reg for channel:%d....\n",
2388 				channel);
2389 			if ((rtlphy->iqk_matrix[indexforchannel].
2390 			     value[0] != NULL)
2391 				/*&&(regea4 != 0) */)
2392 				_rtl92d_phy_patha_fill_iqk_matrix(hw, true,
2393 					rtlphy->iqk_matrix[
2394 					indexforchannel].value,	0,
2395 					(rtlphy->iqk_matrix[
2396 					indexforchannel].value[0][2] == 0));
2397 			if (IS_92D_SINGLEPHY(rtlhal->version)) {
2398 				if ((rtlphy->iqk_matrix[
2399 					indexforchannel].value[0][4] != 0)
2400 					/*&&(regec4 != 0) */)
2401 					_rtl92d_phy_pathb_fill_iqk_matrix(hw,
2402 						true,
2403 						rtlphy->iqk_matrix[
2404 						indexforchannel].value, 0,
2405 						(rtlphy->iqk_matrix[
2406 						indexforchannel].value[0][6]
2407 						== 0));
2408 			}
2409 		}
2410 	}
2411 	rtlphy->need_iqk = false;
2412 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2413 }
2414 
2415 static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2)
2416 {
2417 	u32 ret;
2418 
2419 	if (val1 >= val2)
2420 		ret = val1 - val2;
2421 	else
2422 		ret = val2 - val1;
2423 	return ret;
2424 }
2425 
2426 static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel)
2427 {
2428 
2429 	int i;
2430 
2431 	for (i = 0; i < sizeof(channel5g); i++)
2432 		if (channel == channel5g[i])
2433 			return true;
2434 	return false;
2435 }
2436 
2437 static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw,
2438 				       u32 *targetchnl, u32 * curvecount_val,
2439 				       bool is5g, u32 *curveindex)
2440 {
2441 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2442 	u32 smallest_abs_val = 0xffffffff, u4tmp;
2443 	u8 i, j;
2444 	u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G;
2445 
2446 	for (i = 0; i < chnl_num; i++) {
2447 		if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1))
2448 			continue;
2449 		curveindex[i] = 0;
2450 		for (j = 0; j < (CV_CURVE_CNT * 2); j++) {
2451 			u4tmp = _rtl92d_phy_get_abs(targetchnl[i],
2452 				curvecount_val[j]);
2453 
2454 			if (u4tmp < smallest_abs_val) {
2455 				curveindex[i] = j;
2456 				smallest_abs_val = u4tmp;
2457 			}
2458 		}
2459 		smallest_abs_val = 0xffffffff;
2460 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n",
2461 			i, curveindex[i]);
2462 	}
2463 }
2464 
2465 static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2466 		u8 channel)
2467 {
2468 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2469 	u8 erfpath = rtlpriv->rtlhal.current_bandtype ==
2470 		BAND_ON_5G ? RF90_PATH_A :
2471 		IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ?
2472 		RF90_PATH_B : RF90_PATH_A;
2473 	u32 u4tmp = 0, u4regvalue = 0;
2474 	bool bneed_powerdown_radio = false;
2475 
2476 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath);
2477 	RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n",
2478 		rtlpriv->rtlhal.current_bandtype);
2479 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "channel = %d\n", channel);
2480 	if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */
2481 		u4tmp = curveindex_5g[channel-1];
2482 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2483 			"ver 1 set RF-A, 5G,	0x28 = 0x%x !!\n", u4tmp);
2484 		if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2485 			rtlpriv->rtlhal.interfaceindex == 1) {
2486 			bneed_powerdown_radio =
2487 				rtl92d_phy_enable_anotherphy(hw, false);
2488 			rtlpriv->rtlhal.during_mac1init_radioa = true;
2489 			/* asume no this case */
2490 			if (bneed_powerdown_radio)
2491 				_rtl92d_phy_enable_rf_env(hw, erfpath,
2492 							  &u4regvalue);
2493 		}
2494 		rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2495 		if (bneed_powerdown_radio)
2496 			_rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2497 		if (rtlpriv->rtlhal.during_mac1init_radioa)
2498 			rtl92d_phy_powerdown_anotherphy(hw, false);
2499 	} else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) {
2500 		u4tmp = curveindex_2g[channel-1];
2501 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2502 			"ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
2503 		if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2504 			rtlpriv->rtlhal.interfaceindex == 0) {
2505 			bneed_powerdown_radio =
2506 				rtl92d_phy_enable_anotherphy(hw, true);
2507 			rtlpriv->rtlhal.during_mac0init_radiob = true;
2508 			if (bneed_powerdown_radio)
2509 				_rtl92d_phy_enable_rf_env(hw, erfpath,
2510 							  &u4regvalue);
2511 		}
2512 		rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2513 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2514 			"ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
2515 			rtl_get_rfreg(hw,  erfpath, RF_SYN_G4, 0x3f800));
2516 		if (bneed_powerdown_radio)
2517 			_rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2518 		if (rtlpriv->rtlhal.during_mac0init_radiob)
2519 			rtl92d_phy_powerdown_anotherphy(hw, true);
2520 	}
2521 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2522 }
2523 
2524 static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2525 {
2526 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2527 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2528 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2529 	u8 tmpreg, index, rf_mode[2];
2530 	u8 path = is2t ? 2 : 1;
2531 	u8 i;
2532 	u32 u4tmp, offset;
2533 	u32 curvecount_val[CV_CURVE_CNT * 2] = {0};
2534 	u16 timeout = 800, timecount = 0;
2535 
2536 	/* Check continuous TX and Packet TX */
2537 	tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2538 	/* if Deal with contisuous TX case, disable all continuous TX */
2539 	/* if Deal with Packet TX case, block all queues */
2540 	if ((tmpreg & 0x70) != 0)
2541 		rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2542 	else
2543 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2544 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F);
2545 	for (index = 0; index < path; index++) {
2546 		/* 1. Read original RF mode */
2547 		offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2548 		rf_mode[index] = rtl_read_byte(rtlpriv, offset);
2549 		/* 2. Set RF mode = standby mode */
2550 		rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
2551 			      RFREG_OFFSET_MASK, 0x010000);
2552 		if (rtlpci->init_ready) {
2553 			/* switch CV-curve control by LC-calibration */
2554 			rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2555 				      BIT(17), 0x0);
2556 			/* 4. Set LC calibration begin */
2557 			rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2558 				      0x08000, 0x01);
2559 		}
2560 		u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
2561 				  RFREG_OFFSET_MASK);
2562 		while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
2563 			mdelay(50);
2564 			timecount += 50;
2565 			u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
2566 					      RF_SYN_G6, RFREG_OFFSET_MASK);
2567 		}
2568 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2569 			"PHY_LCK finish delay for %d ms=2\n", timecount);
2570 		rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK);
2571 		if (index == 0 && rtlhal->interfaceindex == 0) {
2572 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
2573 				"path-A / 5G LCK\n");
2574 		} else {
2575 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
2576 				"path-B / 2.4G LCK\n");
2577 		}
2578 		memset(curvecount_val, 0, sizeof(curvecount_val));
2579 		/* Set LC calibration off */
2580 		rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2581 			      0x08000, 0x0);
2582 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "set RF 0x18[15] = 0\n");
2583 		/* save Curve-counting number */
2584 		for (i = 0; i < CV_CURVE_CNT; i++) {
2585 			u32 readval = 0, readval2 = 0;
2586 			rtl_set_rfreg(hw, (enum radio_path)index, 0x3F,
2587 				      0x7f, i);
2588 
2589 			rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2590 				RFREG_OFFSET_MASK, 0x0);
2591 			readval = rtl_get_rfreg(hw, (enum radio_path)index,
2592 					  0x4F, RFREG_OFFSET_MASK);
2593 			curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2594 			/* reg 0x4f [4:0] */
2595 			/* reg 0x50 [19:10] */
2596 			readval2 = rtl_get_rfreg(hw, (enum radio_path)index,
2597 						 0x50, 0xffc00);
2598 			curvecount_val[2 * i] = (((readval & 0x1F) << 10) |
2599 						 readval2);
2600 		}
2601 		if (index == 0 && rtlhal->interfaceindex == 0)
2602 			_rtl92d_phy_calc_curvindex(hw, targetchnl_5g,
2603 						   curvecount_val,
2604 						   true, curveindex_5g);
2605 		else
2606 			_rtl92d_phy_calc_curvindex(hw, targetchnl_2g,
2607 						   curvecount_val,
2608 						   false, curveindex_2g);
2609 		/* switch CV-curve control mode */
2610 		rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2611 			      BIT(17), 0x1);
2612 	}
2613 
2614 	/* Restore original situation  */
2615 	for (index = 0; index < path; index++) {
2616 		offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2617 		rtl_write_byte(rtlpriv, offset, 0x50);
2618 		rtl_write_byte(rtlpriv, offset, rf_mode[index]);
2619 	}
2620 	if ((tmpreg & 0x70) != 0)
2621 		rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2622 	else /*Deal with Packet TX case */
2623 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2624 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00);
2625 	_rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel);
2626 }
2627 
2628 static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2629 {
2630 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2631 
2632 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "cosa PHY_LCK ver=2\n");
2633 	_rtl92d_phy_lc_calibrate_sw(hw, is2t);
2634 }
2635 
2636 void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw)
2637 {
2638 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2639 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2640 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2641 	u32 timeout = 2000, timecount = 0;
2642 
2643 	while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2644 		udelay(50);
2645 		timecount += 50;
2646 	}
2647 
2648 	rtlphy->lck_inprogress = true;
2649 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
2650 		"LCK:Start!!! currentband %x delay %d ms\n",
2651 		rtlhal->current_bandtype, timecount);
2652 	if (IS_92D_SINGLEPHY(rtlhal->version)) {
2653 		_rtl92d_phy_lc_calibrate(hw, true);
2654 	} else {
2655 		/* For 1T1R */
2656 		_rtl92d_phy_lc_calibrate(hw, false);
2657 	}
2658 	rtlphy->lck_inprogress = false;
2659 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LCK:Finish!!!\n");
2660 }
2661 
2662 void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
2663 {
2664 	return;
2665 }
2666 
2667 static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
2668 		u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
2669 		u32 para1, u32 para2, u32 msdelay)
2670 {
2671 	struct swchnlcmd *pcmd;
2672 
2673 	if (cmdtable == NULL) {
2674 		WARN_ONCE(true, "rtl8192de: cmdtable cannot be NULL\n");
2675 		return false;
2676 	}
2677 	if (cmdtableidx >= cmdtablesz)
2678 		return false;
2679 
2680 	pcmd = cmdtable + cmdtableidx;
2681 	pcmd->cmdid = cmdid;
2682 	pcmd->para1 = para1;
2683 	pcmd->para2 = para2;
2684 	pcmd->msdelay = msdelay;
2685 	return true;
2686 }
2687 
2688 void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw)
2689 {
2690 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2691 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2692 	u8 i;
2693 
2694 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2695 		"settings regs %d default regs %d\n",
2696 		(int)(sizeof(rtlphy->iqk_matrix) /
2697 		      sizeof(struct iqk_matrix_regs)),
2698 		IQK_MATRIX_REG_NUM);
2699 	/* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
2700 	for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
2701 		rtlphy->iqk_matrix[i].value[0][0] = 0x100;
2702 		rtlphy->iqk_matrix[i].value[0][2] = 0x100;
2703 		rtlphy->iqk_matrix[i].value[0][4] = 0x100;
2704 		rtlphy->iqk_matrix[i].value[0][6] = 0x100;
2705 		rtlphy->iqk_matrix[i].value[0][1] = 0x0;
2706 		rtlphy->iqk_matrix[i].value[0][3] = 0x0;
2707 		rtlphy->iqk_matrix[i].value[0][5] = 0x0;
2708 		rtlphy->iqk_matrix[i].value[0][7] = 0x0;
2709 		rtlphy->iqk_matrix[i].iqk_done = false;
2710 	}
2711 }
2712 
2713 static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
2714 					     u8 channel, u8 *stage, u8 *step,
2715 					     u32 *delay)
2716 {
2717 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2718 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2719 	struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
2720 	u32 precommoncmdcnt;
2721 	struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
2722 	u32 postcommoncmdcnt;
2723 	struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
2724 	u32 rfdependcmdcnt;
2725 	struct swchnlcmd *currentcmd = NULL;
2726 	u8 rfpath;
2727 	u8 num_total_rfpath = rtlphy->num_total_rfpath;
2728 
2729 	precommoncmdcnt = 0;
2730 	_rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2731 					 MAX_PRECMD_CNT,
2732 					 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
2733 	_rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2734 					 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
2735 	postcommoncmdcnt = 0;
2736 	_rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
2737 					 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
2738 	rfdependcmdcnt = 0;
2739 	_rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2740 					 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
2741 					 RF_CHNLBW, channel, 0);
2742 	_rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2743 					 MAX_RFDEPENDCMD_CNT, CMDID_END,
2744 					 0, 0, 0);
2745 
2746 	do {
2747 		switch (*stage) {
2748 		case 0:
2749 			currentcmd = &precommoncmd[*step];
2750 			break;
2751 		case 1:
2752 			currentcmd = &rfdependcmd[*step];
2753 			break;
2754 		case 2:
2755 			currentcmd = &postcommoncmd[*step];
2756 			break;
2757 		}
2758 		if (currentcmd->cmdid == CMDID_END) {
2759 			if ((*stage) == 2) {
2760 				return true;
2761 			} else {
2762 				(*stage)++;
2763 				(*step) = 0;
2764 				continue;
2765 			}
2766 		}
2767 		switch (currentcmd->cmdid) {
2768 		case CMDID_SET_TXPOWEROWER_LEVEL:
2769 			rtl92d_phy_set_txpower_level(hw, channel);
2770 			break;
2771 		case CMDID_WRITEPORT_ULONG:
2772 			rtl_write_dword(rtlpriv, currentcmd->para1,
2773 					currentcmd->para2);
2774 			break;
2775 		case CMDID_WRITEPORT_USHORT:
2776 			rtl_write_word(rtlpriv, currentcmd->para1,
2777 				       (u16)currentcmd->para2);
2778 			break;
2779 		case CMDID_WRITEPORT_UCHAR:
2780 			rtl_write_byte(rtlpriv, currentcmd->para1,
2781 				       (u8)currentcmd->para2);
2782 			break;
2783 		case CMDID_RF_WRITEREG:
2784 			for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
2785 				rtlphy->rfreg_chnlval[rfpath] =
2786 					((rtlphy->rfreg_chnlval[rfpath] &
2787 					0xffffff00) | currentcmd->para2);
2788 				if (rtlpriv->rtlhal.current_bandtype ==
2789 				    BAND_ON_5G) {
2790 					if (currentcmd->para2 > 99)
2791 						rtlphy->rfreg_chnlval[rfpath] =
2792 						    rtlphy->rfreg_chnlval
2793 						    [rfpath] | (BIT(18));
2794 					else
2795 						rtlphy->rfreg_chnlval[rfpath] =
2796 						    rtlphy->rfreg_chnlval
2797 						    [rfpath] & (~BIT(18));
2798 					rtlphy->rfreg_chnlval[rfpath] |=
2799 						 (BIT(16) | BIT(8));
2800 				} else {
2801 					rtlphy->rfreg_chnlval[rfpath] &=
2802 						~(BIT(8) | BIT(16) | BIT(18));
2803 				}
2804 				rtl_set_rfreg(hw, (enum radio_path)rfpath,
2805 					      currentcmd->para1,
2806 					      RFREG_OFFSET_MASK,
2807 					      rtlphy->rfreg_chnlval[rfpath]);
2808 				_rtl92d_phy_reload_imr_setting(hw, channel,
2809 							       rfpath);
2810 			}
2811 			_rtl92d_phy_switch_rf_setting(hw, channel);
2812 			/* do IQK when all parameters are ready */
2813 			rtl92d_phy_reload_iqk_setting(hw, channel);
2814 			break;
2815 		default:
2816 			pr_err("switch case %#x not processed\n",
2817 			       currentcmd->cmdid);
2818 			break;
2819 		}
2820 		break;
2821 	} while (true);
2822 	(*delay) = currentcmd->msdelay;
2823 	(*step)++;
2824 	return false;
2825 }
2826 
2827 u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
2828 {
2829 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2830 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2831 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2832 	u32 delay;
2833 	u32 timeout = 1000, timecount = 0;
2834 	u8 channel = rtlphy->current_channel;
2835 	u32 ret_value;
2836 
2837 	if (rtlphy->sw_chnl_inprogress)
2838 		return 0;
2839 	if (rtlphy->set_bwmode_inprogress)
2840 		return 0;
2841 
2842 	if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
2843 		rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
2844 			"sw_chnl_inprogress false driver sleep or unload\n");
2845 		return 0;
2846 	}
2847 	while (rtlphy->lck_inprogress && timecount < timeout) {
2848 		mdelay(50);
2849 		timecount += 50;
2850 	}
2851 	if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
2852 	    rtlhal->bandset == BAND_ON_BOTH) {
2853 		ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
2854 					  MASKDWORD);
2855 		if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
2856 			rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
2857 		else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
2858 			rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G);
2859 	}
2860 	switch (rtlhal->current_bandtype) {
2861 	case BAND_ON_5G:
2862 		/* Get first channel error when change between
2863 		 * 5G and 2.4G band. */
2864 		if (channel <= 14)
2865 			return 0;
2866 		WARN_ONCE((channel <= 14), "rtl8192de: 5G but channel<=14\n");
2867 		break;
2868 	case BAND_ON_2_4G:
2869 		/* Get first channel error when change between
2870 		 * 5G and 2.4G band. */
2871 		if (channel > 14)
2872 			return 0;
2873 		WARN_ONCE((channel > 14), "rtl8192de: 2G but channel>14\n");
2874 		break;
2875 	default:
2876 		WARN_ONCE(true, "rtl8192de: Invalid WirelessMode(%#x)!!\n",
2877 			  rtlpriv->mac80211.mode);
2878 		break;
2879 	}
2880 	rtlphy->sw_chnl_inprogress = true;
2881 	if (channel == 0)
2882 		channel = 1;
2883 	rtlphy->sw_chnl_stage = 0;
2884 	rtlphy->sw_chnl_step = 0;
2885 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
2886 		"switch to channel%d\n", rtlphy->current_channel);
2887 
2888 	do {
2889 		if (!rtlphy->sw_chnl_inprogress)
2890 			break;
2891 		if (!_rtl92d_phy_sw_chnl_step_by_step(hw,
2892 						      rtlphy->current_channel,
2893 		    &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) {
2894 			if (delay > 0)
2895 				mdelay(delay);
2896 			else
2897 				continue;
2898 		} else {
2899 			rtlphy->sw_chnl_inprogress = false;
2900 		}
2901 		break;
2902 	} while (true);
2903 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
2904 	rtlphy->sw_chnl_inprogress = false;
2905 	return 1;
2906 }
2907 
2908 static void rtl92d_phy_set_io(struct ieee80211_hw *hw)
2909 {
2910 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2911 	struct dig_t *de_digtable = &rtlpriv->dm_digtable;
2912 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2913 
2914 	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2915 		"--->Cmd(%#x), set_io_inprogress(%d)\n",
2916 		rtlphy->current_io_type, rtlphy->set_io_inprogress);
2917 	switch (rtlphy->current_io_type) {
2918 	case IO_CMD_RESUME_DM_BY_SCAN:
2919 		de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
2920 		rtl92d_dm_write_dig(hw);
2921 		rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
2922 		break;
2923 	case IO_CMD_PAUSE_DM_BY_SCAN:
2924 		rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue;
2925 		de_digtable->cur_igvalue = 0x37;
2926 		rtl92d_dm_write_dig(hw);
2927 		break;
2928 	default:
2929 		pr_err("switch case %#x not processed\n",
2930 		       rtlphy->current_io_type);
2931 		break;
2932 	}
2933 	rtlphy->set_io_inprogress = false;
2934 	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n",
2935 		rtlphy->current_io_type);
2936 }
2937 
2938 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2939 {
2940 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2941 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2942 	bool postprocessing = false;
2943 
2944 	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2945 		"-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2946 		 iotype, rtlphy->set_io_inprogress);
2947 	do {
2948 		switch (iotype) {
2949 		case IO_CMD_RESUME_DM_BY_SCAN:
2950 			rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2951 				"[IO CMD] Resume DM after scan\n");
2952 			postprocessing = true;
2953 			break;
2954 		case IO_CMD_PAUSE_DM_BY_SCAN:
2955 			rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2956 				"[IO CMD] Pause DM before scan\n");
2957 			postprocessing = true;
2958 			break;
2959 		default:
2960 			pr_err("switch case %#x not processed\n",
2961 			       iotype);
2962 			break;
2963 		}
2964 	} while (false);
2965 	if (postprocessing && !rtlphy->set_io_inprogress) {
2966 		rtlphy->set_io_inprogress = true;
2967 		rtlphy->current_io_type = iotype;
2968 	} else {
2969 		return false;
2970 	}
2971 	rtl92d_phy_set_io(hw);
2972 	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
2973 	return true;
2974 }
2975 
2976 static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw)
2977 {
2978 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2979 
2980 	/* a.  SYS_CLKR 0x08[11] = 1  restore MAC clock */
2981 	/* b.  SPS_CTRL 0x11[7:0] = 0x2b */
2982 	if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
2983 		rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
2984 	/* c.  For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */
2985 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2986 	/* RF_ON_EXCEP(d~g): */
2987 	/* d.  APSD_CTRL 0x600[7:0] = 0x00 */
2988 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2989 	/* e.  SYS_FUNC_EN 0x02[7:0] = 0xE2  reset BB TRX function again */
2990 	/* f.  SYS_FUNC_EN 0x02[7:0] = 0xE3  enable BB TRX function*/
2991 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2992 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2993 	/* g.   txpause 0x522[7:0] = 0x00  enable mac tx queue */
2994 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2995 }
2996 
2997 static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
2998 {
2999 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3000 	u32 u4btmp;
3001 	u8 delay = 5;
3002 
3003 	/* a.   TXPAUSE 0x522[7:0] = 0xFF  Pause MAC TX queue  */
3004 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3005 	/* b.   RF path 0 offset 0x00 = 0x00  disable RF  */
3006 	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3007 	/* c.   APSD_CTRL 0x600[7:0] = 0x40 */
3008 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3009 	/* d. APSD_CTRL 0x600[7:0] = 0x00
3010 	 * APSD_CTRL 0x600[7:0] = 0x00
3011 	 * RF path 0 offset 0x00 = 0x00
3012 	 * APSD_CTRL 0x600[7:0] = 0x40
3013 	 * */
3014 	u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3015 	while (u4btmp != 0 && delay > 0) {
3016 		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
3017 		rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3018 		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3019 		u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3020 		delay--;
3021 	}
3022 	if (delay == 0) {
3023 		/* Jump out the LPS turn off sequence to RF_ON_EXCEP */
3024 		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3025 
3026 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3027 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3028 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3029 		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
3030 			"Fail !!! Switch RF timeout\n");
3031 		return;
3032 	}
3033 	/* e.   For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */
3034 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3035 	/* f.   SPS_CTRL 0x11[7:0] = 0x22 */
3036 	if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3037 		rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3038 	/* g.    SYS_CLKR 0x08[11] = 0  gated MAC clock */
3039 }
3040 
3041 bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
3042 				   enum rf_pwrstate rfpwr_state)
3043 {
3044 
3045 	bool bresult = true;
3046 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3047 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3048 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3049 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3050 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3051 	u8 i, queue_id;
3052 	struct rtl8192_tx_ring *ring = NULL;
3053 
3054 	if (rfpwr_state == ppsc->rfpwr_state)
3055 		return false;
3056 	switch (rfpwr_state) {
3057 	case ERFON:
3058 		if ((ppsc->rfpwr_state == ERFOFF) &&
3059 		    RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3060 			bool rtstatus;
3061 			u32 initializecount = 0;
3062 			do {
3063 				initializecount++;
3064 				rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3065 					"IPS Set eRf nic enable\n");
3066 				rtstatus = rtl_ps_enable_nic(hw);
3067 			} while (!rtstatus && (initializecount < 10));
3068 
3069 			RT_CLEAR_PS_LEVEL(ppsc,
3070 					  RT_RF_OFF_LEVL_HALT_NIC);
3071 		} else {
3072 			rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
3073 				"awake, slept:%d ms state_inap:%x\n",
3074 				jiffies_to_msecs(jiffies -
3075 						 ppsc->last_sleep_jiffies),
3076 				 rtlpriv->psc.state_inap);
3077 			ppsc->last_awake_jiffies = jiffies;
3078 			_rtl92d_phy_set_rfon(hw);
3079 		}
3080 
3081 		if (mac->link_state == MAC80211_LINKED)
3082 			rtlpriv->cfg->ops->led_control(hw,
3083 					 LED_CTL_LINK);
3084 		else
3085 			rtlpriv->cfg->ops->led_control(hw,
3086 					 LED_CTL_NO_LINK);
3087 		break;
3088 	case ERFOFF:
3089 		if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3090 			rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3091 				"IPS Set eRf nic disable\n");
3092 			rtl_ps_disable_nic(hw);
3093 			RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3094 		} else {
3095 			if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
3096 				rtlpriv->cfg->ops->led_control(hw,
3097 						 LED_CTL_NO_LINK);
3098 			else
3099 				rtlpriv->cfg->ops->led_control(hw,
3100 						 LED_CTL_POWER_OFF);
3101 		}
3102 		break;
3103 	case ERFSLEEP:
3104 		if (ppsc->rfpwr_state == ERFOFF)
3105 			return false;
3106 
3107 		for (queue_id = 0, i = 0;
3108 		     queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3109 			ring = &pcipriv->dev.tx_ring[queue_id];
3110 			if (skb_queue_len(&ring->queue) == 0 ||
3111 			    queue_id == BEACON_QUEUE) {
3112 				queue_id++;
3113 				continue;
3114 			} else if (rtlpci->pdev->current_state != PCI_D0) {
3115 				rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
3116 					"eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n",
3117 					i + 1, queue_id);
3118 				break;
3119 			} else {
3120 				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3121 					"eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3122 					i + 1, queue_id,
3123 					skb_queue_len(&ring->queue));
3124 				udelay(10);
3125 				i++;
3126 			}
3127 
3128 			if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3129 				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3130 					"ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
3131 					MAX_DOZE_WAITING_TIMES_9x, queue_id,
3132 					skb_queue_len(&ring->queue));
3133 				break;
3134 			}
3135 		}
3136 		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
3137 			"Set rfsleep awakened:%d ms\n",
3138 			 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
3139 		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
3140 			"sleep awakened:%d ms state_inap:%x\n",
3141 			jiffies_to_msecs(jiffies -
3142 					 ppsc->last_awake_jiffies),
3143 			rtlpriv->psc.state_inap);
3144 		ppsc->last_sleep_jiffies = jiffies;
3145 		_rtl92d_phy_set_rfsleep(hw);
3146 		break;
3147 	default:
3148 		pr_err("switch case %#x not processed\n",
3149 		       rfpwr_state);
3150 		bresult = false;
3151 		break;
3152 	}
3153 	if (bresult)
3154 		ppsc->rfpwr_state = rfpwr_state;
3155 	return bresult;
3156 }
3157 
3158 void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw)
3159 {
3160 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3161 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3162 	u8 offset = REG_MAC_PHY_CTRL_NORMAL;
3163 
3164 	switch (rtlhal->macphymode) {
3165 	case DUALMAC_DUALPHY:
3166 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3167 			"MacPhyMode: DUALMAC_DUALPHY\n");
3168 		rtl_write_byte(rtlpriv, offset, 0xF3);
3169 		break;
3170 	case SINGLEMAC_SINGLEPHY:
3171 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3172 			"MacPhyMode: SINGLEMAC_SINGLEPHY\n");
3173 		rtl_write_byte(rtlpriv, offset, 0xF4);
3174 		break;
3175 	case DUALMAC_SINGLEPHY:
3176 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3177 			"MacPhyMode: DUALMAC_SINGLEPHY\n");
3178 		rtl_write_byte(rtlpriv, offset, 0xF1);
3179 		break;
3180 	}
3181 }
3182 
3183 void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw)
3184 {
3185 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3186 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3187 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
3188 
3189 	switch (rtlhal->macphymode) {
3190 	case DUALMAC_SINGLEPHY:
3191 		rtlphy->rf_type = RF_2T2R;
3192 		rtlhal->version |= RF_TYPE_2T2R;
3193 		rtlhal->bandset = BAND_ON_BOTH;
3194 		rtlhal->current_bandtype = BAND_ON_2_4G;
3195 		break;
3196 
3197 	case SINGLEMAC_SINGLEPHY:
3198 		rtlphy->rf_type = RF_2T2R;
3199 		rtlhal->version |= RF_TYPE_2T2R;
3200 		rtlhal->bandset = BAND_ON_BOTH;
3201 		rtlhal->current_bandtype = BAND_ON_2_4G;
3202 		break;
3203 
3204 	case DUALMAC_DUALPHY:
3205 		rtlphy->rf_type = RF_1T1R;
3206 		rtlhal->version &= RF_TYPE_1T1R;
3207 		/* Now we let MAC0 run on 5G band. */
3208 		if (rtlhal->interfaceindex == 0) {
3209 			rtlhal->bandset = BAND_ON_5G;
3210 			rtlhal->current_bandtype = BAND_ON_5G;
3211 		} else {
3212 			rtlhal->bandset = BAND_ON_2_4G;
3213 			rtlhal->current_bandtype = BAND_ON_2_4G;
3214 		}
3215 		break;
3216 	default:
3217 		break;
3218 	}
3219 }
3220 
3221 u8 rtl92d_get_chnlgroup_fromarray(u8 chnl)
3222 {
3223 	u8 group;
3224 
3225 	if (channel_all[chnl] <= 3)
3226 		group = 0;
3227 	else if (channel_all[chnl] <= 9)
3228 		group = 1;
3229 	else if (channel_all[chnl] <= 14)
3230 		group = 2;
3231 	else if (channel_all[chnl] <= 44)
3232 		group = 3;
3233 	else if (channel_all[chnl] <= 54)
3234 		group = 4;
3235 	else if (channel_all[chnl] <= 64)
3236 		group = 5;
3237 	else if (channel_all[chnl] <= 112)
3238 		group = 6;
3239 	else if (channel_all[chnl] <= 126)
3240 		group = 7;
3241 	else if (channel_all[chnl] <= 140)
3242 		group = 8;
3243 	else if (channel_all[chnl] <= 153)
3244 		group = 9;
3245 	else if (channel_all[chnl] <= 159)
3246 		group = 10;
3247 	else
3248 		group = 11;
3249 	return group;
3250 }
3251 
3252 void rtl92d_phy_set_poweron(struct ieee80211_hw *hw)
3253 {
3254 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3255 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3256 	unsigned long flags;
3257 	u8 value8;
3258 	u16 i;
3259 	u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
3260 
3261 	/* notice fw know band status  0x81[1]/0x53[1] = 0: 5G, 1: 2G */
3262 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3263 		value8 = rtl_read_byte(rtlpriv, mac_reg);
3264 		value8 |= BIT(1);
3265 		rtl_write_byte(rtlpriv, mac_reg, value8);
3266 	} else {
3267 		value8 = rtl_read_byte(rtlpriv, mac_reg);
3268 		value8 &= (~BIT(1));
3269 		rtl_write_byte(rtlpriv, mac_reg, value8);
3270 	}
3271 
3272 	if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3273 		value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3274 		rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3275 	} else {
3276 		spin_lock_irqsave(&globalmutex_power, flags);
3277 		if (rtlhal->interfaceindex == 0) {
3278 			value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3279 			rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3280 		} else {
3281 			value8 = rtl_read_byte(rtlpriv, REG_MAC1);
3282 			rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON);
3283 		}
3284 		value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3285 		spin_unlock_irqrestore(&globalmutex_power, flags);
3286 		for (i = 0; i < 200; i++) {
3287 			if ((value8 & BIT(7)) == 0) {
3288 				break;
3289 			} else {
3290 				udelay(500);
3291 				spin_lock_irqsave(&globalmutex_power, flags);
3292 				value8 = rtl_read_byte(rtlpriv,
3293 						    REG_POWER_OFF_IN_PROCESS);
3294 				spin_unlock_irqrestore(&globalmutex_power,
3295 						       flags);
3296 			}
3297 		}
3298 		if (i == 200)
3299 			WARN_ONCE(true, "rtl8192de: Another mac power off over time\n");
3300 	}
3301 }
3302 
3303 void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw)
3304 {
3305 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3306 
3307 	switch (rtlpriv->rtlhal.macphymode) {
3308 	case DUALMAC_DUALPHY:
3309 		rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3310 		rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3311 		rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3312 		break;
3313 	case DUALMAC_SINGLEPHY:
3314 		rtl_write_byte(rtlpriv, REG_DMC, 0xf8);
3315 		rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3316 		rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3317 		break;
3318 	case SINGLEMAC_SINGLEPHY:
3319 		rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3320 		rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10);
3321 		rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
3322 		break;
3323 	default:
3324 		break;
3325 	}
3326 }
3327 
3328 void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3329 {
3330 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3331 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3332 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
3333 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3334 	u8 rfpath, i;
3335 
3336 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
3337 	/* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */
3338 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3339 		/* r_select_5G for path_A/B,0x878 */
3340 		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0);
3341 		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0);
3342 		if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3343 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0);
3344 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0);
3345 		}
3346 		/* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */
3347 		rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
3348 		/* fc_area  0xd2c */
3349 		rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
3350 		/* 5G LAN ON */
3351 		rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3352 		/* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3353 		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3354 			      0x40000100);
3355 		rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3356 			      0x40000100);
3357 		if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3358 			rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3359 				      BIT(10) | BIT(6) | BIT(5),
3360 				      ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3361 				      (rtlefuse->eeprom_c9 & BIT(1)) |
3362 				      ((rtlefuse->eeprom_cc & BIT(1)) << 4));
3363 			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3364 				      BIT(10) | BIT(6) | BIT(5),
3365 				      ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3366 				      ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3367 				      ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3368 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0);
3369 		} else {
3370 			rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3371 				      BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3372 				      BIT(6) | BIT(5),
3373 				      ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3374 				      (rtlefuse->eeprom_c9 & BIT(1)) |
3375 				      ((rtlefuse->eeprom_cc & BIT(1)) << 4) |
3376 				      ((rtlefuse->eeprom_c9 & BIT(7)) << 9) |
3377 				      ((rtlefuse->eeprom_c9 & BIT(5)) << 12) |
3378 				      ((rtlefuse->eeprom_cc & BIT(3)) << 18));
3379 			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3380 				      BIT(10) | BIT(6) | BIT(5),
3381 				      ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3382 				      ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3383 				      ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3384 			rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
3385 				      BIT(10) | BIT(6) | BIT(5),
3386 				      ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) |
3387 				      ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) |
3388 				      ((rtlefuse->eeprom_cc & BIT(2)) << 3));
3389 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3390 				      BIT(31) | BIT(15), 0);
3391 		}
3392 		/* 1.5V_LDO */
3393 	} else {
3394 		/* r_select_5G for path_A/B */
3395 		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1);
3396 		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1);
3397 		if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3398 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1);
3399 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1);
3400 		}
3401 		/* rssi_table_select:index 0 for 2.4G.1~3 for 5G */
3402 		rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
3403 		/* fc_area */
3404 		rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
3405 		/* 5G LAN ON */
3406 		rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3407 		/* TX BB gain shift,Just for testchip,0xc80,0xc88 */
3408 		if (rtlefuse->internal_pa_5g[0])
3409 			rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3410 				      0x2d4000b5);
3411 		else
3412 			rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3413 				      0x20000080);
3414 		if (rtlefuse->internal_pa_5g[1])
3415 			rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3416 				      0x2d4000b5);
3417 		else
3418 			rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3419 				      0x20000080);
3420 		if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3421 			rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3422 				      BIT(10) | BIT(6) | BIT(5),
3423 				      (rtlefuse->eeprom_cc & BIT(5)));
3424 			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3425 				      ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3426 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15),
3427 				      (rtlefuse->eeprom_cc & BIT(4)) >> 4);
3428 		} else {
3429 			rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3430 				      BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3431 				      BIT(6) | BIT(5),
3432 				      (rtlefuse->eeprom_cc & BIT(5)) |
3433 				      ((rtlefuse->eeprom_cc & BIT(7)) << 14));
3434 			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3435 				      ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3436 			rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10),
3437 				      ((rtlefuse->eeprom_cc & BIT(6)) >> 6));
3438 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3439 				      BIT(31) | BIT(15),
3440 				      ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
3441 				      ((rtlefuse->eeprom_cc & BIT(6)) << 10));
3442 		}
3443 	}
3444 	/* update IQK related settings */
3445 	rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
3446 	rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
3447 	rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00);
3448 	rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3449 		      BIT(26) | BIT(24), 0x00);
3450 	rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00);
3451 	rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
3452 	rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
3453 
3454 	/* Update RF */
3455 	for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3456 	     rfpath++) {
3457 		if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3458 			/* MOD_AG for RF path_A 0x18 BIT8,BIT16 */
3459 			rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) |
3460 				      BIT(18), 0);
3461 			/* RF0x0b[16:14] =3b'111 */
3462 			rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
3463 				      0x1c000, 0x07);
3464 		} else {
3465 			/* MOD_AG for RF path_A 0x18 BIT8,BIT16 */
3466 			rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) |
3467 				      BIT(16) | BIT(18),
3468 				      (BIT(16) | BIT(8)) >> 8);
3469 		}
3470 	}
3471 	/* Update for all band. */
3472 	/* DMDP */
3473 	if (rtlphy->rf_type == RF_1T1R) {
3474 		/* Use antenna 0,0xc04,0xd04 */
3475 		rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11);
3476 		rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
3477 
3478 		/* enable ad/da clock1 for dual-phy reg0x888 */
3479 		if (rtlhal->interfaceindex == 0) {
3480 			rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) |
3481 				      BIT(13), 0x3);
3482 		} else {
3483 			rtl92d_phy_enable_anotherphy(hw, false);
3484 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3485 				"MAC1 use DBI to update 0x888\n");
3486 			/* 0x888 */
3487 			rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN,
3488 						rtl92de_read_dword_dbi(hw,
3489 						RFPGA0_ADDALLOCKEN,
3490 						BIT(3)) | BIT(12) | BIT(13),
3491 						BIT(3));
3492 			rtl92d_phy_powerdown_anotherphy(hw, false);
3493 		}
3494 	} else {
3495 		/* Single PHY */
3496 		/* Use antenna 0 & 1,0xc04,0xd04 */
3497 		rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33);
3498 		rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
3499 		/* disable ad/da clock1,0x888 */
3500 		rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
3501 	}
3502 	for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3503 	     rfpath++) {
3504 		rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
3505 						RF_CHNLBW, RFREG_OFFSET_MASK);
3506 		rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
3507 			RFREG_OFFSET_MASK);
3508 	}
3509 	for (i = 0; i < 2; i++)
3510 		rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n",
3511 			rtlphy->rfreg_chnlval[i]);
3512 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n");
3513 
3514 }
3515 
3516 bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw)
3517 {
3518 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3519 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3520 	u8 u1btmp;
3521 	unsigned long flags;
3522 
3523 	if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3524 		u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3525 		rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3526 		return true;
3527 	}
3528 	spin_lock_irqsave(&globalmutex_power, flags);
3529 	if (rtlhal->interfaceindex == 0) {
3530 		u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3531 		rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3532 		u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3533 		u1btmp &= MAC1_ON;
3534 	} else {
3535 		u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3536 		rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON));
3537 		u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3538 		u1btmp &= MAC0_ON;
3539 	}
3540 	if (u1btmp) {
3541 		spin_unlock_irqrestore(&globalmutex_power, flags);
3542 		return false;
3543 	}
3544 	u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3545 	u1btmp |= BIT(7);
3546 	rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp);
3547 	spin_unlock_irqrestore(&globalmutex_power, flags);
3548 	return true;
3549 }
3550