1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../pci.h"
6 #include "../ps.h"
7 #include "../core.h"
8 #include "reg.h"
9 #include "def.h"
10 #include "phy.h"
11 #include "rf.h"
12 #include "dm.h"
13 #include "table.h"
14 #include "sw.h"
15 #include "hw.h"
16 
17 #define MAX_RF_IMR_INDEX			12
18 #define MAX_RF_IMR_INDEX_NORMAL			13
19 #define RF_REG_NUM_FOR_C_CUT_5G			6
20 #define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA	7
21 #define RF_REG_NUM_FOR_C_CUT_2G			5
22 #define RF_CHNL_NUM_5G				19
23 #define RF_CHNL_NUM_5G_40M			17
24 #define TARGET_CHNL_NUM_5G			221
25 #define TARGET_CHNL_NUM_2G			14
26 #define CV_CURVE_CNT				64
27 
28 static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = {
29 	0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
30 };
31 
32 static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = {
33 	RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6
34 };
35 
36 static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
37 	RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8
38 };
39 
40 static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
41 	0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
42 };
43 
44 static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
45 	BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1),
46 	BIT(10) | BIT(9),
47 	BIT(18) | BIT(17) | BIT(16) | BIT(1),
48 	BIT(2) | BIT(1),
49 	BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11)
50 };
51 
52 static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = {
53 	36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108,
54 	112, 116, 120, 124, 128, 132, 136, 140
55 };
56 
57 static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = {
58 	38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114,
59 	118, 122, 126, 130, 134, 138
60 };
61 static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = {
62 	{0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
63 	{0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
64 	{0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
65 	{0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
66 	{0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
67 };
68 
69 static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = {
70 	{0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
71 	{0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
72 	{0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
73 };
74 
75 static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
76 
77 static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
78 	{0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
79 	{0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
80 	{0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
81 };
82 
83 /* [mode][patha+b][reg] */
84 static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = {
85 	{
86 		/* channel 1-14. */
87 		{
88 			0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
89 			0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
90 		},
91 		/* path 36-64 */
92 		{
93 			0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
94 			0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
95 			0x32c9a
96 		},
97 		/* 100 -165 */
98 		{
99 			0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
100 			0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
101 		}
102 	}
103 };
104 
105 static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
106 
107 static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
108 
109 static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = {
110 	25141, 25116, 25091, 25066, 25041,
111 	25016, 24991, 24966, 24941, 24917,
112 	24892, 24867, 24843, 24818, 24794,
113 	24770, 24765, 24721, 24697, 24672,
114 	24648, 24624, 24600, 24576, 24552,
115 	24528, 24504, 24480, 24457, 24433,
116 	24409, 24385, 24362, 24338, 24315,
117 	24291, 24268, 24245, 24221, 24198,
118 	24175, 24151, 24128, 24105, 24082,
119 	24059, 24036, 24013, 23990, 23967,
120 	23945, 23922, 23899, 23876, 23854,
121 	23831, 23809, 23786, 23764, 23741,
122 	23719, 23697, 23674, 23652, 23630,
123 	23608, 23586, 23564, 23541, 23519,
124 	23498, 23476, 23454, 23432, 23410,
125 	23388, 23367, 23345, 23323, 23302,
126 	23280, 23259, 23237, 23216, 23194,
127 	23173, 23152, 23130, 23109, 23088,
128 	23067, 23046, 23025, 23003, 22982,
129 	22962, 22941, 22920, 22899, 22878,
130 	22857, 22837, 22816, 22795, 22775,
131 	22754, 22733, 22713, 22692, 22672,
132 	22652, 22631, 22611, 22591, 22570,
133 	22550, 22530, 22510, 22490, 22469,
134 	22449, 22429, 22409, 22390, 22370,
135 	22350, 22336, 22310, 22290, 22271,
136 	22251, 22231, 22212, 22192, 22173,
137 	22153, 22134, 22114, 22095, 22075,
138 	22056, 22037, 22017, 21998, 21979,
139 	21960, 21941, 21921, 21902, 21883,
140 	21864, 21845, 21826, 21807, 21789,
141 	21770, 21751, 21732, 21713, 21695,
142 	21676, 21657, 21639, 21620, 21602,
143 	21583, 21565, 21546, 21528, 21509,
144 	21491, 21473, 21454, 21436, 21418,
145 	21400, 21381, 21363, 21345, 21327,
146 	21309, 21291, 21273, 21255, 21237,
147 	21219, 21201, 21183, 21166, 21148,
148 	21130, 21112, 21095, 21077, 21059,
149 	21042, 21024, 21007, 20989, 20972,
150 	25679, 25653, 25627, 25601, 25575,
151 	25549, 25523, 25497, 25471, 25446,
152 	25420, 25394, 25369, 25343, 25318,
153 	25292, 25267, 25242, 25216, 25191,
154 	25166
155 };
156 
157 /* channel 1~14 */
158 static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = {
159 	26084, 26030, 25976, 25923, 25869, 25816, 25764,
160 	25711, 25658, 25606, 25554, 25502, 25451, 25328
161 };
162 
163 static const u8 channel_all[59] = {
164 	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
165 	36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
166 	60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
167 	114, 116, 118, 120, 122, 124, 126, 128,	130,
168 	132, 134, 136, 138, 140, 149, 151, 153, 155,
169 	157, 159, 161, 163, 165
170 };
171 
172 u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
173 {
174 	struct rtl_priv *rtlpriv = rtl_priv(hw);
175 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
176 	u32 returnvalue, originalvalue, bitshift;
177 
178 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
179 		regaddr, bitmask);
180 	if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) {
181 		u8 dbi_direct = 0;
182 
183 		/* mac1 use phy0 read radio_b. */
184 		/* mac0 use phy1 read radio_b. */
185 		if (rtlhal->during_mac1init_radioa)
186 			dbi_direct = BIT(3);
187 		else if (rtlhal->during_mac0init_radiob)
188 			dbi_direct = BIT(3) | BIT(2);
189 		originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr,
190 			dbi_direct);
191 	} else {
192 		originalvalue = rtl_read_dword(rtlpriv, regaddr);
193 	}
194 	bitshift = calculate_bit_shift(bitmask);
195 	returnvalue = (originalvalue & bitmask) >> bitshift;
196 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
197 		"BBR MASK=0x%x Addr[0x%x]=0x%x\n",
198 		bitmask, regaddr, originalvalue);
199 	return returnvalue;
200 }
201 
202 void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
203 			   u32 regaddr, u32 bitmask, u32 data)
204 {
205 	struct rtl_priv *rtlpriv = rtl_priv(hw);
206 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
207 	u8 dbi_direct = 0;
208 	u32 originalvalue, bitshift;
209 
210 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
211 		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
212 		regaddr, bitmask, data);
213 	if (rtlhal->during_mac1init_radioa)
214 		dbi_direct = BIT(3);
215 	else if (rtlhal->during_mac0init_radiob)
216 		/* mac0 use phy1 write radio_b. */
217 		dbi_direct = BIT(3) | BIT(2);
218 	if (bitmask != MASKDWORD) {
219 		if (rtlhal->during_mac1init_radioa ||
220 		    rtlhal->during_mac0init_radiob)
221 			originalvalue = rtl92de_read_dword_dbi(hw,
222 					(u16) regaddr,
223 					dbi_direct);
224 		else
225 			originalvalue = rtl_read_dword(rtlpriv, regaddr);
226 		bitshift = calculate_bit_shift(bitmask);
227 		data = ((originalvalue & (~bitmask)) | (data << bitshift));
228 	}
229 	if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob)
230 		rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct);
231 	else
232 		rtl_write_dword(rtlpriv, regaddr, data);
233 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
234 		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
235 		regaddr, bitmask, data);
236 }
237 
238 static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
239 				      enum radio_path rfpath, u32 offset)
240 {
241 
242 	struct rtl_priv *rtlpriv = rtl_priv(hw);
243 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
244 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
245 	u32 newoffset;
246 	u32 tmplong, tmplong2;
247 	u8 rfpi_enable = 0;
248 	u32 retvalue;
249 
250 	newoffset = offset;
251 	tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
252 	if (rfpath == RF90_PATH_A)
253 		tmplong2 = tmplong;
254 	else
255 		tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
256 	tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
257 		(newoffset << 23) | BLSSIREADEDGE;
258 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
259 		tmplong & (~BLSSIREADEDGE));
260 	udelay(10);
261 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
262 	udelay(50);
263 	udelay(50);
264 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
265 		tmplong | BLSSIREADEDGE);
266 	udelay(10);
267 	if (rfpath == RF90_PATH_A)
268 		rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
269 			      BIT(8));
270 	else if (rfpath == RF90_PATH_B)
271 		rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
272 			      BIT(8));
273 	if (rfpi_enable)
274 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
275 			BLSSIREADBACKDATA);
276 	else
277 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
278 			BLSSIREADBACKDATA);
279 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n",
280 		rfpath, pphyreg->rf_rb, retvalue);
281 	return retvalue;
282 }
283 
284 static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
285 					enum radio_path rfpath,
286 					u32 offset, u32 data)
287 {
288 	u32 data_and_addr;
289 	u32 newoffset;
290 	struct rtl_priv *rtlpriv = rtl_priv(hw);
291 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
292 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
293 
294 	newoffset = offset;
295 	/* T65 RF */
296 	data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
297 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
298 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
299 		rfpath, pphyreg->rf3wire_offset, data_and_addr);
300 }
301 
302 u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
303 			    enum radio_path rfpath, u32 regaddr, u32 bitmask)
304 {
305 	struct rtl_priv *rtlpriv = rtl_priv(hw);
306 	u32 original_value, readback_value, bitshift;
307 
308 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
309 		"regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
310 		regaddr, rfpath, bitmask);
311 	spin_lock(&rtlpriv->locks.rf_lock);
312 	original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);
313 	bitshift = calculate_bit_shift(bitmask);
314 	readback_value = (original_value & bitmask) >> bitshift;
315 	spin_unlock(&rtlpriv->locks.rf_lock);
316 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
317 		"regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
318 		regaddr, rfpath, bitmask, original_value);
319 	return readback_value;
320 }
321 
322 void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
323 	u32 regaddr, u32 bitmask, u32 data)
324 {
325 	struct rtl_priv *rtlpriv = rtl_priv(hw);
326 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
327 	u32 original_value, bitshift;
328 
329 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
330 		"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
331 		regaddr, bitmask, data, rfpath);
332 	if (bitmask == 0)
333 		return;
334 	spin_lock(&rtlpriv->locks.rf_lock);
335 	if (rtlphy->rf_mode != RF_OP_BY_FW) {
336 		if (bitmask != RFREG_OFFSET_MASK) {
337 			original_value = _rtl92d_phy_rf_serial_read(hw,
338 				rfpath, regaddr);
339 			bitshift = calculate_bit_shift(bitmask);
340 			data = ((original_value & (~bitmask)) |
341 				(data << bitshift));
342 		}
343 		_rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);
344 	}
345 	spin_unlock(&rtlpriv->locks.rf_lock);
346 	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
347 		"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
348 		regaddr, bitmask, data, rfpath);
349 }
350 
351 bool rtl92d_phy_mac_config(struct ieee80211_hw *hw)
352 {
353 	struct rtl_priv *rtlpriv = rtl_priv(hw);
354 	u32 i;
355 	u32 arraylength;
356 	u32 *ptrarray;
357 
358 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
359 	arraylength = MAC_2T_ARRAYLENGTH;
360 	ptrarray = rtl8192de_mac_2tarray;
361 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n");
362 	for (i = 0; i < arraylength; i = i + 2)
363 		rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
364 	if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
365 		/* improve 2-stream TX EVM */
366 		/* rtl_write_byte(rtlpriv, 0x14,0x71); */
367 		/* AMPDU aggregation number 9 */
368 		/* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */
369 		rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B);
370 	} else {
371 		/* 92D need to test to decide the num. */
372 		rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07);
373 	}
374 	return true;
375 }
376 
377 static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
378 {
379 	struct rtl_priv *rtlpriv = rtl_priv(hw);
380 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
381 
382 	/* RF Interface Sowrtware Control */
383 	/* 16 LSBs if read 32-bit from 0x870 */
384 	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
385 	/* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
386 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
387 	/* 16 LSBs if read 32-bit from 0x874 */
388 	rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
389 	/* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
390 
391 	rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
392 	/* RF Interface Readback Value */
393 	/* 16 LSBs if read 32-bit from 0x8E0 */
394 	rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
395 	/* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
396 	rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
397 	/* 16 LSBs if read 32-bit from 0x8E4 */
398 	rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
399 	/* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
400 	rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
401 
402 	/* RF Interface Output (and Enable) */
403 	/* 16 LSBs if read 32-bit from 0x860 */
404 	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
405 	/* 16 LSBs if read 32-bit from 0x864 */
406 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
407 
408 	/* RF Interface (Output and)  Enable */
409 	/* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
410 	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
411 	/* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
412 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
413 
414 	/* Addr of LSSI. Wirte RF register by driver */
415 	/* LSSI Parameter */
416 	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
417 				 RFPGA0_XA_LSSIPARAMETER;
418 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
419 				 RFPGA0_XB_LSSIPARAMETER;
420 
421 	/* RF parameter */
422 	/* BB Band Select */
423 	rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
424 	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
425 	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
426 	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
427 
428 	/* Tx AGC Gain Stage (same for all path. Should we remove this?) */
429 	/* Tx gain stage */
430 	rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
431 	/* Tx gain stage */
432 	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
433 	/* Tx gain stage */
434 	rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
435 	/* Tx gain stage */
436 	rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
437 
438 	/* Tranceiver A~D HSSI Parameter-1 */
439 	/* wire control parameter1 */
440 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
441 	/* wire control parameter1 */
442 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
443 
444 	/* Tranceiver A~D HSSI Parameter-2 */
445 	/* wire control parameter2 */
446 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
447 	/* wire control parameter2 */
448 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
449 
450 	/* RF switch Control */
451 	/* TR/Ant switch control */
452 	rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
453 	rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
454 	rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
455 	rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
456 
457 	/* AGC control 1 */
458 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
459 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
460 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
461 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
462 
463 	/* AGC control 2  */
464 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
465 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
466 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
467 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
468 
469 	/* RX AFE control 1 */
470 	rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
471 	rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
472 	rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
473 	rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
474 
475 	/*RX AFE control 1 */
476 	rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
477 	rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
478 	rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
479 	rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
480 
481 	/* Tx AFE control 1 */
482 	rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
483 	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
484 	rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
485 	rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
486 
487 	/* Tx AFE control 2 */
488 	rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
489 	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
490 	rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
491 	rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
492 
493 	/* Tranceiver LSSI Readback SI mode */
494 	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
495 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
496 	rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
497 	rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
498 
499 	/* Tranceiver LSSI Readback PI mode */
500 	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
501 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
502 }
503 
504 static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
505 	u8 configtype)
506 {
507 	int i;
508 	u32 *phy_regarray_table;
509 	u32 *agctab_array_table = NULL;
510 	u32 *agctab_5garray_table;
511 	u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen;
512 	struct rtl_priv *rtlpriv = rtl_priv(hw);
513 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
514 
515 	/* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */
516 	if (rtlhal->interfaceindex == 0) {
517 		agctab_arraylen = AGCTAB_ARRAYLENGTH;
518 		agctab_array_table = rtl8192de_agctab_array;
519 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
520 			" ===> phy:MAC0, Rtl819XAGCTAB_Array\n");
521 	} else {
522 		if (rtlhal->current_bandtype == BAND_ON_2_4G) {
523 			agctab_arraylen = AGCTAB_2G_ARRAYLENGTH;
524 			agctab_array_table = rtl8192de_agctab_2garray;
525 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
526 				" ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n");
527 		} else {
528 			agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH;
529 			agctab_5garray_table = rtl8192de_agctab_5garray;
530 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
531 				" ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n");
532 
533 		}
534 	}
535 	phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH;
536 	phy_regarray_table = rtl8192de_phy_reg_2tarray;
537 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
538 		" ===> phy:Rtl819XPHY_REG_Array_PG\n");
539 	if (configtype == BASEBAND_CONFIG_PHY_REG) {
540 		for (i = 0; i < phy_reg_arraylen; i = i + 2) {
541 			rtl_addr_delay(phy_regarray_table[i]);
542 			rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
543 				      phy_regarray_table[i + 1]);
544 			udelay(1);
545 			rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
546 				"The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
547 				phy_regarray_table[i],
548 				phy_regarray_table[i + 1]);
549 		}
550 	} else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
551 		if (rtlhal->interfaceindex == 0) {
552 			for (i = 0; i < agctab_arraylen; i = i + 2) {
553 				rtl_set_bbreg(hw, agctab_array_table[i],
554 					MASKDWORD,
555 					agctab_array_table[i + 1]);
556 				/* Add 1us delay between BB/RF register
557 				 * setting. */
558 				udelay(1);
559 				rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
560 					"The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
561 					agctab_array_table[i],
562 					agctab_array_table[i + 1]);
563 			}
564 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
565 				"Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n");
566 		} else {
567 			if (rtlhal->current_bandtype == BAND_ON_2_4G) {
568 				for (i = 0; i < agctab_arraylen; i = i + 2) {
569 					rtl_set_bbreg(hw, agctab_array_table[i],
570 						MASKDWORD,
571 						agctab_array_table[i + 1]);
572 					/* Add 1us delay between BB/RF register
573 					 * setting. */
574 					udelay(1);
575 					rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
576 						"The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
577 						agctab_array_table[i],
578 						agctab_array_table[i + 1]);
579 				}
580 				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
581 					"Load Rtl819XAGCTAB_2GArray\n");
582 			} else {
583 				for (i = 0; i < agctab_5garraylen; i = i + 2) {
584 					rtl_set_bbreg(hw,
585 						agctab_5garray_table[i],
586 						MASKDWORD,
587 						agctab_5garray_table[i + 1]);
588 					/* Add 1us delay between BB/RF registeri
589 					 * setting. */
590 					udelay(1);
591 					rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
592 						"The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
593 						agctab_5garray_table[i],
594 						agctab_5garray_table[i + 1]);
595 				}
596 				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
597 					"Load Rtl819XAGCTAB_5GArray\n");
598 			}
599 		}
600 	}
601 	return true;
602 }
603 
604 static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
605 						   u32 regaddr, u32 bitmask,
606 						   u32 data)
607 {
608 	struct rtl_priv *rtlpriv = rtl_priv(hw);
609 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
610 	int index;
611 
612 	if (regaddr == RTXAGC_A_RATE18_06)
613 		index = 0;
614 	else if (regaddr == RTXAGC_A_RATE54_24)
615 		index = 1;
616 	else if (regaddr == RTXAGC_A_CCK1_MCS32)
617 		index = 6;
618 	else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
619 		index = 7;
620 	else if (regaddr == RTXAGC_A_MCS03_MCS00)
621 		index = 2;
622 	else if (regaddr == RTXAGC_A_MCS07_MCS04)
623 		index = 3;
624 	else if (regaddr == RTXAGC_A_MCS11_MCS08)
625 		index = 4;
626 	else if (regaddr == RTXAGC_A_MCS15_MCS12)
627 		index = 5;
628 	else if (regaddr == RTXAGC_B_RATE18_06)
629 		index = 8;
630 	else if (regaddr == RTXAGC_B_RATE54_24)
631 		index = 9;
632 	else if (regaddr == RTXAGC_B_CCK1_55_MCS32)
633 		index = 14;
634 	else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
635 		index = 15;
636 	else if (regaddr == RTXAGC_B_MCS03_MCS00)
637 		index = 10;
638 	else if (regaddr == RTXAGC_B_MCS07_MCS04)
639 		index = 11;
640 	else if (regaddr == RTXAGC_B_MCS11_MCS08)
641 		index = 12;
642 	else if (regaddr == RTXAGC_B_MCS15_MCS12)
643 		index = 13;
644 	else
645 		return;
646 
647 	rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
648 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
649 		"MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
650 		rtlphy->pwrgroup_cnt, index,
651 		rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]);
652 	if (index == 13)
653 		rtlphy->pwrgroup_cnt++;
654 }
655 
656 static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
657 	u8 configtype)
658 {
659 	struct rtl_priv *rtlpriv = rtl_priv(hw);
660 	int i;
661 	u32 *phy_regarray_table_pg;
662 	u16 phy_regarray_pg_len;
663 
664 	phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH;
665 	phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
666 	if (configtype == BASEBAND_CONFIG_PHY_REG) {
667 		for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
668 			rtl_addr_delay(phy_regarray_table_pg[i]);
669 			_rtl92d_store_pwrindex_diffrate_offset(hw,
670 				phy_regarray_table_pg[i],
671 				phy_regarray_table_pg[i + 1],
672 				phy_regarray_table_pg[i + 2]);
673 		}
674 	} else {
675 		rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,
676 			"configtype != BaseBand_Config_PHY_REG\n");
677 	}
678 	return true;
679 }
680 
681 static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw)
682 {
683 	struct rtl_priv *rtlpriv = rtl_priv(hw);
684 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
685 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
686 	bool rtstatus;
687 
688 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
689 	rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
690 		BASEBAND_CONFIG_PHY_REG);
691 	if (!rtstatus) {
692 		pr_err("Write BB Reg Fail!!\n");
693 		return false;
694 	}
695 
696 	/* if (rtlphy->rf_type == RF_1T2R) {
697 	 *      _rtl92c_phy_bb_config_1t(hw);
698 	 *     rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
699 	 *} */
700 
701 	if (rtlefuse->autoload_failflag == false) {
702 		rtlphy->pwrgroup_cnt = 0;
703 		rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw,
704 			BASEBAND_CONFIG_PHY_REG);
705 	}
706 	if (!rtstatus) {
707 		pr_err("BB_PG Reg Fail!!\n");
708 		return false;
709 	}
710 	rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
711 		BASEBAND_CONFIG_AGC_TAB);
712 	if (!rtstatus) {
713 		pr_err("AGC Table Fail\n");
714 		return false;
715 	}
716 	rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
717 		RFPGA0_XA_HSSIPARAMETER2, 0x200));
718 
719 	return true;
720 }
721 
722 bool rtl92d_phy_bb_config(struct ieee80211_hw *hw)
723 {
724 	struct rtl_priv *rtlpriv = rtl_priv(hw);
725 	u16 regval;
726 	u32 regvaldw;
727 	u8 value;
728 
729 	_rtl92d_phy_init_bb_rf_register_definition(hw);
730 	regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
731 	rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
732 		       regval | BIT(13) | BIT(0) | BIT(1));
733 	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
734 	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
735 	/* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */
736 	value = rtl_read_byte(rtlpriv, REG_RF_CTRL);
737 	rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
738 		RF_SDMRSTB);
739 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
740 		FEN_DIO_PCIE | FEN_BB_GLB_RSTN | FEN_BBRSTB);
741 	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
742 	if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
743 		regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
744 		rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
745 	}
746 
747 	return _rtl92d_phy_bb_config(hw);
748 }
749 
750 bool rtl92d_phy_rf_config(struct ieee80211_hw *hw)
751 {
752 	return rtl92d_phy_rf6052_config(hw);
753 }
754 
755 bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
756 					  enum rf_content content,
757 					  enum radio_path rfpath)
758 {
759 	int i;
760 	u32 *radioa_array_table;
761 	u32 *radiob_array_table;
762 	u16 radioa_arraylen, radiob_arraylen;
763 	struct rtl_priv *rtlpriv = rtl_priv(hw);
764 
765 	radioa_arraylen = RADIOA_2T_ARRAYLENGTH;
766 	radioa_array_table = rtl8192de_radioa_2tarray;
767 	radiob_arraylen = RADIOB_2T_ARRAYLENGTH;
768 	radiob_array_table = rtl8192de_radiob_2tarray;
769 	if (rtlpriv->efuse.internal_pa_5g[0]) {
770 		radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH;
771 		radioa_array_table = rtl8192de_radioa_2t_int_paarray;
772 	}
773 	if (rtlpriv->efuse.internal_pa_5g[1]) {
774 		radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH;
775 		radiob_array_table = rtl8192de_radiob_2t_int_paarray;
776 	}
777 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
778 		"PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n");
779 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
780 		"PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n");
781 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
782 
783 	/* this only happens when DMDP, mac0 start on 2.4G,
784 	 * mac1 start on 5G, mac 0 has to set phy0&phy1
785 	 * pathA or mac1 has to set phy0&phy1 pathA */
786 	if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) {
787 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
788 			" ===> althougth Path A, we load radiob.txt\n");
789 		radioa_arraylen = radiob_arraylen;
790 		radioa_array_table = radiob_array_table;
791 	}
792 	switch (rfpath) {
793 	case RF90_PATH_A:
794 		for (i = 0; i < radioa_arraylen; i = i + 2) {
795 			rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
796 					RFREG_OFFSET_MASK,
797 					radioa_array_table[i + 1]);
798 		}
799 		break;
800 	case RF90_PATH_B:
801 		for (i = 0; i < radiob_arraylen; i = i + 2) {
802 			rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
803 					RFREG_OFFSET_MASK,
804 					radiob_array_table[i + 1]);
805 		}
806 		break;
807 	case RF90_PATH_C:
808 	case RF90_PATH_D:
809 		pr_err("switch case %#x not processed\n", rfpath);
810 		break;
811 	}
812 	return true;
813 }
814 
815 void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
816 {
817 	struct rtl_priv *rtlpriv = rtl_priv(hw);
818 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
819 
820 	rtlphy->default_initialgain[0] =
821 	    (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
822 	rtlphy->default_initialgain[1] =
823 	    (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
824 	rtlphy->default_initialgain[2] =
825 	    (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
826 	rtlphy->default_initialgain[3] =
827 	    (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
828 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
829 		"Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
830 		rtlphy->default_initialgain[0],
831 		rtlphy->default_initialgain[1],
832 		rtlphy->default_initialgain[2],
833 		rtlphy->default_initialgain[3]);
834 	rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
835 					      MASKBYTE0);
836 	rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
837 					      MASKDWORD);
838 	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
839 		"Default framesync (0x%x) = 0x%x\n",
840 		ROFDM0_RXDETECTOR3, rtlphy->framesync);
841 }
842 
843 static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
844 	u8 *cckpowerlevel, u8 *ofdmpowerlevel)
845 {
846 	struct rtl_priv *rtlpriv = rtl_priv(hw);
847 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
848 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
849 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
850 	u8 index = (channel - 1);
851 
852 	/* 1. CCK */
853 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
854 		/* RF-A */
855 		cckpowerlevel[RF90_PATH_A] =
856 				 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
857 		/* RF-B */
858 		cckpowerlevel[RF90_PATH_B] =
859 				 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
860 	} else {
861 		cckpowerlevel[RF90_PATH_A] = 0;
862 		cckpowerlevel[RF90_PATH_B] = 0;
863 	}
864 	/* 2. OFDM for 1S or 2S */
865 	if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
866 		/*  Read HT 40 OFDM TX power */
867 		ofdmpowerlevel[RF90_PATH_A] =
868 		    rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
869 		ofdmpowerlevel[RF90_PATH_B] =
870 		    rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
871 	} else if (rtlphy->rf_type == RF_2T2R) {
872 		/* Read HT 40 OFDM TX power */
873 		ofdmpowerlevel[RF90_PATH_A] =
874 		    rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
875 		ofdmpowerlevel[RF90_PATH_B] =
876 		    rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
877 	}
878 }
879 
880 static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw,
881 	u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
882 {
883 	struct rtl_priv *rtlpriv = rtl_priv(hw);
884 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
885 
886 	rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
887 	rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
888 }
889 
890 static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl)
891 {
892 	u8 place = chnl;
893 
894 	if (chnl > 14) {
895 		for (place = 14; place < ARRAY_SIZE(channel_all); place++) {
896 			if (channel_all[place] == chnl) {
897 				place++;
898 				break;
899 			}
900 		}
901 	}
902 	return place;
903 }
904 
905 void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
906 {
907 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
908 	struct rtl_priv *rtlpriv = rtl_priv(hw);
909 	u8 cckpowerlevel[2], ofdmpowerlevel[2];
910 
911 	if (!rtlefuse->txpwr_fromeprom)
912 		return;
913 	channel = _rtl92c_phy_get_rightchnlplace(channel);
914 	_rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0],
915 		&ofdmpowerlevel[0]);
916 	if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
917 		_rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
918 				&ofdmpowerlevel[0]);
919 	if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
920 		rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
921 	rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
922 }
923 
924 void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
925 			    enum nl80211_channel_type ch_type)
926 {
927 	struct rtl_priv *rtlpriv = rtl_priv(hw);
928 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
929 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
930 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
931 	unsigned long flag = 0;
932 	u8 reg_prsr_rsc;
933 	u8 reg_bw_opmode;
934 
935 	if (rtlphy->set_bwmode_inprogress)
936 		return;
937 	if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
938 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
939 			"FALSE driver sleep or unload\n");
940 		return;
941 	}
942 	rtlphy->set_bwmode_inprogress = true;
943 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
944 		rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
945 		"20MHz" : "40MHz");
946 	reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
947 	reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
948 	switch (rtlphy->current_chan_bw) {
949 	case HT_CHANNEL_WIDTH_20:
950 		reg_bw_opmode |= BW_OPMODE_20MHZ;
951 		rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
952 		break;
953 	case HT_CHANNEL_WIDTH_20_40:
954 		reg_bw_opmode &= ~BW_OPMODE_20MHZ;
955 		rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
956 
957 		reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
958 			(mac->cur_40_prime_sc << 5);
959 		rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
960 		break;
961 	default:
962 		pr_err("unknown bandwidth: %#X\n",
963 		       rtlphy->current_chan_bw);
964 		break;
965 	}
966 	switch (rtlphy->current_chan_bw) {
967 	case HT_CHANNEL_WIDTH_20:
968 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
969 		rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
970 		/* SET BIT10 BIT11  for receive cck */
971 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
972 			      BIT(11), 3);
973 		break;
974 	case HT_CHANNEL_WIDTH_20_40:
975 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
976 		rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
977 		/* Set Control channel to upper or lower.
978 		 * These settings are required only for 40MHz */
979 		if (rtlhal->current_bandtype == BAND_ON_2_4G) {
980 			rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
981 			rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND,
982 				(mac->cur_40_prime_sc >> 1));
983 			rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
984 		}
985 		rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
986 		/* SET BIT10 BIT11  for receive cck */
987 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
988 			      BIT(11), 0);
989 		rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
990 			(mac->cur_40_prime_sc ==
991 			HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
992 		break;
993 	default:
994 		pr_err("unknown bandwidth: %#X\n",
995 		       rtlphy->current_chan_bw);
996 		break;
997 
998 	}
999 	rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1000 	rtlphy->set_bwmode_inprogress = false;
1001 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
1002 }
1003 
1004 static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
1005 {
1006 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
1007 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
1008 	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00);
1009 	rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
1010 }
1011 
1012 static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
1013 {
1014 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1015 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1016 	u8 value8;
1017 
1018 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
1019 	rtlhal->bandset = band;
1020 	rtlhal->current_bandtype = band;
1021 	if (IS_92D_SINGLEPHY(rtlhal->version))
1022 		rtlhal->bandset = BAND_ON_BOTH;
1023 	/* stop RX/Tx */
1024 	_rtl92d_phy_stop_trx_before_changeband(hw);
1025 	/* reconfig BB/RF according to wireless mode */
1026 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1027 		/* BB & RF Config */
1028 		rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n");
1029 		if (rtlhal->interfaceindex == 1)
1030 			_rtl92d_phy_config_bb_with_headerfile(hw,
1031 				BASEBAND_CONFIG_AGC_TAB);
1032 	} else {
1033 		/* 5G band */
1034 		rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n");
1035 		if (rtlhal->interfaceindex == 1)
1036 			_rtl92d_phy_config_bb_with_headerfile(hw,
1037 				BASEBAND_CONFIG_AGC_TAB);
1038 	}
1039 	rtl92d_update_bbrf_configuration(hw);
1040 	if (rtlhal->current_bandtype == BAND_ON_2_4G)
1041 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1042 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1043 
1044 	/* 20M BW. */
1045 	/* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */
1046 	rtlhal->reloadtxpowerindex = true;
1047 	/* notice fw know band status  0x81[1]/0x53[1] = 0: 5G, 1: 2G */
1048 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1049 		value8 = rtl_read_byte(rtlpriv,	(rtlhal->interfaceindex ==
1050 			0 ? REG_MAC0 : REG_MAC1));
1051 		value8 |= BIT(1);
1052 		rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1053 			0 ? REG_MAC0 : REG_MAC1), value8);
1054 	} else {
1055 		value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1056 			0 ? REG_MAC0 : REG_MAC1));
1057 		value8 &= (~BIT(1));
1058 		rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1059 			0 ? REG_MAC0 : REG_MAC1), value8);
1060 	}
1061 	mdelay(1);
1062 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n");
1063 }
1064 
1065 static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1066 	u8 channel, u8 rfpath)
1067 {
1068 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1069 	u32 imr_num = MAX_RF_IMR_INDEX;
1070 	u32 rfmask = RFREG_OFFSET_MASK;
1071 	u8 group, i;
1072 	unsigned long flag = 0;
1073 
1074 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath);
1075 	if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
1076 		rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1077 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1078 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1079 		/* fc area 0xd2c */
1080 		if (channel > 99)
1081 			rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1082 				      BIT(14), 2);
1083 		else
1084 			rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1085 				      BIT(14), 1);
1086 		/* leave 0 for channel1-14. */
1087 		group = channel <= 64 ? 1 : 2;
1088 		imr_num = MAX_RF_IMR_INDEX_NORMAL;
1089 		for (i = 0; i < imr_num; i++)
1090 			rtl_set_rfreg(hw, (enum radio_path)rfpath,
1091 				      rf_reg_for_5g_swchnl_normal[i], rfmask,
1092 				      rf_imr_param_normal[0][group][i]);
1093 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
1094 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1);
1095 	} else {
1096 		/* G band. */
1097 		rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
1098 			"Load RF IMR parameters for G band. IMR already setting %d\n",
1099 			rtlpriv->rtlhal.load_imrandiqk_setting_for2g);
1100 		rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1101 		if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) {
1102 			rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
1103 				"Load RF IMR parameters for G band. %d\n",
1104 				rfpath);
1105 			rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1106 			rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1107 			rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1108 				      0x00f00000, 0xf);
1109 			imr_num = MAX_RF_IMR_INDEX_NORMAL;
1110 			for (i = 0; i < imr_num; i++) {
1111 				rtl_set_rfreg(hw, (enum radio_path)rfpath,
1112 					      rf_reg_for_5g_swchnl_normal[i],
1113 					      RFREG_OFFSET_MASK,
1114 					      rf_imr_param_normal[0][0][i]);
1115 			}
1116 			rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1117 				      0x00f00000, 0);
1118 			rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3);
1119 			rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1120 		}
1121 	}
1122 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1123 }
1124 
1125 static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw,
1126 	u8 rfpath, u32 *pu4_regval)
1127 {
1128 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1129 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1130 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1131 
1132 	rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "====>\n");
1133 	/*----Store original RFENV control type----*/
1134 	switch (rfpath) {
1135 	case RF90_PATH_A:
1136 	case RF90_PATH_C:
1137 		*pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV);
1138 		break;
1139 	case RF90_PATH_B:
1140 	case RF90_PATH_D:
1141 		*pu4_regval =
1142 		    rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16);
1143 		break;
1144 	}
1145 	/*----Set RF_ENV enable----*/
1146 	rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
1147 	udelay(1);
1148 	/*----Set RF_ENV output high----*/
1149 	rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
1150 	udelay(1);
1151 	/* Set bit number of Address and Data for RF register */
1152 	/* Set 1 to 4 bits for 8255 */
1153 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0);
1154 	udelay(1);
1155 	/*Set 0 to 12 bits for 8255 */
1156 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
1157 	udelay(1);
1158 	rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<====\n");
1159 }
1160 
1161 static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath,
1162 				       u32 *pu4_regval)
1163 {
1164 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1165 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1166 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1167 
1168 	rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n");
1169 	/*----Restore RFENV control type----*/
1170 	switch (rfpath) {
1171 	case RF90_PATH_A:
1172 	case RF90_PATH_C:
1173 		rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval);
1174 		break;
1175 	case RF90_PATH_B:
1176 	case RF90_PATH_D:
1177 		rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
1178 			      *pu4_regval);
1179 		break;
1180 	}
1181 	rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n");
1182 }
1183 
1184 static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1185 {
1186 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1187 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1188 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1189 	u8 path = rtlhal->current_bandtype ==
1190 	    BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B;
1191 	u8 index = 0, i = 0, rfpath = RF90_PATH_A;
1192 	bool need_pwr_down = false, internal_pa = false;
1193 	u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2;
1194 
1195 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n");
1196 	/* config path A for 5G */
1197 	if (rtlhal->current_bandtype == BAND_ON_5G) {
1198 		rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1199 		u4tmp = curveindex_5g[channel - 1];
1200 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1201 			"ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
1202 		for (i = 0; i < RF_CHNL_NUM_5G; i++) {
1203 			if (channel == rf_chnl_5g[i] && channel <= 140)
1204 				index = 0;
1205 		}
1206 		for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) {
1207 			if (channel == rf_chnl_5g_40m[i] && channel <= 140)
1208 				index = 1;
1209 		}
1210 		if (channel == 149 || channel == 155 || channel == 161)
1211 			index = 2;
1212 		else if (channel == 151 || channel == 153 || channel == 163
1213 			 || channel == 165)
1214 			index = 3;
1215 		else if (channel == 157 || channel == 159)
1216 			index = 4;
1217 
1218 		if (rtlhal->macphymode == DUALMAC_DUALPHY
1219 		    && rtlhal->interfaceindex == 1) {
1220 			need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false);
1221 			rtlhal->during_mac1init_radioa = true;
1222 			/* asume no this case */
1223 			if (need_pwr_down)
1224 				_rtl92d_phy_enable_rf_env(hw, path,
1225 							  &u4regvalue);
1226 		}
1227 		for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) {
1228 			if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
1229 				rtl_set_rfreg(hw, (enum radio_path)path,
1230 					      rf_reg_for_c_cut_5g[i],
1231 					      RFREG_OFFSET_MASK, 0xE439D);
1232 			} else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
1233 				u4tmp2 = (rf_reg_pram_c_5g[index][i] &
1234 				     0x7FF) | (u4tmp << 11);
1235 				if (channel == 36)
1236 					u4tmp2 &= ~(BIT(7) | BIT(6));
1237 				rtl_set_rfreg(hw, (enum radio_path)path,
1238 					      rf_reg_for_c_cut_5g[i],
1239 					      RFREG_OFFSET_MASK, u4tmp2);
1240 			} else {
1241 				rtl_set_rfreg(hw, (enum radio_path)path,
1242 					      rf_reg_for_c_cut_5g[i],
1243 					      RFREG_OFFSET_MASK,
1244 					      rf_reg_pram_c_5g[index][i]);
1245 			}
1246 			rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
1247 				"offset 0x%x value 0x%x path %d index %d readback 0x%x\n",
1248 				rf_reg_for_c_cut_5g[i],
1249 				rf_reg_pram_c_5g[index][i],
1250 				path, index,
1251 				rtl_get_rfreg(hw, (enum radio_path)path,
1252 					      rf_reg_for_c_cut_5g[i],
1253 					      RFREG_OFFSET_MASK));
1254 		}
1255 		if (need_pwr_down)
1256 			_rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1257 		if (rtlhal->during_mac1init_radioa)
1258 			rtl92d_phy_powerdown_anotherphy(hw, false);
1259 		if (channel < 149)
1260 			value = 0x07;
1261 		else if (channel >= 149)
1262 			value = 0x02;
1263 		if (channel >= 36 && channel <= 64)
1264 			index = 0;
1265 		else if (channel >= 100 && channel <= 140)
1266 			index = 1;
1267 		else
1268 			index = 2;
1269 		for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1270 			rfpath++) {
1271 			if (rtlhal->macphymode == DUALMAC_DUALPHY &&
1272 				rtlhal->interfaceindex == 1)	/* MAC 1 5G */
1273 				internal_pa = rtlpriv->efuse.internal_pa_5g[1];
1274 			else
1275 				internal_pa =
1276 					 rtlpriv->efuse.internal_pa_5g[rfpath];
1277 			if (internal_pa) {
1278 				for (i = 0;
1279 				     i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA;
1280 				     i++) {
1281 					rtl_set_rfreg(hw, rfpath,
1282 						rf_for_c_cut_5g_internal_pa[i],
1283 						RFREG_OFFSET_MASK,
1284 						rf_pram_c_5g_int_pa[index][i]);
1285 					rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD,
1286 						"offset 0x%x value 0x%x path %d index %d\n",
1287 						rf_for_c_cut_5g_internal_pa[i],
1288 						rf_pram_c_5g_int_pa[index][i],
1289 						rfpath, index);
1290 				}
1291 			} else {
1292 				rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
1293 					      mask, value);
1294 			}
1295 		}
1296 	} else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1297 		rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1298 		u4tmp = curveindex_2g[channel - 1];
1299 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1300 			"ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
1301 		if (channel == 1 || channel == 2 || channel == 4 || channel == 9
1302 		    || channel == 10 || channel == 11 || channel == 12)
1303 			index = 0;
1304 		else if (channel == 3 || channel == 13 || channel == 14)
1305 			index = 1;
1306 		else if (channel >= 5 && channel <= 8)
1307 			index = 2;
1308 		if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1309 			path = RF90_PATH_A;
1310 			if (rtlhal->interfaceindex == 0) {
1311 				need_pwr_down =
1312 					 rtl92d_phy_enable_anotherphy(hw, true);
1313 				rtlhal->during_mac0init_radiob = true;
1314 
1315 				if (need_pwr_down)
1316 					_rtl92d_phy_enable_rf_env(hw, path,
1317 								  &u4regvalue);
1318 			}
1319 		}
1320 		for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) {
1321 			if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
1322 				rtl_set_rfreg(hw, (enum radio_path)path,
1323 					rf_reg_for_c_cut_2g[i],
1324 					RFREG_OFFSET_MASK,
1325 					(rf_reg_param_for_c_cut_2g[index][i] |
1326 					BIT(17)));
1327 			else
1328 				rtl_set_rfreg(hw, (enum radio_path)path,
1329 					      rf_reg_for_c_cut_2g[i],
1330 					      RFREG_OFFSET_MASK,
1331 					      rf_reg_param_for_c_cut_2g
1332 					      [index][i]);
1333 			rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
1334 				"offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n",
1335 				rf_reg_for_c_cut_2g[i],
1336 				rf_reg_param_for_c_cut_2g[index][i],
1337 				rf_reg_mask_for_c_cut_2g[i], path, index,
1338 				rtl_get_rfreg(hw, (enum radio_path)path,
1339 					      rf_reg_for_c_cut_2g[i],
1340 					      RFREG_OFFSET_MASK));
1341 		}
1342 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1343 			"cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1344 			rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1345 
1346 		rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1347 			      RFREG_OFFSET_MASK,
1348 			      rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1349 		if (need_pwr_down)
1350 			_rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1351 		if (rtlhal->during_mac0init_radiob)
1352 			rtl92d_phy_powerdown_anotherphy(hw, true);
1353 	}
1354 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1355 }
1356 
1357 u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl)
1358 {
1359 	u8 place;
1360 
1361 	if (chnl > 14) {
1362 		for (place = 14; place < ARRAY_SIZE(channel_all); place++) {
1363 			if (channel_all[place] == chnl)
1364 				return place - 13;
1365 		}
1366 	}
1367 
1368 	return 0;
1369 }
1370 
1371 #define MAX_TOLERANCE		5
1372 #define IQK_DELAY_TIME		1	/* ms */
1373 #define MAX_TOLERANCE_92D	3
1374 
1375 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1376 static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1377 {
1378 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1379 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1380 	u32 regeac, rege94, rege9c, regea4;
1381 	u8 result = 0;
1382 
1383 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK!\n");
1384 	/* path-A IQK setting */
1385 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1386 	if (rtlhal->interfaceindex == 0) {
1387 		rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1388 		rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1389 	} else {
1390 		rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22);
1391 		rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22);
1392 	}
1393 	rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1394 	rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206);
1395 	/* path-B IQK setting */
1396 	if (configpathb) {
1397 		rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1398 		rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1399 		rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1400 		rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206);
1401 	}
1402 	/* LO calibration setting */
1403 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1404 	rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1405 	/* One shot, path A LOK & IQK */
1406 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "One shot, path A LOK & IQK!\n");
1407 	rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1408 	rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1409 	/* delay x ms */
1410 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
1411 		"Delay %d ms for One shot, path A LOK & IQK\n",
1412 		IQK_DELAY_TIME);
1413 	mdelay(IQK_DELAY_TIME);
1414 	/* Check failed */
1415 	regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1416 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1417 	rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1418 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe94 = 0x%x\n", rege94);
1419 	rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1420 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe9c = 0x%x\n", rege9c);
1421 	regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1422 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xea4 = 0x%x\n", regea4);
1423 	if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1424 	    (((rege9c & 0x03FF0000) >> 16) != 0x42))
1425 		result |= 0x01;
1426 	else			/* if Tx not OK, ignore Rx */
1427 		return result;
1428 	/* if Tx is OK, check whether Rx is OK */
1429 	if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) &&
1430 	    (((regeac & 0x03FF0000) >> 16) != 0x36))
1431 		result |= 0x02;
1432 	else
1433 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A Rx IQK fail!!\n");
1434 	return result;
1435 }
1436 
1437 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1438 static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1439 					  bool configpathb)
1440 {
1441 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1442 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1443 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1444 	u32 regeac, rege94, rege9c, regea4;
1445 	u8 result = 0;
1446 	u8 i;
1447 	u8 retrycount = 2;
1448 	u32 TXOKBIT = BIT(28), RXOKBIT = BIT(27);
1449 
1450 	if (rtlhal->interfaceindex == 1) {	/* PHY1 */
1451 		TXOKBIT = BIT(31);
1452 		RXOKBIT = BIT(30);
1453 	}
1454 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK!\n");
1455 	/* path-A IQK setting */
1456 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1457 	rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1458 	rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1459 	rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307);
1460 	rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960);
1461 	/* path-B IQK setting */
1462 	if (configpathb) {
1463 		rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1464 		rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1465 		rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000);
1466 		rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000);
1467 	}
1468 	/* LO calibration setting */
1469 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1470 	rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1471 	/* path-A PA on */
1472 	rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60);
1473 	rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30);
1474 	for (i = 0; i < retrycount; i++) {
1475 		/* One shot, path A LOK & IQK */
1476 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1477 			"One shot, path A LOK & IQK!\n");
1478 		rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1479 		rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1480 		/* delay x ms */
1481 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1482 			"Delay %d ms for One shot, path A LOK & IQK.\n",
1483 			IQK_DELAY_TIME);
1484 		mdelay(IQK_DELAY_TIME * 10);
1485 		/* Check failed */
1486 		regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1487 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1488 		rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1489 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe94 = 0x%x\n", rege94);
1490 		rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1491 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe9c = 0x%x\n", rege9c);
1492 		regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1493 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xea4 = 0x%x\n", regea4);
1494 		if (!(regeac & TXOKBIT) &&
1495 		     (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1496 			result |= 0x01;
1497 		} else { /* if Tx not OK, ignore Rx */
1498 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1499 				"Path A Tx IQK fail!!\n");
1500 			continue;
1501 		}
1502 
1503 		/* if Tx is OK, check whether Rx is OK */
1504 		if (!(regeac & RXOKBIT) &&
1505 		    (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1506 			result |= 0x02;
1507 			break;
1508 		} else {
1509 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1510 				"Path A Rx IQK fail!!\n");
1511 		}
1512 	}
1513 	/* path A PA off */
1514 	rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1515 		      rtlphy->iqk_bb_backup[0]);
1516 	rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD,
1517 		      rtlphy->iqk_bb_backup[1]);
1518 	return result;
1519 }
1520 
1521 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1522 static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1523 {
1524 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1525 	u32 regeac, regeb4, regebc, regec4, regecc;
1526 	u8 result = 0;
1527 
1528 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B IQK!\n");
1529 	/* One shot, path B LOK & IQK */
1530 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "One shot, path A LOK & IQK!\n");
1531 	rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1532 	rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1533 	/* delay x ms  */
1534 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
1535 		"Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME);
1536 	mdelay(IQK_DELAY_TIME);
1537 	/* Check failed */
1538 	regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1539 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1540 	regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1541 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeb4 = 0x%x\n", regeb4);
1542 	regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1543 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xebc = 0x%x\n", regebc);
1544 	regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1545 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xec4 = 0x%x\n", regec4);
1546 	regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1547 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xecc = 0x%x\n", regecc);
1548 	if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1549 	    (((regebc & 0x03FF0000) >> 16) != 0x42))
1550 		result |= 0x01;
1551 	else
1552 		return result;
1553 	if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
1554 	    (((regecc & 0x03FF0000) >> 16) != 0x36))
1555 		result |= 0x02;
1556 	else
1557 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B Rx IQK fail!!\n");
1558 	return result;
1559 }
1560 
1561 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1562 static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1563 {
1564 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1565 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1566 	u32 regeac, regeb4, regebc, regec4, regecc;
1567 	u8 result = 0;
1568 	u8 i;
1569 	u8 retrycount = 2;
1570 
1571 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B IQK!\n");
1572 	/* path-A IQK setting */
1573 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1574 	rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1575 	rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1576 	rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000);
1577 	rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000);
1578 
1579 	/* path-B IQK setting */
1580 	rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1581 	rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1582 	rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307);
1583 	rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960);
1584 
1585 	/* LO calibration setting */
1586 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1587 	rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1588 
1589 	/* path-B PA on */
1590 	rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700);
1591 	rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30);
1592 
1593 	for (i = 0; i < retrycount; i++) {
1594 		/* One shot, path B LOK & IQK */
1595 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1596 			"One shot, path A LOK & IQK!\n");
1597 		rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000);
1598 		rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1599 
1600 		/* delay x ms */
1601 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1602 			"Delay %d ms for One shot, path B LOK & IQK.\n", 10);
1603 		mdelay(IQK_DELAY_TIME * 10);
1604 
1605 		/* Check failed */
1606 		regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1607 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1608 		regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1609 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeb4 = 0x%x\n", regeb4);
1610 		regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1611 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xebc = 0x%x\n", regebc);
1612 		regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1613 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xec4 = 0x%x\n", regec4);
1614 		regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1615 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xecc = 0x%x\n", regecc);
1616 		if (!(regeac & BIT(31)) &&
1617 		    (((regeb4 & 0x03FF0000) >> 16) != 0x142))
1618 			result |= 0x01;
1619 		else
1620 			continue;
1621 		if (!(regeac & BIT(30)) &&
1622 		    (((regec4 & 0x03FF0000) >> 16) != 0x132)) {
1623 			result |= 0x02;
1624 			break;
1625 		} else {
1626 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1627 				"Path B Rx IQK fail!!\n");
1628 		}
1629 	}
1630 
1631 	/* path B PA off */
1632 	rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1633 		      rtlphy->iqk_bb_backup[0]);
1634 	rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD,
1635 		      rtlphy->iqk_bb_backup[2]);
1636 	return result;
1637 }
1638 
1639 static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1640 					    u32 *adda_reg, u32 *adda_backup,
1641 					    u32 regnum)
1642 {
1643 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1644 	u32 i;
1645 
1646 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Save ADDA parameters.\n");
1647 	for (i = 0; i < regnum; i++)
1648 		adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD);
1649 }
1650 
1651 static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
1652 	u32 *macreg, u32 *macbackup)
1653 {
1654 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1655 	u32 i;
1656 
1657 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Save MAC parameters.\n");
1658 	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1659 		macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1660 	macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1661 }
1662 
1663 static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1664 					      u32 *adda_reg, u32 *adda_backup,
1665 					      u32 regnum)
1666 {
1667 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1668 	u32 i;
1669 
1670 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
1671 		"Reload ADDA power saving parameters !\n");
1672 	for (i = 0; i < regnum; i++)
1673 		rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]);
1674 }
1675 
1676 static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
1677 					     u32 *macreg, u32 *macbackup)
1678 {
1679 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1680 	u32 i;
1681 
1682 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Reload MAC parameters !\n");
1683 	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1684 		rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1685 	rtl_write_byte(rtlpriv, macreg[i], macbackup[i]);
1686 }
1687 
1688 static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1689 		u32 *adda_reg, bool patha_on, bool is2t)
1690 {
1691 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1692 	u32 pathon;
1693 	u32 i;
1694 
1695 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "ADDA ON.\n");
1696 	pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;
1697 	if (patha_on)
1698 		pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
1699 		    0x04db25a4 : 0x0b1b25a4;
1700 	for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1701 		rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon);
1702 }
1703 
1704 static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1705 						u32 *macreg, u32 *macbackup)
1706 {
1707 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1708 	u32 i;
1709 
1710 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "MAC settings for Calibration.\n");
1711 	rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1712 
1713 	for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1714 		rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] &
1715 			       (~BIT(3))));
1716 	rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1717 }
1718 
1719 static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1720 {
1721 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1722 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A standby mode!\n");
1723 
1724 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1725 	rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000);
1726 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1727 }
1728 
1729 static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
1730 {
1731 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1732 	u32 mode;
1733 
1734 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
1735 		"BB Switch to %s mode!\n", pi_mode ? "PI" : "SI");
1736 	mode = pi_mode ? 0x01000100 : 0x01000000;
1737 	rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1738 	rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1739 }
1740 
1741 static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1742 				     u8 t, bool is2t)
1743 {
1744 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1745 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1746 	u32 i;
1747 	u8 patha_ok, pathb_ok;
1748 	static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1749 		RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1750 		0xe78, 0xe7c, 0xe80, 0xe84,
1751 		0xe88, 0xe8c, 0xed0, 0xed4,
1752 		0xed8, 0xedc, 0xee0, 0xeec
1753 	};
1754 	static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1755 		0x522, 0x550, 0x551, 0x040
1756 	};
1757 	static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1758 		RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1759 		RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1760 		RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1761 		RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1762 		ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1763 	};
1764 	const u32 retrycount = 2;
1765 	u32 bbvalue;
1766 
1767 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK for 2.4G :Start!!!\n");
1768 	if (t == 0) {
1769 		bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1770 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "==>0x%08x\n", bbvalue);
1771 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1772 			is2t ? "2T2R" : "1T1R");
1773 
1774 		/*  Save ADDA parameters, turn Path A ADDA on */
1775 		_rtl92d_phy_save_adda_registers(hw, adda_reg,
1776 			rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1777 		_rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1778 			rtlphy->iqk_mac_backup);
1779 		_rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1780 			rtlphy->iqk_bb_backup, IQK_BB_REG_NUM);
1781 	}
1782 	_rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1783 	if (t == 0)
1784 		rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1785 				RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1786 
1787 	/*  Switch BB to PI mode to do IQ Calibration. */
1788 	if (!rtlphy->rfpi_enable)
1789 		_rtl92d_phy_pimode_switch(hw, true);
1790 
1791 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1792 	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1793 	rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1794 	rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000);
1795 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1796 	if (is2t) {
1797 		rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD,
1798 			      0x00010000);
1799 		rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD,
1800 			      0x00010000);
1801 	}
1802 	/* MAC settings */
1803 	_rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1804 					    rtlphy->iqk_mac_backup);
1805 	/* Page B init */
1806 	rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1807 	if (is2t)
1808 		rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1809 	/* IQ calibration setting */
1810 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK setting!\n");
1811 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1812 	rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1813 	rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1814 	for (i = 0; i < retrycount; i++) {
1815 		patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
1816 		if (patha_ok == 0x03) {
1817 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1818 				"Path A IQK Success!!\n");
1819 			result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1820 					0x3FF0000) >> 16;
1821 			result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1822 					0x3FF0000) >> 16;
1823 			result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1824 					0x3FF0000) >> 16;
1825 			result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1826 					0x3FF0000) >> 16;
1827 			break;
1828 		} else if (i == (retrycount - 1) && patha_ok == 0x01) {
1829 			/* Tx IQK OK */
1830 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1831 				"Path A IQK Only  Tx Success!!\n");
1832 
1833 			result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1834 					0x3FF0000) >> 16;
1835 			result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1836 					0x3FF0000) >> 16;
1837 		}
1838 	}
1839 	if (0x00 == patha_ok)
1840 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK failed!!\n");
1841 	if (is2t) {
1842 		_rtl92d_phy_patha_standby(hw);
1843 		/* Turn Path B ADDA on */
1844 		_rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
1845 		for (i = 0; i < retrycount; i++) {
1846 			pathb_ok = _rtl92d_phy_pathb_iqk(hw);
1847 			if (pathb_ok == 0x03) {
1848 				RTPRINT(rtlpriv, FINIT, INIT_IQK,
1849 					"Path B IQK Success!!\n");
1850 				result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1851 					       MASKDWORD) & 0x3FF0000) >> 16;
1852 				result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1853 					       MASKDWORD) & 0x3FF0000) >> 16;
1854 				result[t][6] = (rtl_get_bbreg(hw, 0xec4,
1855 					       MASKDWORD) & 0x3FF0000) >> 16;
1856 				result[t][7] = (rtl_get_bbreg(hw, 0xecc,
1857 					       MASKDWORD) & 0x3FF0000) >> 16;
1858 				break;
1859 			} else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1860 				/* Tx IQK OK */
1861 				RTPRINT(rtlpriv, FINIT, INIT_IQK,
1862 					"Path B Only Tx IQK Success!!\n");
1863 				result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1864 					       MASKDWORD) & 0x3FF0000) >> 16;
1865 				result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1866 					       MASKDWORD) & 0x3FF0000) >> 16;
1867 			}
1868 		}
1869 		if (0x00 == pathb_ok)
1870 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1871 				"Path B IQK failed!!\n");
1872 	}
1873 
1874 	/* Back to BB mode, load original value */
1875 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
1876 		"IQK:Back to BB mode, load original value!\n");
1877 
1878 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1879 	if (t != 0) {
1880 		/* Switch back BB to SI mode after finish IQ Calibration. */
1881 		if (!rtlphy->rfpi_enable)
1882 			_rtl92d_phy_pimode_switch(hw, false);
1883 		/* Reload ADDA power saving parameters */
1884 		_rtl92d_phy_reload_adda_registers(hw, adda_reg,
1885 				rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1886 		/* Reload MAC parameters */
1887 		_rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
1888 					rtlphy->iqk_mac_backup);
1889 		if (is2t)
1890 			_rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
1891 							  rtlphy->iqk_bb_backup,
1892 							  IQK_BB_REG_NUM);
1893 		else
1894 			_rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
1895 							  rtlphy->iqk_bb_backup,
1896 							  IQK_BB_REG_NUM - 1);
1897 		/* load 0xe30 IQC default value */
1898 		rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
1899 		rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
1900 	}
1901 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "<==\n");
1902 }
1903 
1904 static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
1905 					       long result[][8], u8 t)
1906 {
1907 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1908 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1909 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1910 	u8 patha_ok, pathb_ok;
1911 	static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1912 		RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1913 		0xe78, 0xe7c, 0xe80, 0xe84,
1914 		0xe88, 0xe8c, 0xed0, 0xed4,
1915 		0xed8, 0xedc, 0xee0, 0xeec
1916 	};
1917 	static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1918 		0x522, 0x550, 0x551, 0x040
1919 	};
1920 	static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1921 		RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1922 		RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1923 		RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1924 		RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1925 		ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1926 	};
1927 	u32 bbvalue;
1928 	bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
1929 
1930 	/* Note: IQ calibration must be performed after loading
1931 	 * PHY_REG.txt , and radio_a, radio_b.txt */
1932 
1933 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK for 5G NORMAL:Start!!!\n");
1934 	mdelay(IQK_DELAY_TIME * 20);
1935 	if (t == 0) {
1936 		bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1937 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "==>0x%08x\n", bbvalue);
1938 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1939 			is2t ? "2T2R" : "1T1R");
1940 		/* Save ADDA parameters, turn Path A ADDA on */
1941 		_rtl92d_phy_save_adda_registers(hw, adda_reg,
1942 						rtlphy->adda_backup,
1943 						IQK_ADDA_REG_NUM);
1944 		_rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1945 					       rtlphy->iqk_mac_backup);
1946 		if (is2t)
1947 			_rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1948 							rtlphy->iqk_bb_backup,
1949 							IQK_BB_REG_NUM);
1950 		else
1951 			_rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1952 							rtlphy->iqk_bb_backup,
1953 							IQK_BB_REG_NUM - 1);
1954 	}
1955 	_rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1956 	/* MAC settings */
1957 	_rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1958 			rtlphy->iqk_mac_backup);
1959 	if (t == 0)
1960 		rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1961 			RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1962 	/*  Switch BB to PI mode to do IQ Calibration. */
1963 	if (!rtlphy->rfpi_enable)
1964 		_rtl92d_phy_pimode_switch(hw, true);
1965 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1966 	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1967 	rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1968 	rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000);
1969 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1970 
1971 	/* Page B init */
1972 	rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1973 	if (is2t)
1974 		rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1975 	/* IQ calibration setting  */
1976 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK setting!\n");
1977 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1978 	rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00);
1979 	rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1980 	patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
1981 	if (patha_ok == 0x03) {
1982 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK Success!!\n");
1983 		result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1984 				0x3FF0000) >> 16;
1985 		result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1986 				0x3FF0000) >> 16;
1987 		result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1988 				0x3FF0000) >> 16;
1989 		result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1990 				0x3FF0000) >> 16;
1991 	} else if (patha_ok == 0x01) {	/* Tx IQK OK */
1992 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1993 			"Path A IQK Only  Tx Success!!\n");
1994 
1995 		result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1996 				0x3FF0000) >> 16;
1997 		result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1998 				0x3FF0000) >> 16;
1999 	} else {
2000 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK Fail!!\n");
2001 	}
2002 	if (is2t) {
2003 		/* _rtl92d_phy_patha_standby(hw); */
2004 		/* Turn Path B ADDA on  */
2005 		_rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2006 		pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw);
2007 		if (pathb_ok == 0x03) {
2008 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
2009 				"Path B IQK Success!!\n");
2010 			result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2011 			     0x3FF0000) >> 16;
2012 			result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2013 			     0x3FF0000) >> 16;
2014 			result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
2015 			     0x3FF0000) >> 16;
2016 			result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
2017 			     0x3FF0000) >> 16;
2018 		} else if (pathb_ok == 0x01) { /* Tx IQK OK */
2019 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
2020 				"Path B Only Tx IQK Success!!\n");
2021 			result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2022 			     0x3FF0000) >> 16;
2023 			result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2024 			     0x3FF0000) >> 16;
2025 		} else {
2026 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
2027 				"Path B IQK failed!!\n");
2028 		}
2029 	}
2030 
2031 	/* Back to BB mode, load original value */
2032 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
2033 		"IQK:Back to BB mode, load original value!\n");
2034 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
2035 	if (t != 0) {
2036 		if (is2t)
2037 			_rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2038 							  rtlphy->iqk_bb_backup,
2039 							  IQK_BB_REG_NUM);
2040 		else
2041 			_rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2042 							  rtlphy->iqk_bb_backup,
2043 							  IQK_BB_REG_NUM - 1);
2044 		/* Reload MAC parameters */
2045 		_rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2046 				rtlphy->iqk_mac_backup);
2047 		/*  Switch back BB to SI mode after finish IQ Calibration. */
2048 		if (!rtlphy->rfpi_enable)
2049 			_rtl92d_phy_pimode_switch(hw, false);
2050 		/* Reload ADDA power saving parameters */
2051 		_rtl92d_phy_reload_adda_registers(hw, adda_reg,
2052 						  rtlphy->adda_backup,
2053 						  IQK_ADDA_REG_NUM);
2054 	}
2055 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "<==\n");
2056 }
2057 
2058 static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw,
2059 	long result[][8], u8 c1, u8 c2)
2060 {
2061 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2062 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2063 	u32 i, j, diff, sim_bitmap, bound;
2064 	u8 final_candidate[2] = {0xFF, 0xFF};	/* for path A and path B */
2065 	bool bresult = true;
2066 	bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2067 
2068 	if (is2t)
2069 		bound = 8;
2070 	else
2071 		bound = 4;
2072 	sim_bitmap = 0;
2073 	for (i = 0; i < bound; i++) {
2074 		diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] -
2075 		       result[c2][i]) : (result[c2][i] - result[c1][i]);
2076 		if (diff > MAX_TOLERANCE_92D) {
2077 			if ((i == 2 || i == 6) && !sim_bitmap) {
2078 				if (result[c1][i] + result[c1][i + 1] == 0)
2079 					final_candidate[(i / 4)] = c2;
2080 				else if (result[c2][i] + result[c2][i + 1] == 0)
2081 					final_candidate[(i / 4)] = c1;
2082 				else
2083 					sim_bitmap = sim_bitmap | (1 << i);
2084 			} else {
2085 				sim_bitmap = sim_bitmap | (1 << i);
2086 			}
2087 		}
2088 	}
2089 	if (sim_bitmap == 0) {
2090 		for (i = 0; i < (bound / 4); i++) {
2091 			if (final_candidate[i] != 0xFF) {
2092 				for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2093 					result[3][j] =
2094 						 result[final_candidate[i]][j];
2095 				bresult = false;
2096 			}
2097 		}
2098 		return bresult;
2099 	}
2100 	if (!(sim_bitmap & 0x0F)) { /* path A OK */
2101 		for (i = 0; i < 4; i++)
2102 			result[3][i] = result[c1][i];
2103 	} else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */
2104 		for (i = 0; i < 2; i++)
2105 			result[3][i] = result[c1][i];
2106 	}
2107 	if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */
2108 		for (i = 4; i < 8; i++)
2109 			result[3][i] = result[c1][i];
2110 	} else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */
2111 		for (i = 4; i < 6; i++)
2112 			result[3][i] = result[c1][i];
2113 	}
2114 	return false;
2115 }
2116 
2117 static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2118 					      bool iqk_ok, long result[][8],
2119 					      u8 final_candidate, bool txonly)
2120 {
2121 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2122 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2123 	u32 oldval_0, val_x, tx0_a, reg;
2124 	long val_y, tx0_c;
2125 	bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
2126 	    rtlhal->macphymode == DUALMAC_DUALPHY;
2127 
2128 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
2129 		"Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed");
2130 	if (final_candidate == 0xFF) {
2131 		return;
2132 	} else if (iqk_ok) {
2133 		oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2134 			MASKDWORD) >> 22) & 0x3FF;	/* OFDM0_D */
2135 		val_x = result[final_candidate][0];
2136 		if ((val_x & 0x00000200) != 0)
2137 			val_x = val_x | 0xFFFFFC00;
2138 		tx0_a = (val_x * oldval_0) >> 8;
2139 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2140 			"X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n",
2141 			val_x, tx0_a, oldval_0);
2142 		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
2143 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2144 			      ((val_x * oldval_0 >> 7) & 0x1));
2145 		val_y = result[final_candidate][1];
2146 		if ((val_y & 0x00000200) != 0)
2147 			val_y = val_y | 0xFFFFFC00;
2148 		/* path B IQK result + 3 */
2149 		if (rtlhal->interfaceindex == 1 &&
2150 			rtlhal->current_bandtype == BAND_ON_5G)
2151 			val_y += 3;
2152 		tx0_c = (val_y * oldval_0) >> 8;
2153 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2154 			"Y = 0x%lx, tx0_c = 0x%lx\n",
2155 			val_y, tx0_c);
2156 		rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
2157 			      ((tx0_c & 0x3C0) >> 6));
2158 		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
2159 			      (tx0_c & 0x3F));
2160 		if (is2t)
2161 			rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2162 				      ((val_y * oldval_0 >> 7) & 0x1));
2163 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
2164 			rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2165 				      MASKDWORD));
2166 		if (txonly) {
2167 			RTPRINT(rtlpriv, FINIT, INIT_IQK,  "only Tx OK\n");
2168 			return;
2169 		}
2170 		reg = result[final_candidate][2];
2171 		rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2172 		reg = result[final_candidate][3] & 0x3F;
2173 		rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2174 		reg = (result[final_candidate][3] >> 6) & 0xF;
2175 		rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
2176 	}
2177 }
2178 
2179 static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2180 	bool iqk_ok, long result[][8], u8 final_candidate, bool txonly)
2181 {
2182 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2183 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2184 	u32 oldval_1, val_x, tx1_a, reg;
2185 	long val_y, tx1_c;
2186 
2187 	RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n",
2188 		iqk_ok ? "Success" : "Failed");
2189 	if (final_candidate == 0xFF) {
2190 		return;
2191 	} else if (iqk_ok) {
2192 		oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
2193 					  MASKDWORD) >> 22) & 0x3FF;
2194 		val_x = result[final_candidate][4];
2195 		if ((val_x & 0x00000200) != 0)
2196 			val_x = val_x | 0xFFFFFC00;
2197 		tx1_a = (val_x * oldval_1) >> 8;
2198 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n",
2199 			val_x, tx1_a);
2200 		rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
2201 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2202 			      ((val_x * oldval_1 >> 7) & 0x1));
2203 		val_y = result[final_candidate][5];
2204 		if ((val_y & 0x00000200) != 0)
2205 			val_y = val_y | 0xFFFFFC00;
2206 		if (rtlhal->current_bandtype == BAND_ON_5G)
2207 			val_y += 3;
2208 		tx1_c = (val_y * oldval_1) >> 8;
2209 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n",
2210 			val_y, tx1_c);
2211 		rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
2212 			      ((tx1_c & 0x3C0) >> 6));
2213 		rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
2214 			      (tx1_c & 0x3F));
2215 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
2216 			      ((val_y * oldval_1 >> 7) & 0x1));
2217 		if (txonly)
2218 			return;
2219 		reg = result[final_candidate][6];
2220 		rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2221 		reg = result[final_candidate][7] & 0x3F;
2222 		rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2223 		reg = (result[final_candidate][7] >> 6) & 0xF;
2224 		rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
2225 	}
2226 }
2227 
2228 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2229 {
2230 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2231 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2232 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2233 	long result[4][8];
2234 	u8 i, final_candidate, indexforchannel;
2235 	bool patha_ok, pathb_ok;
2236 	long rege94, rege9c, regea4, regeac, regeb4;
2237 	long regebc, regec4, regecc, regtmp = 0;
2238 	bool is12simular, is13simular, is23simular;
2239 	unsigned long flag = 0;
2240 
2241 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
2242 		"IQK:Start!!!channel %d\n", rtlphy->current_channel);
2243 	for (i = 0; i < 8; i++) {
2244 		result[0][i] = 0;
2245 		result[1][i] = 0;
2246 		result[2][i] = 0;
2247 		result[3][i] = 0;
2248 	}
2249 	final_candidate = 0xff;
2250 	patha_ok = false;
2251 	pathb_ok = false;
2252 	is12simular = false;
2253 	is23simular = false;
2254 	is13simular = false;
2255 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
2256 		"IQK !!!currentband %d\n", rtlhal->current_bandtype);
2257 	rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
2258 	for (i = 0; i < 3; i++) {
2259 		if (rtlhal->current_bandtype == BAND_ON_5G) {
2260 			_rtl92d_phy_iq_calibrate_5g_normal(hw, result, i);
2261 		} else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2262 			if (IS_92D_SINGLEPHY(rtlhal->version))
2263 				_rtl92d_phy_iq_calibrate(hw, result, i, true);
2264 			else
2265 				_rtl92d_phy_iq_calibrate(hw, result, i, false);
2266 		}
2267 		if (i == 1) {
2268 			is12simular = _rtl92d_phy_simularity_compare(hw, result,
2269 								     0, 1);
2270 			if (is12simular) {
2271 				final_candidate = 0;
2272 				break;
2273 			}
2274 		}
2275 		if (i == 2) {
2276 			is13simular = _rtl92d_phy_simularity_compare(hw, result,
2277 								     0, 2);
2278 			if (is13simular) {
2279 				final_candidate = 0;
2280 				break;
2281 			}
2282 			is23simular = _rtl92d_phy_simularity_compare(hw, result,
2283 								     1, 2);
2284 			if (is23simular) {
2285 				final_candidate = 1;
2286 			} else {
2287 				for (i = 0; i < 8; i++)
2288 					regtmp += result[3][i];
2289 
2290 				if (regtmp != 0)
2291 					final_candidate = 3;
2292 				else
2293 					final_candidate = 0xFF;
2294 			}
2295 		}
2296 	}
2297 	rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
2298 	for (i = 0; i < 4; i++) {
2299 		rege94 = result[i][0];
2300 		rege9c = result[i][1];
2301 		regea4 = result[i][2];
2302 		regeac = result[i][3];
2303 		regeb4 = result[i][4];
2304 		regebc = result[i][5];
2305 		regec4 = result[i][6];
2306 		regecc = result[i][7];
2307 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2308 			"IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2309 			rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2310 			regecc);
2311 	}
2312 	if (final_candidate != 0xff) {
2313 		rtlphy->reg_e94 = rege94 = result[final_candidate][0];
2314 		rtlphy->reg_e9c = rege9c = result[final_candidate][1];
2315 		regea4 = result[final_candidate][2];
2316 		regeac = result[final_candidate][3];
2317 		rtlphy->reg_eb4 = regeb4 = result[final_candidate][4];
2318 		rtlphy->reg_ebc = regebc = result[final_candidate][5];
2319 		regec4 = result[final_candidate][6];
2320 		regecc = result[final_candidate][7];
2321 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2322 			"IQK: final_candidate is %x\n", final_candidate);
2323 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2324 			"IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2325 			rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2326 			regecc);
2327 		patha_ok = pathb_ok = true;
2328 	} else {
2329 		rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */
2330 		rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;   /* Y default value */
2331 	}
2332 	if ((rege94 != 0) /*&&(regea4 != 0) */)
2333 		_rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result,
2334 				final_candidate, (regea4 == 0));
2335 	if (IS_92D_SINGLEPHY(rtlhal->version)) {
2336 		if ((regeb4 != 0) /*&&(regec4 != 0) */)
2337 			_rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result,
2338 						final_candidate, (regec4 == 0));
2339 	}
2340 	if (final_candidate != 0xFF) {
2341 		indexforchannel = rtl92d_get_rightchnlplace_for_iqk(
2342 				  rtlphy->current_channel);
2343 
2344 		for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2345 			rtlphy->iqk_matrix[indexforchannel].
2346 				value[0][i] = result[final_candidate][i];
2347 		rtlphy->iqk_matrix[indexforchannel].iqk_done =
2348 			true;
2349 
2350 		rtl_dbg(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD,
2351 			"IQK OK indexforchannel %d\n", indexforchannel);
2352 	}
2353 }
2354 
2355 void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel)
2356 {
2357 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2358 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2359 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2360 	u8 indexforchannel;
2361 
2362 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel);
2363 	/*------Do IQK for normal chip and test chip 5G band------- */
2364 	indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
2365 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n",
2366 		indexforchannel,
2367 		 rtlphy->iqk_matrix[indexforchannel].iqk_done);
2368 	if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done &&
2369 		rtlphy->need_iqk) {
2370 		/* Re Do IQK. */
2371 		rtl_dbg(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD,
2372 			"Do IQK Matrix reg for channel:%d....\n", channel);
2373 		rtl92d_phy_iq_calibrate(hw);
2374 	} else {
2375 		/* Just load the value. */
2376 		/* 2G band just load once. */
2377 		if (((!rtlhal->load_imrandiqk_setting_for2g) &&
2378 		    indexforchannel == 0) || indexforchannel > 0) {
2379 			rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD,
2380 				"Just Read IQK Matrix reg for channel:%d....\n",
2381 				channel);
2382 			if (rtlphy->iqk_matrix[indexforchannel].value[0][0] != 0)
2383 				_rtl92d_phy_patha_fill_iqk_matrix(hw, true,
2384 					rtlphy->iqk_matrix[indexforchannel].value, 0,
2385 					rtlphy->iqk_matrix[indexforchannel].value[0][2] == 0);
2386 			if (IS_92D_SINGLEPHY(rtlhal->version)) {
2387 				if ((rtlphy->iqk_matrix[
2388 					indexforchannel].value[0][4] != 0)
2389 					/*&&(regec4 != 0) */)
2390 					_rtl92d_phy_pathb_fill_iqk_matrix(hw,
2391 						true,
2392 						rtlphy->iqk_matrix[
2393 						indexforchannel].value, 0,
2394 						(rtlphy->iqk_matrix[
2395 						indexforchannel].value[0][6]
2396 						== 0));
2397 			}
2398 		}
2399 	}
2400 	rtlphy->need_iqk = false;
2401 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2402 }
2403 
2404 static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2)
2405 {
2406 	u32 ret;
2407 
2408 	if (val1 >= val2)
2409 		ret = val1 - val2;
2410 	else
2411 		ret = val2 - val1;
2412 	return ret;
2413 }
2414 
2415 static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel)
2416 {
2417 
2418 	int i;
2419 
2420 	for (i = 0; i < ARRAY_SIZE(channel5g); i++)
2421 		if (channel == channel5g[i])
2422 			return true;
2423 	return false;
2424 }
2425 
2426 static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw,
2427 				       u32 *targetchnl, u32 * curvecount_val,
2428 				       bool is5g, u32 *curveindex)
2429 {
2430 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2431 	u32 smallest_abs_val = 0xffffffff, u4tmp;
2432 	u8 i, j;
2433 	u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G;
2434 
2435 	for (i = 0; i < chnl_num; i++) {
2436 		if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1))
2437 			continue;
2438 		curveindex[i] = 0;
2439 		for (j = 0; j < (CV_CURVE_CNT * 2); j++) {
2440 			u4tmp = _rtl92d_phy_get_abs(targetchnl[i],
2441 				curvecount_val[j]);
2442 
2443 			if (u4tmp < smallest_abs_val) {
2444 				curveindex[i] = j;
2445 				smallest_abs_val = u4tmp;
2446 			}
2447 		}
2448 		smallest_abs_val = 0xffffffff;
2449 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n",
2450 			i, curveindex[i]);
2451 	}
2452 }
2453 
2454 static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2455 		u8 channel)
2456 {
2457 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2458 	u8 erfpath = rtlpriv->rtlhal.current_bandtype ==
2459 		BAND_ON_5G ? RF90_PATH_A :
2460 		IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ?
2461 		RF90_PATH_B : RF90_PATH_A;
2462 	u32 u4tmp = 0, u4regvalue = 0;
2463 	bool bneed_powerdown_radio = false;
2464 
2465 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath);
2466 	RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n",
2467 		rtlpriv->rtlhal.current_bandtype);
2468 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "channel = %d\n", channel);
2469 	if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */
2470 		u4tmp = curveindex_5g[channel-1];
2471 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2472 			"ver 1 set RF-A, 5G,	0x28 = 0x%x !!\n", u4tmp);
2473 		if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2474 			rtlpriv->rtlhal.interfaceindex == 1) {
2475 			bneed_powerdown_radio =
2476 				rtl92d_phy_enable_anotherphy(hw, false);
2477 			rtlpriv->rtlhal.during_mac1init_radioa = true;
2478 			/* asume no this case */
2479 			if (bneed_powerdown_radio)
2480 				_rtl92d_phy_enable_rf_env(hw, erfpath,
2481 							  &u4regvalue);
2482 		}
2483 		rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2484 		if (bneed_powerdown_radio)
2485 			_rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2486 		if (rtlpriv->rtlhal.during_mac1init_radioa)
2487 			rtl92d_phy_powerdown_anotherphy(hw, false);
2488 	} else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) {
2489 		u4tmp = curveindex_2g[channel-1];
2490 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2491 			"ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
2492 		if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2493 			rtlpriv->rtlhal.interfaceindex == 0) {
2494 			bneed_powerdown_radio =
2495 				rtl92d_phy_enable_anotherphy(hw, true);
2496 			rtlpriv->rtlhal.during_mac0init_radiob = true;
2497 			if (bneed_powerdown_radio)
2498 				_rtl92d_phy_enable_rf_env(hw, erfpath,
2499 							  &u4regvalue);
2500 		}
2501 		rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2502 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2503 			"ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
2504 			rtl_get_rfreg(hw,  erfpath, RF_SYN_G4, 0x3f800));
2505 		if (bneed_powerdown_radio)
2506 			_rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2507 		if (rtlpriv->rtlhal.during_mac0init_radiob)
2508 			rtl92d_phy_powerdown_anotherphy(hw, true);
2509 	}
2510 	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2511 }
2512 
2513 static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2514 {
2515 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2516 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2517 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2518 	u8 tmpreg, index, rf_mode[2];
2519 	u8 path = is2t ? 2 : 1;
2520 	u8 i;
2521 	u32 u4tmp, offset;
2522 	u32 curvecount_val[CV_CURVE_CNT * 2] = {0};
2523 	u16 timeout = 800, timecount = 0;
2524 
2525 	/* Check continuous TX and Packet TX */
2526 	tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2527 	/* if Deal with contisuous TX case, disable all continuous TX */
2528 	/* if Deal with Packet TX case, block all queues */
2529 	if ((tmpreg & 0x70) != 0)
2530 		rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2531 	else
2532 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2533 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F);
2534 	for (index = 0; index < path; index++) {
2535 		/* 1. Read original RF mode */
2536 		offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2537 		rf_mode[index] = rtl_read_byte(rtlpriv, offset);
2538 		/* 2. Set RF mode = standby mode */
2539 		rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
2540 			      RFREG_OFFSET_MASK, 0x010000);
2541 		if (rtlpci->init_ready) {
2542 			/* switch CV-curve control by LC-calibration */
2543 			rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2544 				      BIT(17), 0x0);
2545 			/* 4. Set LC calibration begin */
2546 			rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2547 				      0x08000, 0x01);
2548 		}
2549 		u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
2550 				  RFREG_OFFSET_MASK);
2551 		while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
2552 			mdelay(50);
2553 			timecount += 50;
2554 			u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
2555 					      RF_SYN_G6, RFREG_OFFSET_MASK);
2556 		}
2557 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2558 			"PHY_LCK finish delay for %d ms=2\n", timecount);
2559 		rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK);
2560 		if (index == 0 && rtlhal->interfaceindex == 0) {
2561 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
2562 				"path-A / 5G LCK\n");
2563 		} else {
2564 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
2565 				"path-B / 2.4G LCK\n");
2566 		}
2567 		memset(curvecount_val, 0, sizeof(curvecount_val));
2568 		/* Set LC calibration off */
2569 		rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2570 			      0x08000, 0x0);
2571 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "set RF 0x18[15] = 0\n");
2572 		/* save Curve-counting number */
2573 		for (i = 0; i < CV_CURVE_CNT; i++) {
2574 			u32 readval = 0, readval2 = 0;
2575 			rtl_set_rfreg(hw, (enum radio_path)index, 0x3F,
2576 				      0x7f, i);
2577 
2578 			rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2579 				RFREG_OFFSET_MASK, 0x0);
2580 			readval = rtl_get_rfreg(hw, (enum radio_path)index,
2581 					  0x4F, RFREG_OFFSET_MASK);
2582 			curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2583 			/* reg 0x4f [4:0] */
2584 			/* reg 0x50 [19:10] */
2585 			readval2 = rtl_get_rfreg(hw, (enum radio_path)index,
2586 						 0x50, 0xffc00);
2587 			curvecount_val[2 * i] = (((readval & 0x1F) << 10) |
2588 						 readval2);
2589 		}
2590 		if (index == 0 && rtlhal->interfaceindex == 0)
2591 			_rtl92d_phy_calc_curvindex(hw, targetchnl_5g,
2592 						   curvecount_val,
2593 						   true, curveindex_5g);
2594 		else
2595 			_rtl92d_phy_calc_curvindex(hw, targetchnl_2g,
2596 						   curvecount_val,
2597 						   false, curveindex_2g);
2598 		/* switch CV-curve control mode */
2599 		rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2600 			      BIT(17), 0x1);
2601 	}
2602 
2603 	/* Restore original situation  */
2604 	for (index = 0; index < path; index++) {
2605 		offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2606 		rtl_write_byte(rtlpriv, offset, 0x50);
2607 		rtl_write_byte(rtlpriv, offset, rf_mode[index]);
2608 	}
2609 	if ((tmpreg & 0x70) != 0)
2610 		rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2611 	else /*Deal with Packet TX case */
2612 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2613 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00);
2614 	_rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel);
2615 }
2616 
2617 static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2618 {
2619 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2620 
2621 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "cosa PHY_LCK ver=2\n");
2622 	_rtl92d_phy_lc_calibrate_sw(hw, is2t);
2623 }
2624 
2625 void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw)
2626 {
2627 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2628 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2629 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2630 	u32 timeout = 2000, timecount = 0;
2631 
2632 	while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2633 		udelay(50);
2634 		timecount += 50;
2635 	}
2636 
2637 	rtlphy->lck_inprogress = true;
2638 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
2639 		"LCK:Start!!! currentband %x delay %d ms\n",
2640 		rtlhal->current_bandtype, timecount);
2641 	if (IS_92D_SINGLEPHY(rtlhal->version)) {
2642 		_rtl92d_phy_lc_calibrate(hw, true);
2643 	} else {
2644 		/* For 1T1R */
2645 		_rtl92d_phy_lc_calibrate(hw, false);
2646 	}
2647 	rtlphy->lck_inprogress = false;
2648 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LCK:Finish!!!\n");
2649 }
2650 
2651 void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
2652 {
2653 	return;
2654 }
2655 
2656 static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
2657 		u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
2658 		u32 para1, u32 para2, u32 msdelay)
2659 {
2660 	struct swchnlcmd *pcmd;
2661 
2662 	if (cmdtable == NULL) {
2663 		WARN_ONCE(true, "rtl8192de: cmdtable cannot be NULL\n");
2664 		return false;
2665 	}
2666 	if (cmdtableidx >= cmdtablesz)
2667 		return false;
2668 
2669 	pcmd = cmdtable + cmdtableidx;
2670 	pcmd->cmdid = cmdid;
2671 	pcmd->para1 = para1;
2672 	pcmd->para2 = para2;
2673 	pcmd->msdelay = msdelay;
2674 	return true;
2675 }
2676 
2677 void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw)
2678 {
2679 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2680 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2681 	u8 i;
2682 
2683 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
2684 		"settings regs %zu default regs %d\n",
2685 		ARRAY_SIZE(rtlphy->iqk_matrix),
2686 		IQK_MATRIX_REG_NUM);
2687 	/* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
2688 	for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
2689 		rtlphy->iqk_matrix[i].value[0][0] = 0x100;
2690 		rtlphy->iqk_matrix[i].value[0][2] = 0x100;
2691 		rtlphy->iqk_matrix[i].value[0][4] = 0x100;
2692 		rtlphy->iqk_matrix[i].value[0][6] = 0x100;
2693 		rtlphy->iqk_matrix[i].value[0][1] = 0x0;
2694 		rtlphy->iqk_matrix[i].value[0][3] = 0x0;
2695 		rtlphy->iqk_matrix[i].value[0][5] = 0x0;
2696 		rtlphy->iqk_matrix[i].value[0][7] = 0x0;
2697 		rtlphy->iqk_matrix[i].iqk_done = false;
2698 	}
2699 }
2700 
2701 static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
2702 					     u8 channel, u8 *stage, u8 *step,
2703 					     u32 *delay)
2704 {
2705 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2706 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2707 	struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
2708 	u32 precommoncmdcnt;
2709 	struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
2710 	u32 postcommoncmdcnt;
2711 	struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
2712 	u32 rfdependcmdcnt;
2713 	struct swchnlcmd *currentcmd = NULL;
2714 	u8 rfpath;
2715 	u8 num_total_rfpath = rtlphy->num_total_rfpath;
2716 
2717 	precommoncmdcnt = 0;
2718 	_rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2719 					 MAX_PRECMD_CNT,
2720 					 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
2721 	_rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2722 					 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
2723 	postcommoncmdcnt = 0;
2724 	_rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
2725 					 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
2726 	rfdependcmdcnt = 0;
2727 	_rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2728 					 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
2729 					 RF_CHNLBW, channel, 0);
2730 	_rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2731 					 MAX_RFDEPENDCMD_CNT, CMDID_END,
2732 					 0, 0, 0);
2733 
2734 	do {
2735 		switch (*stage) {
2736 		case 0:
2737 			currentcmd = &precommoncmd[*step];
2738 			break;
2739 		case 1:
2740 			currentcmd = &rfdependcmd[*step];
2741 			break;
2742 		case 2:
2743 			currentcmd = &postcommoncmd[*step];
2744 			break;
2745 		}
2746 		if (currentcmd->cmdid == CMDID_END) {
2747 			if ((*stage) == 2) {
2748 				return true;
2749 			} else {
2750 				(*stage)++;
2751 				(*step) = 0;
2752 				continue;
2753 			}
2754 		}
2755 		switch (currentcmd->cmdid) {
2756 		case CMDID_SET_TXPOWEROWER_LEVEL:
2757 			rtl92d_phy_set_txpower_level(hw, channel);
2758 			break;
2759 		case CMDID_WRITEPORT_ULONG:
2760 			rtl_write_dword(rtlpriv, currentcmd->para1,
2761 					currentcmd->para2);
2762 			break;
2763 		case CMDID_WRITEPORT_USHORT:
2764 			rtl_write_word(rtlpriv, currentcmd->para1,
2765 				       (u16)currentcmd->para2);
2766 			break;
2767 		case CMDID_WRITEPORT_UCHAR:
2768 			rtl_write_byte(rtlpriv, currentcmd->para1,
2769 				       (u8)currentcmd->para2);
2770 			break;
2771 		case CMDID_RF_WRITEREG:
2772 			for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
2773 				rtlphy->rfreg_chnlval[rfpath] =
2774 					((rtlphy->rfreg_chnlval[rfpath] &
2775 					0xffffff00) | currentcmd->para2);
2776 				if (rtlpriv->rtlhal.current_bandtype ==
2777 				    BAND_ON_5G) {
2778 					if (currentcmd->para2 > 99)
2779 						rtlphy->rfreg_chnlval[rfpath] =
2780 						    rtlphy->rfreg_chnlval
2781 						    [rfpath] | (BIT(18));
2782 					else
2783 						rtlphy->rfreg_chnlval[rfpath] =
2784 						    rtlphy->rfreg_chnlval
2785 						    [rfpath] & (~BIT(18));
2786 					rtlphy->rfreg_chnlval[rfpath] |=
2787 						 (BIT(16) | BIT(8));
2788 				} else {
2789 					rtlphy->rfreg_chnlval[rfpath] &=
2790 						~(BIT(8) | BIT(16) | BIT(18));
2791 				}
2792 				rtl_set_rfreg(hw, (enum radio_path)rfpath,
2793 					      currentcmd->para1,
2794 					      RFREG_OFFSET_MASK,
2795 					      rtlphy->rfreg_chnlval[rfpath]);
2796 				_rtl92d_phy_reload_imr_setting(hw, channel,
2797 							       rfpath);
2798 			}
2799 			_rtl92d_phy_switch_rf_setting(hw, channel);
2800 			/* do IQK when all parameters are ready */
2801 			rtl92d_phy_reload_iqk_setting(hw, channel);
2802 			break;
2803 		default:
2804 			pr_err("switch case %#x not processed\n",
2805 			       currentcmd->cmdid);
2806 			break;
2807 		}
2808 		break;
2809 	} while (true);
2810 	(*delay) = currentcmd->msdelay;
2811 	(*step)++;
2812 	return false;
2813 }
2814 
2815 u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
2816 {
2817 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2818 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2819 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2820 	u32 delay;
2821 	u32 timeout = 1000, timecount = 0;
2822 	u8 channel = rtlphy->current_channel;
2823 	u32 ret_value;
2824 
2825 	if (rtlphy->sw_chnl_inprogress)
2826 		return 0;
2827 	if (rtlphy->set_bwmode_inprogress)
2828 		return 0;
2829 
2830 	if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
2831 		rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
2832 			"sw_chnl_inprogress false driver sleep or unload\n");
2833 		return 0;
2834 	}
2835 	while (rtlphy->lck_inprogress && timecount < timeout) {
2836 		mdelay(50);
2837 		timecount += 50;
2838 	}
2839 	if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
2840 	    rtlhal->bandset == BAND_ON_BOTH) {
2841 		ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
2842 					  MASKDWORD);
2843 		if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
2844 			rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
2845 		else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
2846 			rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G);
2847 	}
2848 	switch (rtlhal->current_bandtype) {
2849 	case BAND_ON_5G:
2850 		/* Get first channel error when change between
2851 		 * 5G and 2.4G band. */
2852 		if (WARN_ONCE(channel <= 14, "rtl8192de: 5G but channel<=14\n"))
2853 			return 0;
2854 		break;
2855 	case BAND_ON_2_4G:
2856 		/* Get first channel error when change between
2857 		 * 5G and 2.4G band. */
2858 		if (WARN_ONCE(channel > 14, "rtl8192de: 2G but channel>14\n"))
2859 			return 0;
2860 		break;
2861 	default:
2862 		WARN_ONCE(true, "rtl8192de: Invalid WirelessMode(%#x)!!\n",
2863 			  rtlpriv->mac80211.mode);
2864 		break;
2865 	}
2866 	rtlphy->sw_chnl_inprogress = true;
2867 	if (channel == 0)
2868 		channel = 1;
2869 	rtlphy->sw_chnl_stage = 0;
2870 	rtlphy->sw_chnl_step = 0;
2871 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
2872 		"switch to channel%d\n", rtlphy->current_channel);
2873 
2874 	do {
2875 		if (!rtlphy->sw_chnl_inprogress)
2876 			break;
2877 		if (!_rtl92d_phy_sw_chnl_step_by_step(hw,
2878 						      rtlphy->current_channel,
2879 		    &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) {
2880 			if (delay > 0)
2881 				mdelay(delay);
2882 			else
2883 				continue;
2884 		} else {
2885 			rtlphy->sw_chnl_inprogress = false;
2886 		}
2887 		break;
2888 	} while (true);
2889 	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
2890 	rtlphy->sw_chnl_inprogress = false;
2891 	return 1;
2892 }
2893 
2894 static void rtl92d_phy_set_io(struct ieee80211_hw *hw)
2895 {
2896 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2897 	struct dig_t *de_digtable = &rtlpriv->dm_digtable;
2898 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2899 
2900 	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2901 		"--->Cmd(%#x), set_io_inprogress(%d)\n",
2902 		rtlphy->current_io_type, rtlphy->set_io_inprogress);
2903 	switch (rtlphy->current_io_type) {
2904 	case IO_CMD_RESUME_DM_BY_SCAN:
2905 		de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
2906 		rtl92d_dm_write_dig(hw);
2907 		rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
2908 		break;
2909 	case IO_CMD_PAUSE_DM_BY_SCAN:
2910 		rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue;
2911 		de_digtable->cur_igvalue = 0x37;
2912 		rtl92d_dm_write_dig(hw);
2913 		break;
2914 	default:
2915 		pr_err("switch case %#x not processed\n",
2916 		       rtlphy->current_io_type);
2917 		break;
2918 	}
2919 	rtlphy->set_io_inprogress = false;
2920 	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n",
2921 		rtlphy->current_io_type);
2922 }
2923 
2924 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2925 {
2926 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2927 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2928 	bool postprocessing = false;
2929 
2930 	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2931 		"-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2932 		 iotype, rtlphy->set_io_inprogress);
2933 	do {
2934 		switch (iotype) {
2935 		case IO_CMD_RESUME_DM_BY_SCAN:
2936 			rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2937 				"[IO CMD] Resume DM after scan\n");
2938 			postprocessing = true;
2939 			break;
2940 		case IO_CMD_PAUSE_DM_BY_SCAN:
2941 			rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
2942 				"[IO CMD] Pause DM before scan\n");
2943 			postprocessing = true;
2944 			break;
2945 		default:
2946 			pr_err("switch case %#x not processed\n",
2947 			       iotype);
2948 			break;
2949 		}
2950 	} while (false);
2951 	if (postprocessing && !rtlphy->set_io_inprogress) {
2952 		rtlphy->set_io_inprogress = true;
2953 		rtlphy->current_io_type = iotype;
2954 	} else {
2955 		return false;
2956 	}
2957 	rtl92d_phy_set_io(hw);
2958 	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
2959 	return true;
2960 }
2961 
2962 static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw)
2963 {
2964 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2965 
2966 	/* a.  SYS_CLKR 0x08[11] = 1  restore MAC clock */
2967 	/* b.  SPS_CTRL 0x11[7:0] = 0x2b */
2968 	if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
2969 		rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
2970 	/* c.  For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */
2971 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2972 	/* RF_ON_EXCEP(d~g): */
2973 	/* d.  APSD_CTRL 0x600[7:0] = 0x00 */
2974 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2975 	/* e.  SYS_FUNC_EN 0x02[7:0] = 0xE2  reset BB TRX function again */
2976 	/* f.  SYS_FUNC_EN 0x02[7:0] = 0xE3  enable BB TRX function*/
2977 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2978 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2979 	/* g.   txpause 0x522[7:0] = 0x00  enable mac tx queue */
2980 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2981 }
2982 
2983 static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
2984 {
2985 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2986 	u32 u4btmp;
2987 	u8 delay = 5;
2988 
2989 	/* a.   TXPAUSE 0x522[7:0] = 0xFF  Pause MAC TX queue  */
2990 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2991 	/* b.   RF path 0 offset 0x00 = 0x00  disable RF  */
2992 	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2993 	/* c.   APSD_CTRL 0x600[7:0] = 0x40 */
2994 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
2995 	/* d. APSD_CTRL 0x600[7:0] = 0x00
2996 	 * APSD_CTRL 0x600[7:0] = 0x00
2997 	 * RF path 0 offset 0x00 = 0x00
2998 	 * APSD_CTRL 0x600[7:0] = 0x40
2999 	 * */
3000 	u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3001 	while (u4btmp != 0 && delay > 0) {
3002 		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
3003 		rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3004 		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3005 		u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3006 		delay--;
3007 	}
3008 	if (delay == 0) {
3009 		/* Jump out the LPS turn off sequence to RF_ON_EXCEP */
3010 		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3011 
3012 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3013 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3014 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3015 		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
3016 			"Fail !!! Switch RF timeout\n");
3017 		return;
3018 	}
3019 	/* e.   For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */
3020 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3021 	/* f.   SPS_CTRL 0x11[7:0] = 0x22 */
3022 	if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3023 		rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3024 	/* g.    SYS_CLKR 0x08[11] = 0  gated MAC clock */
3025 }
3026 
3027 bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
3028 				   enum rf_pwrstate rfpwr_state)
3029 {
3030 
3031 	bool bresult = true;
3032 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3033 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3034 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3035 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3036 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3037 	u8 i, queue_id;
3038 	struct rtl8192_tx_ring *ring = NULL;
3039 
3040 	if (rfpwr_state == ppsc->rfpwr_state)
3041 		return false;
3042 	switch (rfpwr_state) {
3043 	case ERFON:
3044 		if ((ppsc->rfpwr_state == ERFOFF) &&
3045 		    RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3046 			bool rtstatus;
3047 			u32 initializecount = 0;
3048 			do {
3049 				initializecount++;
3050 				rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3051 					"IPS Set eRf nic enable\n");
3052 				rtstatus = rtl_ps_enable_nic(hw);
3053 			} while (!rtstatus && (initializecount < 10));
3054 
3055 			RT_CLEAR_PS_LEVEL(ppsc,
3056 					  RT_RF_OFF_LEVL_HALT_NIC);
3057 		} else {
3058 			rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
3059 				"awake, slept:%d ms state_inap:%x\n",
3060 				jiffies_to_msecs(jiffies -
3061 						 ppsc->last_sleep_jiffies),
3062 				 rtlpriv->psc.state_inap);
3063 			ppsc->last_awake_jiffies = jiffies;
3064 			_rtl92d_phy_set_rfon(hw);
3065 		}
3066 
3067 		if (mac->link_state == MAC80211_LINKED)
3068 			rtlpriv->cfg->ops->led_control(hw,
3069 					 LED_CTL_LINK);
3070 		else
3071 			rtlpriv->cfg->ops->led_control(hw,
3072 					 LED_CTL_NO_LINK);
3073 		break;
3074 	case ERFOFF:
3075 		if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3076 			rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
3077 				"IPS Set eRf nic disable\n");
3078 			rtl_ps_disable_nic(hw);
3079 			RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3080 		} else {
3081 			if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
3082 				rtlpriv->cfg->ops->led_control(hw,
3083 						 LED_CTL_NO_LINK);
3084 			else
3085 				rtlpriv->cfg->ops->led_control(hw,
3086 						 LED_CTL_POWER_OFF);
3087 		}
3088 		break;
3089 	case ERFSLEEP:
3090 		if (ppsc->rfpwr_state == ERFOFF)
3091 			return false;
3092 
3093 		for (queue_id = 0, i = 0;
3094 		     queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3095 			ring = &pcipriv->dev.tx_ring[queue_id];
3096 			if (skb_queue_len(&ring->queue) == 0 ||
3097 			    queue_id == BEACON_QUEUE) {
3098 				queue_id++;
3099 				continue;
3100 			} else if (rtlpci->pdev->current_state != PCI_D0) {
3101 				rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
3102 					"eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n",
3103 					i + 1, queue_id);
3104 				break;
3105 			} else {
3106 				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3107 					"eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3108 					i + 1, queue_id,
3109 					skb_queue_len(&ring->queue));
3110 				udelay(10);
3111 				i++;
3112 			}
3113 
3114 			if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3115 				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
3116 					"ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
3117 					MAX_DOZE_WAITING_TIMES_9x, queue_id,
3118 					skb_queue_len(&ring->queue));
3119 				break;
3120 			}
3121 		}
3122 		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
3123 			"Set rfsleep awakened:%d ms\n",
3124 			 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
3125 		rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
3126 			"sleep awakened:%d ms state_inap:%x\n",
3127 			jiffies_to_msecs(jiffies -
3128 					 ppsc->last_awake_jiffies),
3129 			rtlpriv->psc.state_inap);
3130 		ppsc->last_sleep_jiffies = jiffies;
3131 		_rtl92d_phy_set_rfsleep(hw);
3132 		break;
3133 	default:
3134 		pr_err("switch case %#x not processed\n",
3135 		       rfpwr_state);
3136 		bresult = false;
3137 		break;
3138 	}
3139 	if (bresult)
3140 		ppsc->rfpwr_state = rfpwr_state;
3141 	return bresult;
3142 }
3143 
3144 void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw)
3145 {
3146 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3147 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3148 	u8 offset = REG_MAC_PHY_CTRL_NORMAL;
3149 
3150 	switch (rtlhal->macphymode) {
3151 	case DUALMAC_DUALPHY:
3152 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3153 			"MacPhyMode: DUALMAC_DUALPHY\n");
3154 		rtl_write_byte(rtlpriv, offset, 0xF3);
3155 		break;
3156 	case SINGLEMAC_SINGLEPHY:
3157 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3158 			"MacPhyMode: SINGLEMAC_SINGLEPHY\n");
3159 		rtl_write_byte(rtlpriv, offset, 0xF4);
3160 		break;
3161 	case DUALMAC_SINGLEPHY:
3162 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3163 			"MacPhyMode: DUALMAC_SINGLEPHY\n");
3164 		rtl_write_byte(rtlpriv, offset, 0xF1);
3165 		break;
3166 	}
3167 }
3168 
3169 void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw)
3170 {
3171 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3172 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3173 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
3174 
3175 	switch (rtlhal->macphymode) {
3176 	case DUALMAC_SINGLEPHY:
3177 		rtlphy->rf_type = RF_2T2R;
3178 		rtlhal->version |= RF_TYPE_2T2R;
3179 		rtlhal->bandset = BAND_ON_BOTH;
3180 		rtlhal->current_bandtype = BAND_ON_2_4G;
3181 		break;
3182 
3183 	case SINGLEMAC_SINGLEPHY:
3184 		rtlphy->rf_type = RF_2T2R;
3185 		rtlhal->version |= RF_TYPE_2T2R;
3186 		rtlhal->bandset = BAND_ON_BOTH;
3187 		rtlhal->current_bandtype = BAND_ON_2_4G;
3188 		break;
3189 
3190 	case DUALMAC_DUALPHY:
3191 		rtlphy->rf_type = RF_1T1R;
3192 		rtlhal->version &= RF_TYPE_1T1R;
3193 		/* Now we let MAC0 run on 5G band. */
3194 		if (rtlhal->interfaceindex == 0) {
3195 			rtlhal->bandset = BAND_ON_5G;
3196 			rtlhal->current_bandtype = BAND_ON_5G;
3197 		} else {
3198 			rtlhal->bandset = BAND_ON_2_4G;
3199 			rtlhal->current_bandtype = BAND_ON_2_4G;
3200 		}
3201 		break;
3202 	default:
3203 		break;
3204 	}
3205 }
3206 
3207 u8 rtl92d_get_chnlgroup_fromarray(u8 chnl)
3208 {
3209 	u8 group;
3210 
3211 	if (channel_all[chnl] <= 3)
3212 		group = 0;
3213 	else if (channel_all[chnl] <= 9)
3214 		group = 1;
3215 	else if (channel_all[chnl] <= 14)
3216 		group = 2;
3217 	else if (channel_all[chnl] <= 44)
3218 		group = 3;
3219 	else if (channel_all[chnl] <= 54)
3220 		group = 4;
3221 	else if (channel_all[chnl] <= 64)
3222 		group = 5;
3223 	else if (channel_all[chnl] <= 112)
3224 		group = 6;
3225 	else if (channel_all[chnl] <= 126)
3226 		group = 7;
3227 	else if (channel_all[chnl] <= 140)
3228 		group = 8;
3229 	else if (channel_all[chnl] <= 153)
3230 		group = 9;
3231 	else if (channel_all[chnl] <= 159)
3232 		group = 10;
3233 	else
3234 		group = 11;
3235 	return group;
3236 }
3237 
3238 void rtl92d_phy_set_poweron(struct ieee80211_hw *hw)
3239 {
3240 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3241 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3242 	unsigned long flags;
3243 	u8 value8;
3244 	u16 i;
3245 	u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
3246 
3247 	/* notice fw know band status  0x81[1]/0x53[1] = 0: 5G, 1: 2G */
3248 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3249 		value8 = rtl_read_byte(rtlpriv, mac_reg);
3250 		value8 |= BIT(1);
3251 		rtl_write_byte(rtlpriv, mac_reg, value8);
3252 	} else {
3253 		value8 = rtl_read_byte(rtlpriv, mac_reg);
3254 		value8 &= (~BIT(1));
3255 		rtl_write_byte(rtlpriv, mac_reg, value8);
3256 	}
3257 
3258 	if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3259 		value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3260 		rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3261 	} else {
3262 		spin_lock_irqsave(&globalmutex_power, flags);
3263 		if (rtlhal->interfaceindex == 0) {
3264 			value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3265 			rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3266 		} else {
3267 			value8 = rtl_read_byte(rtlpriv, REG_MAC1);
3268 			rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON);
3269 		}
3270 		value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3271 		spin_unlock_irqrestore(&globalmutex_power, flags);
3272 		for (i = 0; i < 200; i++) {
3273 			if ((value8 & BIT(7)) == 0) {
3274 				break;
3275 			} else {
3276 				udelay(500);
3277 				spin_lock_irqsave(&globalmutex_power, flags);
3278 				value8 = rtl_read_byte(rtlpriv,
3279 						    REG_POWER_OFF_IN_PROCESS);
3280 				spin_unlock_irqrestore(&globalmutex_power,
3281 						       flags);
3282 			}
3283 		}
3284 		if (i == 200)
3285 			WARN_ONCE(true, "rtl8192de: Another mac power off over time\n");
3286 	}
3287 }
3288 
3289 void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw)
3290 {
3291 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3292 
3293 	switch (rtlpriv->rtlhal.macphymode) {
3294 	case DUALMAC_DUALPHY:
3295 		rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3296 		rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3297 		rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3298 		break;
3299 	case DUALMAC_SINGLEPHY:
3300 		rtl_write_byte(rtlpriv, REG_DMC, 0xf8);
3301 		rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3302 		rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3303 		break;
3304 	case SINGLEMAC_SINGLEPHY:
3305 		rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3306 		rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10);
3307 		rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
3308 		break;
3309 	default:
3310 		break;
3311 	}
3312 }
3313 
3314 void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3315 {
3316 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3317 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3318 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
3319 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3320 	u8 rfpath, i;
3321 
3322 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
3323 	/* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */
3324 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3325 		/* r_select_5G for path_A/B,0x878 */
3326 		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0);
3327 		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0);
3328 		if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3329 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0);
3330 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0);
3331 		}
3332 		/* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */
3333 		rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
3334 		/* fc_area  0xd2c */
3335 		rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
3336 		/* 5G LAN ON */
3337 		rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3338 		/* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3339 		rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3340 			      0x40000100);
3341 		rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3342 			      0x40000100);
3343 		if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3344 			rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3345 				      BIT(10) | BIT(6) | BIT(5),
3346 				      ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3347 				      (rtlefuse->eeprom_c9 & BIT(1)) |
3348 				      ((rtlefuse->eeprom_cc & BIT(1)) << 4));
3349 			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3350 				      BIT(10) | BIT(6) | BIT(5),
3351 				      ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3352 				      ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3353 				      ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3354 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0);
3355 		} else {
3356 			rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3357 				      BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3358 				      BIT(6) | BIT(5),
3359 				      ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3360 				      (rtlefuse->eeprom_c9 & BIT(1)) |
3361 				      ((rtlefuse->eeprom_cc & BIT(1)) << 4) |
3362 				      ((rtlefuse->eeprom_c9 & BIT(7)) << 9) |
3363 				      ((rtlefuse->eeprom_c9 & BIT(5)) << 12) |
3364 				      ((rtlefuse->eeprom_cc & BIT(3)) << 18));
3365 			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3366 				      BIT(10) | BIT(6) | BIT(5),
3367 				      ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3368 				      ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3369 				      ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3370 			rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
3371 				      BIT(10) | BIT(6) | BIT(5),
3372 				      ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) |
3373 				      ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) |
3374 				      ((rtlefuse->eeprom_cc & BIT(2)) << 3));
3375 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3376 				      BIT(31) | BIT(15), 0);
3377 		}
3378 		/* 1.5V_LDO */
3379 	} else {
3380 		/* r_select_5G for path_A/B */
3381 		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1);
3382 		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1);
3383 		if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3384 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1);
3385 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1);
3386 		}
3387 		/* rssi_table_select:index 0 for 2.4G.1~3 for 5G */
3388 		rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
3389 		/* fc_area */
3390 		rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
3391 		/* 5G LAN ON */
3392 		rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3393 		/* TX BB gain shift,Just for testchip,0xc80,0xc88 */
3394 		if (rtlefuse->internal_pa_5g[0])
3395 			rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3396 				      0x2d4000b5);
3397 		else
3398 			rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3399 				      0x20000080);
3400 		if (rtlefuse->internal_pa_5g[1])
3401 			rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3402 				      0x2d4000b5);
3403 		else
3404 			rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3405 				      0x20000080);
3406 		if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3407 			rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3408 				      BIT(10) | BIT(6) | BIT(5),
3409 				      (rtlefuse->eeprom_cc & BIT(5)));
3410 			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3411 				      ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3412 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15),
3413 				      (rtlefuse->eeprom_cc & BIT(4)) >> 4);
3414 		} else {
3415 			rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3416 				      BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3417 				      BIT(6) | BIT(5),
3418 				      (rtlefuse->eeprom_cc & BIT(5)) |
3419 				      ((rtlefuse->eeprom_cc & BIT(7)) << 14));
3420 			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3421 				      ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3422 			rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10),
3423 				      ((rtlefuse->eeprom_cc & BIT(6)) >> 6));
3424 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3425 				      BIT(31) | BIT(15),
3426 				      ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
3427 				      ((rtlefuse->eeprom_cc & BIT(6)) << 10));
3428 		}
3429 	}
3430 	/* update IQK related settings */
3431 	rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
3432 	rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
3433 	rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00);
3434 	rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3435 		      BIT(26) | BIT(24), 0x00);
3436 	rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00);
3437 	rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
3438 	rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
3439 
3440 	/* Update RF */
3441 	for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3442 	     rfpath++) {
3443 		if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3444 			/* MOD_AG for RF path_A 0x18 BIT8,BIT16 */
3445 			rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) |
3446 				      BIT(18), 0);
3447 			/* RF0x0b[16:14] =3b'111 */
3448 			rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
3449 				      0x1c000, 0x07);
3450 		} else {
3451 			/* MOD_AG for RF path_A 0x18 BIT8,BIT16 */
3452 			rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) |
3453 				      BIT(16) | BIT(18),
3454 				      (BIT(16) | BIT(8)) >> 8);
3455 		}
3456 	}
3457 	/* Update for all band. */
3458 	/* DMDP */
3459 	if (rtlphy->rf_type == RF_1T1R) {
3460 		/* Use antenna 0,0xc04,0xd04 */
3461 		rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11);
3462 		rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
3463 
3464 		/* enable ad/da clock1 for dual-phy reg0x888 */
3465 		if (rtlhal->interfaceindex == 0) {
3466 			rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) |
3467 				      BIT(13), 0x3);
3468 		} else {
3469 			rtl92d_phy_enable_anotherphy(hw, false);
3470 			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
3471 				"MAC1 use DBI to update 0x888\n");
3472 			/* 0x888 */
3473 			rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN,
3474 						rtl92de_read_dword_dbi(hw,
3475 						RFPGA0_ADDALLOCKEN,
3476 						BIT(3)) | BIT(12) | BIT(13),
3477 						BIT(3));
3478 			rtl92d_phy_powerdown_anotherphy(hw, false);
3479 		}
3480 	} else {
3481 		/* Single PHY */
3482 		/* Use antenna 0 & 1,0xc04,0xd04 */
3483 		rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33);
3484 		rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
3485 		/* disable ad/da clock1,0x888 */
3486 		rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
3487 	}
3488 	for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3489 	     rfpath++) {
3490 		rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
3491 						RF_CHNLBW, RFREG_OFFSET_MASK);
3492 		rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
3493 			RFREG_OFFSET_MASK);
3494 	}
3495 	for (i = 0; i < 2; i++)
3496 		rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n",
3497 			rtlphy->rfreg_chnlval[i]);
3498 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n");
3499 
3500 }
3501 
3502 bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw)
3503 {
3504 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3505 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3506 	u8 u1btmp;
3507 	unsigned long flags;
3508 
3509 	if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3510 		u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3511 		rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3512 		return true;
3513 	}
3514 	spin_lock_irqsave(&globalmutex_power, flags);
3515 	if (rtlhal->interfaceindex == 0) {
3516 		u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3517 		rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3518 		u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3519 		u1btmp &= MAC1_ON;
3520 	} else {
3521 		u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3522 		rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON));
3523 		u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3524 		u1btmp &= MAC0_ON;
3525 	}
3526 	if (u1btmp) {
3527 		spin_unlock_irqrestore(&globalmutex_power, flags);
3528 		return false;
3529 	}
3530 	u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3531 	u1btmp |= BIT(7);
3532 	rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp);
3533 	spin_unlock_irqrestore(&globalmutex_power, flags);
3534 	return true;
3535 }
3536