1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../pci.h" 28 #include "../ps.h" 29 #include "../core.h" 30 #include "reg.h" 31 #include "def.h" 32 #include "phy.h" 33 #include "rf.h" 34 #include "dm.h" 35 #include "table.h" 36 #include "sw.h" 37 #include "hw.h" 38 39 #define MAX_RF_IMR_INDEX 12 40 #define MAX_RF_IMR_INDEX_NORMAL 13 41 #define RF_REG_NUM_FOR_C_CUT_5G 6 42 #define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA 7 43 #define RF_REG_NUM_FOR_C_CUT_2G 5 44 #define RF_CHNL_NUM_5G 19 45 #define RF_CHNL_NUM_5G_40M 17 46 #define TARGET_CHNL_NUM_5G 221 47 #define TARGET_CHNL_NUM_2G 14 48 #define CV_CURVE_CNT 64 49 50 static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = { 51 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0 52 }; 53 54 static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = { 55 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6 56 }; 57 58 static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = { 59 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8 60 }; 61 62 static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = { 63 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E 64 }; 65 66 static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = { 67 BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1), 68 BIT(10) | BIT(9), 69 BIT(18) | BIT(17) | BIT(16) | BIT(1), 70 BIT(2) | BIT(1), 71 BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11) 72 }; 73 74 static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = { 75 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 76 112, 116, 120, 124, 128, 132, 136, 140 77 }; 78 79 static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = { 80 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114, 81 118, 122, 126, 130, 134, 138 82 }; 83 static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = { 84 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04}, 85 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04}, 86 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04}, 87 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04}, 88 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04} 89 }; 90 91 static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = { 92 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}, 93 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840}, 94 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41} 95 }; 96 97 static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF; 98 99 static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = { 100 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12}, 101 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52}, 102 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12} 103 }; 104 105 /* [mode][patha+b][reg] */ 106 static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = { 107 { 108 /* channel 1-14. */ 109 { 110 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0, 111 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff 112 }, 113 /* path 36-64 */ 114 { 115 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000, 116 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090, 117 0x32c9a 118 }, 119 /* 100 -165 */ 120 { 121 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000, 122 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a 123 } 124 } 125 }; 126 127 static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0}; 128 129 static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0}; 130 131 static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = { 132 25141, 25116, 25091, 25066, 25041, 133 25016, 24991, 24966, 24941, 24917, 134 24892, 24867, 24843, 24818, 24794, 135 24770, 24765, 24721, 24697, 24672, 136 24648, 24624, 24600, 24576, 24552, 137 24528, 24504, 24480, 24457, 24433, 138 24409, 24385, 24362, 24338, 24315, 139 24291, 24268, 24245, 24221, 24198, 140 24175, 24151, 24128, 24105, 24082, 141 24059, 24036, 24013, 23990, 23967, 142 23945, 23922, 23899, 23876, 23854, 143 23831, 23809, 23786, 23764, 23741, 144 23719, 23697, 23674, 23652, 23630, 145 23608, 23586, 23564, 23541, 23519, 146 23498, 23476, 23454, 23432, 23410, 147 23388, 23367, 23345, 23323, 23302, 148 23280, 23259, 23237, 23216, 23194, 149 23173, 23152, 23130, 23109, 23088, 150 23067, 23046, 23025, 23003, 22982, 151 22962, 22941, 22920, 22899, 22878, 152 22857, 22837, 22816, 22795, 22775, 153 22754, 22733, 22713, 22692, 22672, 154 22652, 22631, 22611, 22591, 22570, 155 22550, 22530, 22510, 22490, 22469, 156 22449, 22429, 22409, 22390, 22370, 157 22350, 22336, 22310, 22290, 22271, 158 22251, 22231, 22212, 22192, 22173, 159 22153, 22134, 22114, 22095, 22075, 160 22056, 22037, 22017, 21998, 21979, 161 21960, 21941, 21921, 21902, 21883, 162 21864, 21845, 21826, 21807, 21789, 163 21770, 21751, 21732, 21713, 21695, 164 21676, 21657, 21639, 21620, 21602, 165 21583, 21565, 21546, 21528, 21509, 166 21491, 21473, 21454, 21436, 21418, 167 21400, 21381, 21363, 21345, 21327, 168 21309, 21291, 21273, 21255, 21237, 169 21219, 21201, 21183, 21166, 21148, 170 21130, 21112, 21095, 21077, 21059, 171 21042, 21024, 21007, 20989, 20972, 172 25679, 25653, 25627, 25601, 25575, 173 25549, 25523, 25497, 25471, 25446, 174 25420, 25394, 25369, 25343, 25318, 175 25292, 25267, 25242, 25216, 25191, 176 25166 177 }; 178 179 /* channel 1~14 */ 180 static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = { 181 26084, 26030, 25976, 25923, 25869, 25816, 25764, 182 25711, 25658, 25606, 25554, 25502, 25451, 25328 183 }; 184 185 static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask) 186 { 187 u32 i; 188 189 for (i = 0; i <= 31; i++) { 190 if (((bitmask >> i) & 0x1) == 1) 191 break; 192 } 193 194 return i; 195 } 196 197 u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) 198 { 199 struct rtl_priv *rtlpriv = rtl_priv(hw); 200 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 201 u32 returnvalue, originalvalue, bitshift; 202 203 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n", 204 regaddr, bitmask); 205 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) { 206 u8 dbi_direct = 0; 207 208 /* mac1 use phy0 read radio_b. */ 209 /* mac0 use phy1 read radio_b. */ 210 if (rtlhal->during_mac1init_radioa) 211 dbi_direct = BIT(3); 212 else if (rtlhal->during_mac0init_radiob) 213 dbi_direct = BIT(3) | BIT(2); 214 originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr, 215 dbi_direct); 216 } else { 217 originalvalue = rtl_read_dword(rtlpriv, regaddr); 218 } 219 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); 220 returnvalue = (originalvalue & bitmask) >> bitshift; 221 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 222 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", 223 bitmask, regaddr, originalvalue); 224 return returnvalue; 225 } 226 227 void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw, 228 u32 regaddr, u32 bitmask, u32 data) 229 { 230 struct rtl_priv *rtlpriv = rtl_priv(hw); 231 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 232 u8 dbi_direct = 0; 233 u32 originalvalue, bitshift; 234 235 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 236 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 237 regaddr, bitmask, data); 238 if (rtlhal->during_mac1init_radioa) 239 dbi_direct = BIT(3); 240 else if (rtlhal->during_mac0init_radiob) 241 /* mac0 use phy1 write radio_b. */ 242 dbi_direct = BIT(3) | BIT(2); 243 if (bitmask != MASKDWORD) { 244 if (rtlhal->during_mac1init_radioa || 245 rtlhal->during_mac0init_radiob) 246 originalvalue = rtl92de_read_dword_dbi(hw, 247 (u16) regaddr, 248 dbi_direct); 249 else 250 originalvalue = rtl_read_dword(rtlpriv, regaddr); 251 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); 252 data = ((originalvalue & (~bitmask)) | (data << bitshift)); 253 } 254 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) 255 rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct); 256 else 257 rtl_write_dword(rtlpriv, regaddr, data); 258 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 259 "regaddr(%#x), bitmask(%#x), data(%#x)\n", 260 regaddr, bitmask, data); 261 } 262 263 static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw, 264 enum radio_path rfpath, u32 offset) 265 { 266 267 struct rtl_priv *rtlpriv = rtl_priv(hw); 268 struct rtl_phy *rtlphy = &(rtlpriv->phy); 269 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 270 u32 newoffset; 271 u32 tmplong, tmplong2; 272 u8 rfpi_enable = 0; 273 u32 retvalue; 274 275 newoffset = offset; 276 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); 277 if (rfpath == RF90_PATH_A) 278 tmplong2 = tmplong; 279 else 280 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); 281 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | 282 (newoffset << 23) | BLSSIREADEDGE; 283 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 284 tmplong & (~BLSSIREADEDGE)); 285 udelay(10); 286 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); 287 udelay(50); 288 udelay(50); 289 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, 290 tmplong | BLSSIREADEDGE); 291 udelay(10); 292 if (rfpath == RF90_PATH_A) 293 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, 294 BIT(8)); 295 else if (rfpath == RF90_PATH_B) 296 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, 297 BIT(8)); 298 if (rfpi_enable) 299 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, 300 BLSSIREADBACKDATA); 301 else 302 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, 303 BLSSIREADBACKDATA); 304 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n", 305 rfpath, pphyreg->rf_rb, retvalue); 306 return retvalue; 307 } 308 309 static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw, 310 enum radio_path rfpath, 311 u32 offset, u32 data) 312 { 313 u32 data_and_addr; 314 u32 newoffset; 315 struct rtl_priv *rtlpriv = rtl_priv(hw); 316 struct rtl_phy *rtlphy = &(rtlpriv->phy); 317 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 318 319 newoffset = offset; 320 /* T65 RF */ 321 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 322 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); 323 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", 324 rfpath, pphyreg->rf3wire_offset, data_and_addr); 325 } 326 327 u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, 328 enum radio_path rfpath, u32 regaddr, u32 bitmask) 329 { 330 struct rtl_priv *rtlpriv = rtl_priv(hw); 331 u32 original_value, readback_value, bitshift; 332 unsigned long flags; 333 334 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 335 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", 336 regaddr, rfpath, bitmask); 337 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 338 original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr); 339 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); 340 readback_value = (original_value & bitmask) >> bitshift; 341 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 342 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 343 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", 344 regaddr, rfpath, bitmask, original_value); 345 return readback_value; 346 } 347 348 void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, 349 u32 regaddr, u32 bitmask, u32 data) 350 { 351 struct rtl_priv *rtlpriv = rtl_priv(hw); 352 struct rtl_phy *rtlphy = &(rtlpriv->phy); 353 u32 original_value, bitshift; 354 unsigned long flags; 355 356 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 357 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 358 regaddr, bitmask, data, rfpath); 359 if (bitmask == 0) 360 return; 361 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 362 if (rtlphy->rf_mode != RF_OP_BY_FW) { 363 if (bitmask != RFREG_OFFSET_MASK) { 364 original_value = _rtl92d_phy_rf_serial_read(hw, 365 rfpath, regaddr); 366 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); 367 data = ((original_value & (~bitmask)) | 368 (data << bitshift)); 369 } 370 _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data); 371 } 372 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 373 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 374 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 375 regaddr, bitmask, data, rfpath); 376 } 377 378 bool rtl92d_phy_mac_config(struct ieee80211_hw *hw) 379 { 380 struct rtl_priv *rtlpriv = rtl_priv(hw); 381 u32 i; 382 u32 arraylength; 383 u32 *ptrarray; 384 385 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n"); 386 arraylength = MAC_2T_ARRAYLENGTH; 387 ptrarray = rtl8192de_mac_2tarray; 388 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n"); 389 for (i = 0; i < arraylength; i = i + 2) 390 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]); 391 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) { 392 /* improve 2-stream TX EVM */ 393 /* rtl_write_byte(rtlpriv, 0x14,0x71); */ 394 /* AMPDU aggregation number 9 */ 395 /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */ 396 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B); 397 } else { 398 /* 92D need to test to decide the num. */ 399 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07); 400 } 401 return true; 402 } 403 404 static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) 405 { 406 struct rtl_priv *rtlpriv = rtl_priv(hw); 407 struct rtl_phy *rtlphy = &(rtlpriv->phy); 408 409 /* RF Interface Sowrtware Control */ 410 /* 16 LSBs if read 32-bit from 0x870 */ 411 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; 412 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ 413 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; 414 /* 16 LSBs if read 32-bit from 0x874 */ 415 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; 416 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ 417 418 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; 419 /* RF Interface Readback Value */ 420 /* 16 LSBs if read 32-bit from 0x8E0 */ 421 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; 422 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ 423 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; 424 /* 16 LSBs if read 32-bit from 0x8E4 */ 425 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; 426 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ 427 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; 428 429 /* RF Interface Output (and Enable) */ 430 /* 16 LSBs if read 32-bit from 0x860 */ 431 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; 432 /* 16 LSBs if read 32-bit from 0x864 */ 433 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; 434 435 /* RF Interface (Output and) Enable */ 436 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ 437 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; 438 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ 439 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; 440 441 /* Addr of LSSI. Wirte RF register by driver */ 442 /* LSSI Parameter */ 443 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = 444 RFPGA0_XA_LSSIPARAMETER; 445 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = 446 RFPGA0_XB_LSSIPARAMETER; 447 448 /* RF parameter */ 449 /* BB Band Select */ 450 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; 451 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; 452 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; 453 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; 454 455 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ 456 /* Tx gain stage */ 457 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; 458 /* Tx gain stage */ 459 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; 460 /* Tx gain stage */ 461 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; 462 /* Tx gain stage */ 463 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; 464 465 /* Tranceiver A~D HSSI Parameter-1 */ 466 /* wire control parameter1 */ 467 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; 468 /* wire control parameter1 */ 469 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; 470 471 /* Tranceiver A~D HSSI Parameter-2 */ 472 /* wire control parameter2 */ 473 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; 474 /* wire control parameter2 */ 475 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; 476 477 /* RF switch Control */ 478 /* TR/Ant switch control */ 479 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 480 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; 481 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 482 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; 483 484 /* AGC control 1 */ 485 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; 486 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; 487 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; 488 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; 489 490 /* AGC control 2 */ 491 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; 492 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; 493 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; 494 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; 495 496 /* RX AFE control 1 */ 497 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; 498 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; 499 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE; 500 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; 501 502 /*RX AFE control 1 */ 503 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; 504 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; 505 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; 506 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; 507 508 /* Tx AFE control 1 */ 509 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATxIQIMBALANCE; 510 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTxIQIMBALANCE; 511 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTxIQIMBALANCE; 512 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTxIQIMBALANCE; 513 514 /* Tx AFE control 2 */ 515 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATxAFE; 516 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE; 517 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTxAFE; 518 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE; 519 520 /* Tranceiver LSSI Readback SI mode */ 521 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; 522 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; 523 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; 524 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; 525 526 /* Tranceiver LSSI Readback PI mode */ 527 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK; 528 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK; 529 } 530 531 static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 532 u8 configtype) 533 { 534 int i; 535 u32 *phy_regarray_table; 536 u32 *agctab_array_table = NULL; 537 u32 *agctab_5garray_table; 538 u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen; 539 struct rtl_priv *rtlpriv = rtl_priv(hw); 540 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 541 542 /* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */ 543 if (rtlhal->interfaceindex == 0) { 544 agctab_arraylen = AGCTAB_ARRAYLENGTH; 545 agctab_array_table = rtl8192de_agctab_array; 546 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 547 " ===> phy:MAC0, Rtl819XAGCTAB_Array\n"); 548 } else { 549 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 550 agctab_arraylen = AGCTAB_2G_ARRAYLENGTH; 551 agctab_array_table = rtl8192de_agctab_2garray; 552 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 553 " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n"); 554 } else { 555 agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH; 556 agctab_5garray_table = rtl8192de_agctab_5garray; 557 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 558 " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n"); 559 560 } 561 } 562 phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH; 563 phy_regarray_table = rtl8192de_phy_reg_2tarray; 564 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 565 " ===> phy:Rtl819XPHY_REG_Array_PG\n"); 566 if (configtype == BASEBAND_CONFIG_PHY_REG) { 567 for (i = 0; i < phy_reg_arraylen; i = i + 2) { 568 rtl_addr_delay(phy_regarray_table[i]); 569 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, 570 phy_regarray_table[i + 1]); 571 udelay(1); 572 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 573 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", 574 phy_regarray_table[i], 575 phy_regarray_table[i + 1]); 576 } 577 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 578 if (rtlhal->interfaceindex == 0) { 579 for (i = 0; i < agctab_arraylen; i = i + 2) { 580 rtl_set_bbreg(hw, agctab_array_table[i], 581 MASKDWORD, 582 agctab_array_table[i + 1]); 583 /* Add 1us delay between BB/RF register 584 * setting. */ 585 udelay(1); 586 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 587 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", 588 agctab_array_table[i], 589 agctab_array_table[i + 1]); 590 } 591 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 592 "Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n"); 593 } else { 594 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 595 for (i = 0; i < agctab_arraylen; i = i + 2) { 596 rtl_set_bbreg(hw, agctab_array_table[i], 597 MASKDWORD, 598 agctab_array_table[i + 1]); 599 /* Add 1us delay between BB/RF register 600 * setting. */ 601 udelay(1); 602 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 603 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", 604 agctab_array_table[i], 605 agctab_array_table[i + 1]); 606 } 607 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 608 "Load Rtl819XAGCTAB_2GArray\n"); 609 } else { 610 for (i = 0; i < agctab_5garraylen; i = i + 2) { 611 rtl_set_bbreg(hw, 612 agctab_5garray_table[i], 613 MASKDWORD, 614 agctab_5garray_table[i + 1]); 615 /* Add 1us delay between BB/RF registeri 616 * setting. */ 617 udelay(1); 618 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 619 "The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", 620 agctab_5garray_table[i], 621 agctab_5garray_table[i + 1]); 622 } 623 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 624 "Load Rtl819XAGCTAB_5GArray\n"); 625 } 626 } 627 } 628 return true; 629 } 630 631 static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, 632 u32 regaddr, u32 bitmask, 633 u32 data) 634 { 635 struct rtl_priv *rtlpriv = rtl_priv(hw); 636 struct rtl_phy *rtlphy = &(rtlpriv->phy); 637 int index; 638 639 if (regaddr == RTXAGC_A_RATE18_06) 640 index = 0; 641 else if (regaddr == RTXAGC_A_RATE54_24) 642 index = 1; 643 else if (regaddr == RTXAGC_A_CCK1_MCS32) 644 index = 6; 645 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) 646 index = 7; 647 else if (regaddr == RTXAGC_A_MCS03_MCS00) 648 index = 2; 649 else if (regaddr == RTXAGC_A_MCS07_MCS04) 650 index = 3; 651 else if (regaddr == RTXAGC_A_MCS11_MCS08) 652 index = 4; 653 else if (regaddr == RTXAGC_A_MCS15_MCS12) 654 index = 5; 655 else if (regaddr == RTXAGC_B_RATE18_06) 656 index = 8; 657 else if (regaddr == RTXAGC_B_RATE54_24) 658 index = 9; 659 else if (regaddr == RTXAGC_B_CCK1_55_MCS32) 660 index = 14; 661 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) 662 index = 15; 663 else if (regaddr == RTXAGC_B_MCS03_MCS00) 664 index = 10; 665 else if (regaddr == RTXAGC_B_MCS07_MCS04) 666 index = 11; 667 else if (regaddr == RTXAGC_B_MCS11_MCS08) 668 index = 12; 669 else if (regaddr == RTXAGC_B_MCS15_MCS12) 670 index = 13; 671 else 672 return; 673 674 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; 675 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 676 "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", 677 rtlphy->pwrgroup_cnt, index, 678 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]); 679 if (index == 13) 680 rtlphy->pwrgroup_cnt++; 681 } 682 683 static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, 684 u8 configtype) 685 { 686 struct rtl_priv *rtlpriv = rtl_priv(hw); 687 int i; 688 u32 *phy_regarray_table_pg; 689 u16 phy_regarray_pg_len; 690 691 phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH; 692 phy_regarray_table_pg = rtl8192de_phy_reg_array_pg; 693 if (configtype == BASEBAND_CONFIG_PHY_REG) { 694 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { 695 rtl_addr_delay(phy_regarray_table_pg[i]); 696 _rtl92d_store_pwrindex_diffrate_offset(hw, 697 phy_regarray_table_pg[i], 698 phy_regarray_table_pg[i + 1], 699 phy_regarray_table_pg[i + 2]); 700 } 701 } else { 702 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, 703 "configtype != BaseBand_Config_PHY_REG\n"); 704 } 705 return true; 706 } 707 708 static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw) 709 { 710 struct rtl_priv *rtlpriv = rtl_priv(hw); 711 struct rtl_phy *rtlphy = &(rtlpriv->phy); 712 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 713 bool rtstatus = true; 714 715 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n"); 716 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw, 717 BASEBAND_CONFIG_PHY_REG); 718 if (!rtstatus) { 719 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!\n"); 720 return false; 721 } 722 723 /* if (rtlphy->rf_type == RF_1T2R) { 724 * _rtl92c_phy_bb_config_1t(hw); 725 * RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n"); 726 *} */ 727 728 if (rtlefuse->autoload_failflag == false) { 729 rtlphy->pwrgroup_cnt = 0; 730 rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw, 731 BASEBAND_CONFIG_PHY_REG); 732 } 733 if (!rtstatus) { 734 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!\n"); 735 return false; 736 } 737 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw, 738 BASEBAND_CONFIG_AGC_TAB); 739 if (!rtstatus) { 740 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n"); 741 return false; 742 } 743 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw, 744 RFPGA0_XA_HSSIPARAMETER2, 0x200)); 745 746 return true; 747 } 748 749 bool rtl92d_phy_bb_config(struct ieee80211_hw *hw) 750 { 751 struct rtl_priv *rtlpriv = rtl_priv(hw); 752 u16 regval; 753 u32 regvaldw; 754 u8 value; 755 756 _rtl92d_phy_init_bb_rf_register_definition(hw); 757 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 758 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, 759 regval | BIT(13) | BIT(0) | BIT(1)); 760 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83); 761 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb); 762 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */ 763 value = rtl_read_byte(rtlpriv, REG_RF_CTRL); 764 rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB | 765 RF_SDMRSTB); 766 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA | 767 FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB); 768 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); 769 if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) { 770 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0); 771 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23)); 772 } 773 774 return _rtl92d_phy_bb_config(hw); 775 } 776 777 bool rtl92d_phy_rf_config(struct ieee80211_hw *hw) 778 { 779 return rtl92d_phy_rf6052_config(hw); 780 } 781 782 bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 783 enum rf_content content, 784 enum radio_path rfpath) 785 { 786 int i; 787 u32 *radioa_array_table; 788 u32 *radiob_array_table; 789 u16 radioa_arraylen, radiob_arraylen; 790 struct rtl_priv *rtlpriv = rtl_priv(hw); 791 792 radioa_arraylen = RADIOA_2T_ARRAYLENGTH; 793 radioa_array_table = rtl8192de_radioa_2tarray; 794 radiob_arraylen = RADIOB_2T_ARRAYLENGTH; 795 radiob_array_table = rtl8192de_radiob_2tarray; 796 if (rtlpriv->efuse.internal_pa_5g[0]) { 797 radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH; 798 radioa_array_table = rtl8192de_radioa_2t_int_paarray; 799 } 800 if (rtlpriv->efuse.internal_pa_5g[1]) { 801 radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH; 802 radiob_array_table = rtl8192de_radiob_2t_int_paarray; 803 } 804 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 805 "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n"); 806 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 807 "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n"); 808 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath); 809 810 /* this only happens when DMDP, mac0 start on 2.4G, 811 * mac1 start on 5G, mac 0 has to set phy0&phy1 812 * pathA or mac1 has to set phy0&phy1 pathA */ 813 if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) { 814 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 815 " ===> althougth Path A, we load radiob.txt\n"); 816 radioa_arraylen = radiob_arraylen; 817 radioa_array_table = radiob_array_table; 818 } 819 switch (rfpath) { 820 case RF90_PATH_A: 821 for (i = 0; i < radioa_arraylen; i = i + 2) { 822 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i], 823 RFREG_OFFSET_MASK, 824 radioa_array_table[i + 1]); 825 } 826 break; 827 case RF90_PATH_B: 828 for (i = 0; i < radiob_arraylen; i = i + 2) { 829 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i], 830 RFREG_OFFSET_MASK, 831 radiob_array_table[i + 1]); 832 } 833 break; 834 case RF90_PATH_C: 835 case RF90_PATH_D: 836 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 837 "switch case %#x not processed\n", rfpath); 838 break; 839 } 840 return true; 841 } 842 843 void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 844 { 845 struct rtl_priv *rtlpriv = rtl_priv(hw); 846 struct rtl_phy *rtlphy = &(rtlpriv->phy); 847 848 rtlphy->default_initialgain[0] = 849 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); 850 rtlphy->default_initialgain[1] = 851 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); 852 rtlphy->default_initialgain[2] = 853 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); 854 rtlphy->default_initialgain[3] = 855 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); 856 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 857 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", 858 rtlphy->default_initialgain[0], 859 rtlphy->default_initialgain[1], 860 rtlphy->default_initialgain[2], 861 rtlphy->default_initialgain[3]); 862 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, 863 MASKBYTE0); 864 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, 865 MASKDWORD); 866 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 867 "Default framesync (0x%x) = 0x%x\n", 868 ROFDM0_RXDETECTOR3, rtlphy->framesync); 869 } 870 871 static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel, 872 u8 *cckpowerlevel, u8 *ofdmpowerlevel) 873 { 874 struct rtl_priv *rtlpriv = rtl_priv(hw); 875 struct rtl_phy *rtlphy = &(rtlpriv->phy); 876 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 877 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 878 u8 index = (channel - 1); 879 880 /* 1. CCK */ 881 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 882 /* RF-A */ 883 cckpowerlevel[RF90_PATH_A] = 884 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index]; 885 /* RF-B */ 886 cckpowerlevel[RF90_PATH_B] = 887 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index]; 888 } else { 889 cckpowerlevel[RF90_PATH_A] = 0; 890 cckpowerlevel[RF90_PATH_B] = 0; 891 } 892 /* 2. OFDM for 1S or 2S */ 893 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) { 894 /* Read HT 40 OFDM TX power */ 895 ofdmpowerlevel[RF90_PATH_A] = 896 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index]; 897 ofdmpowerlevel[RF90_PATH_B] = 898 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index]; 899 } else if (rtlphy->rf_type == RF_2T2R) { 900 /* Read HT 40 OFDM TX power */ 901 ofdmpowerlevel[RF90_PATH_A] = 902 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index]; 903 ofdmpowerlevel[RF90_PATH_B] = 904 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index]; 905 } 906 } 907 908 static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw, 909 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel) 910 { 911 struct rtl_priv *rtlpriv = rtl_priv(hw); 912 struct rtl_phy *rtlphy = &(rtlpriv->phy); 913 914 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; 915 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; 916 } 917 918 static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl) 919 { 920 u8 place = chnl; 921 922 if (chnl > 14) { 923 for (place = 14; place < sizeof(channel5g); place++) { 924 if (channel5g[place] == chnl) { 925 place++; 926 break; 927 } 928 } 929 } 930 return place; 931 } 932 933 void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) 934 { 935 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 936 struct rtl_priv *rtlpriv = rtl_priv(hw); 937 u8 cckpowerlevel[2], ofdmpowerlevel[2]; 938 939 if (!rtlefuse->txpwr_fromeprom) 940 return; 941 channel = _rtl92c_phy_get_rightchnlplace(channel); 942 _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0], 943 &ofdmpowerlevel[0]); 944 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) 945 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0], 946 &ofdmpowerlevel[0]); 947 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) 948 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); 949 rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel); 950 } 951 952 void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw, 953 enum nl80211_channel_type ch_type) 954 { 955 struct rtl_priv *rtlpriv = rtl_priv(hw); 956 struct rtl_phy *rtlphy = &(rtlpriv->phy); 957 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 958 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 959 unsigned long flag = 0; 960 u8 reg_prsr_rsc; 961 u8 reg_bw_opmode; 962 963 if (rtlphy->set_bwmode_inprogress) 964 return; 965 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { 966 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 967 "FALSE driver sleep or unload\n"); 968 return; 969 } 970 rtlphy->set_bwmode_inprogress = true; 971 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n", 972 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 973 "20MHz" : "40MHz"); 974 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE); 975 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2); 976 switch (rtlphy->current_chan_bw) { 977 case HT_CHANNEL_WIDTH_20: 978 reg_bw_opmode |= BW_OPMODE_20MHZ; 979 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 980 break; 981 case HT_CHANNEL_WIDTH_20_40: 982 reg_bw_opmode &= ~BW_OPMODE_20MHZ; 983 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 984 985 reg_prsr_rsc = (reg_prsr_rsc & 0x90) | 986 (mac->cur_40_prime_sc << 5); 987 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc); 988 break; 989 default: 990 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 991 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); 992 break; 993 } 994 switch (rtlphy->current_chan_bw) { 995 case HT_CHANNEL_WIDTH_20: 996 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); 997 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); 998 /* SET BIT10 BIT11 for receive cck */ 999 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | 1000 BIT(11), 3); 1001 break; 1002 case HT_CHANNEL_WIDTH_20_40: 1003 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); 1004 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); 1005 /* Set Control channel to upper or lower. 1006 * These settings are required only for 40MHz */ 1007 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 1008 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 1009 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND, 1010 (mac->cur_40_prime_sc >> 1)); 1011 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 1012 } 1013 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); 1014 /* SET BIT10 BIT11 for receive cck */ 1015 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | 1016 BIT(11), 0); 1017 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), 1018 (mac->cur_40_prime_sc == 1019 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); 1020 break; 1021 default: 1022 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1023 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); 1024 break; 1025 1026 } 1027 rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 1028 rtlphy->set_bwmode_inprogress = false; 1029 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 1030 } 1031 1032 static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw) 1033 { 1034 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0); 1035 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0); 1036 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); 1037 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); 1038 } 1039 1040 static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band) 1041 { 1042 struct rtl_priv *rtlpriv = rtl_priv(hw); 1043 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1044 u8 value8; 1045 1046 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n"); 1047 rtlhal->bandset = band; 1048 rtlhal->current_bandtype = band; 1049 if (IS_92D_SINGLEPHY(rtlhal->version)) 1050 rtlhal->bandset = BAND_ON_BOTH; 1051 /* stop RX/Tx */ 1052 _rtl92d_phy_stop_trx_before_changeband(hw); 1053 /* reconfig BB/RF according to wireless mode */ 1054 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 1055 /* BB & RF Config */ 1056 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n"); 1057 if (rtlhal->interfaceindex == 1) 1058 _rtl92d_phy_config_bb_with_headerfile(hw, 1059 BASEBAND_CONFIG_AGC_TAB); 1060 } else { 1061 /* 5G band */ 1062 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n"); 1063 if (rtlhal->interfaceindex == 1) 1064 _rtl92d_phy_config_bb_with_headerfile(hw, 1065 BASEBAND_CONFIG_AGC_TAB); 1066 } 1067 rtl92d_update_bbrf_configuration(hw); 1068 if (rtlhal->current_bandtype == BAND_ON_2_4G) 1069 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1070 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1071 1072 /* 20M BW. */ 1073 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */ 1074 rtlhal->reloadtxpowerindex = true; 1075 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ 1076 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 1077 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex == 1078 0 ? REG_MAC0 : REG_MAC1)); 1079 value8 |= BIT(1); 1080 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex == 1081 0 ? REG_MAC0 : REG_MAC1), value8); 1082 } else { 1083 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex == 1084 0 ? REG_MAC0 : REG_MAC1)); 1085 value8 &= (~BIT(1)); 1086 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex == 1087 0 ? REG_MAC0 : REG_MAC1), value8); 1088 } 1089 mdelay(1); 1090 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n"); 1091 } 1092 1093 static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw, 1094 u8 channel, u8 rfpath) 1095 { 1096 struct rtl_priv *rtlpriv = rtl_priv(hw); 1097 u32 imr_num = MAX_RF_IMR_INDEX; 1098 u32 rfmask = RFREG_OFFSET_MASK; 1099 u8 group, i; 1100 unsigned long flag = 0; 1101 1102 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath); 1103 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) { 1104 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); 1105 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); 1106 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); 1107 /* fc area 0xd2c */ 1108 if (channel > 99) 1109 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | 1110 BIT(14), 2); 1111 else 1112 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | 1113 BIT(14), 1); 1114 /* leave 0 for channel1-14. */ 1115 group = channel <= 64 ? 1 : 2; 1116 imr_num = MAX_RF_IMR_INDEX_NORMAL; 1117 for (i = 0; i < imr_num; i++) 1118 rtl_set_rfreg(hw, (enum radio_path)rfpath, 1119 rf_reg_for_5g_swchnl_normal[i], rfmask, 1120 rf_imr_param_normal[0][group][i]); 1121 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); 1122 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1); 1123 } else { 1124 /* G band. */ 1125 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, 1126 "Load RF IMR parameters for G band. IMR already setting %d\n", 1127 rtlpriv->rtlhal.load_imrandiqk_setting_for2g); 1128 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); 1129 if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) { 1130 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, 1131 "Load RF IMR parameters for G band. %d\n", 1132 rfpath); 1133 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 1134 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); 1135 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 1136 0x00f00000, 0xf); 1137 imr_num = MAX_RF_IMR_INDEX_NORMAL; 1138 for (i = 0; i < imr_num; i++) { 1139 rtl_set_rfreg(hw, (enum radio_path)rfpath, 1140 rf_reg_for_5g_swchnl_normal[i], 1141 RFREG_OFFSET_MASK, 1142 rf_imr_param_normal[0][0][i]); 1143 } 1144 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 1145 0x00f00000, 0); 1146 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3); 1147 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 1148 } 1149 } 1150 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 1151 } 1152 1153 static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw, 1154 u8 rfpath, u32 *pu4_regval) 1155 { 1156 struct rtl_priv *rtlpriv = rtl_priv(hw); 1157 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1158 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 1159 1160 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "====>\n"); 1161 /*----Store original RFENV control type----*/ 1162 switch (rfpath) { 1163 case RF90_PATH_A: 1164 case RF90_PATH_C: 1165 *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV); 1166 break; 1167 case RF90_PATH_B: 1168 case RF90_PATH_D: 1169 *pu4_regval = 1170 rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16); 1171 break; 1172 } 1173 /*----Set RF_ENV enable----*/ 1174 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); 1175 udelay(1); 1176 /*----Set RF_ENV output high----*/ 1177 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); 1178 udelay(1); 1179 /* Set bit number of Address and Data for RF register */ 1180 /* Set 1 to 4 bits for 8255 */ 1181 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0); 1182 udelay(1); 1183 /*Set 0 to 12 bits for 8255 */ 1184 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); 1185 udelay(1); 1186 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<====\n"); 1187 } 1188 1189 static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath, 1190 u32 *pu4_regval) 1191 { 1192 struct rtl_priv *rtlpriv = rtl_priv(hw); 1193 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1194 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; 1195 1196 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n"); 1197 /*----Restore RFENV control type----*/ 1198 switch (rfpath) { 1199 case RF90_PATH_A: 1200 case RF90_PATH_C: 1201 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval); 1202 break; 1203 case RF90_PATH_B: 1204 case RF90_PATH_D: 1205 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16, 1206 *pu4_regval); 1207 break; 1208 } 1209 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n"); 1210 } 1211 1212 static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) 1213 { 1214 struct rtl_priv *rtlpriv = rtl_priv(hw); 1215 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1216 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 1217 u8 path = rtlhal->current_bandtype == 1218 BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B; 1219 u8 index = 0, i = 0, rfpath = RF90_PATH_A; 1220 bool need_pwr_down = false, internal_pa = false; 1221 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2; 1222 1223 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n"); 1224 /* config path A for 5G */ 1225 if (rtlhal->current_bandtype == BAND_ON_5G) { 1226 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); 1227 u4tmp = curveindex_5g[channel - 1]; 1228 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1229 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); 1230 for (i = 0; i < RF_CHNL_NUM_5G; i++) { 1231 if (channel == rf_chnl_5g[i] && channel <= 140) 1232 index = 0; 1233 } 1234 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) { 1235 if (channel == rf_chnl_5g_40m[i] && channel <= 140) 1236 index = 1; 1237 } 1238 if (channel == 149 || channel == 155 || channel == 161) 1239 index = 2; 1240 else if (channel == 151 || channel == 153 || channel == 163 1241 || channel == 165) 1242 index = 3; 1243 else if (channel == 157 || channel == 159) 1244 index = 4; 1245 1246 if (rtlhal->macphymode == DUALMAC_DUALPHY 1247 && rtlhal->interfaceindex == 1) { 1248 need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false); 1249 rtlhal->during_mac1init_radioa = true; 1250 /* asume no this case */ 1251 if (need_pwr_down) 1252 _rtl92d_phy_enable_rf_env(hw, path, 1253 &u4regvalue); 1254 } 1255 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) { 1256 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) { 1257 rtl_set_rfreg(hw, (enum radio_path)path, 1258 rf_reg_for_c_cut_5g[i], 1259 RFREG_OFFSET_MASK, 0xE439D); 1260 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) { 1261 u4tmp2 = (rf_reg_pram_c_5g[index][i] & 1262 0x7FF) | (u4tmp << 11); 1263 if (channel == 36) 1264 u4tmp2 &= ~(BIT(7) | BIT(6)); 1265 rtl_set_rfreg(hw, (enum radio_path)path, 1266 rf_reg_for_c_cut_5g[i], 1267 RFREG_OFFSET_MASK, u4tmp2); 1268 } else { 1269 rtl_set_rfreg(hw, (enum radio_path)path, 1270 rf_reg_for_c_cut_5g[i], 1271 RFREG_OFFSET_MASK, 1272 rf_reg_pram_c_5g[index][i]); 1273 } 1274 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 1275 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n", 1276 rf_reg_for_c_cut_5g[i], 1277 rf_reg_pram_c_5g[index][i], 1278 path, index, 1279 rtl_get_rfreg(hw, (enum radio_path)path, 1280 rf_reg_for_c_cut_5g[i], 1281 RFREG_OFFSET_MASK)); 1282 } 1283 if (need_pwr_down) 1284 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); 1285 if (rtlhal->during_mac1init_radioa) 1286 rtl92d_phy_powerdown_anotherphy(hw, false); 1287 if (channel < 149) 1288 value = 0x07; 1289 else if (channel >= 149) 1290 value = 0x02; 1291 if (channel >= 36 && channel <= 64) 1292 index = 0; 1293 else if (channel >= 100 && channel <= 140) 1294 index = 1; 1295 else 1296 index = 2; 1297 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 1298 rfpath++) { 1299 if (rtlhal->macphymode == DUALMAC_DUALPHY && 1300 rtlhal->interfaceindex == 1) /* MAC 1 5G */ 1301 internal_pa = rtlpriv->efuse.internal_pa_5g[1]; 1302 else 1303 internal_pa = 1304 rtlpriv->efuse.internal_pa_5g[rfpath]; 1305 if (internal_pa) { 1306 for (i = 0; 1307 i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA; 1308 i++) { 1309 rtl_set_rfreg(hw, rfpath, 1310 rf_for_c_cut_5g_internal_pa[i], 1311 RFREG_OFFSET_MASK, 1312 rf_pram_c_5g_int_pa[index][i]); 1313 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, 1314 "offset 0x%x value 0x%x path %d index %d\n", 1315 rf_for_c_cut_5g_internal_pa[i], 1316 rf_pram_c_5g_int_pa[index][i], 1317 rfpath, index); 1318 } 1319 } else { 1320 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, 1321 mask, value); 1322 } 1323 } 1324 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { 1325 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); 1326 u4tmp = curveindex_2g[channel - 1]; 1327 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1328 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); 1329 if (channel == 1 || channel == 2 || channel == 4 || channel == 9 1330 || channel == 10 || channel == 11 || channel == 12) 1331 index = 0; 1332 else if (channel == 3 || channel == 13 || channel == 14) 1333 index = 1; 1334 else if (channel >= 5 && channel <= 8) 1335 index = 2; 1336 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 1337 path = RF90_PATH_A; 1338 if (rtlhal->interfaceindex == 0) { 1339 need_pwr_down = 1340 rtl92d_phy_enable_anotherphy(hw, true); 1341 rtlhal->during_mac0init_radiob = true; 1342 1343 if (need_pwr_down) 1344 _rtl92d_phy_enable_rf_env(hw, path, 1345 &u4regvalue); 1346 } 1347 } 1348 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) { 1349 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7) 1350 rtl_set_rfreg(hw, (enum radio_path)path, 1351 rf_reg_for_c_cut_2g[i], 1352 RFREG_OFFSET_MASK, 1353 (rf_reg_param_for_c_cut_2g[index][i] | 1354 BIT(17))); 1355 else 1356 rtl_set_rfreg(hw, (enum radio_path)path, 1357 rf_reg_for_c_cut_2g[i], 1358 RFREG_OFFSET_MASK, 1359 rf_reg_param_for_c_cut_2g 1360 [index][i]); 1361 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 1362 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n", 1363 rf_reg_for_c_cut_2g[i], 1364 rf_reg_param_for_c_cut_2g[index][i], 1365 rf_reg_mask_for_c_cut_2g[i], path, index, 1366 rtl_get_rfreg(hw, (enum radio_path)path, 1367 rf_reg_for_c_cut_2g[i], 1368 RFREG_OFFSET_MASK)); 1369 } 1370 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1371 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", 1372 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); 1373 1374 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4, 1375 RFREG_OFFSET_MASK, 1376 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); 1377 if (need_pwr_down) 1378 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); 1379 if (rtlhal->during_mac0init_radiob) 1380 rtl92d_phy_powerdown_anotherphy(hw, true); 1381 } 1382 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 1383 } 1384 1385 u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl) 1386 { 1387 u8 channel_all[59] = { 1388 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 1389 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 1390 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 1391 114, 116, 118, 120, 122, 124, 126, 128, 130, 1392 132, 134, 136, 138, 140, 149, 151, 153, 155, 1393 157, 159, 161, 163, 165 1394 }; 1395 u8 place = chnl; 1396 1397 if (chnl > 14) { 1398 for (place = 14; place < sizeof(channel_all); place++) { 1399 if (channel_all[place] == chnl) 1400 return place - 13; 1401 } 1402 } 1403 1404 return 0; 1405 } 1406 1407 #define MAX_TOLERANCE 5 1408 #define IQK_DELAY_TIME 1 /* ms */ 1409 #define MAX_TOLERANCE_92D 3 1410 1411 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1412 static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb) 1413 { 1414 struct rtl_priv *rtlpriv = rtl_priv(hw); 1415 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1416 u32 regeac, rege94, rege9c, regea4; 1417 u8 result = 0; 1418 1419 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n"); 1420 /* path-A IQK setting */ 1421 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1422 if (rtlhal->interfaceindex == 0) { 1423 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); 1424 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); 1425 } else { 1426 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); 1427 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); 1428 } 1429 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); 1430 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); 1431 /* path-B IQK setting */ 1432 if (configpathb) { 1433 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); 1434 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); 1435 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); 1436 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); 1437 } 1438 /* LO calibration setting */ 1439 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1440 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); 1441 /* One shot, path A LOK & IQK */ 1442 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); 1443 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); 1444 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 1445 /* delay x ms */ 1446 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1447 "Delay %d ms for One shot, path A LOK & IQK\n", 1448 IQK_DELAY_TIME); 1449 mdelay(IQK_DELAY_TIME); 1450 /* Check failed */ 1451 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1452 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1453 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); 1454 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); 1455 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); 1456 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); 1457 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); 1458 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); 1459 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) && 1460 (((rege9c & 0x03FF0000) >> 16) != 0x42)) 1461 result |= 0x01; 1462 else /* if Tx not OK, ignore Rx */ 1463 return result; 1464 /* if Tx is OK, check whether Rx is OK */ 1465 if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) && 1466 (((regeac & 0x03FF0000) >> 16) != 0x36)) 1467 result |= 0x02; 1468 else 1469 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A Rx IQK fail!!\n"); 1470 return result; 1471 } 1472 1473 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1474 static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw, 1475 bool configpathb) 1476 { 1477 struct rtl_priv *rtlpriv = rtl_priv(hw); 1478 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1479 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1480 u32 regeac, rege94, rege9c, regea4; 1481 u8 result = 0; 1482 u8 i; 1483 u8 retrycount = 2; 1484 u32 TxOKBit = BIT(28), RxOKBit = BIT(27); 1485 1486 if (rtlhal->interfaceindex == 1) { /* PHY1 */ 1487 TxOKBit = BIT(31); 1488 RxOKBit = BIT(30); 1489 } 1490 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n"); 1491 /* path-A IQK setting */ 1492 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1493 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); 1494 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); 1495 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); 1496 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); 1497 /* path-B IQK setting */ 1498 if (configpathb) { 1499 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); 1500 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); 1501 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); 1502 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); 1503 } 1504 /* LO calibration setting */ 1505 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1506 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); 1507 /* path-A PA on */ 1508 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); 1509 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); 1510 for (i = 0; i < retrycount; i++) { 1511 /* One shot, path A LOK & IQK */ 1512 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1513 "One shot, path A LOK & IQK!\n"); 1514 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); 1515 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 1516 /* delay x ms */ 1517 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1518 "Delay %d ms for One shot, path A LOK & IQK.\n", 1519 IQK_DELAY_TIME); 1520 mdelay(IQK_DELAY_TIME * 10); 1521 /* Check failed */ 1522 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1523 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1524 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); 1525 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); 1526 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); 1527 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); 1528 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); 1529 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); 1530 if (!(regeac & TxOKBit) && 1531 (((rege94 & 0x03FF0000) >> 16) != 0x142)) { 1532 result |= 0x01; 1533 } else { /* if Tx not OK, ignore Rx */ 1534 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1535 "Path A Tx IQK fail!!\n"); 1536 continue; 1537 } 1538 1539 /* if Tx is OK, check whether Rx is OK */ 1540 if (!(regeac & RxOKBit) && 1541 (((regea4 & 0x03FF0000) >> 16) != 0x132)) { 1542 result |= 0x02; 1543 break; 1544 } else { 1545 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1546 "Path A Rx IQK fail!!\n"); 1547 } 1548 } 1549 /* path A PA off */ 1550 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 1551 rtlphy->iqk_bb_backup[0]); 1552 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 1553 rtlphy->iqk_bb_backup[1]); 1554 return result; 1555 } 1556 1557 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1558 static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw) 1559 { 1560 struct rtl_priv *rtlpriv = rtl_priv(hw); 1561 u32 regeac, regeb4, regebc, regec4, regecc; 1562 u8 result = 0; 1563 1564 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n"); 1565 /* One shot, path B LOK & IQK */ 1566 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); 1567 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); 1568 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); 1569 /* delay x ms */ 1570 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1571 "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME); 1572 mdelay(IQK_DELAY_TIME); 1573 /* Check failed */ 1574 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1575 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1576 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); 1577 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); 1578 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); 1579 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); 1580 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); 1581 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); 1582 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); 1583 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); 1584 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) && 1585 (((regebc & 0x03FF0000) >> 16) != 0x42)) 1586 result |= 0x01; 1587 else 1588 return result; 1589 if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) && 1590 (((regecc & 0x03FF0000) >> 16) != 0x36)) 1591 result |= 0x02; 1592 else 1593 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B Rx IQK fail!!\n"); 1594 return result; 1595 } 1596 1597 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 1598 static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw) 1599 { 1600 struct rtl_priv *rtlpriv = rtl_priv(hw); 1601 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1602 u32 regeac, regeb4, regebc, regec4, regecc; 1603 u8 result = 0; 1604 u8 i; 1605 u8 retrycount = 2; 1606 1607 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n"); 1608 /* path-A IQK setting */ 1609 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1610 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); 1611 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); 1612 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); 1613 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); 1614 1615 /* path-B IQK setting */ 1616 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); 1617 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); 1618 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); 1619 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); 1620 1621 /* LO calibration setting */ 1622 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1623 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); 1624 1625 /* path-B PA on */ 1626 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); 1627 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); 1628 1629 for (i = 0; i < retrycount; i++) { 1630 /* One shot, path B LOK & IQK */ 1631 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1632 "One shot, path A LOK & IQK!\n"); 1633 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); 1634 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); 1635 1636 /* delay x ms */ 1637 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1638 "Delay %d ms for One shot, path B LOK & IQK.\n", 10); 1639 mdelay(IQK_DELAY_TIME * 10); 1640 1641 /* Check failed */ 1642 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); 1643 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1644 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); 1645 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); 1646 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); 1647 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); 1648 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); 1649 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); 1650 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); 1651 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); 1652 if (!(regeac & BIT(31)) && 1653 (((regeb4 & 0x03FF0000) >> 16) != 0x142)) 1654 result |= 0x01; 1655 else 1656 continue; 1657 if (!(regeac & BIT(30)) && 1658 (((regec4 & 0x03FF0000) >> 16) != 0x132)) { 1659 result |= 0x02; 1660 break; 1661 } else { 1662 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1663 "Path B Rx IQK fail!!\n"); 1664 } 1665 } 1666 1667 /* path B PA off */ 1668 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 1669 rtlphy->iqk_bb_backup[0]); 1670 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 1671 rtlphy->iqk_bb_backup[2]); 1672 return result; 1673 } 1674 1675 static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw, 1676 u32 *adda_reg, u32 *adda_backup, 1677 u32 regnum) 1678 { 1679 struct rtl_priv *rtlpriv = rtl_priv(hw); 1680 u32 i; 1681 1682 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n"); 1683 for (i = 0; i < regnum; i++) 1684 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD); 1685 } 1686 1687 static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw, 1688 u32 *macreg, u32 *macbackup) 1689 { 1690 struct rtl_priv *rtlpriv = rtl_priv(hw); 1691 u32 i; 1692 1693 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save MAC parameters.\n"); 1694 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1695 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]); 1696 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]); 1697 } 1698 1699 static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw, 1700 u32 *adda_reg, u32 *adda_backup, 1701 u32 regnum) 1702 { 1703 struct rtl_priv *rtlpriv = rtl_priv(hw); 1704 u32 i; 1705 1706 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1707 "Reload ADDA power saving parameters !\n"); 1708 for (i = 0; i < regnum; i++) 1709 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); 1710 } 1711 1712 static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw, 1713 u32 *macreg, u32 *macbackup) 1714 { 1715 struct rtl_priv *rtlpriv = rtl_priv(hw); 1716 u32 i; 1717 1718 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Reload MAC parameters !\n"); 1719 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) 1720 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]); 1721 rtl_write_byte(rtlpriv, macreg[i], macbackup[i]); 1722 } 1723 1724 static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw, 1725 u32 *adda_reg, bool patha_on, bool is2t) 1726 { 1727 struct rtl_priv *rtlpriv = rtl_priv(hw); 1728 u32 pathon; 1729 u32 i; 1730 1731 RTPRINT(rtlpriv, FINIT, INIT_IQK, "ADDA ON.\n"); 1732 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4; 1733 if (patha_on) 1734 pathon = rtlpriv->rtlhal.interfaceindex == 0 ? 1735 0x04db25a4 : 0x0b1b25a4; 1736 for (i = 0; i < IQK_ADDA_REG_NUM; i++) 1737 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon); 1738 } 1739 1740 static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw, 1741 u32 *macreg, u32 *macbackup) 1742 { 1743 struct rtl_priv *rtlpriv = rtl_priv(hw); 1744 u32 i; 1745 1746 RTPRINT(rtlpriv, FINIT, INIT_IQK, "MAC settings for Calibration.\n"); 1747 rtl_write_byte(rtlpriv, macreg[0], 0x3F); 1748 1749 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) 1750 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & 1751 (~BIT(3)))); 1752 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5)))); 1753 } 1754 1755 static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw) 1756 { 1757 struct rtl_priv *rtlpriv = rtl_priv(hw); 1758 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n"); 1759 1760 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); 1761 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); 1762 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1763 } 1764 1765 static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode) 1766 { 1767 struct rtl_priv *rtlpriv = rtl_priv(hw); 1768 u32 mode; 1769 1770 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1771 "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI"); 1772 mode = pi_mode ? 0x01000100 : 0x01000000; 1773 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); 1774 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); 1775 } 1776 1777 static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], 1778 u8 t, bool is2t) 1779 { 1780 struct rtl_priv *rtlpriv = rtl_priv(hw); 1781 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1782 u32 i; 1783 u8 patha_ok, pathb_ok; 1784 static u32 adda_reg[IQK_ADDA_REG_NUM] = { 1785 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, 1786 0xe78, 0xe7c, 0xe80, 0xe84, 1787 0xe88, 0xe8c, 0xed0, 0xed4, 1788 0xed8, 0xedc, 0xee0, 0xeec 1789 }; 1790 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 1791 0x522, 0x550, 0x551, 0x040 1792 }; 1793 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = { 1794 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE, 1795 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR, 1796 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE, 1797 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4, 1798 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1 1799 }; 1800 const u32 retrycount = 2; 1801 u32 bbvalue; 1802 1803 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n"); 1804 if (t == 0) { 1805 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); 1806 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); 1807 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", 1808 is2t ? "2T2R" : "1T1R"); 1809 1810 /* Save ADDA parameters, turn Path A ADDA on */ 1811 _rtl92d_phy_save_adda_registers(hw, adda_reg, 1812 rtlphy->adda_backup, IQK_ADDA_REG_NUM); 1813 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, 1814 rtlphy->iqk_mac_backup); 1815 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, 1816 rtlphy->iqk_bb_backup, IQK_BB_REG_NUM); 1817 } 1818 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); 1819 if (t == 0) 1820 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, 1821 RFPGA0_XA_HSSIPARAMETER1, BIT(8)); 1822 1823 /* Switch BB to PI mode to do IQ Calibration. */ 1824 if (!rtlphy->rfpi_enable) 1825 _rtl92d_phy_pimode_switch(hw, true); 1826 1827 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); 1828 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); 1829 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); 1830 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); 1831 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); 1832 if (is2t) { 1833 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 1834 0x00010000); 1835 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, 1836 0x00010000); 1837 } 1838 /* MAC settings */ 1839 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, 1840 rtlphy->iqk_mac_backup); 1841 /* Page B init */ 1842 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); 1843 if (is2t) 1844 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); 1845 /* IQ calibration setting */ 1846 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); 1847 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 1848 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); 1849 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); 1850 for (i = 0; i < retrycount; i++) { 1851 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t); 1852 if (patha_ok == 0x03) { 1853 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1854 "Path A IQK Success!!\n"); 1855 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 1856 0x3FF0000) >> 16; 1857 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 1858 0x3FF0000) >> 16; 1859 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & 1860 0x3FF0000) >> 16; 1861 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & 1862 0x3FF0000) >> 16; 1863 break; 1864 } else if (i == (retrycount - 1) && patha_ok == 0x01) { 1865 /* Tx IQK OK */ 1866 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1867 "Path A IQK Only Tx Success!!\n"); 1868 1869 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 1870 0x3FF0000) >> 16; 1871 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 1872 0x3FF0000) >> 16; 1873 } 1874 } 1875 if (0x00 == patha_ok) 1876 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK failed!!\n"); 1877 if (is2t) { 1878 _rtl92d_phy_patha_standby(hw); 1879 /* Turn Path B ADDA on */ 1880 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); 1881 for (i = 0; i < retrycount; i++) { 1882 pathb_ok = _rtl92d_phy_pathb_iqk(hw); 1883 if (pathb_ok == 0x03) { 1884 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1885 "Path B IQK Success!!\n"); 1886 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, 1887 MASKDWORD) & 0x3FF0000) >> 16; 1888 result[t][5] = (rtl_get_bbreg(hw, 0xebc, 1889 MASKDWORD) & 0x3FF0000) >> 16; 1890 result[t][6] = (rtl_get_bbreg(hw, 0xec4, 1891 MASKDWORD) & 0x3FF0000) >> 16; 1892 result[t][7] = (rtl_get_bbreg(hw, 0xecc, 1893 MASKDWORD) & 0x3FF0000) >> 16; 1894 break; 1895 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { 1896 /* Tx IQK OK */ 1897 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1898 "Path B Only Tx IQK Success!!\n"); 1899 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, 1900 MASKDWORD) & 0x3FF0000) >> 16; 1901 result[t][5] = (rtl_get_bbreg(hw, 0xebc, 1902 MASKDWORD) & 0x3FF0000) >> 16; 1903 } 1904 } 1905 if (0x00 == pathb_ok) 1906 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1907 "Path B IQK failed!!\n"); 1908 } 1909 1910 /* Back to BB mode, load original value */ 1911 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1912 "IQK:Back to BB mode, load original value!\n"); 1913 1914 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); 1915 if (t != 0) { 1916 /* Switch back BB to SI mode after finish IQ Calibration. */ 1917 if (!rtlphy->rfpi_enable) 1918 _rtl92d_phy_pimode_switch(hw, false); 1919 /* Reload ADDA power saving parameters */ 1920 _rtl92d_phy_reload_adda_registers(hw, adda_reg, 1921 rtlphy->adda_backup, IQK_ADDA_REG_NUM); 1922 /* Reload MAC parameters */ 1923 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg, 1924 rtlphy->iqk_mac_backup); 1925 if (is2t) 1926 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 1927 rtlphy->iqk_bb_backup, 1928 IQK_BB_REG_NUM); 1929 else 1930 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 1931 rtlphy->iqk_bb_backup, 1932 IQK_BB_REG_NUM - 1); 1933 /* load 0xe30 IQC default value */ 1934 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); 1935 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); 1936 } 1937 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); 1938 } 1939 1940 static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw, 1941 long result[][8], u8 t) 1942 { 1943 struct rtl_priv *rtlpriv = rtl_priv(hw); 1944 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1945 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 1946 u8 patha_ok, pathb_ok; 1947 static u32 adda_reg[IQK_ADDA_REG_NUM] = { 1948 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, 1949 0xe78, 0xe7c, 0xe80, 0xe84, 1950 0xe88, 0xe8c, 0xed0, 0xed4, 1951 0xed8, 0xedc, 0xee0, 0xeec 1952 }; 1953 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { 1954 0x522, 0x550, 0x551, 0x040 1955 }; 1956 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = { 1957 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE, 1958 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR, 1959 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE, 1960 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4, 1961 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1 1962 }; 1963 u32 bbvalue; 1964 bool is2t = IS_92D_SINGLEPHY(rtlhal->version); 1965 1966 /* Note: IQ calibration must be performed after loading 1967 * PHY_REG.txt , and radio_a, radio_b.txt */ 1968 1969 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n"); 1970 mdelay(IQK_DELAY_TIME * 20); 1971 if (t == 0) { 1972 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); 1973 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); 1974 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", 1975 is2t ? "2T2R" : "1T1R"); 1976 /* Save ADDA parameters, turn Path A ADDA on */ 1977 _rtl92d_phy_save_adda_registers(hw, adda_reg, 1978 rtlphy->adda_backup, 1979 IQK_ADDA_REG_NUM); 1980 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, 1981 rtlphy->iqk_mac_backup); 1982 if (is2t) 1983 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, 1984 rtlphy->iqk_bb_backup, 1985 IQK_BB_REG_NUM); 1986 else 1987 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, 1988 rtlphy->iqk_bb_backup, 1989 IQK_BB_REG_NUM - 1); 1990 } 1991 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); 1992 /* MAC settings */ 1993 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, 1994 rtlphy->iqk_mac_backup); 1995 if (t == 0) 1996 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, 1997 RFPGA0_XA_HSSIPARAMETER1, BIT(8)); 1998 /* Switch BB to PI mode to do IQ Calibration. */ 1999 if (!rtlphy->rfpi_enable) 2000 _rtl92d_phy_pimode_switch(hw, true); 2001 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); 2002 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); 2003 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); 2004 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); 2005 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); 2006 2007 /* Page B init */ 2008 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); 2009 if (is2t) 2010 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); 2011 /* IQ calibration setting */ 2012 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); 2013 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); 2014 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); 2015 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); 2016 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t); 2017 if (patha_ok == 0x03) { 2018 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n"); 2019 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 2020 0x3FF0000) >> 16; 2021 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 2022 0x3FF0000) >> 16; 2023 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & 2024 0x3FF0000) >> 16; 2025 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & 2026 0x3FF0000) >> 16; 2027 } else if (patha_ok == 0x01) { /* Tx IQK OK */ 2028 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2029 "Path A IQK Only Tx Success!!\n"); 2030 2031 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & 2032 0x3FF0000) >> 16; 2033 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 2034 0x3FF0000) >> 16; 2035 } else { 2036 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n"); 2037 } 2038 if (is2t) { 2039 /* _rtl92d_phy_patha_standby(hw); */ 2040 /* Turn Path B ADDA on */ 2041 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); 2042 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw); 2043 if (pathb_ok == 0x03) { 2044 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2045 "Path B IQK Success!!\n"); 2046 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & 2047 0x3FF0000) >> 16; 2048 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 2049 0x3FF0000) >> 16; 2050 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & 2051 0x3FF0000) >> 16; 2052 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & 2053 0x3FF0000) >> 16; 2054 } else if (pathb_ok == 0x01) { /* Tx IQK OK */ 2055 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2056 "Path B Only Tx IQK Success!!\n"); 2057 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & 2058 0x3FF0000) >> 16; 2059 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & 2060 0x3FF0000) >> 16; 2061 } else { 2062 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2063 "Path B IQK failed!!\n"); 2064 } 2065 } 2066 2067 /* Back to BB mode, load original value */ 2068 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2069 "IQK:Back to BB mode, load original value!\n"); 2070 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); 2071 if (t != 0) { 2072 if (is2t) 2073 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 2074 rtlphy->iqk_bb_backup, 2075 IQK_BB_REG_NUM); 2076 else 2077 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 2078 rtlphy->iqk_bb_backup, 2079 IQK_BB_REG_NUM - 1); 2080 /* Reload MAC parameters */ 2081 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg, 2082 rtlphy->iqk_mac_backup); 2083 /* Switch back BB to SI mode after finish IQ Calibration. */ 2084 if (!rtlphy->rfpi_enable) 2085 _rtl92d_phy_pimode_switch(hw, false); 2086 /* Reload ADDA power saving parameters */ 2087 _rtl92d_phy_reload_adda_registers(hw, adda_reg, 2088 rtlphy->adda_backup, 2089 IQK_ADDA_REG_NUM); 2090 } 2091 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); 2092 } 2093 2094 static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw, 2095 long result[][8], u8 c1, u8 c2) 2096 { 2097 struct rtl_priv *rtlpriv = rtl_priv(hw); 2098 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2099 u32 i, j, diff, sim_bitmap, bound; 2100 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ 2101 bool bresult = true; 2102 bool is2t = IS_92D_SINGLEPHY(rtlhal->version); 2103 2104 if (is2t) 2105 bound = 8; 2106 else 2107 bound = 4; 2108 sim_bitmap = 0; 2109 for (i = 0; i < bound; i++) { 2110 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - 2111 result[c2][i]) : (result[c2][i] - result[c1][i]); 2112 if (diff > MAX_TOLERANCE_92D) { 2113 if ((i == 2 || i == 6) && !sim_bitmap) { 2114 if (result[c1][i] + result[c1][i + 1] == 0) 2115 final_candidate[(i / 4)] = c2; 2116 else if (result[c2][i] + result[c2][i + 1] == 0) 2117 final_candidate[(i / 4)] = c1; 2118 else 2119 sim_bitmap = sim_bitmap | (1 << i); 2120 } else { 2121 sim_bitmap = sim_bitmap | (1 << i); 2122 } 2123 } 2124 } 2125 if (sim_bitmap == 0) { 2126 for (i = 0; i < (bound / 4); i++) { 2127 if (final_candidate[i] != 0xFF) { 2128 for (j = i * 4; j < (i + 1) * 4 - 2; j++) 2129 result[3][j] = 2130 result[final_candidate[i]][j]; 2131 bresult = false; 2132 } 2133 } 2134 return bresult; 2135 } 2136 if (!(sim_bitmap & 0x0F)) { /* path A OK */ 2137 for (i = 0; i < 4; i++) 2138 result[3][i] = result[c1][i]; 2139 } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */ 2140 for (i = 0; i < 2; i++) 2141 result[3][i] = result[c1][i]; 2142 } 2143 if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */ 2144 for (i = 4; i < 8; i++) 2145 result[3][i] = result[c1][i]; 2146 } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */ 2147 for (i = 4; i < 6; i++) 2148 result[3][i] = result[c1][i]; 2149 } 2150 return false; 2151 } 2152 2153 static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw, 2154 bool iqk_ok, long result[][8], 2155 u8 final_candidate, bool txonly) 2156 { 2157 struct rtl_priv *rtlpriv = rtl_priv(hw); 2158 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2159 u32 oldval_0, val_x, tx0_a, reg; 2160 long val_y, tx0_c; 2161 bool is2t = IS_92D_SINGLEPHY(rtlhal->version) || 2162 rtlhal->macphymode == DUALMAC_DUALPHY; 2163 2164 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2165 "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed"); 2166 if (final_candidate == 0xFF) { 2167 return; 2168 } else if (iqk_ok) { 2169 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 2170 MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */ 2171 val_x = result[final_candidate][0]; 2172 if ((val_x & 0x00000200) != 0) 2173 val_x = val_x | 0xFFFFFC00; 2174 tx0_a = (val_x * oldval_0) >> 8; 2175 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2176 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n", 2177 val_x, tx0_a, oldval_0); 2178 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a); 2179 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), 2180 ((val_x * oldval_0 >> 7) & 0x1)); 2181 val_y = result[final_candidate][1]; 2182 if ((val_y & 0x00000200) != 0) 2183 val_y = val_y | 0xFFFFFC00; 2184 /* path B IQK result + 3 */ 2185 if (rtlhal->interfaceindex == 1 && 2186 rtlhal->current_bandtype == BAND_ON_5G) 2187 val_y += 3; 2188 tx0_c = (val_y * oldval_0) >> 8; 2189 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2190 "Y = 0x%lx, tx0_c = 0x%lx\n", 2191 val_y, tx0_c); 2192 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 2193 ((tx0_c & 0x3C0) >> 6)); 2194 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000, 2195 (tx0_c & 0x3F)); 2196 if (is2t) 2197 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), 2198 ((val_y * oldval_0 >> 7) & 0x1)); 2199 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n", 2200 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 2201 MASKDWORD)); 2202 if (txonly) { 2203 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n"); 2204 return; 2205 } 2206 reg = result[final_candidate][2]; 2207 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); 2208 reg = result[final_candidate][3] & 0x3F; 2209 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); 2210 reg = (result[final_candidate][3] >> 6) & 0xF; 2211 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); 2212 } 2213 } 2214 2215 static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw, 2216 bool iqk_ok, long result[][8], u8 final_candidate, bool txonly) 2217 { 2218 struct rtl_priv *rtlpriv = rtl_priv(hw); 2219 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2220 u32 oldval_1, val_x, tx1_a, reg; 2221 long val_y, tx1_c; 2222 2223 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n", 2224 iqk_ok ? "Success" : "Failed"); 2225 if (final_candidate == 0xFF) { 2226 return; 2227 } else if (iqk_ok) { 2228 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 2229 MASKDWORD) >> 22) & 0x3FF; 2230 val_x = result[final_candidate][4]; 2231 if ((val_x & 0x00000200) != 0) 2232 val_x = val_x | 0xFFFFFC00; 2233 tx1_a = (val_x * oldval_1) >> 8; 2234 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n", 2235 val_x, tx1_a); 2236 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a); 2237 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), 2238 ((val_x * oldval_1 >> 7) & 0x1)); 2239 val_y = result[final_candidate][5]; 2240 if ((val_y & 0x00000200) != 0) 2241 val_y = val_y | 0xFFFFFC00; 2242 if (rtlhal->current_bandtype == BAND_ON_5G) 2243 val_y += 3; 2244 tx1_c = (val_y * oldval_1) >> 8; 2245 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n", 2246 val_y, tx1_c); 2247 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 2248 ((tx1_c & 0x3C0) >> 6)); 2249 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000, 2250 (tx1_c & 0x3F)); 2251 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), 2252 ((val_y * oldval_1 >> 7) & 0x1)); 2253 if (txonly) 2254 return; 2255 reg = result[final_candidate][6]; 2256 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); 2257 reg = result[final_candidate][7] & 0x3F; 2258 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); 2259 reg = (result[final_candidate][7] >> 6) & 0xF; 2260 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); 2261 } 2262 } 2263 2264 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw) 2265 { 2266 struct rtl_priv *rtlpriv = rtl_priv(hw); 2267 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2268 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2269 long result[4][8]; 2270 u8 i, final_candidate, indexforchannel; 2271 bool patha_ok, pathb_ok; 2272 long rege94, rege9c, regea4, regeac, regeb4; 2273 long regebc, regec4, regecc, regtmp = 0; 2274 bool is12simular, is13simular, is23simular; 2275 unsigned long flag = 0; 2276 2277 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2278 "IQK:Start!!!channel %d\n", rtlphy->current_channel); 2279 for (i = 0; i < 8; i++) { 2280 result[0][i] = 0; 2281 result[1][i] = 0; 2282 result[2][i] = 0; 2283 result[3][i] = 0; 2284 } 2285 final_candidate = 0xff; 2286 patha_ok = false; 2287 pathb_ok = false; 2288 is12simular = false; 2289 is23simular = false; 2290 is13simular = false; 2291 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2292 "IQK !!!currentband %d\n", rtlhal->current_bandtype); 2293 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); 2294 for (i = 0; i < 3; i++) { 2295 if (rtlhal->current_bandtype == BAND_ON_5G) { 2296 _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i); 2297 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { 2298 if (IS_92D_SINGLEPHY(rtlhal->version)) 2299 _rtl92d_phy_iq_calibrate(hw, result, i, true); 2300 else 2301 _rtl92d_phy_iq_calibrate(hw, result, i, false); 2302 } 2303 if (i == 1) { 2304 is12simular = _rtl92d_phy_simularity_compare(hw, result, 2305 0, 1); 2306 if (is12simular) { 2307 final_candidate = 0; 2308 break; 2309 } 2310 } 2311 if (i == 2) { 2312 is13simular = _rtl92d_phy_simularity_compare(hw, result, 2313 0, 2); 2314 if (is13simular) { 2315 final_candidate = 0; 2316 break; 2317 } 2318 is23simular = _rtl92d_phy_simularity_compare(hw, result, 2319 1, 2); 2320 if (is23simular) { 2321 final_candidate = 1; 2322 } else { 2323 for (i = 0; i < 8; i++) 2324 regtmp += result[3][i]; 2325 2326 if (regtmp != 0) 2327 final_candidate = 3; 2328 else 2329 final_candidate = 0xFF; 2330 } 2331 } 2332 } 2333 rtl92d_release_cckandrw_pagea_ctl(hw, &flag); 2334 for (i = 0; i < 4; i++) { 2335 rege94 = result[i][0]; 2336 rege9c = result[i][1]; 2337 regea4 = result[i][2]; 2338 regeac = result[i][3]; 2339 regeb4 = result[i][4]; 2340 regebc = result[i][5]; 2341 regec4 = result[i][6]; 2342 regecc = result[i][7]; 2343 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2344 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n", 2345 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, 2346 regecc); 2347 } 2348 if (final_candidate != 0xff) { 2349 rtlphy->reg_e94 = rege94 = result[final_candidate][0]; 2350 rtlphy->reg_e9c = rege9c = result[final_candidate][1]; 2351 regea4 = result[final_candidate][2]; 2352 regeac = result[final_candidate][3]; 2353 rtlphy->reg_eb4 = regeb4 = result[final_candidate][4]; 2354 rtlphy->reg_ebc = regebc = result[final_candidate][5]; 2355 regec4 = result[final_candidate][6]; 2356 regecc = result[final_candidate][7]; 2357 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2358 "IQK: final_candidate is %x\n", final_candidate); 2359 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2360 "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n", 2361 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, 2362 regecc); 2363 patha_ok = pathb_ok = true; 2364 } else { 2365 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */ 2366 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; /* Y default value */ 2367 } 2368 if ((rege94 != 0) /*&&(regea4 != 0) */) 2369 _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result, 2370 final_candidate, (regea4 == 0)); 2371 if (IS_92D_SINGLEPHY(rtlhal->version)) { 2372 if ((regeb4 != 0) /*&&(regec4 != 0) */) 2373 _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result, 2374 final_candidate, (regec4 == 0)); 2375 } 2376 if (final_candidate != 0xFF) { 2377 indexforchannel = rtl92d_get_rightchnlplace_for_iqk( 2378 rtlphy->current_channel); 2379 2380 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) 2381 rtlphy->iqk_matrix[indexforchannel]. 2382 value[0][i] = result[final_candidate][i]; 2383 rtlphy->iqk_matrix[indexforchannel].iqk_done = 2384 true; 2385 2386 RT_TRACE(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD, 2387 "IQK OK indexforchannel %d\n", indexforchannel); 2388 } 2389 } 2390 2391 void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel) 2392 { 2393 struct rtl_priv *rtlpriv = rtl_priv(hw); 2394 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2395 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2396 u8 indexforchannel; 2397 2398 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel); 2399 /*------Do IQK for normal chip and test chip 5G band------- */ 2400 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel); 2401 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n", 2402 indexforchannel, 2403 rtlphy->iqk_matrix[indexforchannel].iqk_done); 2404 if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done && 2405 rtlphy->need_iqk) { 2406 /* Re Do IQK. */ 2407 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD, 2408 "Do IQK Matrix reg for channel:%d....\n", channel); 2409 rtl92d_phy_iq_calibrate(hw); 2410 } else { 2411 /* Just load the value. */ 2412 /* 2G band just load once. */ 2413 if (((!rtlhal->load_imrandiqk_setting_for2g) && 2414 indexforchannel == 0) || indexforchannel > 0) { 2415 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, 2416 "Just Read IQK Matrix reg for channel:%d....\n", 2417 channel); 2418 if ((rtlphy->iqk_matrix[indexforchannel]. 2419 value[0] != NULL) 2420 /*&&(regea4 != 0) */) 2421 _rtl92d_phy_patha_fill_iqk_matrix(hw, true, 2422 rtlphy->iqk_matrix[ 2423 indexforchannel].value, 0, 2424 (rtlphy->iqk_matrix[ 2425 indexforchannel].value[0][2] == 0)); 2426 if (IS_92D_SINGLEPHY(rtlhal->version)) { 2427 if ((rtlphy->iqk_matrix[ 2428 indexforchannel].value[0][4] != 0) 2429 /*&&(regec4 != 0) */) 2430 _rtl92d_phy_pathb_fill_iqk_matrix(hw, 2431 true, 2432 rtlphy->iqk_matrix[ 2433 indexforchannel].value, 0, 2434 (rtlphy->iqk_matrix[ 2435 indexforchannel].value[0][6] 2436 == 0)); 2437 } 2438 } 2439 } 2440 rtlphy->need_iqk = false; 2441 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 2442 } 2443 2444 static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2) 2445 { 2446 u32 ret; 2447 2448 if (val1 >= val2) 2449 ret = val1 - val2; 2450 else 2451 ret = val2 - val1; 2452 return ret; 2453 } 2454 2455 static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel) 2456 { 2457 2458 int i; 2459 2460 for (i = 0; i < sizeof(channel5g); i++) 2461 if (channel == channel5g[i]) 2462 return true; 2463 return false; 2464 } 2465 2466 static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw, 2467 u32 *targetchnl, u32 * curvecount_val, 2468 bool is5g, u32 *curveindex) 2469 { 2470 struct rtl_priv *rtlpriv = rtl_priv(hw); 2471 u32 smallest_abs_val = 0xffffffff, u4tmp; 2472 u8 i, j; 2473 u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G; 2474 2475 for (i = 0; i < chnl_num; i++) { 2476 if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1)) 2477 continue; 2478 curveindex[i] = 0; 2479 for (j = 0; j < (CV_CURVE_CNT * 2); j++) { 2480 u4tmp = _rtl92d_phy_get_abs(targetchnl[i], 2481 curvecount_val[j]); 2482 2483 if (u4tmp < smallest_abs_val) { 2484 curveindex[i] = j; 2485 smallest_abs_val = u4tmp; 2486 } 2487 } 2488 smallest_abs_val = 0xffffffff; 2489 RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n", 2490 i, curveindex[i]); 2491 } 2492 } 2493 2494 static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw, 2495 u8 channel) 2496 { 2497 struct rtl_priv *rtlpriv = rtl_priv(hw); 2498 u8 erfpath = rtlpriv->rtlhal.current_bandtype == 2499 BAND_ON_5G ? RF90_PATH_A : 2500 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ? 2501 RF90_PATH_B : RF90_PATH_A; 2502 u32 u4tmp = 0, u4regvalue = 0; 2503 bool bneed_powerdown_radio = false; 2504 2505 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath); 2506 RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n", 2507 rtlpriv->rtlhal.current_bandtype); 2508 RTPRINT(rtlpriv, FINIT, INIT_IQK, "channel = %d\n", channel); 2509 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */ 2510 u4tmp = curveindex_5g[channel-1]; 2511 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2512 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); 2513 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && 2514 rtlpriv->rtlhal.interfaceindex == 1) { 2515 bneed_powerdown_radio = 2516 rtl92d_phy_enable_anotherphy(hw, false); 2517 rtlpriv->rtlhal.during_mac1init_radioa = true; 2518 /* asume no this case */ 2519 if (bneed_powerdown_radio) 2520 _rtl92d_phy_enable_rf_env(hw, erfpath, 2521 &u4regvalue); 2522 } 2523 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); 2524 if (bneed_powerdown_radio) 2525 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); 2526 if (rtlpriv->rtlhal.during_mac1init_radioa) 2527 rtl92d_phy_powerdown_anotherphy(hw, false); 2528 } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) { 2529 u4tmp = curveindex_2g[channel-1]; 2530 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2531 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); 2532 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && 2533 rtlpriv->rtlhal.interfaceindex == 0) { 2534 bneed_powerdown_radio = 2535 rtl92d_phy_enable_anotherphy(hw, true); 2536 rtlpriv->rtlhal.during_mac0init_radiob = true; 2537 if (bneed_powerdown_radio) 2538 _rtl92d_phy_enable_rf_env(hw, erfpath, 2539 &u4regvalue); 2540 } 2541 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); 2542 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2543 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", 2544 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)); 2545 if (bneed_powerdown_radio) 2546 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); 2547 if (rtlpriv->rtlhal.during_mac0init_radiob) 2548 rtl92d_phy_powerdown_anotherphy(hw, true); 2549 } 2550 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); 2551 } 2552 2553 static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t) 2554 { 2555 struct rtl_priv *rtlpriv = rtl_priv(hw); 2556 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2557 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2558 u8 tmpreg, index, rf_mode[2]; 2559 u8 path = is2t ? 2 : 1; 2560 u8 i; 2561 u32 u4tmp, offset; 2562 u32 curvecount_val[CV_CURVE_CNT * 2] = {0}; 2563 u16 timeout = 800, timecount = 0; 2564 2565 /* Check continuous TX and Packet TX */ 2566 tmpreg = rtl_read_byte(rtlpriv, 0xd03); 2567 /* if Deal with contisuous TX case, disable all continuous TX */ 2568 /* if Deal with Packet TX case, block all queues */ 2569 if ((tmpreg & 0x70) != 0) 2570 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); 2571 else 2572 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 2573 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); 2574 for (index = 0; index < path; index++) { 2575 /* 1. Read original RF mode */ 2576 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; 2577 rf_mode[index] = rtl_read_byte(rtlpriv, offset); 2578 /* 2. Set RF mode = standby mode */ 2579 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC, 2580 RFREG_OFFSET_MASK, 0x010000); 2581 if (rtlpci->init_ready) { 2582 /* switch CV-curve control by LC-calibration */ 2583 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, 2584 BIT(17), 0x0); 2585 /* 4. Set LC calibration begin */ 2586 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, 2587 0x08000, 0x01); 2588 } 2589 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6, 2590 RFREG_OFFSET_MASK); 2591 while ((!(u4tmp & BIT(11))) && timecount <= timeout) { 2592 mdelay(50); 2593 timecount += 50; 2594 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, 2595 RF_SYN_G6, RFREG_OFFSET_MASK); 2596 } 2597 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2598 "PHY_LCK finish delay for %d ms=2\n", timecount); 2599 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK); 2600 if (index == 0 && rtlhal->interfaceindex == 0) { 2601 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2602 "path-A / 5G LCK\n"); 2603 } else { 2604 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2605 "path-B / 2.4G LCK\n"); 2606 } 2607 memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2); 2608 /* Set LC calibration off */ 2609 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, 2610 0x08000, 0x0); 2611 RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n"); 2612 /* save Curve-counting number */ 2613 for (i = 0; i < CV_CURVE_CNT; i++) { 2614 u32 readval = 0, readval2 = 0; 2615 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F, 2616 0x7f, i); 2617 2618 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D, 2619 RFREG_OFFSET_MASK, 0x0); 2620 readval = rtl_get_rfreg(hw, (enum radio_path)index, 2621 0x4F, RFREG_OFFSET_MASK); 2622 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5; 2623 /* reg 0x4f [4:0] */ 2624 /* reg 0x50 [19:10] */ 2625 readval2 = rtl_get_rfreg(hw, (enum radio_path)index, 2626 0x50, 0xffc00); 2627 curvecount_val[2 * i] = (((readval & 0x1F) << 10) | 2628 readval2); 2629 } 2630 if (index == 0 && rtlhal->interfaceindex == 0) 2631 _rtl92d_phy_calc_curvindex(hw, targetchnl_5g, 2632 curvecount_val, 2633 true, curveindex_5g); 2634 else 2635 _rtl92d_phy_calc_curvindex(hw, targetchnl_2g, 2636 curvecount_val, 2637 false, curveindex_2g); 2638 /* switch CV-curve control mode */ 2639 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, 2640 BIT(17), 0x1); 2641 } 2642 2643 /* Restore original situation */ 2644 for (index = 0; index < path; index++) { 2645 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; 2646 rtl_write_byte(rtlpriv, offset, 0x50); 2647 rtl_write_byte(rtlpriv, offset, rf_mode[index]); 2648 } 2649 if ((tmpreg & 0x70) != 0) 2650 rtl_write_byte(rtlpriv, 0xd03, tmpreg); 2651 else /*Deal with Packet TX case */ 2652 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 2653 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); 2654 _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel); 2655 } 2656 2657 static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) 2658 { 2659 struct rtl_priv *rtlpriv = rtl_priv(hw); 2660 2661 RTPRINT(rtlpriv, FINIT, INIT_IQK, "cosa PHY_LCK ver=2\n"); 2662 _rtl92d_phy_lc_calibrate_sw(hw, is2t); 2663 } 2664 2665 void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw) 2666 { 2667 struct rtl_priv *rtlpriv = rtl_priv(hw); 2668 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2669 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); 2670 u32 timeout = 2000, timecount = 0; 2671 2672 while (rtlpriv->mac80211.act_scanning && timecount < timeout) { 2673 udelay(50); 2674 timecount += 50; 2675 } 2676 2677 rtlphy->lck_inprogress = true; 2678 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2679 "LCK:Start!!! currentband %x delay %d ms\n", 2680 rtlhal->current_bandtype, timecount); 2681 if (IS_92D_SINGLEPHY(rtlhal->version)) { 2682 _rtl92d_phy_lc_calibrate(hw, true); 2683 } else { 2684 /* For 1T1R */ 2685 _rtl92d_phy_lc_calibrate(hw, false); 2686 } 2687 rtlphy->lck_inprogress = false; 2688 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LCK:Finish!!!\n"); 2689 } 2690 2691 void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta) 2692 { 2693 return; 2694 } 2695 2696 static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, 2697 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid, 2698 u32 para1, u32 para2, u32 msdelay) 2699 { 2700 struct swchnlcmd *pcmd; 2701 2702 if (cmdtable == NULL) { 2703 RT_ASSERT(false, "cmdtable cannot be NULL\n"); 2704 return false; 2705 } 2706 if (cmdtableidx >= cmdtablesz) 2707 return false; 2708 2709 pcmd = cmdtable + cmdtableidx; 2710 pcmd->cmdid = cmdid; 2711 pcmd->para1 = para1; 2712 pcmd->para2 = para2; 2713 pcmd->msdelay = msdelay; 2714 return true; 2715 } 2716 2717 void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw) 2718 { 2719 struct rtl_priv *rtlpriv = rtl_priv(hw); 2720 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2721 u8 i; 2722 2723 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 2724 "settings regs %d default regs %d\n", 2725 (int)(sizeof(rtlphy->iqk_matrix) / 2726 sizeof(struct iqk_matrix_regs)), 2727 IQK_MATRIX_REG_NUM); 2728 /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */ 2729 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) { 2730 rtlphy->iqk_matrix[i].value[0][0] = 0x100; 2731 rtlphy->iqk_matrix[i].value[0][2] = 0x100; 2732 rtlphy->iqk_matrix[i].value[0][4] = 0x100; 2733 rtlphy->iqk_matrix[i].value[0][6] = 0x100; 2734 rtlphy->iqk_matrix[i].value[0][1] = 0x0; 2735 rtlphy->iqk_matrix[i].value[0][3] = 0x0; 2736 rtlphy->iqk_matrix[i].value[0][5] = 0x0; 2737 rtlphy->iqk_matrix[i].value[0][7] = 0x0; 2738 rtlphy->iqk_matrix[i].iqk_done = false; 2739 } 2740 } 2741 2742 static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, 2743 u8 channel, u8 *stage, u8 *step, 2744 u32 *delay) 2745 { 2746 struct rtl_priv *rtlpriv = rtl_priv(hw); 2747 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2748 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT]; 2749 u32 precommoncmdcnt; 2750 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT]; 2751 u32 postcommoncmdcnt; 2752 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT]; 2753 u32 rfdependcmdcnt; 2754 struct swchnlcmd *currentcmd = NULL; 2755 u8 rfpath; 2756 u8 num_total_rfpath = rtlphy->num_total_rfpath; 2757 2758 precommoncmdcnt = 0; 2759 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 2760 MAX_PRECMD_CNT, 2761 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); 2762 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 2763 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); 2764 postcommoncmdcnt = 0; 2765 _rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, 2766 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); 2767 rfdependcmdcnt = 0; 2768 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 2769 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, 2770 RF_CHNLBW, channel, 0); 2771 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 2772 MAX_RFDEPENDCMD_CNT, CMDID_END, 2773 0, 0, 0); 2774 2775 do { 2776 switch (*stage) { 2777 case 0: 2778 currentcmd = &precommoncmd[*step]; 2779 break; 2780 case 1: 2781 currentcmd = &rfdependcmd[*step]; 2782 break; 2783 case 2: 2784 currentcmd = &postcommoncmd[*step]; 2785 break; 2786 } 2787 if (currentcmd->cmdid == CMDID_END) { 2788 if ((*stage) == 2) { 2789 return true; 2790 } else { 2791 (*stage)++; 2792 (*step) = 0; 2793 continue; 2794 } 2795 } 2796 switch (currentcmd->cmdid) { 2797 case CMDID_SET_TXPOWEROWER_LEVEL: 2798 rtl92d_phy_set_txpower_level(hw, channel); 2799 break; 2800 case CMDID_WRITEPORT_ULONG: 2801 rtl_write_dword(rtlpriv, currentcmd->para1, 2802 currentcmd->para2); 2803 break; 2804 case CMDID_WRITEPORT_USHORT: 2805 rtl_write_word(rtlpriv, currentcmd->para1, 2806 (u16)currentcmd->para2); 2807 break; 2808 case CMDID_WRITEPORT_UCHAR: 2809 rtl_write_byte(rtlpriv, currentcmd->para1, 2810 (u8)currentcmd->para2); 2811 break; 2812 case CMDID_RF_WRITEREG: 2813 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { 2814 rtlphy->rfreg_chnlval[rfpath] = 2815 ((rtlphy->rfreg_chnlval[rfpath] & 2816 0xffffff00) | currentcmd->para2); 2817 if (rtlpriv->rtlhal.current_bandtype == 2818 BAND_ON_5G) { 2819 if (currentcmd->para2 > 99) 2820 rtlphy->rfreg_chnlval[rfpath] = 2821 rtlphy->rfreg_chnlval 2822 [rfpath] | (BIT(18)); 2823 else 2824 rtlphy->rfreg_chnlval[rfpath] = 2825 rtlphy->rfreg_chnlval 2826 [rfpath] & (~BIT(18)); 2827 rtlphy->rfreg_chnlval[rfpath] |= 2828 (BIT(16) | BIT(8)); 2829 } else { 2830 rtlphy->rfreg_chnlval[rfpath] &= 2831 ~(BIT(8) | BIT(16) | BIT(18)); 2832 } 2833 rtl_set_rfreg(hw, (enum radio_path)rfpath, 2834 currentcmd->para1, 2835 RFREG_OFFSET_MASK, 2836 rtlphy->rfreg_chnlval[rfpath]); 2837 _rtl92d_phy_reload_imr_setting(hw, channel, 2838 rfpath); 2839 } 2840 _rtl92d_phy_switch_rf_setting(hw, channel); 2841 /* do IQK when all parameters are ready */ 2842 rtl92d_phy_reload_iqk_setting(hw, channel); 2843 break; 2844 default: 2845 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2846 "switch case %#x not processed\n", 2847 currentcmd->cmdid); 2848 break; 2849 } 2850 break; 2851 } while (true); 2852 (*delay) = currentcmd->msdelay; 2853 (*step)++; 2854 return false; 2855 } 2856 2857 u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw) 2858 { 2859 struct rtl_priv *rtlpriv = rtl_priv(hw); 2860 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2861 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2862 u32 delay; 2863 u32 timeout = 1000, timecount = 0; 2864 u8 channel = rtlphy->current_channel; 2865 u32 ret_value; 2866 2867 if (rtlphy->sw_chnl_inprogress) 2868 return 0; 2869 if (rtlphy->set_bwmode_inprogress) 2870 return 0; 2871 2872 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { 2873 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, 2874 "sw_chnl_inprogress false driver sleep or unload\n"); 2875 return 0; 2876 } 2877 while (rtlphy->lck_inprogress && timecount < timeout) { 2878 mdelay(50); 2879 timecount += 50; 2880 } 2881 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY && 2882 rtlhal->bandset == BAND_ON_BOTH) { 2883 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 2884 MASKDWORD); 2885 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0))) 2886 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G); 2887 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0))) 2888 rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G); 2889 } 2890 switch (rtlhal->current_bandtype) { 2891 case BAND_ON_5G: 2892 /* Get first channel error when change between 2893 * 5G and 2.4G band. */ 2894 if (channel <= 14) 2895 return 0; 2896 RT_ASSERT((channel > 14), "5G but channel<=14\n"); 2897 break; 2898 case BAND_ON_2_4G: 2899 /* Get first channel error when change between 2900 * 5G and 2.4G band. */ 2901 if (channel > 14) 2902 return 0; 2903 RT_ASSERT((channel <= 14), "2G but channel>14\n"); 2904 break; 2905 default: 2906 RT_ASSERT(false, "Invalid WirelessMode(%#x)!!\n", 2907 rtlpriv->mac80211.mode); 2908 break; 2909 } 2910 rtlphy->sw_chnl_inprogress = true; 2911 if (channel == 0) 2912 channel = 1; 2913 rtlphy->sw_chnl_stage = 0; 2914 rtlphy->sw_chnl_step = 0; 2915 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, 2916 "switch to channel%d\n", rtlphy->current_channel); 2917 2918 do { 2919 if (!rtlphy->sw_chnl_inprogress) 2920 break; 2921 if (!_rtl92d_phy_sw_chnl_step_by_step(hw, 2922 rtlphy->current_channel, 2923 &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) { 2924 if (delay > 0) 2925 mdelay(delay); 2926 else 2927 continue; 2928 } else { 2929 rtlphy->sw_chnl_inprogress = false; 2930 } 2931 break; 2932 } while (true); 2933 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 2934 rtlphy->sw_chnl_inprogress = false; 2935 return 1; 2936 } 2937 2938 static void rtl92d_phy_set_io(struct ieee80211_hw *hw) 2939 { 2940 struct rtl_priv *rtlpriv = rtl_priv(hw); 2941 struct dig_t *de_digtable = &rtlpriv->dm_digtable; 2942 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2943 2944 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2945 "--->Cmd(%#x), set_io_inprogress(%d)\n", 2946 rtlphy->current_io_type, rtlphy->set_io_inprogress); 2947 switch (rtlphy->current_io_type) { 2948 case IO_CMD_RESUME_DM_BY_SCAN: 2949 de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; 2950 rtl92d_dm_write_dig(hw); 2951 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel); 2952 break; 2953 case IO_CMD_PAUSE_DM_BY_SCAN: 2954 rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue; 2955 de_digtable->cur_igvalue = 0x37; 2956 rtl92d_dm_write_dig(hw); 2957 break; 2958 default: 2959 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2960 "switch case %#x not processed\n", 2961 rtlphy->current_io_type); 2962 break; 2963 } 2964 rtlphy->set_io_inprogress = false; 2965 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n", 2966 rtlphy->current_io_type); 2967 } 2968 2969 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) 2970 { 2971 struct rtl_priv *rtlpriv = rtl_priv(hw); 2972 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2973 bool postprocessing = false; 2974 2975 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2976 "-->IO Cmd(%#x), set_io_inprogress(%d)\n", 2977 iotype, rtlphy->set_io_inprogress); 2978 do { 2979 switch (iotype) { 2980 case IO_CMD_RESUME_DM_BY_SCAN: 2981 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2982 "[IO CMD] Resume DM after scan\n"); 2983 postprocessing = true; 2984 break; 2985 case IO_CMD_PAUSE_DM_BY_SCAN: 2986 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, 2987 "[IO CMD] Pause DM before scan\n"); 2988 postprocessing = true; 2989 break; 2990 default: 2991 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2992 "switch case %#x not processed\n", iotype); 2993 break; 2994 } 2995 } while (false); 2996 if (postprocessing && !rtlphy->set_io_inprogress) { 2997 rtlphy->set_io_inprogress = true; 2998 rtlphy->current_io_type = iotype; 2999 } else { 3000 return false; 3001 } 3002 rtl92d_phy_set_io(hw); 3003 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype); 3004 return true; 3005 } 3006 3007 static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw) 3008 { 3009 struct rtl_priv *rtlpriv = rtl_priv(hw); 3010 3011 /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */ 3012 /* b. SPS_CTRL 0x11[7:0] = 0x2b */ 3013 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) 3014 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 3015 /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */ 3016 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 3017 /* RF_ON_EXCEP(d~g): */ 3018 /* d. APSD_CTRL 0x600[7:0] = 0x00 */ 3019 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); 3020 /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */ 3021 /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/ 3022 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 3023 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 3024 /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */ 3025 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 3026 } 3027 3028 static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw) 3029 { 3030 struct rtl_priv *rtlpriv = rtl_priv(hw); 3031 u32 u4btmp; 3032 u8 delay = 5; 3033 3034 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ 3035 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 3036 /* b. RF path 0 offset 0x00 = 0x00 disable RF */ 3037 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 3038 /* c. APSD_CTRL 0x600[7:0] = 0x40 */ 3039 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 3040 /* d. APSD_CTRL 0x600[7:0] = 0x00 3041 * APSD_CTRL 0x600[7:0] = 0x00 3042 * RF path 0 offset 0x00 = 0x00 3043 * APSD_CTRL 0x600[7:0] = 0x40 3044 * */ 3045 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); 3046 while (u4btmp != 0 && delay > 0) { 3047 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); 3048 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 3049 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 3050 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); 3051 delay--; 3052 } 3053 if (delay == 0) { 3054 /* Jump out the LPS turn off sequence to RF_ON_EXCEP */ 3055 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); 3056 3057 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 3058 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 3059 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 3060 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 3061 "Fail !!! Switch RF timeout\n"); 3062 return; 3063 } 3064 /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */ 3065 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 3066 /* f. SPS_CTRL 0x11[7:0] = 0x22 */ 3067 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) 3068 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); 3069 /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */ 3070 } 3071 3072 bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw, 3073 enum rf_pwrstate rfpwr_state) 3074 { 3075 3076 bool bresult = true; 3077 struct rtl_priv *rtlpriv = rtl_priv(hw); 3078 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 3079 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 3080 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 3081 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 3082 u8 i, queue_id; 3083 struct rtl8192_tx_ring *ring = NULL; 3084 3085 if (rfpwr_state == ppsc->rfpwr_state) 3086 return false; 3087 switch (rfpwr_state) { 3088 case ERFON: 3089 if ((ppsc->rfpwr_state == ERFOFF) && 3090 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 3091 bool rtstatus; 3092 u32 InitializeCount = 0; 3093 do { 3094 InitializeCount++; 3095 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 3096 "IPS Set eRf nic enable\n"); 3097 rtstatus = rtl_ps_enable_nic(hw); 3098 } while (!rtstatus && (InitializeCount < 10)); 3099 3100 RT_CLEAR_PS_LEVEL(ppsc, 3101 RT_RF_OFF_LEVL_HALT_NIC); 3102 } else { 3103 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 3104 "awake, sleeped:%d ms state_inap:%x\n", 3105 jiffies_to_msecs(jiffies - 3106 ppsc->last_sleep_jiffies), 3107 rtlpriv->psc.state_inap); 3108 ppsc->last_awake_jiffies = jiffies; 3109 _rtl92d_phy_set_rfon(hw); 3110 } 3111 3112 if (mac->link_state == MAC80211_LINKED) 3113 rtlpriv->cfg->ops->led_control(hw, 3114 LED_CTL_LINK); 3115 else 3116 rtlpriv->cfg->ops->led_control(hw, 3117 LED_CTL_NO_LINK); 3118 break; 3119 case ERFOFF: 3120 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 3121 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 3122 "IPS Set eRf nic disable\n"); 3123 rtl_ps_disable_nic(hw); 3124 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 3125 } else { 3126 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 3127 rtlpriv->cfg->ops->led_control(hw, 3128 LED_CTL_NO_LINK); 3129 else 3130 rtlpriv->cfg->ops->led_control(hw, 3131 LED_CTL_POWER_OFF); 3132 } 3133 break; 3134 case ERFSLEEP: 3135 if (ppsc->rfpwr_state == ERFOFF) 3136 return false; 3137 3138 for (queue_id = 0, i = 0; 3139 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 3140 ring = &pcipriv->dev.tx_ring[queue_id]; 3141 if (skb_queue_len(&ring->queue) == 0 || 3142 queue_id == BEACON_QUEUE) { 3143 queue_id++; 3144 continue; 3145 } else if (rtlpci->pdev->current_state != PCI_D0) { 3146 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 3147 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", 3148 i + 1, queue_id); 3149 break; 3150 } else { 3151 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 3152 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", 3153 i + 1, queue_id, 3154 skb_queue_len(&ring->queue)); 3155 udelay(10); 3156 i++; 3157 } 3158 3159 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 3160 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 3161 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n", 3162 MAX_DOZE_WAITING_TIMES_9x, queue_id, 3163 skb_queue_len(&ring->queue)); 3164 break; 3165 } 3166 } 3167 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 3168 "Set rfsleep awaked:%d ms\n", 3169 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies)); 3170 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 3171 "sleep awaked:%d ms state_inap:%x\n", 3172 jiffies_to_msecs(jiffies - 3173 ppsc->last_awake_jiffies), 3174 rtlpriv->psc.state_inap); 3175 ppsc->last_sleep_jiffies = jiffies; 3176 _rtl92d_phy_set_rfsleep(hw); 3177 break; 3178 default: 3179 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 3180 "switch case %#x not processed\n", rfpwr_state); 3181 bresult = false; 3182 break; 3183 } 3184 if (bresult) 3185 ppsc->rfpwr_state = rfpwr_state; 3186 return bresult; 3187 } 3188 3189 void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw) 3190 { 3191 struct rtl_priv *rtlpriv = rtl_priv(hw); 3192 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3193 u8 offset = REG_MAC_PHY_CTRL_NORMAL; 3194 3195 switch (rtlhal->macphymode) { 3196 case DUALMAC_DUALPHY: 3197 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3198 "MacPhyMode: DUALMAC_DUALPHY\n"); 3199 rtl_write_byte(rtlpriv, offset, 0xF3); 3200 break; 3201 case SINGLEMAC_SINGLEPHY: 3202 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3203 "MacPhyMode: SINGLEMAC_SINGLEPHY\n"); 3204 rtl_write_byte(rtlpriv, offset, 0xF4); 3205 break; 3206 case DUALMAC_SINGLEPHY: 3207 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3208 "MacPhyMode: DUALMAC_SINGLEPHY\n"); 3209 rtl_write_byte(rtlpriv, offset, 0xF1); 3210 break; 3211 } 3212 } 3213 3214 void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw) 3215 { 3216 struct rtl_priv *rtlpriv = rtl_priv(hw); 3217 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3218 struct rtl_phy *rtlphy = &(rtlpriv->phy); 3219 3220 switch (rtlhal->macphymode) { 3221 case DUALMAC_SINGLEPHY: 3222 rtlphy->rf_type = RF_2T2R; 3223 rtlhal->version |= RF_TYPE_2T2R; 3224 rtlhal->bandset = BAND_ON_BOTH; 3225 rtlhal->current_bandtype = BAND_ON_2_4G; 3226 break; 3227 3228 case SINGLEMAC_SINGLEPHY: 3229 rtlphy->rf_type = RF_2T2R; 3230 rtlhal->version |= RF_TYPE_2T2R; 3231 rtlhal->bandset = BAND_ON_BOTH; 3232 rtlhal->current_bandtype = BAND_ON_2_4G; 3233 break; 3234 3235 case DUALMAC_DUALPHY: 3236 rtlphy->rf_type = RF_1T1R; 3237 rtlhal->version &= RF_TYPE_1T1R; 3238 /* Now we let MAC0 run on 5G band. */ 3239 if (rtlhal->interfaceindex == 0) { 3240 rtlhal->bandset = BAND_ON_5G; 3241 rtlhal->current_bandtype = BAND_ON_5G; 3242 } else { 3243 rtlhal->bandset = BAND_ON_2_4G; 3244 rtlhal->current_bandtype = BAND_ON_2_4G; 3245 } 3246 break; 3247 default: 3248 break; 3249 } 3250 } 3251 3252 u8 rtl92d_get_chnlgroup_fromarray(u8 chnl) 3253 { 3254 u8 group; 3255 u8 channel_info[59] = { 3256 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 3257 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 3258 58, 60, 62, 64, 100, 102, 104, 106, 108, 3259 110, 112, 114, 116, 118, 120, 122, 124, 3260 126, 128, 130, 132, 134, 136, 138, 140, 3261 149, 151, 153, 155, 157, 159, 161, 163, 3262 165 3263 }; 3264 3265 if (channel_info[chnl] <= 3) 3266 group = 0; 3267 else if (channel_info[chnl] <= 9) 3268 group = 1; 3269 else if (channel_info[chnl] <= 14) 3270 group = 2; 3271 else if (channel_info[chnl] <= 44) 3272 group = 3; 3273 else if (channel_info[chnl] <= 54) 3274 group = 4; 3275 else if (channel_info[chnl] <= 64) 3276 group = 5; 3277 else if (channel_info[chnl] <= 112) 3278 group = 6; 3279 else if (channel_info[chnl] <= 126) 3280 group = 7; 3281 else if (channel_info[chnl] <= 140) 3282 group = 8; 3283 else if (channel_info[chnl] <= 153) 3284 group = 9; 3285 else if (channel_info[chnl] <= 159) 3286 group = 10; 3287 else 3288 group = 11; 3289 return group; 3290 } 3291 3292 void rtl92d_phy_set_poweron(struct ieee80211_hw *hw) 3293 { 3294 struct rtl_priv *rtlpriv = rtl_priv(hw); 3295 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3296 unsigned long flags; 3297 u8 value8; 3298 u16 i; 3299 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1); 3300 3301 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ 3302 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 3303 value8 = rtl_read_byte(rtlpriv, mac_reg); 3304 value8 |= BIT(1); 3305 rtl_write_byte(rtlpriv, mac_reg, value8); 3306 } else { 3307 value8 = rtl_read_byte(rtlpriv, mac_reg); 3308 value8 &= (~BIT(1)); 3309 rtl_write_byte(rtlpriv, mac_reg, value8); 3310 } 3311 3312 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { 3313 value8 = rtl_read_byte(rtlpriv, REG_MAC0); 3314 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); 3315 } else { 3316 spin_lock_irqsave(&globalmutex_power, flags); 3317 if (rtlhal->interfaceindex == 0) { 3318 value8 = rtl_read_byte(rtlpriv, REG_MAC0); 3319 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); 3320 } else { 3321 value8 = rtl_read_byte(rtlpriv, REG_MAC1); 3322 rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON); 3323 } 3324 value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); 3325 spin_unlock_irqrestore(&globalmutex_power, flags); 3326 for (i = 0; i < 200; i++) { 3327 if ((value8 & BIT(7)) == 0) { 3328 break; 3329 } else { 3330 udelay(500); 3331 spin_lock_irqsave(&globalmutex_power, flags); 3332 value8 = rtl_read_byte(rtlpriv, 3333 REG_POWER_OFF_IN_PROCESS); 3334 spin_unlock_irqrestore(&globalmutex_power, 3335 flags); 3336 } 3337 } 3338 if (i == 200) 3339 RT_ASSERT(false, "Another mac power off over time\n"); 3340 } 3341 } 3342 3343 void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw) 3344 { 3345 struct rtl_priv *rtlpriv = rtl_priv(hw); 3346 3347 switch (rtlpriv->rtlhal.macphymode) { 3348 case DUALMAC_DUALPHY: 3349 rtl_write_byte(rtlpriv, REG_DMC, 0x0); 3350 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); 3351 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); 3352 break; 3353 case DUALMAC_SINGLEPHY: 3354 rtl_write_byte(rtlpriv, REG_DMC, 0xf8); 3355 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); 3356 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); 3357 break; 3358 case SINGLEMAC_SINGLEPHY: 3359 rtl_write_byte(rtlpriv, REG_DMC, 0x0); 3360 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10); 3361 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); 3362 break; 3363 default: 3364 break; 3365 } 3366 } 3367 3368 void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw) 3369 { 3370 struct rtl_priv *rtlpriv = rtl_priv(hw); 3371 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3372 struct rtl_phy *rtlphy = &(rtlpriv->phy); 3373 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 3374 u8 rfpath, i; 3375 3376 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n"); 3377 /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */ 3378 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 3379 /* r_select_5G for path_A/B,0x878 */ 3380 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); 3381 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); 3382 if (rtlhal->macphymode != DUALMAC_DUALPHY) { 3383 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); 3384 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); 3385 } 3386 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */ 3387 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); 3388 /* fc_area 0xd2c */ 3389 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); 3390 /* 5G LAN ON */ 3391 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); 3392 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */ 3393 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, 3394 0x40000100); 3395 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, 3396 0x40000100); 3397 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 3398 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 3399 BIT(10) | BIT(6) | BIT(5), 3400 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | 3401 (rtlefuse->eeprom_c9 & BIT(1)) | 3402 ((rtlefuse->eeprom_cc & BIT(1)) << 4)); 3403 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 3404 BIT(10) | BIT(6) | BIT(5), 3405 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | 3406 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | 3407 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); 3408 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); 3409 } else { 3410 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 3411 BIT(26) | BIT(22) | BIT(21) | BIT(10) | 3412 BIT(6) | BIT(5), 3413 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | 3414 (rtlefuse->eeprom_c9 & BIT(1)) | 3415 ((rtlefuse->eeprom_cc & BIT(1)) << 4) | 3416 ((rtlefuse->eeprom_c9 & BIT(7)) << 9) | 3417 ((rtlefuse->eeprom_c9 & BIT(5)) << 12) | 3418 ((rtlefuse->eeprom_cc & BIT(3)) << 18)); 3419 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 3420 BIT(10) | BIT(6) | BIT(5), 3421 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | 3422 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | 3423 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); 3424 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, 3425 BIT(10) | BIT(6) | BIT(5), 3426 ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) | 3427 ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) | 3428 ((rtlefuse->eeprom_cc & BIT(2)) << 3)); 3429 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 3430 BIT(31) | BIT(15), 0); 3431 } 3432 /* 1.5V_LDO */ 3433 } else { 3434 /* r_select_5G for path_A/B */ 3435 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); 3436 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); 3437 if (rtlhal->macphymode != DUALMAC_DUALPHY) { 3438 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); 3439 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); 3440 } 3441 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */ 3442 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); 3443 /* fc_area */ 3444 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); 3445 /* 5G LAN ON */ 3446 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); 3447 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */ 3448 if (rtlefuse->internal_pa_5g[0]) 3449 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, 3450 0x2d4000b5); 3451 else 3452 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, 3453 0x20000080); 3454 if (rtlefuse->internal_pa_5g[1]) 3455 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, 3456 0x2d4000b5); 3457 else 3458 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, 3459 0x20000080); 3460 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 3461 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 3462 BIT(10) | BIT(6) | BIT(5), 3463 (rtlefuse->eeprom_cc & BIT(5))); 3464 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 3465 ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); 3466 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 3467 (rtlefuse->eeprom_cc & BIT(4)) >> 4); 3468 } else { 3469 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 3470 BIT(26) | BIT(22) | BIT(21) | BIT(10) | 3471 BIT(6) | BIT(5), 3472 (rtlefuse->eeprom_cc & BIT(5)) | 3473 ((rtlefuse->eeprom_cc & BIT(7)) << 14)); 3474 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 3475 ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); 3476 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 3477 ((rtlefuse->eeprom_cc & BIT(6)) >> 6)); 3478 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 3479 BIT(31) | BIT(15), 3480 ((rtlefuse->eeprom_cc & BIT(4)) >> 4) | 3481 ((rtlefuse->eeprom_cc & BIT(6)) << 10)); 3482 } 3483 } 3484 /* update IQK related settings */ 3485 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); 3486 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); 3487 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00); 3488 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) | 3489 BIT(26) | BIT(24), 0x00); 3490 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 0x00); 3491 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00); 3492 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); 3493 3494 /* Update RF */ 3495 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 3496 rfpath++) { 3497 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 3498 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ 3499 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) | 3500 BIT(18), 0); 3501 /* RF0x0b[16:14] =3b'111 */ 3502 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, 3503 0x1c000, 0x07); 3504 } else { 3505 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ 3506 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | 3507 BIT(16) | BIT(18), 3508 (BIT(16) | BIT(8)) >> 8); 3509 } 3510 } 3511 /* Update for all band. */ 3512 /* DMDP */ 3513 if (rtlphy->rf_type == RF_1T1R) { 3514 /* Use antenna 0,0xc04,0xd04 */ 3515 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); 3516 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); 3517 3518 /* enable ad/da clock1 for dual-phy reg0x888 */ 3519 if (rtlhal->interfaceindex == 0) { 3520 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | 3521 BIT(13), 0x3); 3522 } else { 3523 rtl92d_phy_enable_anotherphy(hw, false); 3524 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 3525 "MAC1 use DBI to update 0x888\n"); 3526 /* 0x888 */ 3527 rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN, 3528 rtl92de_read_dword_dbi(hw, 3529 RFPGA0_ADDALLOCKEN, 3530 BIT(3)) | BIT(12) | BIT(13), 3531 BIT(3)); 3532 rtl92d_phy_powerdown_anotherphy(hw, false); 3533 } 3534 } else { 3535 /* Single PHY */ 3536 /* Use antenna 0 & 1,0xc04,0xd04 */ 3537 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); 3538 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); 3539 /* disable ad/da clock1,0x888 */ 3540 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); 3541 } 3542 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 3543 rfpath++) { 3544 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath, 3545 RF_CHNLBW, RFREG_OFFSET_MASK); 3546 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C, 3547 RFREG_OFFSET_MASK); 3548 } 3549 for (i = 0; i < 2; i++) 3550 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n", 3551 rtlphy->rfreg_chnlval[i]); 3552 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n"); 3553 3554 } 3555 3556 bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw) 3557 { 3558 struct rtl_priv *rtlpriv = rtl_priv(hw); 3559 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 3560 u8 u1btmp; 3561 unsigned long flags; 3562 3563 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { 3564 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); 3565 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON)); 3566 return true; 3567 } 3568 spin_lock_irqsave(&globalmutex_power, flags); 3569 if (rtlhal->interfaceindex == 0) { 3570 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); 3571 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON)); 3572 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1); 3573 u1btmp &= MAC1_ON; 3574 } else { 3575 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1); 3576 rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON)); 3577 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); 3578 u1btmp &= MAC0_ON; 3579 } 3580 if (u1btmp) { 3581 spin_unlock_irqrestore(&globalmutex_power, flags); 3582 return false; 3583 } 3584 u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); 3585 u1btmp |= BIT(7); 3586 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp); 3587 spin_unlock_irqrestore(&globalmutex_power, flags); 3588 return true; 3589 } 3590