1 /******************************************************************************
2  *
3  * Copyright(c) 2009-2012  Realtek Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * The full GNU General Public License is included in this distribution in the
15  * file called LICENSE.
16  *
17  * Contact Information:
18  * wlanfae <wlanfae@realtek.com>
19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20  * Hsinchu 300, Taiwan.
21  *
22  * Larry Finger <Larry.Finger@lwfinger.net>
23  *
24  *****************************************************************************/
25 
26 #include "../wifi.h"
27 #include "../pci.h"
28 #include "../ps.h"
29 #include "../core.h"
30 #include "reg.h"
31 #include "def.h"
32 #include "phy.h"
33 #include "rf.h"
34 #include "dm.h"
35 #include "table.h"
36 #include "sw.h"
37 #include "hw.h"
38 
39 #define MAX_RF_IMR_INDEX			12
40 #define MAX_RF_IMR_INDEX_NORMAL			13
41 #define RF_REG_NUM_FOR_C_CUT_5G			6
42 #define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA	7
43 #define RF_REG_NUM_FOR_C_CUT_2G			5
44 #define RF_CHNL_NUM_5G				19
45 #define RF_CHNL_NUM_5G_40M			17
46 #define TARGET_CHNL_NUM_5G			221
47 #define TARGET_CHNL_NUM_2G			14
48 #define CV_CURVE_CNT				64
49 
50 static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = {
51 	0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
52 };
53 
54 static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = {
55 	RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6
56 };
57 
58 static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
59 	RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8
60 };
61 
62 static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
63 	0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
64 };
65 
66 static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
67 	BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1),
68 	BIT(10) | BIT(9),
69 	BIT(18) | BIT(17) | BIT(16) | BIT(1),
70 	BIT(2) | BIT(1),
71 	BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11)
72 };
73 
74 static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = {
75 	36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108,
76 	112, 116, 120, 124, 128, 132, 136, 140
77 };
78 
79 static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = {
80 	38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114,
81 	118, 122, 126, 130, 134, 138
82 };
83 static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = {
84 	{0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
85 	{0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
86 	{0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
87 	{0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
88 	{0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
89 };
90 
91 static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = {
92 	{0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
93 	{0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
94 	{0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
95 };
96 
97 static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
98 
99 static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
100 	{0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
101 	{0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
102 	{0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
103 };
104 
105 /* [mode][patha+b][reg] */
106 static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = {
107 	{
108 		/* channel 1-14. */
109 		{
110 			0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
111 			0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
112 		},
113 		/* path 36-64 */
114 		{
115 			0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
116 			0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
117 			0x32c9a
118 		},
119 		/* 100 -165 */
120 		{
121 			0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
122 			0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
123 		}
124 	}
125 };
126 
127 static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
128 
129 static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
130 
131 static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = {
132 	25141, 25116, 25091, 25066, 25041,
133 	25016, 24991, 24966, 24941, 24917,
134 	24892, 24867, 24843, 24818, 24794,
135 	24770, 24765, 24721, 24697, 24672,
136 	24648, 24624, 24600, 24576, 24552,
137 	24528, 24504, 24480, 24457, 24433,
138 	24409, 24385, 24362, 24338, 24315,
139 	24291, 24268, 24245, 24221, 24198,
140 	24175, 24151, 24128, 24105, 24082,
141 	24059, 24036, 24013, 23990, 23967,
142 	23945, 23922, 23899, 23876, 23854,
143 	23831, 23809, 23786, 23764, 23741,
144 	23719, 23697, 23674, 23652, 23630,
145 	23608, 23586, 23564, 23541, 23519,
146 	23498, 23476, 23454, 23432, 23410,
147 	23388, 23367, 23345, 23323, 23302,
148 	23280, 23259, 23237, 23216, 23194,
149 	23173, 23152, 23130, 23109, 23088,
150 	23067, 23046, 23025, 23003, 22982,
151 	22962, 22941, 22920, 22899, 22878,
152 	22857, 22837, 22816, 22795, 22775,
153 	22754, 22733, 22713, 22692, 22672,
154 	22652, 22631, 22611, 22591, 22570,
155 	22550, 22530, 22510, 22490, 22469,
156 	22449, 22429, 22409, 22390, 22370,
157 	22350, 22336, 22310, 22290, 22271,
158 	22251, 22231, 22212, 22192, 22173,
159 	22153, 22134, 22114, 22095, 22075,
160 	22056, 22037, 22017, 21998, 21979,
161 	21960, 21941, 21921, 21902, 21883,
162 	21864, 21845, 21826, 21807, 21789,
163 	21770, 21751, 21732, 21713, 21695,
164 	21676, 21657, 21639, 21620, 21602,
165 	21583, 21565, 21546, 21528, 21509,
166 	21491, 21473, 21454, 21436, 21418,
167 	21400, 21381, 21363, 21345, 21327,
168 	21309, 21291, 21273, 21255, 21237,
169 	21219, 21201, 21183, 21166, 21148,
170 	21130, 21112, 21095, 21077, 21059,
171 	21042, 21024, 21007, 20989, 20972,
172 	25679, 25653, 25627, 25601, 25575,
173 	25549, 25523, 25497, 25471, 25446,
174 	25420, 25394, 25369, 25343, 25318,
175 	25292, 25267, 25242, 25216, 25191,
176 	25166
177 };
178 
179 /* channel 1~14 */
180 static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = {
181 	26084, 26030, 25976, 25923, 25869, 25816, 25764,
182 	25711, 25658, 25606, 25554, 25502, 25451, 25328
183 };
184 
185 static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask)
186 {
187 	u32 i;
188 
189 	for (i = 0; i <= 31; i++) {
190 		if (((bitmask >> i) & 0x1) == 1)
191 			break;
192 	}
193 
194 	return i;
195 }
196 
197 u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
198 {
199 	struct rtl_priv *rtlpriv = rtl_priv(hw);
200 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
201 	u32 returnvalue, originalvalue, bitshift;
202 
203 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
204 		 regaddr, bitmask);
205 	if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) {
206 		u8 dbi_direct = 0;
207 
208 		/* mac1 use phy0 read radio_b. */
209 		/* mac0 use phy1 read radio_b. */
210 		if (rtlhal->during_mac1init_radioa)
211 			dbi_direct = BIT(3);
212 		else if (rtlhal->during_mac0init_radiob)
213 			dbi_direct = BIT(3) | BIT(2);
214 		originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr,
215 			dbi_direct);
216 	} else {
217 		originalvalue = rtl_read_dword(rtlpriv, regaddr);
218 	}
219 	bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
220 	returnvalue = (originalvalue & bitmask) >> bitshift;
221 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
222 		 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
223 		 bitmask, regaddr, originalvalue);
224 	return returnvalue;
225 }
226 
227 void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
228 			   u32 regaddr, u32 bitmask, u32 data)
229 {
230 	struct rtl_priv *rtlpriv = rtl_priv(hw);
231 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
232 	u8 dbi_direct = 0;
233 	u32 originalvalue, bitshift;
234 
235 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
236 		 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
237 		 regaddr, bitmask, data);
238 	if (rtlhal->during_mac1init_radioa)
239 		dbi_direct = BIT(3);
240 	else if (rtlhal->during_mac0init_radiob)
241 		/* mac0 use phy1 write radio_b. */
242 		dbi_direct = BIT(3) | BIT(2);
243 	if (bitmask != MASKDWORD) {
244 		if (rtlhal->during_mac1init_radioa ||
245 		    rtlhal->during_mac0init_radiob)
246 			originalvalue = rtl92de_read_dword_dbi(hw,
247 					(u16) regaddr,
248 					dbi_direct);
249 		else
250 			originalvalue = rtl_read_dword(rtlpriv, regaddr);
251 		bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
252 		data = ((originalvalue & (~bitmask)) | (data << bitshift));
253 	}
254 	if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob)
255 		rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct);
256 	else
257 		rtl_write_dword(rtlpriv, regaddr, data);
258 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
259 		 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
260 		 regaddr, bitmask, data);
261 }
262 
263 static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
264 				      enum radio_path rfpath, u32 offset)
265 {
266 
267 	struct rtl_priv *rtlpriv = rtl_priv(hw);
268 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
269 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
270 	u32 newoffset;
271 	u32 tmplong, tmplong2;
272 	u8 rfpi_enable = 0;
273 	u32 retvalue;
274 
275 	newoffset = offset;
276 	tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
277 	if (rfpath == RF90_PATH_A)
278 		tmplong2 = tmplong;
279 	else
280 		tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
281 	tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
282 		(newoffset << 23) | BLSSIREADEDGE;
283 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
284 		tmplong & (~BLSSIREADEDGE));
285 	udelay(10);
286 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
287 	udelay(50);
288 	udelay(50);
289 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
290 		tmplong | BLSSIREADEDGE);
291 	udelay(10);
292 	if (rfpath == RF90_PATH_A)
293 		rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
294 			      BIT(8));
295 	else if (rfpath == RF90_PATH_B)
296 		rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
297 			      BIT(8));
298 	if (rfpi_enable)
299 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
300 			BLSSIREADBACKDATA);
301 	else
302 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
303 			BLSSIREADBACKDATA);
304 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n",
305 		 rfpath, pphyreg->rf_rb, retvalue);
306 	return retvalue;
307 }
308 
309 static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
310 					enum radio_path rfpath,
311 					u32 offset, u32 data)
312 {
313 	u32 data_and_addr;
314 	u32 newoffset;
315 	struct rtl_priv *rtlpriv = rtl_priv(hw);
316 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
317 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
318 
319 	newoffset = offset;
320 	/* T65 RF */
321 	data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
322 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
323 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
324 		 rfpath, pphyreg->rf3wire_offset, data_and_addr);
325 }
326 
327 u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
328 			    enum radio_path rfpath, u32 regaddr, u32 bitmask)
329 {
330 	struct rtl_priv *rtlpriv = rtl_priv(hw);
331 	u32 original_value, readback_value, bitshift;
332 	unsigned long flags;
333 
334 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
335 		 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
336 		 regaddr, rfpath, bitmask);
337 	spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
338 	original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);
339 	bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
340 	readback_value = (original_value & bitmask) >> bitshift;
341 	spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
342 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
343 		 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
344 		 regaddr, rfpath, bitmask, original_value);
345 	return readback_value;
346 }
347 
348 void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
349 	u32 regaddr, u32 bitmask, u32 data)
350 {
351 	struct rtl_priv *rtlpriv = rtl_priv(hw);
352 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
353 	u32 original_value, bitshift;
354 	unsigned long flags;
355 
356 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
357 		 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
358 		 regaddr, bitmask, data, rfpath);
359 	if (bitmask == 0)
360 		return;
361 	spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
362 	if (rtlphy->rf_mode != RF_OP_BY_FW) {
363 		if (bitmask != RFREG_OFFSET_MASK) {
364 			original_value = _rtl92d_phy_rf_serial_read(hw,
365 				rfpath, regaddr);
366 			bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
367 			data = ((original_value & (~bitmask)) |
368 				(data << bitshift));
369 		}
370 		_rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);
371 	}
372 	spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
373 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
374 		 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
375 		 regaddr, bitmask, data, rfpath);
376 }
377 
378 bool rtl92d_phy_mac_config(struct ieee80211_hw *hw)
379 {
380 	struct rtl_priv *rtlpriv = rtl_priv(hw);
381 	u32 i;
382 	u32 arraylength;
383 	u32 *ptrarray;
384 
385 	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
386 	arraylength = MAC_2T_ARRAYLENGTH;
387 	ptrarray = rtl8192de_mac_2tarray;
388 	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:Rtl819XMAC_Array\n");
389 	for (i = 0; i < arraylength; i = i + 2)
390 		rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
391 	if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
392 		/* improve 2-stream TX EVM */
393 		/* rtl_write_byte(rtlpriv, 0x14,0x71); */
394 		/* AMPDU aggregation number 9 */
395 		/* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */
396 		rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B);
397 	} else {
398 		/* 92D need to test to decide the num. */
399 		rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07);
400 	}
401 	return true;
402 }
403 
404 static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
405 {
406 	struct rtl_priv *rtlpriv = rtl_priv(hw);
407 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
408 
409 	/* RF Interface Sowrtware Control */
410 	/* 16 LSBs if read 32-bit from 0x870 */
411 	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
412 	/* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
413 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
414 	/* 16 LSBs if read 32-bit from 0x874 */
415 	rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
416 	/* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
417 
418 	rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
419 	/* RF Interface Readback Value */
420 	/* 16 LSBs if read 32-bit from 0x8E0 */
421 	rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
422 	/* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
423 	rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
424 	/* 16 LSBs if read 32-bit from 0x8E4 */
425 	rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
426 	/* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
427 	rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
428 
429 	/* RF Interface Output (and Enable) */
430 	/* 16 LSBs if read 32-bit from 0x860 */
431 	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
432 	/* 16 LSBs if read 32-bit from 0x864 */
433 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
434 
435 	/* RF Interface (Output and)  Enable */
436 	/* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
437 	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
438 	/* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
439 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
440 
441 	/* Addr of LSSI. Wirte RF register by driver */
442 	/* LSSI Parameter */
443 	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
444 				 RFPGA0_XA_LSSIPARAMETER;
445 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
446 				 RFPGA0_XB_LSSIPARAMETER;
447 
448 	/* RF parameter */
449 	/* BB Band Select */
450 	rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
451 	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
452 	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
453 	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
454 
455 	/* Tx AGC Gain Stage (same for all path. Should we remove this?) */
456 	/* Tx gain stage */
457 	rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
458 	/* Tx gain stage */
459 	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
460 	/* Tx gain stage */
461 	rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
462 	/* Tx gain stage */
463 	rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
464 
465 	/* Tranceiver A~D HSSI Parameter-1 */
466 	/* wire control parameter1 */
467 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
468 	/* wire control parameter1 */
469 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
470 
471 	/* Tranceiver A~D HSSI Parameter-2 */
472 	/* wire control parameter2 */
473 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
474 	/* wire control parameter2 */
475 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
476 
477 	/* RF switch Control */
478 	/* TR/Ant switch control */
479 	rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
480 	rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
481 	rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
482 	rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
483 
484 	/* AGC control 1 */
485 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
486 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
487 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
488 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
489 
490 	/* AGC control 2  */
491 	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
492 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
493 	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
494 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
495 
496 	/* RX AFE control 1 */
497 	rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
498 	rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
499 	rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
500 	rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
501 
502 	/*RX AFE control 1 */
503 	rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
504 	rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
505 	rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
506 	rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
507 
508 	/* Tx AFE control 1 */
509 	rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATxIQIMBALANCE;
510 	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTxIQIMBALANCE;
511 	rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTxIQIMBALANCE;
512 	rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTxIQIMBALANCE;
513 
514 	/* Tx AFE control 2 */
515 	rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATxAFE;
516 	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE;
517 	rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTxAFE;
518 	rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE;
519 
520 	/* Tranceiver LSSI Readback SI mode */
521 	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
522 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
523 	rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
524 	rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
525 
526 	/* Tranceiver LSSI Readback PI mode */
527 	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
528 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
529 }
530 
531 static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
532 	u8 configtype)
533 {
534 	int i;
535 	u32 *phy_regarray_table;
536 	u32 *agctab_array_table = NULL;
537 	u32 *agctab_5garray_table;
538 	u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen;
539 	struct rtl_priv *rtlpriv = rtl_priv(hw);
540 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
541 
542 	/* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */
543 	if (rtlhal->interfaceindex == 0) {
544 		agctab_arraylen = AGCTAB_ARRAYLENGTH;
545 		agctab_array_table = rtl8192de_agctab_array;
546 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
547 			 " ===> phy:MAC0, Rtl819XAGCTAB_Array\n");
548 	} else {
549 		if (rtlhal->current_bandtype == BAND_ON_2_4G) {
550 			agctab_arraylen = AGCTAB_2G_ARRAYLENGTH;
551 			agctab_array_table = rtl8192de_agctab_2garray;
552 			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
553 				 " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n");
554 		} else {
555 			agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH;
556 			agctab_5garray_table = rtl8192de_agctab_5garray;
557 			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
558 				 " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n");
559 
560 		}
561 	}
562 	phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH;
563 	phy_regarray_table = rtl8192de_phy_reg_2tarray;
564 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
565 		 " ===> phy:Rtl819XPHY_REG_Array_PG\n");
566 	if (configtype == BASEBAND_CONFIG_PHY_REG) {
567 		for (i = 0; i < phy_reg_arraylen; i = i + 2) {
568 			rtl_addr_delay(phy_regarray_table[i]);
569 			rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
570 				      phy_regarray_table[i + 1]);
571 			udelay(1);
572 			RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
573 				 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
574 				 phy_regarray_table[i],
575 				 phy_regarray_table[i + 1]);
576 		}
577 	} else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
578 		if (rtlhal->interfaceindex == 0) {
579 			for (i = 0; i < agctab_arraylen; i = i + 2) {
580 				rtl_set_bbreg(hw, agctab_array_table[i],
581 					MASKDWORD,
582 					agctab_array_table[i + 1]);
583 				/* Add 1us delay between BB/RF register
584 				 * setting. */
585 				udelay(1);
586 				RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
587 					 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
588 					 agctab_array_table[i],
589 					 agctab_array_table[i + 1]);
590 			}
591 			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
592 				 "Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n");
593 		} else {
594 			if (rtlhal->current_bandtype == BAND_ON_2_4G) {
595 				for (i = 0; i < agctab_arraylen; i = i + 2) {
596 					rtl_set_bbreg(hw, agctab_array_table[i],
597 						MASKDWORD,
598 						agctab_array_table[i + 1]);
599 					/* Add 1us delay between BB/RF register
600 					 * setting. */
601 					udelay(1);
602 					RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
603 						 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
604 						 agctab_array_table[i],
605 						 agctab_array_table[i + 1]);
606 				}
607 				RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
608 					 "Load Rtl819XAGCTAB_2GArray\n");
609 			} else {
610 				for (i = 0; i < agctab_5garraylen; i = i + 2) {
611 					rtl_set_bbreg(hw,
612 						agctab_5garray_table[i],
613 						MASKDWORD,
614 						agctab_5garray_table[i + 1]);
615 					/* Add 1us delay between BB/RF registeri
616 					 * setting. */
617 					udelay(1);
618 					RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
619 						 "The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
620 						 agctab_5garray_table[i],
621 						 agctab_5garray_table[i + 1]);
622 				}
623 				RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
624 					 "Load Rtl819XAGCTAB_5GArray\n");
625 			}
626 		}
627 	}
628 	return true;
629 }
630 
631 static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
632 						   u32 regaddr, u32 bitmask,
633 						   u32 data)
634 {
635 	struct rtl_priv *rtlpriv = rtl_priv(hw);
636 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
637 	int index;
638 
639 	if (regaddr == RTXAGC_A_RATE18_06)
640 		index = 0;
641 	else if (regaddr == RTXAGC_A_RATE54_24)
642 		index = 1;
643 	else if (regaddr == RTXAGC_A_CCK1_MCS32)
644 		index = 6;
645 	else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00)
646 		index = 7;
647 	else if (regaddr == RTXAGC_A_MCS03_MCS00)
648 		index = 2;
649 	else if (regaddr == RTXAGC_A_MCS07_MCS04)
650 		index = 3;
651 	else if (regaddr == RTXAGC_A_MCS11_MCS08)
652 		index = 4;
653 	else if (regaddr == RTXAGC_A_MCS15_MCS12)
654 		index = 5;
655 	else if (regaddr == RTXAGC_B_RATE18_06)
656 		index = 8;
657 	else if (regaddr == RTXAGC_B_RATE54_24)
658 		index = 9;
659 	else if (regaddr == RTXAGC_B_CCK1_55_MCS32)
660 		index = 14;
661 	else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff)
662 		index = 15;
663 	else if (regaddr == RTXAGC_B_MCS03_MCS00)
664 		index = 10;
665 	else if (regaddr == RTXAGC_B_MCS07_MCS04)
666 		index = 11;
667 	else if (regaddr == RTXAGC_B_MCS11_MCS08)
668 		index = 12;
669 	else if (regaddr == RTXAGC_B_MCS15_MCS12)
670 		index = 13;
671 	else
672 		return;
673 
674 	rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
675 	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
676 		 "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
677 		 rtlphy->pwrgroup_cnt, index,
678 		 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]);
679 	if (index == 13)
680 		rtlphy->pwrgroup_cnt++;
681 }
682 
683 static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
684 	u8 configtype)
685 {
686 	struct rtl_priv *rtlpriv = rtl_priv(hw);
687 	int i;
688 	u32 *phy_regarray_table_pg;
689 	u16 phy_regarray_pg_len;
690 
691 	phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH;
692 	phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
693 	if (configtype == BASEBAND_CONFIG_PHY_REG) {
694 		for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
695 			rtl_addr_delay(phy_regarray_table_pg[i]);
696 			_rtl92d_store_pwrindex_diffrate_offset(hw,
697 				phy_regarray_table_pg[i],
698 				phy_regarray_table_pg[i + 1],
699 				phy_regarray_table_pg[i + 2]);
700 		}
701 	} else {
702 		RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
703 			 "configtype != BaseBand_Config_PHY_REG\n");
704 	}
705 	return true;
706 }
707 
708 static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw)
709 {
710 	struct rtl_priv *rtlpriv = rtl_priv(hw);
711 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
712 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
713 	bool rtstatus = true;
714 
715 	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n");
716 	rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
717 		BASEBAND_CONFIG_PHY_REG);
718 	if (!rtstatus) {
719 		pr_err("Write BB Reg Fail!!\n");
720 		return false;
721 	}
722 
723 	/* if (rtlphy->rf_type == RF_1T2R) {
724 	 *      _rtl92c_phy_bb_config_1t(hw);
725 	 *     RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
726 	 *} */
727 
728 	if (rtlefuse->autoload_failflag == false) {
729 		rtlphy->pwrgroup_cnt = 0;
730 		rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw,
731 			BASEBAND_CONFIG_PHY_REG);
732 	}
733 	if (!rtstatus) {
734 		pr_err("BB_PG Reg Fail!!\n");
735 		return false;
736 	}
737 	rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
738 		BASEBAND_CONFIG_AGC_TAB);
739 	if (!rtstatus) {
740 		pr_err("AGC Table Fail\n");
741 		return false;
742 	}
743 	rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
744 		RFPGA0_XA_HSSIPARAMETER2, 0x200));
745 
746 	return true;
747 }
748 
749 bool rtl92d_phy_bb_config(struct ieee80211_hw *hw)
750 {
751 	struct rtl_priv *rtlpriv = rtl_priv(hw);
752 	u16 regval;
753 	u32 regvaldw;
754 	u8 value;
755 
756 	_rtl92d_phy_init_bb_rf_register_definition(hw);
757 	regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
758 	rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
759 		       regval | BIT(13) | BIT(0) | BIT(1));
760 	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
761 	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
762 	/* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */
763 	value = rtl_read_byte(rtlpriv, REG_RF_CTRL);
764 	rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
765 		RF_SDMRSTB);
766 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
767 		FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
768 	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
769 	if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
770 		regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
771 		rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
772 	}
773 
774 	return _rtl92d_phy_bb_config(hw);
775 }
776 
777 bool rtl92d_phy_rf_config(struct ieee80211_hw *hw)
778 {
779 	return rtl92d_phy_rf6052_config(hw);
780 }
781 
782 bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
783 					  enum rf_content content,
784 					  enum radio_path rfpath)
785 {
786 	int i;
787 	u32 *radioa_array_table;
788 	u32 *radiob_array_table;
789 	u16 radioa_arraylen, radiob_arraylen;
790 	struct rtl_priv *rtlpriv = rtl_priv(hw);
791 
792 	radioa_arraylen = RADIOA_2T_ARRAYLENGTH;
793 	radioa_array_table = rtl8192de_radioa_2tarray;
794 	radiob_arraylen = RADIOB_2T_ARRAYLENGTH;
795 	radiob_array_table = rtl8192de_radiob_2tarray;
796 	if (rtlpriv->efuse.internal_pa_5g[0]) {
797 		radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH;
798 		radioa_array_table = rtl8192de_radioa_2t_int_paarray;
799 	}
800 	if (rtlpriv->efuse.internal_pa_5g[1]) {
801 		radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH;
802 		radiob_array_table = rtl8192de_radiob_2t_int_paarray;
803 	}
804 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
805 		 "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n");
806 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
807 		 "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n");
808 	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
809 
810 	/* this only happens when DMDP, mac0 start on 2.4G,
811 	 * mac1 start on 5G, mac 0 has to set phy0&phy1
812 	 * pathA or mac1 has to set phy0&phy1 pathA */
813 	if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) {
814 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
815 			 " ===> althougth Path A, we load radiob.txt\n");
816 		radioa_arraylen = radiob_arraylen;
817 		radioa_array_table = radiob_array_table;
818 	}
819 	switch (rfpath) {
820 	case RF90_PATH_A:
821 		for (i = 0; i < radioa_arraylen; i = i + 2) {
822 			rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
823 					RFREG_OFFSET_MASK,
824 					radioa_array_table[i + 1]);
825 		}
826 		break;
827 	case RF90_PATH_B:
828 		for (i = 0; i < radiob_arraylen; i = i + 2) {
829 			rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
830 					RFREG_OFFSET_MASK,
831 					radiob_array_table[i + 1]);
832 		}
833 		break;
834 	case RF90_PATH_C:
835 	case RF90_PATH_D:
836 		pr_err("switch case %#x not processed\n", rfpath);
837 		break;
838 	}
839 	return true;
840 }
841 
842 void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
843 {
844 	struct rtl_priv *rtlpriv = rtl_priv(hw);
845 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
846 
847 	rtlphy->default_initialgain[0] =
848 	    (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
849 	rtlphy->default_initialgain[1] =
850 	    (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
851 	rtlphy->default_initialgain[2] =
852 	    (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
853 	rtlphy->default_initialgain[3] =
854 	    (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
855 	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
856 		 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
857 		 rtlphy->default_initialgain[0],
858 		 rtlphy->default_initialgain[1],
859 		 rtlphy->default_initialgain[2],
860 		 rtlphy->default_initialgain[3]);
861 	rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
862 					      MASKBYTE0);
863 	rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
864 					      MASKDWORD);
865 	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
866 		 "Default framesync (0x%x) = 0x%x\n",
867 		 ROFDM0_RXDETECTOR3, rtlphy->framesync);
868 }
869 
870 static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
871 	u8 *cckpowerlevel, u8 *ofdmpowerlevel)
872 {
873 	struct rtl_priv *rtlpriv = rtl_priv(hw);
874 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
875 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
876 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
877 	u8 index = (channel - 1);
878 
879 	/* 1. CCK */
880 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
881 		/* RF-A */
882 		cckpowerlevel[RF90_PATH_A] =
883 				 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
884 		/* RF-B */
885 		cckpowerlevel[RF90_PATH_B] =
886 				 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
887 	} else {
888 		cckpowerlevel[RF90_PATH_A] = 0;
889 		cckpowerlevel[RF90_PATH_B] = 0;
890 	}
891 	/* 2. OFDM for 1S or 2S */
892 	if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
893 		/*  Read HT 40 OFDM TX power */
894 		ofdmpowerlevel[RF90_PATH_A] =
895 		    rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
896 		ofdmpowerlevel[RF90_PATH_B] =
897 		    rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
898 	} else if (rtlphy->rf_type == RF_2T2R) {
899 		/* Read HT 40 OFDM TX power */
900 		ofdmpowerlevel[RF90_PATH_A] =
901 		    rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
902 		ofdmpowerlevel[RF90_PATH_B] =
903 		    rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
904 	}
905 }
906 
907 static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw,
908 	u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
909 {
910 	struct rtl_priv *rtlpriv = rtl_priv(hw);
911 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
912 
913 	rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
914 	rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
915 }
916 
917 static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl)
918 {
919 	u8 place = chnl;
920 
921 	if (chnl > 14) {
922 		for (place = 14; place < sizeof(channel5g); place++) {
923 			if (channel5g[place] == chnl) {
924 				place++;
925 				break;
926 			}
927 		}
928 	}
929 	return place;
930 }
931 
932 void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
933 {
934 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
935 	struct rtl_priv *rtlpriv = rtl_priv(hw);
936 	u8 cckpowerlevel[2], ofdmpowerlevel[2];
937 
938 	if (!rtlefuse->txpwr_fromeprom)
939 		return;
940 	channel = _rtl92c_phy_get_rightchnlplace(channel);
941 	_rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0],
942 		&ofdmpowerlevel[0]);
943 	if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
944 		_rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
945 				&ofdmpowerlevel[0]);
946 	if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
947 		rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
948 	rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
949 }
950 
951 void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
952 			    enum nl80211_channel_type ch_type)
953 {
954 	struct rtl_priv *rtlpriv = rtl_priv(hw);
955 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
956 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
957 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
958 	unsigned long flag = 0;
959 	u8 reg_prsr_rsc;
960 	u8 reg_bw_opmode;
961 
962 	if (rtlphy->set_bwmode_inprogress)
963 		return;
964 	if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
965 		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
966 			 "FALSE driver sleep or unload\n");
967 		return;
968 	}
969 	rtlphy->set_bwmode_inprogress = true;
970 	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
971 		 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
972 		 "20MHz" : "40MHz");
973 	reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
974 	reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
975 	switch (rtlphy->current_chan_bw) {
976 	case HT_CHANNEL_WIDTH_20:
977 		reg_bw_opmode |= BW_OPMODE_20MHZ;
978 		rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
979 		break;
980 	case HT_CHANNEL_WIDTH_20_40:
981 		reg_bw_opmode &= ~BW_OPMODE_20MHZ;
982 		rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
983 
984 		reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
985 			(mac->cur_40_prime_sc << 5);
986 		rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
987 		break;
988 	default:
989 		pr_err("unknown bandwidth: %#X\n",
990 		       rtlphy->current_chan_bw);
991 		break;
992 	}
993 	switch (rtlphy->current_chan_bw) {
994 	case HT_CHANNEL_WIDTH_20:
995 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
996 		rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
997 		/* SET BIT10 BIT11  for receive cck */
998 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
999 			      BIT(11), 3);
1000 		break;
1001 	case HT_CHANNEL_WIDTH_20_40:
1002 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1003 		rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1004 		/* Set Control channel to upper or lower.
1005 		 * These settings are required only for 40MHz */
1006 		if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1007 			rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1008 			rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND,
1009 				(mac->cur_40_prime_sc >> 1));
1010 			rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1011 		}
1012 		rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1013 		/* SET BIT10 BIT11  for receive cck */
1014 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1015 			      BIT(11), 0);
1016 		rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1017 			(mac->cur_40_prime_sc ==
1018 			HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1019 		break;
1020 	default:
1021 		pr_err("unknown bandwidth: %#X\n",
1022 		       rtlphy->current_chan_bw);
1023 		break;
1024 
1025 	}
1026 	rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1027 	rtlphy->set_bwmode_inprogress = false;
1028 	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
1029 }
1030 
1031 static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
1032 {
1033 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
1034 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
1035 	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00);
1036 	rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
1037 }
1038 
1039 static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
1040 {
1041 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1042 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1043 	u8 value8;
1044 
1045 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
1046 	rtlhal->bandset = band;
1047 	rtlhal->current_bandtype = band;
1048 	if (IS_92D_SINGLEPHY(rtlhal->version))
1049 		rtlhal->bandset = BAND_ON_BOTH;
1050 	/* stop RX/Tx */
1051 	_rtl92d_phy_stop_trx_before_changeband(hw);
1052 	/* reconfig BB/RF according to wireless mode */
1053 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1054 		/* BB & RF Config */
1055 		RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n");
1056 		if (rtlhal->interfaceindex == 1)
1057 			_rtl92d_phy_config_bb_with_headerfile(hw,
1058 				BASEBAND_CONFIG_AGC_TAB);
1059 	} else {
1060 		/* 5G band */
1061 		RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n");
1062 		if (rtlhal->interfaceindex == 1)
1063 			_rtl92d_phy_config_bb_with_headerfile(hw,
1064 				BASEBAND_CONFIG_AGC_TAB);
1065 	}
1066 	rtl92d_update_bbrf_configuration(hw);
1067 	if (rtlhal->current_bandtype == BAND_ON_2_4G)
1068 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1069 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1070 
1071 	/* 20M BW. */
1072 	/* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */
1073 	rtlhal->reloadtxpowerindex = true;
1074 	/* notice fw know band status  0x81[1]/0x53[1] = 0: 5G, 1: 2G */
1075 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1076 		value8 = rtl_read_byte(rtlpriv,	(rtlhal->interfaceindex ==
1077 			0 ? REG_MAC0 : REG_MAC1));
1078 		value8 |= BIT(1);
1079 		rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1080 			0 ? REG_MAC0 : REG_MAC1), value8);
1081 	} else {
1082 		value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1083 			0 ? REG_MAC0 : REG_MAC1));
1084 		value8 &= (~BIT(1));
1085 		rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1086 			0 ? REG_MAC0 : REG_MAC1), value8);
1087 	}
1088 	mdelay(1);
1089 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n");
1090 }
1091 
1092 static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1093 	u8 channel, u8 rfpath)
1094 {
1095 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1096 	u32 imr_num = MAX_RF_IMR_INDEX;
1097 	u32 rfmask = RFREG_OFFSET_MASK;
1098 	u8 group, i;
1099 	unsigned long flag = 0;
1100 
1101 	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath);
1102 	if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
1103 		RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1104 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1105 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1106 		/* fc area 0xd2c */
1107 		if (channel > 99)
1108 			rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1109 				      BIT(14), 2);
1110 		else
1111 			rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1112 				      BIT(14), 1);
1113 		/* leave 0 for channel1-14. */
1114 		group = channel <= 64 ? 1 : 2;
1115 		imr_num = MAX_RF_IMR_INDEX_NORMAL;
1116 		for (i = 0; i < imr_num; i++)
1117 			rtl_set_rfreg(hw, (enum radio_path)rfpath,
1118 				      rf_reg_for_5g_swchnl_normal[i], rfmask,
1119 				      rf_imr_param_normal[0][group][i]);
1120 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
1121 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1);
1122 	} else {
1123 		/* G band. */
1124 		RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1125 			 "Load RF IMR parameters for G band. IMR already setting %d\n",
1126 			 rtlpriv->rtlhal.load_imrandiqk_setting_for2g);
1127 		RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1128 		if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) {
1129 			RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1130 				 "Load RF IMR parameters for G band. %d\n",
1131 				 rfpath);
1132 			rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1133 			rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1134 			rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1135 				      0x00f00000, 0xf);
1136 			imr_num = MAX_RF_IMR_INDEX_NORMAL;
1137 			for (i = 0; i < imr_num; i++) {
1138 				rtl_set_rfreg(hw, (enum radio_path)rfpath,
1139 					      rf_reg_for_5g_swchnl_normal[i],
1140 					      RFREG_OFFSET_MASK,
1141 					      rf_imr_param_normal[0][0][i]);
1142 			}
1143 			rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1144 				      0x00f00000, 0);
1145 			rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3);
1146 			rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1147 		}
1148 	}
1149 	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1150 }
1151 
1152 static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw,
1153 	u8 rfpath, u32 *pu4_regval)
1154 {
1155 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1156 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1157 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1158 
1159 	RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "====>\n");
1160 	/*----Store original RFENV control type----*/
1161 	switch (rfpath) {
1162 	case RF90_PATH_A:
1163 	case RF90_PATH_C:
1164 		*pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV);
1165 		break;
1166 	case RF90_PATH_B:
1167 	case RF90_PATH_D:
1168 		*pu4_regval =
1169 		    rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16);
1170 		break;
1171 	}
1172 	/*----Set RF_ENV enable----*/
1173 	rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
1174 	udelay(1);
1175 	/*----Set RF_ENV output high----*/
1176 	rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
1177 	udelay(1);
1178 	/* Set bit number of Address and Data for RF register */
1179 	/* Set 1 to 4 bits for 8255 */
1180 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0);
1181 	udelay(1);
1182 	/*Set 0 to 12 bits for 8255 */
1183 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
1184 	udelay(1);
1185 	RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<====\n");
1186 }
1187 
1188 static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath,
1189 				       u32 *pu4_regval)
1190 {
1191 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1192 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1193 	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1194 
1195 	RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n");
1196 	/*----Restore RFENV control type----*/
1197 	switch (rfpath) {
1198 	case RF90_PATH_A:
1199 	case RF90_PATH_C:
1200 		rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval);
1201 		break;
1202 	case RF90_PATH_B:
1203 	case RF90_PATH_D:
1204 		rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
1205 			      *pu4_regval);
1206 		break;
1207 	}
1208 	RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n");
1209 }
1210 
1211 static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1212 {
1213 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1214 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1215 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1216 	u8 path = rtlhal->current_bandtype ==
1217 	    BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B;
1218 	u8 index = 0, i = 0, rfpath = RF90_PATH_A;
1219 	bool need_pwr_down = false, internal_pa = false;
1220 	u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2;
1221 
1222 	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n");
1223 	/* config path A for 5G */
1224 	if (rtlhal->current_bandtype == BAND_ON_5G) {
1225 		RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n");
1226 		u4tmp = curveindex_5g[channel - 1];
1227 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1228 			"ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp);
1229 		for (i = 0; i < RF_CHNL_NUM_5G; i++) {
1230 			if (channel == rf_chnl_5g[i] && channel <= 140)
1231 				index = 0;
1232 		}
1233 		for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) {
1234 			if (channel == rf_chnl_5g_40m[i] && channel <= 140)
1235 				index = 1;
1236 		}
1237 		if (channel == 149 || channel == 155 || channel == 161)
1238 			index = 2;
1239 		else if (channel == 151 || channel == 153 || channel == 163
1240 			 || channel == 165)
1241 			index = 3;
1242 		else if (channel == 157 || channel == 159)
1243 			index = 4;
1244 
1245 		if (rtlhal->macphymode == DUALMAC_DUALPHY
1246 		    && rtlhal->interfaceindex == 1) {
1247 			need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false);
1248 			rtlhal->during_mac1init_radioa = true;
1249 			/* asume no this case */
1250 			if (need_pwr_down)
1251 				_rtl92d_phy_enable_rf_env(hw, path,
1252 							  &u4regvalue);
1253 		}
1254 		for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) {
1255 			if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
1256 				rtl_set_rfreg(hw, (enum radio_path)path,
1257 					      rf_reg_for_c_cut_5g[i],
1258 					      RFREG_OFFSET_MASK, 0xE439D);
1259 			} else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
1260 				u4tmp2 = (rf_reg_pram_c_5g[index][i] &
1261 				     0x7FF) | (u4tmp << 11);
1262 				if (channel == 36)
1263 					u4tmp2 &= ~(BIT(7) | BIT(6));
1264 				rtl_set_rfreg(hw, (enum radio_path)path,
1265 					      rf_reg_for_c_cut_5g[i],
1266 					      RFREG_OFFSET_MASK, u4tmp2);
1267 			} else {
1268 				rtl_set_rfreg(hw, (enum radio_path)path,
1269 					      rf_reg_for_c_cut_5g[i],
1270 					      RFREG_OFFSET_MASK,
1271 					      rf_reg_pram_c_5g[index][i]);
1272 			}
1273 			RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1274 				 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n",
1275 				 rf_reg_for_c_cut_5g[i],
1276 				 rf_reg_pram_c_5g[index][i],
1277 				 path, index,
1278 				 rtl_get_rfreg(hw, (enum radio_path)path,
1279 					       rf_reg_for_c_cut_5g[i],
1280 					       RFREG_OFFSET_MASK));
1281 		}
1282 		if (need_pwr_down)
1283 			_rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1284 		if (rtlhal->during_mac1init_radioa)
1285 			rtl92d_phy_powerdown_anotherphy(hw, false);
1286 		if (channel < 149)
1287 			value = 0x07;
1288 		else if (channel >= 149)
1289 			value = 0x02;
1290 		if (channel >= 36 && channel <= 64)
1291 			index = 0;
1292 		else if (channel >= 100 && channel <= 140)
1293 			index = 1;
1294 		else
1295 			index = 2;
1296 		for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1297 			rfpath++) {
1298 			if (rtlhal->macphymode == DUALMAC_DUALPHY &&
1299 				rtlhal->interfaceindex == 1)	/* MAC 1 5G */
1300 				internal_pa = rtlpriv->efuse.internal_pa_5g[1];
1301 			else
1302 				internal_pa =
1303 					 rtlpriv->efuse.internal_pa_5g[rfpath];
1304 			if (internal_pa) {
1305 				for (i = 0;
1306 				     i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA;
1307 				     i++) {
1308 					rtl_set_rfreg(hw, rfpath,
1309 						rf_for_c_cut_5g_internal_pa[i],
1310 						RFREG_OFFSET_MASK,
1311 						rf_pram_c_5g_int_pa[index][i]);
1312 					RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
1313 						 "offset 0x%x value 0x%x path %d index %d\n",
1314 						 rf_for_c_cut_5g_internal_pa[i],
1315 						 rf_pram_c_5g_int_pa[index][i],
1316 						 rfpath, index);
1317 				}
1318 			} else {
1319 				rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
1320 					      mask, value);
1321 			}
1322 		}
1323 	} else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1324 		RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n");
1325 		u4tmp = curveindex_2g[channel - 1];
1326 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1327 			"ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
1328 		if (channel == 1 || channel == 2 || channel == 4 || channel == 9
1329 		    || channel == 10 || channel == 11 || channel == 12)
1330 			index = 0;
1331 		else if (channel == 3 || channel == 13 || channel == 14)
1332 			index = 1;
1333 		else if (channel >= 5 && channel <= 8)
1334 			index = 2;
1335 		if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1336 			path = RF90_PATH_A;
1337 			if (rtlhal->interfaceindex == 0) {
1338 				need_pwr_down =
1339 					 rtl92d_phy_enable_anotherphy(hw, true);
1340 				rtlhal->during_mac0init_radiob = true;
1341 
1342 				if (need_pwr_down)
1343 					_rtl92d_phy_enable_rf_env(hw, path,
1344 								  &u4regvalue);
1345 			}
1346 		}
1347 		for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) {
1348 			if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
1349 				rtl_set_rfreg(hw, (enum radio_path)path,
1350 					rf_reg_for_c_cut_2g[i],
1351 					RFREG_OFFSET_MASK,
1352 					(rf_reg_param_for_c_cut_2g[index][i] |
1353 					BIT(17)));
1354 			else
1355 				rtl_set_rfreg(hw, (enum radio_path)path,
1356 					      rf_reg_for_c_cut_2g[i],
1357 					      RFREG_OFFSET_MASK,
1358 					      rf_reg_param_for_c_cut_2g
1359 					      [index][i]);
1360 			RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1361 				 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n",
1362 				 rf_reg_for_c_cut_2g[i],
1363 				 rf_reg_param_for_c_cut_2g[index][i],
1364 				 rf_reg_mask_for_c_cut_2g[i], path, index,
1365 				 rtl_get_rfreg(hw, (enum radio_path)path,
1366 					       rf_reg_for_c_cut_2g[i],
1367 					       RFREG_OFFSET_MASK));
1368 		}
1369 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1370 			"cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1371 			rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1372 
1373 		rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1374 			      RFREG_OFFSET_MASK,
1375 			      rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1376 		if (need_pwr_down)
1377 			_rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1378 		if (rtlhal->during_mac0init_radiob)
1379 			rtl92d_phy_powerdown_anotherphy(hw, true);
1380 	}
1381 	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
1382 }
1383 
1384 u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl)
1385 {
1386 	u8 channel_all[59] = {
1387 		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
1388 		36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
1389 		60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
1390 		114, 116, 118, 120, 122, 124, 126, 128,	130,
1391 		132, 134, 136, 138, 140, 149, 151, 153, 155,
1392 		157, 159, 161, 163, 165
1393 	};
1394 	u8 place = chnl;
1395 
1396 	if (chnl > 14) {
1397 		for (place = 14; place < sizeof(channel_all); place++) {
1398 			if (channel_all[place] == chnl)
1399 				return place - 13;
1400 		}
1401 	}
1402 
1403 	return 0;
1404 }
1405 
1406 #define MAX_TOLERANCE		5
1407 #define IQK_DELAY_TIME		1	/* ms */
1408 #define MAX_TOLERANCE_92D	3
1409 
1410 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1411 static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1412 {
1413 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1414 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1415 	u32 regeac, rege94, rege9c, regea4;
1416 	u8 result = 0;
1417 
1418 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK!\n");
1419 	/* path-A IQK setting */
1420 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1421 	if (rtlhal->interfaceindex == 0) {
1422 		rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1423 		rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1424 	} else {
1425 		rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22);
1426 		rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22);
1427 	}
1428 	rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1429 	rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206);
1430 	/* path-B IQK setting */
1431 	if (configpathb) {
1432 		rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1433 		rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1434 		rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1435 		rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206);
1436 	}
1437 	/* LO calibration setting */
1438 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1439 	rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1440 	/* One shot, path A LOK & IQK */
1441 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "One shot, path A LOK & IQK!\n");
1442 	rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1443 	rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1444 	/* delay x ms */
1445 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
1446 		"Delay %d ms for One shot, path A LOK & IQK\n",
1447 		IQK_DELAY_TIME);
1448 	mdelay(IQK_DELAY_TIME);
1449 	/* Check failed */
1450 	regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1451 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1452 	rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1453 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe94 = 0x%x\n", rege94);
1454 	rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1455 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe9c = 0x%x\n", rege9c);
1456 	regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1457 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xea4 = 0x%x\n", regea4);
1458 	if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1459 	    (((rege9c & 0x03FF0000) >> 16) != 0x42))
1460 		result |= 0x01;
1461 	else			/* if Tx not OK, ignore Rx */
1462 		return result;
1463 	/* if Tx is OK, check whether Rx is OK */
1464 	if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) &&
1465 	    (((regeac & 0x03FF0000) >> 16) != 0x36))
1466 		result |= 0x02;
1467 	else
1468 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A Rx IQK fail!!\n");
1469 	return result;
1470 }
1471 
1472 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1473 static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1474 					  bool configpathb)
1475 {
1476 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1477 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1478 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1479 	u32 regeac, rege94, rege9c, regea4;
1480 	u8 result = 0;
1481 	u8 i;
1482 	u8 retrycount = 2;
1483 	u32 TxOKBit = BIT(28), RxOKBit = BIT(27);
1484 
1485 	if (rtlhal->interfaceindex == 1) {	/* PHY1 */
1486 		TxOKBit = BIT(31);
1487 		RxOKBit = BIT(30);
1488 	}
1489 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK!\n");
1490 	/* path-A IQK setting */
1491 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1492 	rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1493 	rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1494 	rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307);
1495 	rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960);
1496 	/* path-B IQK setting */
1497 	if (configpathb) {
1498 		rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1499 		rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1500 		rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000);
1501 		rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000);
1502 	}
1503 	/* LO calibration setting */
1504 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1505 	rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1506 	/* path-A PA on */
1507 	rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60);
1508 	rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30);
1509 	for (i = 0; i < retrycount; i++) {
1510 		/* One shot, path A LOK & IQK */
1511 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1512 			"One shot, path A LOK & IQK!\n");
1513 		rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1514 		rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1515 		/* delay x ms */
1516 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1517 			"Delay %d ms for One shot, path A LOK & IQK.\n",
1518 			IQK_DELAY_TIME);
1519 		mdelay(IQK_DELAY_TIME * 10);
1520 		/* Check failed */
1521 		regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1522 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1523 		rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1524 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe94 = 0x%x\n", rege94);
1525 		rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1526 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xe9c = 0x%x\n", rege9c);
1527 		regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1528 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xea4 = 0x%x\n", regea4);
1529 		if (!(regeac & TxOKBit) &&
1530 		     (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1531 			result |= 0x01;
1532 		} else { /* if Tx not OK, ignore Rx */
1533 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1534 				"Path A Tx IQK fail!!\n");
1535 			continue;
1536 		}
1537 
1538 		/* if Tx is OK, check whether Rx is OK */
1539 		if (!(regeac & RxOKBit) &&
1540 		    (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1541 			result |= 0x02;
1542 			break;
1543 		} else {
1544 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1545 				"Path A Rx IQK fail!!\n");
1546 		}
1547 	}
1548 	/* path A PA off */
1549 	rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1550 		      rtlphy->iqk_bb_backup[0]);
1551 	rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD,
1552 		      rtlphy->iqk_bb_backup[1]);
1553 	return result;
1554 }
1555 
1556 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1557 static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1558 {
1559 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1560 	u32 regeac, regeb4, regebc, regec4, regecc;
1561 	u8 result = 0;
1562 
1563 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B IQK!\n");
1564 	/* One shot, path B LOK & IQK */
1565 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "One shot, path A LOK & IQK!\n");
1566 	rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1567 	rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1568 	/* delay x ms  */
1569 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
1570 		"Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME);
1571 	mdelay(IQK_DELAY_TIME);
1572 	/* Check failed */
1573 	regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1574 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1575 	regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1576 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeb4 = 0x%x\n", regeb4);
1577 	regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1578 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xebc = 0x%x\n", regebc);
1579 	regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1580 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xec4 = 0x%x\n", regec4);
1581 	regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1582 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xecc = 0x%x\n", regecc);
1583 	if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1584 	    (((regebc & 0x03FF0000) >> 16) != 0x42))
1585 		result |= 0x01;
1586 	else
1587 		return result;
1588 	if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
1589 	    (((regecc & 0x03FF0000) >> 16) != 0x36))
1590 		result |= 0x02;
1591 	else
1592 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B Rx IQK fail!!\n");
1593 	return result;
1594 }
1595 
1596 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1597 static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1598 {
1599 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1600 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1601 	u32 regeac, regeb4, regebc, regec4, regecc;
1602 	u8 result = 0;
1603 	u8 i;
1604 	u8 retrycount = 2;
1605 
1606 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path B IQK!\n");
1607 	/* path-A IQK setting */
1608 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A IQK setting!\n");
1609 	rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1610 	rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1611 	rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000);
1612 	rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000);
1613 
1614 	/* path-B IQK setting */
1615 	rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1616 	rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1617 	rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307);
1618 	rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960);
1619 
1620 	/* LO calibration setting */
1621 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LO calibration setting!\n");
1622 	rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1623 
1624 	/* path-B PA on */
1625 	rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700);
1626 	rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30);
1627 
1628 	for (i = 0; i < retrycount; i++) {
1629 		/* One shot, path B LOK & IQK */
1630 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1631 			"One shot, path A LOK & IQK!\n");
1632 		rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000);
1633 		rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1634 
1635 		/* delay x ms */
1636 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
1637 			"Delay %d ms for One shot, path B LOK & IQK.\n", 10);
1638 		mdelay(IQK_DELAY_TIME * 10);
1639 
1640 		/* Check failed */
1641 		regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1642 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeac = 0x%x\n", regeac);
1643 		regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1644 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xeb4 = 0x%x\n", regeb4);
1645 		regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1646 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xebc = 0x%x\n", regebc);
1647 		regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1648 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xec4 = 0x%x\n", regec4);
1649 		regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1650 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "0xecc = 0x%x\n", regecc);
1651 		if (!(regeac & BIT(31)) &&
1652 		    (((regeb4 & 0x03FF0000) >> 16) != 0x142))
1653 			result |= 0x01;
1654 		else
1655 			continue;
1656 		if (!(regeac & BIT(30)) &&
1657 		    (((regec4 & 0x03FF0000) >> 16) != 0x132)) {
1658 			result |= 0x02;
1659 			break;
1660 		} else {
1661 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1662 				"Path B Rx IQK fail!!\n");
1663 		}
1664 	}
1665 
1666 	/* path B PA off */
1667 	rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1668 		      rtlphy->iqk_bb_backup[0]);
1669 	rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD,
1670 		      rtlphy->iqk_bb_backup[2]);
1671 	return result;
1672 }
1673 
1674 static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1675 					    u32 *adda_reg, u32 *adda_backup,
1676 					    u32 regnum)
1677 {
1678 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1679 	u32 i;
1680 
1681 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Save ADDA parameters.\n");
1682 	for (i = 0; i < regnum; i++)
1683 		adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD);
1684 }
1685 
1686 static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
1687 	u32 *macreg, u32 *macbackup)
1688 {
1689 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1690 	u32 i;
1691 
1692 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Save MAC parameters.\n");
1693 	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1694 		macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1695 	macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1696 }
1697 
1698 static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1699 					      u32 *adda_reg, u32 *adda_backup,
1700 					      u32 regnum)
1701 {
1702 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1703 	u32 i;
1704 
1705 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
1706 		"Reload ADDA power saving parameters !\n");
1707 	for (i = 0; i < regnum; i++)
1708 		rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]);
1709 }
1710 
1711 static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
1712 					     u32 *macreg, u32 *macbackup)
1713 {
1714 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1715 	u32 i;
1716 
1717 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Reload MAC parameters !\n");
1718 	for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1719 		rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1720 	rtl_write_byte(rtlpriv, macreg[i], macbackup[i]);
1721 }
1722 
1723 static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1724 		u32 *adda_reg, bool patha_on, bool is2t)
1725 {
1726 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1727 	u32 pathon;
1728 	u32 i;
1729 
1730 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "ADDA ON.\n");
1731 	pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;
1732 	if (patha_on)
1733 		pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
1734 		    0x04db25a4 : 0x0b1b25a4;
1735 	for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1736 		rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon);
1737 }
1738 
1739 static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1740 						u32 *macreg, u32 *macbackup)
1741 {
1742 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1743 	u32 i;
1744 
1745 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "MAC settings for Calibration.\n");
1746 	rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1747 
1748 	for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1749 		rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] &
1750 			       (~BIT(3))));
1751 	rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1752 }
1753 
1754 static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1755 {
1756 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1757 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path-A standby mode!\n");
1758 
1759 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1760 	rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000);
1761 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1762 }
1763 
1764 static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
1765 {
1766 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1767 	u32 mode;
1768 
1769 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
1770 		"BB Switch to %s mode!\n", pi_mode ? "PI" : "SI");
1771 	mode = pi_mode ? 0x01000100 : 0x01000000;
1772 	rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1773 	rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1774 }
1775 
1776 static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1777 				     u8 t, bool is2t)
1778 {
1779 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1780 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1781 	u32 i;
1782 	u8 patha_ok, pathb_ok;
1783 	static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1784 		RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1785 		0xe78, 0xe7c, 0xe80, 0xe84,
1786 		0xe88, 0xe8c, 0xed0, 0xed4,
1787 		0xed8, 0xedc, 0xee0, 0xeec
1788 	};
1789 	static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1790 		0x522, 0x550, 0x551, 0x040
1791 	};
1792 	static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1793 		RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1794 		RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1795 		RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1796 		RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1797 		ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1798 	};
1799 	const u32 retrycount = 2;
1800 	u32 bbvalue;
1801 
1802 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK for 2.4G :Start!!!\n");
1803 	if (t == 0) {
1804 		bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1805 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "==>0x%08x\n", bbvalue);
1806 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1807 			is2t ? "2T2R" : "1T1R");
1808 
1809 		/*  Save ADDA parameters, turn Path A ADDA on */
1810 		_rtl92d_phy_save_adda_registers(hw, adda_reg,
1811 			rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1812 		_rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1813 			rtlphy->iqk_mac_backup);
1814 		_rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1815 			rtlphy->iqk_bb_backup, IQK_BB_REG_NUM);
1816 	}
1817 	_rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1818 	if (t == 0)
1819 		rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1820 				RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1821 
1822 	/*  Switch BB to PI mode to do IQ Calibration. */
1823 	if (!rtlphy->rfpi_enable)
1824 		_rtl92d_phy_pimode_switch(hw, true);
1825 
1826 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1827 	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1828 	rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1829 	rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000);
1830 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1831 	if (is2t) {
1832 		rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD,
1833 			      0x00010000);
1834 		rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD,
1835 			      0x00010000);
1836 	}
1837 	/* MAC settings */
1838 	_rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1839 					    rtlphy->iqk_mac_backup);
1840 	/* Page B init */
1841 	rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1842 	if (is2t)
1843 		rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1844 	/* IQ calibration setting */
1845 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK setting!\n");
1846 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1847 	rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1848 	rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1849 	for (i = 0; i < retrycount; i++) {
1850 		patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
1851 		if (patha_ok == 0x03) {
1852 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1853 				"Path A IQK Success!!\n");
1854 			result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1855 					0x3FF0000) >> 16;
1856 			result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1857 					0x3FF0000) >> 16;
1858 			result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1859 					0x3FF0000) >> 16;
1860 			result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1861 					0x3FF0000) >> 16;
1862 			break;
1863 		} else if (i == (retrycount - 1) && patha_ok == 0x01) {
1864 			/* Tx IQK OK */
1865 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1866 				"Path A IQK Only  Tx Success!!\n");
1867 
1868 			result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1869 					0x3FF0000) >> 16;
1870 			result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1871 					0x3FF0000) >> 16;
1872 		}
1873 	}
1874 	if (0x00 == patha_ok)
1875 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK failed!!\n");
1876 	if (is2t) {
1877 		_rtl92d_phy_patha_standby(hw);
1878 		/* Turn Path B ADDA on */
1879 		_rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
1880 		for (i = 0; i < retrycount; i++) {
1881 			pathb_ok = _rtl92d_phy_pathb_iqk(hw);
1882 			if (pathb_ok == 0x03) {
1883 				RTPRINT(rtlpriv, FINIT, INIT_IQK,
1884 					"Path B IQK Success!!\n");
1885 				result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1886 					       MASKDWORD) & 0x3FF0000) >> 16;
1887 				result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1888 					       MASKDWORD) & 0x3FF0000) >> 16;
1889 				result[t][6] = (rtl_get_bbreg(hw, 0xec4,
1890 					       MASKDWORD) & 0x3FF0000) >> 16;
1891 				result[t][7] = (rtl_get_bbreg(hw, 0xecc,
1892 					       MASKDWORD) & 0x3FF0000) >> 16;
1893 				break;
1894 			} else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1895 				/* Tx IQK OK */
1896 				RTPRINT(rtlpriv, FINIT, INIT_IQK,
1897 					"Path B Only Tx IQK Success!!\n");
1898 				result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1899 					       MASKDWORD) & 0x3FF0000) >> 16;
1900 				result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1901 					       MASKDWORD) & 0x3FF0000) >> 16;
1902 			}
1903 		}
1904 		if (0x00 == pathb_ok)
1905 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
1906 				"Path B IQK failed!!\n");
1907 	}
1908 
1909 	/* Back to BB mode, load original value */
1910 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
1911 		"IQK:Back to BB mode, load original value!\n");
1912 
1913 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1914 	if (t != 0) {
1915 		/* Switch back BB to SI mode after finish IQ Calibration. */
1916 		if (!rtlphy->rfpi_enable)
1917 			_rtl92d_phy_pimode_switch(hw, false);
1918 		/* Reload ADDA power saving parameters */
1919 		_rtl92d_phy_reload_adda_registers(hw, adda_reg,
1920 				rtlphy->adda_backup, IQK_ADDA_REG_NUM);
1921 		/* Reload MAC parameters */
1922 		_rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
1923 					rtlphy->iqk_mac_backup);
1924 		if (is2t)
1925 			_rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
1926 							  rtlphy->iqk_bb_backup,
1927 							  IQK_BB_REG_NUM);
1928 		else
1929 			_rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
1930 							  rtlphy->iqk_bb_backup,
1931 							  IQK_BB_REG_NUM - 1);
1932 		/* load 0xe30 IQC default value */
1933 		rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
1934 		rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
1935 	}
1936 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "<==\n");
1937 }
1938 
1939 static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
1940 					       long result[][8], u8 t)
1941 {
1942 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1943 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1944 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1945 	u8 patha_ok, pathb_ok;
1946 	static u32 adda_reg[IQK_ADDA_REG_NUM] = {
1947 		RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
1948 		0xe78, 0xe7c, 0xe80, 0xe84,
1949 		0xe88, 0xe8c, 0xed0, 0xed4,
1950 		0xed8, 0xedc, 0xee0, 0xeec
1951 	};
1952 	static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1953 		0x522, 0x550, 0x551, 0x040
1954 	};
1955 	static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1956 		RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
1957 		RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
1958 		RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
1959 		RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
1960 		ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
1961 	};
1962 	u32 bbvalue;
1963 	bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
1964 
1965 	/* Note: IQ calibration must be performed after loading
1966 	 * PHY_REG.txt , and radio_a, radio_b.txt */
1967 
1968 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK for 5G NORMAL:Start!!!\n");
1969 	mdelay(IQK_DELAY_TIME * 20);
1970 	if (t == 0) {
1971 		bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1972 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "==>0x%08x\n", bbvalue);
1973 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1974 			is2t ? "2T2R" : "1T1R");
1975 		/* Save ADDA parameters, turn Path A ADDA on */
1976 		_rtl92d_phy_save_adda_registers(hw, adda_reg,
1977 						rtlphy->adda_backup,
1978 						IQK_ADDA_REG_NUM);
1979 		_rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
1980 					       rtlphy->iqk_mac_backup);
1981 		if (is2t)
1982 			_rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1983 							rtlphy->iqk_bb_backup,
1984 							IQK_BB_REG_NUM);
1985 		else
1986 			_rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
1987 							rtlphy->iqk_bb_backup,
1988 							IQK_BB_REG_NUM - 1);
1989 	}
1990 	_rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
1991 	/* MAC settings */
1992 	_rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1993 			rtlphy->iqk_mac_backup);
1994 	if (t == 0)
1995 		rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1996 			RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1997 	/*  Switch BB to PI mode to do IQ Calibration. */
1998 	if (!rtlphy->rfpi_enable)
1999 		_rtl92d_phy_pimode_switch(hw, true);
2000 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2001 	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
2002 	rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
2003 	rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000);
2004 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
2005 
2006 	/* Page B init */
2007 	rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
2008 	if (is2t)
2009 		rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
2010 	/* IQ calibration setting  */
2011 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "IQK setting!\n");
2012 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
2013 	rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00);
2014 	rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
2015 	patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
2016 	if (patha_ok == 0x03) {
2017 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK Success!!\n");
2018 		result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
2019 				0x3FF0000) >> 16;
2020 		result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
2021 				0x3FF0000) >> 16;
2022 		result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
2023 				0x3FF0000) >> 16;
2024 		result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
2025 				0x3FF0000) >> 16;
2026 	} else if (patha_ok == 0x01) {	/* Tx IQK OK */
2027 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2028 			"Path A IQK Only  Tx Success!!\n");
2029 
2030 		result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
2031 				0x3FF0000) >> 16;
2032 		result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
2033 				0x3FF0000) >> 16;
2034 	} else {
2035 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "Path A IQK Fail!!\n");
2036 	}
2037 	if (is2t) {
2038 		/* _rtl92d_phy_patha_standby(hw); */
2039 		/* Turn Path B ADDA on  */
2040 		_rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2041 		pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw);
2042 		if (pathb_ok == 0x03) {
2043 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
2044 				"Path B IQK Success!!\n");
2045 			result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2046 			     0x3FF0000) >> 16;
2047 			result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2048 			     0x3FF0000) >> 16;
2049 			result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
2050 			     0x3FF0000) >> 16;
2051 			result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
2052 			     0x3FF0000) >> 16;
2053 		} else if (pathb_ok == 0x01) { /* Tx IQK OK */
2054 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
2055 				"Path B Only Tx IQK Success!!\n");
2056 			result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2057 			     0x3FF0000) >> 16;
2058 			result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2059 			     0x3FF0000) >> 16;
2060 		} else {
2061 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
2062 				"Path B IQK failed!!\n");
2063 		}
2064 	}
2065 
2066 	/* Back to BB mode, load original value */
2067 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
2068 		"IQK:Back to BB mode, load original value!\n");
2069 	rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
2070 	if (t != 0) {
2071 		if (is2t)
2072 			_rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2073 							  rtlphy->iqk_bb_backup,
2074 							  IQK_BB_REG_NUM);
2075 		else
2076 			_rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2077 							  rtlphy->iqk_bb_backup,
2078 							  IQK_BB_REG_NUM - 1);
2079 		/* Reload MAC parameters */
2080 		_rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2081 				rtlphy->iqk_mac_backup);
2082 		/*  Switch back BB to SI mode after finish IQ Calibration. */
2083 		if (!rtlphy->rfpi_enable)
2084 			_rtl92d_phy_pimode_switch(hw, false);
2085 		/* Reload ADDA power saving parameters */
2086 		_rtl92d_phy_reload_adda_registers(hw, adda_reg,
2087 						  rtlphy->adda_backup,
2088 						  IQK_ADDA_REG_NUM);
2089 	}
2090 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "<==\n");
2091 }
2092 
2093 static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw,
2094 	long result[][8], u8 c1, u8 c2)
2095 {
2096 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2097 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2098 	u32 i, j, diff, sim_bitmap, bound;
2099 	u8 final_candidate[2] = {0xFF, 0xFF};	/* for path A and path B */
2100 	bool bresult = true;
2101 	bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2102 
2103 	if (is2t)
2104 		bound = 8;
2105 	else
2106 		bound = 4;
2107 	sim_bitmap = 0;
2108 	for (i = 0; i < bound; i++) {
2109 		diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] -
2110 		       result[c2][i]) : (result[c2][i] - result[c1][i]);
2111 		if (diff > MAX_TOLERANCE_92D) {
2112 			if ((i == 2 || i == 6) && !sim_bitmap) {
2113 				if (result[c1][i] + result[c1][i + 1] == 0)
2114 					final_candidate[(i / 4)] = c2;
2115 				else if (result[c2][i] + result[c2][i + 1] == 0)
2116 					final_candidate[(i / 4)] = c1;
2117 				else
2118 					sim_bitmap = sim_bitmap | (1 << i);
2119 			} else {
2120 				sim_bitmap = sim_bitmap | (1 << i);
2121 			}
2122 		}
2123 	}
2124 	if (sim_bitmap == 0) {
2125 		for (i = 0; i < (bound / 4); i++) {
2126 			if (final_candidate[i] != 0xFF) {
2127 				for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2128 					result[3][j] =
2129 						 result[final_candidate[i]][j];
2130 				bresult = false;
2131 			}
2132 		}
2133 		return bresult;
2134 	}
2135 	if (!(sim_bitmap & 0x0F)) { /* path A OK */
2136 		for (i = 0; i < 4; i++)
2137 			result[3][i] = result[c1][i];
2138 	} else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */
2139 		for (i = 0; i < 2; i++)
2140 			result[3][i] = result[c1][i];
2141 	}
2142 	if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */
2143 		for (i = 4; i < 8; i++)
2144 			result[3][i] = result[c1][i];
2145 	} else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */
2146 		for (i = 4; i < 6; i++)
2147 			result[3][i] = result[c1][i];
2148 	}
2149 	return false;
2150 }
2151 
2152 static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2153 					      bool iqk_ok, long result[][8],
2154 					      u8 final_candidate, bool txonly)
2155 {
2156 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2157 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2158 	u32 oldval_0, val_x, tx0_a, reg;
2159 	long val_y, tx0_c;
2160 	bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
2161 	    rtlhal->macphymode == DUALMAC_DUALPHY;
2162 
2163 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
2164 		"Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed");
2165 	if (final_candidate == 0xFF) {
2166 		return;
2167 	} else if (iqk_ok) {
2168 		oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2169 			MASKDWORD) >> 22) & 0x3FF;	/* OFDM0_D */
2170 		val_x = result[final_candidate][0];
2171 		if ((val_x & 0x00000200) != 0)
2172 			val_x = val_x | 0xFFFFFC00;
2173 		tx0_a = (val_x * oldval_0) >> 8;
2174 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2175 			"X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n",
2176 			val_x, tx0_a, oldval_0);
2177 		rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a);
2178 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2179 			      ((val_x * oldval_0 >> 7) & 0x1));
2180 		val_y = result[final_candidate][1];
2181 		if ((val_y & 0x00000200) != 0)
2182 			val_y = val_y | 0xFFFFFC00;
2183 		/* path B IQK result + 3 */
2184 		if (rtlhal->interfaceindex == 1 &&
2185 			rtlhal->current_bandtype == BAND_ON_5G)
2186 			val_y += 3;
2187 		tx0_c = (val_y * oldval_0) >> 8;
2188 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2189 			"Y = 0x%lx, tx0_c = 0x%lx\n",
2190 			val_y, tx0_c);
2191 		rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000,
2192 			      ((tx0_c & 0x3C0) >> 6));
2193 		rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000,
2194 			      (tx0_c & 0x3F));
2195 		if (is2t)
2196 			rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2197 				      ((val_y * oldval_0 >> 7) & 0x1));
2198 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
2199 			rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2200 				      MASKDWORD));
2201 		if (txonly) {
2202 			RTPRINT(rtlpriv, FINIT, INIT_IQK,  "only Tx OK\n");
2203 			return;
2204 		}
2205 		reg = result[final_candidate][2];
2206 		rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2207 		reg = result[final_candidate][3] & 0x3F;
2208 		rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2209 		reg = (result[final_candidate][3] >> 6) & 0xF;
2210 		rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
2211 	}
2212 }
2213 
2214 static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2215 	bool iqk_ok, long result[][8], u8 final_candidate, bool txonly)
2216 {
2217 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2218 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2219 	u32 oldval_1, val_x, tx1_a, reg;
2220 	long val_y, tx1_c;
2221 
2222 	RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n",
2223 		iqk_ok ? "Success" : "Failed");
2224 	if (final_candidate == 0xFF) {
2225 		return;
2226 	} else if (iqk_ok) {
2227 		oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
2228 					  MASKDWORD) >> 22) & 0x3FF;
2229 		val_x = result[final_candidate][4];
2230 		if ((val_x & 0x00000200) != 0)
2231 			val_x = val_x | 0xFFFFFC00;
2232 		tx1_a = (val_x * oldval_1) >> 8;
2233 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n",
2234 			val_x, tx1_a);
2235 		rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a);
2236 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2237 			      ((val_x * oldval_1 >> 7) & 0x1));
2238 		val_y = result[final_candidate][5];
2239 		if ((val_y & 0x00000200) != 0)
2240 			val_y = val_y | 0xFFFFFC00;
2241 		if (rtlhal->current_bandtype == BAND_ON_5G)
2242 			val_y += 3;
2243 		tx1_c = (val_y * oldval_1) >> 8;
2244 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n",
2245 			val_y, tx1_c);
2246 		rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000,
2247 			      ((tx1_c & 0x3C0) >> 6));
2248 		rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000,
2249 			      (tx1_c & 0x3F));
2250 		rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
2251 			      ((val_y * oldval_1 >> 7) & 0x1));
2252 		if (txonly)
2253 			return;
2254 		reg = result[final_candidate][6];
2255 		rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2256 		reg = result[final_candidate][7] & 0x3F;
2257 		rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2258 		reg = (result[final_candidate][7] >> 6) & 0xF;
2259 		rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
2260 	}
2261 }
2262 
2263 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2264 {
2265 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2266 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2267 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2268 	long result[4][8];
2269 	u8 i, final_candidate, indexforchannel;
2270 	bool patha_ok, pathb_ok;
2271 	long rege94, rege9c, regea4, regeac, regeb4;
2272 	long regebc, regec4, regecc, regtmp = 0;
2273 	bool is12simular, is13simular, is23simular;
2274 	unsigned long flag = 0;
2275 
2276 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
2277 		"IQK:Start!!!channel %d\n", rtlphy->current_channel);
2278 	for (i = 0; i < 8; i++) {
2279 		result[0][i] = 0;
2280 		result[1][i] = 0;
2281 		result[2][i] = 0;
2282 		result[3][i] = 0;
2283 	}
2284 	final_candidate = 0xff;
2285 	patha_ok = false;
2286 	pathb_ok = false;
2287 	is12simular = false;
2288 	is23simular = false;
2289 	is13simular = false;
2290 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
2291 		"IQK !!!currentband %d\n", rtlhal->current_bandtype);
2292 	rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
2293 	for (i = 0; i < 3; i++) {
2294 		if (rtlhal->current_bandtype == BAND_ON_5G) {
2295 			_rtl92d_phy_iq_calibrate_5g_normal(hw, result, i);
2296 		} else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2297 			if (IS_92D_SINGLEPHY(rtlhal->version))
2298 				_rtl92d_phy_iq_calibrate(hw, result, i, true);
2299 			else
2300 				_rtl92d_phy_iq_calibrate(hw, result, i, false);
2301 		}
2302 		if (i == 1) {
2303 			is12simular = _rtl92d_phy_simularity_compare(hw, result,
2304 								     0, 1);
2305 			if (is12simular) {
2306 				final_candidate = 0;
2307 				break;
2308 			}
2309 		}
2310 		if (i == 2) {
2311 			is13simular = _rtl92d_phy_simularity_compare(hw, result,
2312 								     0, 2);
2313 			if (is13simular) {
2314 				final_candidate = 0;
2315 				break;
2316 			}
2317 			is23simular = _rtl92d_phy_simularity_compare(hw, result,
2318 								     1, 2);
2319 			if (is23simular) {
2320 				final_candidate = 1;
2321 			} else {
2322 				for (i = 0; i < 8; i++)
2323 					regtmp += result[3][i];
2324 
2325 				if (regtmp != 0)
2326 					final_candidate = 3;
2327 				else
2328 					final_candidate = 0xFF;
2329 			}
2330 		}
2331 	}
2332 	rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
2333 	for (i = 0; i < 4; i++) {
2334 		rege94 = result[i][0];
2335 		rege9c = result[i][1];
2336 		regea4 = result[i][2];
2337 		regeac = result[i][3];
2338 		regeb4 = result[i][4];
2339 		regebc = result[i][5];
2340 		regec4 = result[i][6];
2341 		regecc = result[i][7];
2342 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2343 			"IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2344 			rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2345 			regecc);
2346 	}
2347 	if (final_candidate != 0xff) {
2348 		rtlphy->reg_e94 = rege94 = result[final_candidate][0];
2349 		rtlphy->reg_e9c = rege9c = result[final_candidate][1];
2350 		regea4 = result[final_candidate][2];
2351 		regeac = result[final_candidate][3];
2352 		rtlphy->reg_eb4 = regeb4 = result[final_candidate][4];
2353 		rtlphy->reg_ebc = regebc = result[final_candidate][5];
2354 		regec4 = result[final_candidate][6];
2355 		regecc = result[final_candidate][7];
2356 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2357 			"IQK: final_candidate is %x\n", final_candidate);
2358 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2359 			"IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n",
2360 			rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2361 			regecc);
2362 		patha_ok = pathb_ok = true;
2363 	} else {
2364 		rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */
2365 		rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;   /* Y default value */
2366 	}
2367 	if ((rege94 != 0) /*&&(regea4 != 0) */)
2368 		_rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result,
2369 				final_candidate, (regea4 == 0));
2370 	if (IS_92D_SINGLEPHY(rtlhal->version)) {
2371 		if ((regeb4 != 0) /*&&(regec4 != 0) */)
2372 			_rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result,
2373 						final_candidate, (regec4 == 0));
2374 	}
2375 	if (final_candidate != 0xFF) {
2376 		indexforchannel = rtl92d_get_rightchnlplace_for_iqk(
2377 				  rtlphy->current_channel);
2378 
2379 		for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2380 			rtlphy->iqk_matrix[indexforchannel].
2381 				value[0][i] = result[final_candidate][i];
2382 		rtlphy->iqk_matrix[indexforchannel].iqk_done =
2383 			true;
2384 
2385 		RT_TRACE(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD,
2386 			 "IQK OK indexforchannel %d\n", indexforchannel);
2387 	}
2388 }
2389 
2390 void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel)
2391 {
2392 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2393 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2394 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2395 	u8 indexforchannel;
2396 
2397 	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel);
2398 	/*------Do IQK for normal chip and test chip 5G band------- */
2399 	indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
2400 	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n",
2401 		 indexforchannel,
2402 		 rtlphy->iqk_matrix[indexforchannel].iqk_done);
2403 	if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done &&
2404 		rtlphy->need_iqk) {
2405 		/* Re Do IQK. */
2406 		RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD,
2407 			 "Do IQK Matrix reg for channel:%d....\n", channel);
2408 		rtl92d_phy_iq_calibrate(hw);
2409 	} else {
2410 		/* Just load the value. */
2411 		/* 2G band just load once. */
2412 		if (((!rtlhal->load_imrandiqk_setting_for2g) &&
2413 		    indexforchannel == 0) || indexforchannel > 0) {
2414 			RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
2415 				 "Just Read IQK Matrix reg for channel:%d....\n",
2416 				 channel);
2417 			if ((rtlphy->iqk_matrix[indexforchannel].
2418 			     value[0] != NULL)
2419 				/*&&(regea4 != 0) */)
2420 				_rtl92d_phy_patha_fill_iqk_matrix(hw, true,
2421 					rtlphy->iqk_matrix[
2422 					indexforchannel].value,	0,
2423 					(rtlphy->iqk_matrix[
2424 					indexforchannel].value[0][2] == 0));
2425 			if (IS_92D_SINGLEPHY(rtlhal->version)) {
2426 				if ((rtlphy->iqk_matrix[
2427 					indexforchannel].value[0][4] != 0)
2428 					/*&&(regec4 != 0) */)
2429 					_rtl92d_phy_pathb_fill_iqk_matrix(hw,
2430 						true,
2431 						rtlphy->iqk_matrix[
2432 						indexforchannel].value, 0,
2433 						(rtlphy->iqk_matrix[
2434 						indexforchannel].value[0][6]
2435 						== 0));
2436 			}
2437 		}
2438 	}
2439 	rtlphy->need_iqk = false;
2440 	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2441 }
2442 
2443 static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2)
2444 {
2445 	u32 ret;
2446 
2447 	if (val1 >= val2)
2448 		ret = val1 - val2;
2449 	else
2450 		ret = val2 - val1;
2451 	return ret;
2452 }
2453 
2454 static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel)
2455 {
2456 
2457 	int i;
2458 
2459 	for (i = 0; i < sizeof(channel5g); i++)
2460 		if (channel == channel5g[i])
2461 			return true;
2462 	return false;
2463 }
2464 
2465 static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw,
2466 				       u32 *targetchnl, u32 * curvecount_val,
2467 				       bool is5g, u32 *curveindex)
2468 {
2469 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2470 	u32 smallest_abs_val = 0xffffffff, u4tmp;
2471 	u8 i, j;
2472 	u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G;
2473 
2474 	for (i = 0; i < chnl_num; i++) {
2475 		if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1))
2476 			continue;
2477 		curveindex[i] = 0;
2478 		for (j = 0; j < (CV_CURVE_CNT * 2); j++) {
2479 			u4tmp = _rtl92d_phy_get_abs(targetchnl[i],
2480 				curvecount_val[j]);
2481 
2482 			if (u4tmp < smallest_abs_val) {
2483 				curveindex[i] = j;
2484 				smallest_abs_val = u4tmp;
2485 			}
2486 		}
2487 		smallest_abs_val = 0xffffffff;
2488 		RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n",
2489 			i, curveindex[i]);
2490 	}
2491 }
2492 
2493 static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2494 		u8 channel)
2495 {
2496 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2497 	u8 erfpath = rtlpriv->rtlhal.current_bandtype ==
2498 		BAND_ON_5G ? RF90_PATH_A :
2499 		IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ?
2500 		RF90_PATH_B : RF90_PATH_A;
2501 	u32 u4tmp = 0, u4regvalue = 0;
2502 	bool bneed_powerdown_radio = false;
2503 
2504 	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath);
2505 	RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n",
2506 		rtlpriv->rtlhal.current_bandtype);
2507 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "channel = %d\n", channel);
2508 	if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */
2509 		u4tmp = curveindex_5g[channel-1];
2510 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2511 			"ver 1 set RF-A, 5G,	0x28 = 0x%x !!\n", u4tmp);
2512 		if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2513 			rtlpriv->rtlhal.interfaceindex == 1) {
2514 			bneed_powerdown_radio =
2515 				rtl92d_phy_enable_anotherphy(hw, false);
2516 			rtlpriv->rtlhal.during_mac1init_radioa = true;
2517 			/* asume no this case */
2518 			if (bneed_powerdown_radio)
2519 				_rtl92d_phy_enable_rf_env(hw, erfpath,
2520 							  &u4regvalue);
2521 		}
2522 		rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2523 		if (bneed_powerdown_radio)
2524 			_rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2525 		if (rtlpriv->rtlhal.during_mac1init_radioa)
2526 			rtl92d_phy_powerdown_anotherphy(hw, false);
2527 	} else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) {
2528 		u4tmp = curveindex_2g[channel-1];
2529 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2530 			"ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp);
2531 		if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2532 			rtlpriv->rtlhal.interfaceindex == 0) {
2533 			bneed_powerdown_radio =
2534 				rtl92d_phy_enable_anotherphy(hw, true);
2535 			rtlpriv->rtlhal.during_mac0init_radiob = true;
2536 			if (bneed_powerdown_radio)
2537 				_rtl92d_phy_enable_rf_env(hw, erfpath,
2538 							  &u4regvalue);
2539 		}
2540 		rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2541 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2542 			"ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
2543 			rtl_get_rfreg(hw,  erfpath, RF_SYN_G4, 0x3f800));
2544 		if (bneed_powerdown_radio)
2545 			_rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2546 		if (rtlpriv->rtlhal.during_mac0init_radiob)
2547 			rtl92d_phy_powerdown_anotherphy(hw, true);
2548 	}
2549 	RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n");
2550 }
2551 
2552 static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2553 {
2554 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2555 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2556 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2557 	u8 tmpreg, index, rf_mode[2];
2558 	u8 path = is2t ? 2 : 1;
2559 	u8 i;
2560 	u32 u4tmp, offset;
2561 	u32 curvecount_val[CV_CURVE_CNT * 2] = {0};
2562 	u16 timeout = 800, timecount = 0;
2563 
2564 	/* Check continuous TX and Packet TX */
2565 	tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2566 	/* if Deal with contisuous TX case, disable all continuous TX */
2567 	/* if Deal with Packet TX case, block all queues */
2568 	if ((tmpreg & 0x70) != 0)
2569 		rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2570 	else
2571 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2572 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F);
2573 	for (index = 0; index < path; index++) {
2574 		/* 1. Read original RF mode */
2575 		offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2576 		rf_mode[index] = rtl_read_byte(rtlpriv, offset);
2577 		/* 2. Set RF mode = standby mode */
2578 		rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
2579 			      RFREG_OFFSET_MASK, 0x010000);
2580 		if (rtlpci->init_ready) {
2581 			/* switch CV-curve control by LC-calibration */
2582 			rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2583 				      BIT(17), 0x0);
2584 			/* 4. Set LC calibration begin */
2585 			rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2586 				      0x08000, 0x01);
2587 		}
2588 		u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
2589 				  RFREG_OFFSET_MASK);
2590 		while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
2591 			mdelay(50);
2592 			timecount += 50;
2593 			u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
2594 					      RF_SYN_G6, RFREG_OFFSET_MASK);
2595 		}
2596 		RTPRINT(rtlpriv, FINIT, INIT_IQK,
2597 			"PHY_LCK finish delay for %d ms=2\n", timecount);
2598 		u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK);
2599 		if (index == 0 && rtlhal->interfaceindex == 0) {
2600 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
2601 				"path-A / 5G LCK\n");
2602 		} else {
2603 			RTPRINT(rtlpriv, FINIT, INIT_IQK,
2604 				"path-B / 2.4G LCK\n");
2605 		}
2606 		memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2);
2607 		/* Set LC calibration off */
2608 		rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2609 			      0x08000, 0x0);
2610 		RTPRINT(rtlpriv, FINIT, INIT_IQK,  "set RF 0x18[15] = 0\n");
2611 		/* save Curve-counting number */
2612 		for (i = 0; i < CV_CURVE_CNT; i++) {
2613 			u32 readval = 0, readval2 = 0;
2614 			rtl_set_rfreg(hw, (enum radio_path)index, 0x3F,
2615 				      0x7f, i);
2616 
2617 			rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2618 				RFREG_OFFSET_MASK, 0x0);
2619 			readval = rtl_get_rfreg(hw, (enum radio_path)index,
2620 					  0x4F, RFREG_OFFSET_MASK);
2621 			curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2622 			/* reg 0x4f [4:0] */
2623 			/* reg 0x50 [19:10] */
2624 			readval2 = rtl_get_rfreg(hw, (enum radio_path)index,
2625 						 0x50, 0xffc00);
2626 			curvecount_val[2 * i] = (((readval & 0x1F) << 10) |
2627 						 readval2);
2628 		}
2629 		if (index == 0 && rtlhal->interfaceindex == 0)
2630 			_rtl92d_phy_calc_curvindex(hw, targetchnl_5g,
2631 						   curvecount_val,
2632 						   true, curveindex_5g);
2633 		else
2634 			_rtl92d_phy_calc_curvindex(hw, targetchnl_2g,
2635 						   curvecount_val,
2636 						   false, curveindex_2g);
2637 		/* switch CV-curve control mode */
2638 		rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2639 			      BIT(17), 0x1);
2640 	}
2641 
2642 	/* Restore original situation  */
2643 	for (index = 0; index < path; index++) {
2644 		offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2645 		rtl_write_byte(rtlpriv, offset, 0x50);
2646 		rtl_write_byte(rtlpriv, offset, rf_mode[index]);
2647 	}
2648 	if ((tmpreg & 0x70) != 0)
2649 		rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2650 	else /*Deal with Packet TX case */
2651 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2652 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00);
2653 	_rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel);
2654 }
2655 
2656 static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2657 {
2658 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2659 
2660 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "cosa PHY_LCK ver=2\n");
2661 	_rtl92d_phy_lc_calibrate_sw(hw, is2t);
2662 }
2663 
2664 void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw)
2665 {
2666 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2667 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2668 	struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2669 	u32 timeout = 2000, timecount = 0;
2670 
2671 	while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2672 		udelay(50);
2673 		timecount += 50;
2674 	}
2675 
2676 	rtlphy->lck_inprogress = true;
2677 	RTPRINT(rtlpriv, FINIT, INIT_IQK,
2678 		"LCK:Start!!! currentband %x delay %d ms\n",
2679 		rtlhal->current_bandtype, timecount);
2680 	if (IS_92D_SINGLEPHY(rtlhal->version)) {
2681 		_rtl92d_phy_lc_calibrate(hw, true);
2682 	} else {
2683 		/* For 1T1R */
2684 		_rtl92d_phy_lc_calibrate(hw, false);
2685 	}
2686 	rtlphy->lck_inprogress = false;
2687 	RTPRINT(rtlpriv, FINIT, INIT_IQK,  "LCK:Finish!!!\n");
2688 }
2689 
2690 void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
2691 {
2692 	return;
2693 }
2694 
2695 static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
2696 		u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
2697 		u32 para1, u32 para2, u32 msdelay)
2698 {
2699 	struct swchnlcmd *pcmd;
2700 
2701 	if (cmdtable == NULL) {
2702 		WARN_ONCE(true, "rtl8192de: cmdtable cannot be NULL\n");
2703 		return false;
2704 	}
2705 	if (cmdtableidx >= cmdtablesz)
2706 		return false;
2707 
2708 	pcmd = cmdtable + cmdtableidx;
2709 	pcmd->cmdid = cmdid;
2710 	pcmd->para1 = para1;
2711 	pcmd->para2 = para2;
2712 	pcmd->msdelay = msdelay;
2713 	return true;
2714 }
2715 
2716 void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw)
2717 {
2718 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2719 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2720 	u8 i;
2721 
2722 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2723 		 "settings regs %d default regs %d\n",
2724 		 (int)(sizeof(rtlphy->iqk_matrix) /
2725 		       sizeof(struct iqk_matrix_regs)),
2726 		 IQK_MATRIX_REG_NUM);
2727 	/* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
2728 	for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
2729 		rtlphy->iqk_matrix[i].value[0][0] = 0x100;
2730 		rtlphy->iqk_matrix[i].value[0][2] = 0x100;
2731 		rtlphy->iqk_matrix[i].value[0][4] = 0x100;
2732 		rtlphy->iqk_matrix[i].value[0][6] = 0x100;
2733 		rtlphy->iqk_matrix[i].value[0][1] = 0x0;
2734 		rtlphy->iqk_matrix[i].value[0][3] = 0x0;
2735 		rtlphy->iqk_matrix[i].value[0][5] = 0x0;
2736 		rtlphy->iqk_matrix[i].value[0][7] = 0x0;
2737 		rtlphy->iqk_matrix[i].iqk_done = false;
2738 	}
2739 }
2740 
2741 static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
2742 					     u8 channel, u8 *stage, u8 *step,
2743 					     u32 *delay)
2744 {
2745 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2746 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2747 	struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
2748 	u32 precommoncmdcnt;
2749 	struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
2750 	u32 postcommoncmdcnt;
2751 	struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
2752 	u32 rfdependcmdcnt;
2753 	struct swchnlcmd *currentcmd = NULL;
2754 	u8 rfpath;
2755 	u8 num_total_rfpath = rtlphy->num_total_rfpath;
2756 
2757 	precommoncmdcnt = 0;
2758 	_rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2759 					 MAX_PRECMD_CNT,
2760 					 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
2761 	_rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
2762 					 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
2763 	postcommoncmdcnt = 0;
2764 	_rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
2765 					 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
2766 	rfdependcmdcnt = 0;
2767 	_rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2768 					 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
2769 					 RF_CHNLBW, channel, 0);
2770 	_rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
2771 					 MAX_RFDEPENDCMD_CNT, CMDID_END,
2772 					 0, 0, 0);
2773 
2774 	do {
2775 		switch (*stage) {
2776 		case 0:
2777 			currentcmd = &precommoncmd[*step];
2778 			break;
2779 		case 1:
2780 			currentcmd = &rfdependcmd[*step];
2781 			break;
2782 		case 2:
2783 			currentcmd = &postcommoncmd[*step];
2784 			break;
2785 		}
2786 		if (currentcmd->cmdid == CMDID_END) {
2787 			if ((*stage) == 2) {
2788 				return true;
2789 			} else {
2790 				(*stage)++;
2791 				(*step) = 0;
2792 				continue;
2793 			}
2794 		}
2795 		switch (currentcmd->cmdid) {
2796 		case CMDID_SET_TXPOWEROWER_LEVEL:
2797 			rtl92d_phy_set_txpower_level(hw, channel);
2798 			break;
2799 		case CMDID_WRITEPORT_ULONG:
2800 			rtl_write_dword(rtlpriv, currentcmd->para1,
2801 					currentcmd->para2);
2802 			break;
2803 		case CMDID_WRITEPORT_USHORT:
2804 			rtl_write_word(rtlpriv, currentcmd->para1,
2805 				       (u16)currentcmd->para2);
2806 			break;
2807 		case CMDID_WRITEPORT_UCHAR:
2808 			rtl_write_byte(rtlpriv, currentcmd->para1,
2809 				       (u8)currentcmd->para2);
2810 			break;
2811 		case CMDID_RF_WRITEREG:
2812 			for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
2813 				rtlphy->rfreg_chnlval[rfpath] =
2814 					((rtlphy->rfreg_chnlval[rfpath] &
2815 					0xffffff00) | currentcmd->para2);
2816 				if (rtlpriv->rtlhal.current_bandtype ==
2817 				    BAND_ON_5G) {
2818 					if (currentcmd->para2 > 99)
2819 						rtlphy->rfreg_chnlval[rfpath] =
2820 						    rtlphy->rfreg_chnlval
2821 						    [rfpath] | (BIT(18));
2822 					else
2823 						rtlphy->rfreg_chnlval[rfpath] =
2824 						    rtlphy->rfreg_chnlval
2825 						    [rfpath] & (~BIT(18));
2826 					rtlphy->rfreg_chnlval[rfpath] |=
2827 						 (BIT(16) | BIT(8));
2828 				} else {
2829 					rtlphy->rfreg_chnlval[rfpath] &=
2830 						~(BIT(8) | BIT(16) | BIT(18));
2831 				}
2832 				rtl_set_rfreg(hw, (enum radio_path)rfpath,
2833 					      currentcmd->para1,
2834 					      RFREG_OFFSET_MASK,
2835 					      rtlphy->rfreg_chnlval[rfpath]);
2836 				_rtl92d_phy_reload_imr_setting(hw, channel,
2837 							       rfpath);
2838 			}
2839 			_rtl92d_phy_switch_rf_setting(hw, channel);
2840 			/* do IQK when all parameters are ready */
2841 			rtl92d_phy_reload_iqk_setting(hw, channel);
2842 			break;
2843 		default:
2844 			pr_err("switch case %#x not processed\n",
2845 			       currentcmd->cmdid);
2846 			break;
2847 		}
2848 		break;
2849 	} while (true);
2850 	(*delay) = currentcmd->msdelay;
2851 	(*step)++;
2852 	return false;
2853 }
2854 
2855 u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
2856 {
2857 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2858 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2859 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2860 	u32 delay;
2861 	u32 timeout = 1000, timecount = 0;
2862 	u8 channel = rtlphy->current_channel;
2863 	u32 ret_value;
2864 
2865 	if (rtlphy->sw_chnl_inprogress)
2866 		return 0;
2867 	if (rtlphy->set_bwmode_inprogress)
2868 		return 0;
2869 
2870 	if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
2871 		RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
2872 			 "sw_chnl_inprogress false driver sleep or unload\n");
2873 		return 0;
2874 	}
2875 	while (rtlphy->lck_inprogress && timecount < timeout) {
2876 		mdelay(50);
2877 		timecount += 50;
2878 	}
2879 	if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
2880 	    rtlhal->bandset == BAND_ON_BOTH) {
2881 		ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
2882 					  MASKDWORD);
2883 		if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
2884 			rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
2885 		else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
2886 			rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G);
2887 	}
2888 	switch (rtlhal->current_bandtype) {
2889 	case BAND_ON_5G:
2890 		/* Get first channel error when change between
2891 		 * 5G and 2.4G band. */
2892 		if (channel <= 14)
2893 			return 0;
2894 		WARN_ONCE((channel <= 14), "rtl8192de: 5G but channel<=14\n");
2895 		break;
2896 	case BAND_ON_2_4G:
2897 		/* Get first channel error when change between
2898 		 * 5G and 2.4G band. */
2899 		if (channel > 14)
2900 			return 0;
2901 		WARN_ONCE((channel > 14), "rtl8192de: 2G but channel>14\n");
2902 		break;
2903 	default:
2904 		WARN_ONCE(true, "rtl8192de: Invalid WirelessMode(%#x)!!\n",
2905 			  rtlpriv->mac80211.mode);
2906 		break;
2907 	}
2908 	rtlphy->sw_chnl_inprogress = true;
2909 	if (channel == 0)
2910 		channel = 1;
2911 	rtlphy->sw_chnl_stage = 0;
2912 	rtlphy->sw_chnl_step = 0;
2913 	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
2914 		 "switch to channel%d\n", rtlphy->current_channel);
2915 
2916 	do {
2917 		if (!rtlphy->sw_chnl_inprogress)
2918 			break;
2919 		if (!_rtl92d_phy_sw_chnl_step_by_step(hw,
2920 						      rtlphy->current_channel,
2921 		    &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) {
2922 			if (delay > 0)
2923 				mdelay(delay);
2924 			else
2925 				continue;
2926 		} else {
2927 			rtlphy->sw_chnl_inprogress = false;
2928 		}
2929 		break;
2930 	} while (true);
2931 	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
2932 	rtlphy->sw_chnl_inprogress = false;
2933 	return 1;
2934 }
2935 
2936 static void rtl92d_phy_set_io(struct ieee80211_hw *hw)
2937 {
2938 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2939 	struct dig_t *de_digtable = &rtlpriv->dm_digtable;
2940 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2941 
2942 	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2943 		 "--->Cmd(%#x), set_io_inprogress(%d)\n",
2944 		 rtlphy->current_io_type, rtlphy->set_io_inprogress);
2945 	switch (rtlphy->current_io_type) {
2946 	case IO_CMD_RESUME_DM_BY_SCAN:
2947 		de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
2948 		rtl92d_dm_write_dig(hw);
2949 		rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
2950 		break;
2951 	case IO_CMD_PAUSE_DM_BY_SCAN:
2952 		rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue;
2953 		de_digtable->cur_igvalue = 0x37;
2954 		rtl92d_dm_write_dig(hw);
2955 		break;
2956 	default:
2957 		pr_err("switch case %#x not processed\n",
2958 		       rtlphy->current_io_type);
2959 		break;
2960 	}
2961 	rtlphy->set_io_inprogress = false;
2962 	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n",
2963 		 rtlphy->current_io_type);
2964 }
2965 
2966 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2967 {
2968 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2969 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2970 	bool postprocessing = false;
2971 
2972 	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2973 		 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2974 		 iotype, rtlphy->set_io_inprogress);
2975 	do {
2976 		switch (iotype) {
2977 		case IO_CMD_RESUME_DM_BY_SCAN:
2978 			RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2979 				 "[IO CMD] Resume DM after scan\n");
2980 			postprocessing = true;
2981 			break;
2982 		case IO_CMD_PAUSE_DM_BY_SCAN:
2983 			RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2984 				 "[IO CMD] Pause DM before scan\n");
2985 			postprocessing = true;
2986 			break;
2987 		default:
2988 			pr_err("switch case %#x not processed\n",
2989 			       iotype);
2990 			break;
2991 		}
2992 	} while (false);
2993 	if (postprocessing && !rtlphy->set_io_inprogress) {
2994 		rtlphy->set_io_inprogress = true;
2995 		rtlphy->current_io_type = iotype;
2996 	} else {
2997 		return false;
2998 	}
2999 	rtl92d_phy_set_io(hw);
3000 	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype);
3001 	return true;
3002 }
3003 
3004 static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw)
3005 {
3006 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3007 
3008 	/* a.  SYS_CLKR 0x08[11] = 1  restore MAC clock */
3009 	/* b.  SPS_CTRL 0x11[7:0] = 0x2b */
3010 	if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3011 		rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
3012 	/* c.  For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */
3013 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3014 	/* RF_ON_EXCEP(d~g): */
3015 	/* d.  APSD_CTRL 0x600[7:0] = 0x00 */
3016 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3017 	/* e.  SYS_FUNC_EN 0x02[7:0] = 0xE2  reset BB TRX function again */
3018 	/* f.  SYS_FUNC_EN 0x02[7:0] = 0xE3  enable BB TRX function*/
3019 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3020 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3021 	/* g.   txpause 0x522[7:0] = 0x00  enable mac tx queue */
3022 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3023 }
3024 
3025 static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
3026 {
3027 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3028 	u32 u4btmp;
3029 	u8 delay = 5;
3030 
3031 	/* a.   TXPAUSE 0x522[7:0] = 0xFF  Pause MAC TX queue  */
3032 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3033 	/* b.   RF path 0 offset 0x00 = 0x00  disable RF  */
3034 	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3035 	/* c.   APSD_CTRL 0x600[7:0] = 0x40 */
3036 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3037 	/* d. APSD_CTRL 0x600[7:0] = 0x00
3038 	 * APSD_CTRL 0x600[7:0] = 0x00
3039 	 * RF path 0 offset 0x00 = 0x00
3040 	 * APSD_CTRL 0x600[7:0] = 0x40
3041 	 * */
3042 	u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3043 	while (u4btmp != 0 && delay > 0) {
3044 		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
3045 		rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3046 		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3047 		u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3048 		delay--;
3049 	}
3050 	if (delay == 0) {
3051 		/* Jump out the LPS turn off sequence to RF_ON_EXCEP */
3052 		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3053 
3054 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3055 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3056 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3057 		RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3058 			 "Fail !!! Switch RF timeout\n");
3059 		return;
3060 	}
3061 	/* e.   For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */
3062 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3063 	/* f.   SPS_CTRL 0x11[7:0] = 0x22 */
3064 	if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3065 		rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3066 	/* g.    SYS_CLKR 0x08[11] = 0  gated MAC clock */
3067 }
3068 
3069 bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
3070 				   enum rf_pwrstate rfpwr_state)
3071 {
3072 
3073 	bool bresult = true;
3074 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3075 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3076 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3077 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3078 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3079 	u8 i, queue_id;
3080 	struct rtl8192_tx_ring *ring = NULL;
3081 
3082 	if (rfpwr_state == ppsc->rfpwr_state)
3083 		return false;
3084 	switch (rfpwr_state) {
3085 	case ERFON:
3086 		if ((ppsc->rfpwr_state == ERFOFF) &&
3087 		    RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3088 			bool rtstatus;
3089 			u32 InitializeCount = 0;
3090 			do {
3091 				InitializeCount++;
3092 				RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3093 					 "IPS Set eRf nic enable\n");
3094 				rtstatus = rtl_ps_enable_nic(hw);
3095 			} while (!rtstatus && (InitializeCount < 10));
3096 
3097 			RT_CLEAR_PS_LEVEL(ppsc,
3098 					  RT_RF_OFF_LEVL_HALT_NIC);
3099 		} else {
3100 			RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3101 				 "awake, sleeped:%d ms state_inap:%x\n",
3102 				 jiffies_to_msecs(jiffies -
3103 						  ppsc->last_sleep_jiffies),
3104 				 rtlpriv->psc.state_inap);
3105 			ppsc->last_awake_jiffies = jiffies;
3106 			_rtl92d_phy_set_rfon(hw);
3107 		}
3108 
3109 		if (mac->link_state == MAC80211_LINKED)
3110 			rtlpriv->cfg->ops->led_control(hw,
3111 					 LED_CTL_LINK);
3112 		else
3113 			rtlpriv->cfg->ops->led_control(hw,
3114 					 LED_CTL_NO_LINK);
3115 		break;
3116 	case ERFOFF:
3117 		if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3118 			RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3119 				 "IPS Set eRf nic disable\n");
3120 			rtl_ps_disable_nic(hw);
3121 			RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3122 		} else {
3123 			if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
3124 				rtlpriv->cfg->ops->led_control(hw,
3125 						 LED_CTL_NO_LINK);
3126 			else
3127 				rtlpriv->cfg->ops->led_control(hw,
3128 						 LED_CTL_POWER_OFF);
3129 		}
3130 		break;
3131 	case ERFSLEEP:
3132 		if (ppsc->rfpwr_state == ERFOFF)
3133 			return false;
3134 
3135 		for (queue_id = 0, i = 0;
3136 		     queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3137 			ring = &pcipriv->dev.tx_ring[queue_id];
3138 			if (skb_queue_len(&ring->queue) == 0 ||
3139 			    queue_id == BEACON_QUEUE) {
3140 				queue_id++;
3141 				continue;
3142 			} else if (rtlpci->pdev->current_state != PCI_D0) {
3143 				RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3144 					 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n",
3145 					 i + 1, queue_id);
3146 				break;
3147 			} else {
3148 				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3149 					 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
3150 					 i + 1, queue_id,
3151 					 skb_queue_len(&ring->queue));
3152 				udelay(10);
3153 				i++;
3154 			}
3155 
3156 			if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3157 				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3158 					 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
3159 					 MAX_DOZE_WAITING_TIMES_9x, queue_id,
3160 					 skb_queue_len(&ring->queue));
3161 				break;
3162 			}
3163 		}
3164 		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3165 			 "Set rfsleep awaked:%d ms\n",
3166 			 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
3167 		RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3168 			 "sleep awaked:%d ms state_inap:%x\n",
3169 			 jiffies_to_msecs(jiffies -
3170 					  ppsc->last_awake_jiffies),
3171 			 rtlpriv->psc.state_inap);
3172 		ppsc->last_sleep_jiffies = jiffies;
3173 		_rtl92d_phy_set_rfsleep(hw);
3174 		break;
3175 	default:
3176 		pr_err("switch case %#x not processed\n",
3177 		       rfpwr_state);
3178 		bresult = false;
3179 		break;
3180 	}
3181 	if (bresult)
3182 		ppsc->rfpwr_state = rfpwr_state;
3183 	return bresult;
3184 }
3185 
3186 void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw)
3187 {
3188 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3189 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3190 	u8 offset = REG_MAC_PHY_CTRL_NORMAL;
3191 
3192 	switch (rtlhal->macphymode) {
3193 	case DUALMAC_DUALPHY:
3194 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3195 			 "MacPhyMode: DUALMAC_DUALPHY\n");
3196 		rtl_write_byte(rtlpriv, offset, 0xF3);
3197 		break;
3198 	case SINGLEMAC_SINGLEPHY:
3199 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3200 			 "MacPhyMode: SINGLEMAC_SINGLEPHY\n");
3201 		rtl_write_byte(rtlpriv, offset, 0xF4);
3202 		break;
3203 	case DUALMAC_SINGLEPHY:
3204 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3205 			 "MacPhyMode: DUALMAC_SINGLEPHY\n");
3206 		rtl_write_byte(rtlpriv, offset, 0xF1);
3207 		break;
3208 	}
3209 }
3210 
3211 void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw)
3212 {
3213 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3214 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3215 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
3216 
3217 	switch (rtlhal->macphymode) {
3218 	case DUALMAC_SINGLEPHY:
3219 		rtlphy->rf_type = RF_2T2R;
3220 		rtlhal->version |= RF_TYPE_2T2R;
3221 		rtlhal->bandset = BAND_ON_BOTH;
3222 		rtlhal->current_bandtype = BAND_ON_2_4G;
3223 		break;
3224 
3225 	case SINGLEMAC_SINGLEPHY:
3226 		rtlphy->rf_type = RF_2T2R;
3227 		rtlhal->version |= RF_TYPE_2T2R;
3228 		rtlhal->bandset = BAND_ON_BOTH;
3229 		rtlhal->current_bandtype = BAND_ON_2_4G;
3230 		break;
3231 
3232 	case DUALMAC_DUALPHY:
3233 		rtlphy->rf_type = RF_1T1R;
3234 		rtlhal->version &= RF_TYPE_1T1R;
3235 		/* Now we let MAC0 run on 5G band. */
3236 		if (rtlhal->interfaceindex == 0) {
3237 			rtlhal->bandset = BAND_ON_5G;
3238 			rtlhal->current_bandtype = BAND_ON_5G;
3239 		} else {
3240 			rtlhal->bandset = BAND_ON_2_4G;
3241 			rtlhal->current_bandtype = BAND_ON_2_4G;
3242 		}
3243 		break;
3244 	default:
3245 		break;
3246 	}
3247 }
3248 
3249 u8 rtl92d_get_chnlgroup_fromarray(u8 chnl)
3250 {
3251 	u8 group;
3252 	u8 channel_info[59] = {
3253 		1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
3254 		36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56,
3255 		58, 60, 62, 64, 100, 102, 104, 106, 108,
3256 		110, 112, 114, 116, 118, 120, 122, 124,
3257 		126, 128, 130, 132, 134, 136, 138, 140,
3258 		149, 151, 153, 155, 157, 159, 161, 163,
3259 		165
3260 	};
3261 
3262 	if (channel_info[chnl] <= 3)
3263 		group = 0;
3264 	else if (channel_info[chnl] <= 9)
3265 		group = 1;
3266 	else if (channel_info[chnl] <= 14)
3267 		group = 2;
3268 	else if (channel_info[chnl] <= 44)
3269 		group = 3;
3270 	else if (channel_info[chnl] <= 54)
3271 		group = 4;
3272 	else if (channel_info[chnl] <= 64)
3273 		group = 5;
3274 	else if (channel_info[chnl] <= 112)
3275 		group = 6;
3276 	else if (channel_info[chnl] <= 126)
3277 		group = 7;
3278 	else if (channel_info[chnl] <= 140)
3279 		group = 8;
3280 	else if (channel_info[chnl] <= 153)
3281 		group = 9;
3282 	else if (channel_info[chnl] <= 159)
3283 		group = 10;
3284 	else
3285 		group = 11;
3286 	return group;
3287 }
3288 
3289 void rtl92d_phy_set_poweron(struct ieee80211_hw *hw)
3290 {
3291 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3292 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3293 	unsigned long flags;
3294 	u8 value8;
3295 	u16 i;
3296 	u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
3297 
3298 	/* notice fw know band status  0x81[1]/0x53[1] = 0: 5G, 1: 2G */
3299 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3300 		value8 = rtl_read_byte(rtlpriv, mac_reg);
3301 		value8 |= BIT(1);
3302 		rtl_write_byte(rtlpriv, mac_reg, value8);
3303 	} else {
3304 		value8 = rtl_read_byte(rtlpriv, mac_reg);
3305 		value8 &= (~BIT(1));
3306 		rtl_write_byte(rtlpriv, mac_reg, value8);
3307 	}
3308 
3309 	if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3310 		value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3311 		rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3312 	} else {
3313 		spin_lock_irqsave(&globalmutex_power, flags);
3314 		if (rtlhal->interfaceindex == 0) {
3315 			value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3316 			rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3317 		} else {
3318 			value8 = rtl_read_byte(rtlpriv, REG_MAC1);
3319 			rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON);
3320 		}
3321 		value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3322 		spin_unlock_irqrestore(&globalmutex_power, flags);
3323 		for (i = 0; i < 200; i++) {
3324 			if ((value8 & BIT(7)) == 0) {
3325 				break;
3326 			} else {
3327 				udelay(500);
3328 				spin_lock_irqsave(&globalmutex_power, flags);
3329 				value8 = rtl_read_byte(rtlpriv,
3330 						    REG_POWER_OFF_IN_PROCESS);
3331 				spin_unlock_irqrestore(&globalmutex_power,
3332 						       flags);
3333 			}
3334 		}
3335 		if (i == 200)
3336 			WARN_ONCE(true, "rtl8192de: Another mac power off over time\n");
3337 	}
3338 }
3339 
3340 void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw)
3341 {
3342 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3343 
3344 	switch (rtlpriv->rtlhal.macphymode) {
3345 	case DUALMAC_DUALPHY:
3346 		rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3347 		rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3348 		rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3349 		break;
3350 	case DUALMAC_SINGLEPHY:
3351 		rtl_write_byte(rtlpriv, REG_DMC, 0xf8);
3352 		rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3353 		rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3354 		break;
3355 	case SINGLEMAC_SINGLEPHY:
3356 		rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3357 		rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10);
3358 		rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
3359 		break;
3360 	default:
3361 		break;
3362 	}
3363 }
3364 
3365 void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3366 {
3367 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3368 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3369 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
3370 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3371 	u8 rfpath, i;
3372 
3373 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
3374 	/* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */
3375 	if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3376 		/* r_select_5G for path_A/B,0x878 */
3377 		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0);
3378 		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0);
3379 		if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3380 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0);
3381 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0);
3382 		}
3383 		/* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */
3384 		rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
3385 		/* fc_area  0xd2c */
3386 		rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
3387 		/* 5G LAN ON */
3388 		rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3389 		/* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3390 		rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3391 			      0x40000100);
3392 		rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3393 			      0x40000100);
3394 		if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3395 			rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3396 				      BIT(10) | BIT(6) | BIT(5),
3397 				      ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3398 				      (rtlefuse->eeprom_c9 & BIT(1)) |
3399 				      ((rtlefuse->eeprom_cc & BIT(1)) << 4));
3400 			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3401 				      BIT(10) | BIT(6) | BIT(5),
3402 				      ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3403 				      ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3404 				      ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3405 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0);
3406 		} else {
3407 			rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3408 				      BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3409 				      BIT(6) | BIT(5),
3410 				      ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3411 				      (rtlefuse->eeprom_c9 & BIT(1)) |
3412 				      ((rtlefuse->eeprom_cc & BIT(1)) << 4) |
3413 				      ((rtlefuse->eeprom_c9 & BIT(7)) << 9) |
3414 				      ((rtlefuse->eeprom_c9 & BIT(5)) << 12) |
3415 				      ((rtlefuse->eeprom_cc & BIT(3)) << 18));
3416 			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3417 				      BIT(10) | BIT(6) | BIT(5),
3418 				      ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3419 				      ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3420 				      ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3421 			rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
3422 				      BIT(10) | BIT(6) | BIT(5),
3423 				      ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) |
3424 				      ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) |
3425 				      ((rtlefuse->eeprom_cc & BIT(2)) << 3));
3426 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3427 				      BIT(31) | BIT(15), 0);
3428 		}
3429 		/* 1.5V_LDO */
3430 	} else {
3431 		/* r_select_5G for path_A/B */
3432 		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1);
3433 		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1);
3434 		if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3435 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1);
3436 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1);
3437 		}
3438 		/* rssi_table_select:index 0 for 2.4G.1~3 for 5G */
3439 		rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
3440 		/* fc_area */
3441 		rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
3442 		/* 5G LAN ON */
3443 		rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3444 		/* TX BB gain shift,Just for testchip,0xc80,0xc88 */
3445 		if (rtlefuse->internal_pa_5g[0])
3446 			rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3447 				      0x2d4000b5);
3448 		else
3449 			rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3450 				      0x20000080);
3451 		if (rtlefuse->internal_pa_5g[1])
3452 			rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3453 				      0x2d4000b5);
3454 		else
3455 			rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3456 				      0x20000080);
3457 		if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3458 			rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3459 				      BIT(10) | BIT(6) | BIT(5),
3460 				      (rtlefuse->eeprom_cc & BIT(5)));
3461 			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3462 				      ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3463 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15),
3464 				      (rtlefuse->eeprom_cc & BIT(4)) >> 4);
3465 		} else {
3466 			rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3467 				      BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3468 				      BIT(6) | BIT(5),
3469 				      (rtlefuse->eeprom_cc & BIT(5)) |
3470 				      ((rtlefuse->eeprom_cc & BIT(7)) << 14));
3471 			rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3472 				      ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3473 			rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10),
3474 				      ((rtlefuse->eeprom_cc & BIT(6)) >> 6));
3475 			rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3476 				      BIT(31) | BIT(15),
3477 				      ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
3478 				      ((rtlefuse->eeprom_cc & BIT(6)) << 10));
3479 		}
3480 	}
3481 	/* update IQK related settings */
3482 	rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
3483 	rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
3484 	rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00);
3485 	rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3486 		      BIT(26) | BIT(24), 0x00);
3487 	rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 0x00);
3488 	rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
3489 	rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
3490 
3491 	/* Update RF */
3492 	for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3493 	     rfpath++) {
3494 		if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3495 			/* MOD_AG for RF path_A 0x18 BIT8,BIT16 */
3496 			rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) |
3497 				      BIT(18), 0);
3498 			/* RF0x0b[16:14] =3b'111 */
3499 			rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
3500 				      0x1c000, 0x07);
3501 		} else {
3502 			/* MOD_AG for RF path_A 0x18 BIT8,BIT16 */
3503 			rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) |
3504 				      BIT(16) | BIT(18),
3505 				      (BIT(16) | BIT(8)) >> 8);
3506 		}
3507 	}
3508 	/* Update for all band. */
3509 	/* DMDP */
3510 	if (rtlphy->rf_type == RF_1T1R) {
3511 		/* Use antenna 0,0xc04,0xd04 */
3512 		rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11);
3513 		rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
3514 
3515 		/* enable ad/da clock1 for dual-phy reg0x888 */
3516 		if (rtlhal->interfaceindex == 0) {
3517 			rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) |
3518 				      BIT(13), 0x3);
3519 		} else {
3520 			rtl92d_phy_enable_anotherphy(hw, false);
3521 			RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3522 				 "MAC1 use DBI to update 0x888\n");
3523 			/* 0x888 */
3524 			rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN,
3525 						rtl92de_read_dword_dbi(hw,
3526 						RFPGA0_ADDALLOCKEN,
3527 						BIT(3)) | BIT(12) | BIT(13),
3528 						BIT(3));
3529 			rtl92d_phy_powerdown_anotherphy(hw, false);
3530 		}
3531 	} else {
3532 		/* Single PHY */
3533 		/* Use antenna 0 & 1,0xc04,0xd04 */
3534 		rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33);
3535 		rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
3536 		/* disable ad/da clock1,0x888 */
3537 		rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
3538 	}
3539 	for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3540 	     rfpath++) {
3541 		rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
3542 						RF_CHNLBW, RFREG_OFFSET_MASK);
3543 		rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
3544 			RFREG_OFFSET_MASK);
3545 	}
3546 	for (i = 0; i < 2; i++)
3547 		RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n",
3548 			 rtlphy->rfreg_chnlval[i]);
3549 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n");
3550 
3551 }
3552 
3553 bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw)
3554 {
3555 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3556 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3557 	u8 u1btmp;
3558 	unsigned long flags;
3559 
3560 	if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3561 		u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3562 		rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3563 		return true;
3564 	}
3565 	spin_lock_irqsave(&globalmutex_power, flags);
3566 	if (rtlhal->interfaceindex == 0) {
3567 		u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3568 		rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3569 		u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3570 		u1btmp &= MAC1_ON;
3571 	} else {
3572 		u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3573 		rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON));
3574 		u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3575 		u1btmp &= MAC0_ON;
3576 	}
3577 	if (u1btmp) {
3578 		spin_unlock_irqrestore(&globalmutex_power, flags);
3579 		return false;
3580 	}
3581 	u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3582 	u1btmp |= BIT(7);
3583 	rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp);
3584 	spin_unlock_irqrestore(&globalmutex_power, flags);
3585 	return true;
3586 }
3587