1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../efuse.h"
6 #include "../base.h"
7 #include "../regd.h"
8 #include "../cam.h"
9 #include "../ps.h"
10 #include "../pci.h"
11 #include "reg.h"
12 #include "def.h"
13 #include "phy.h"
14 #include "dm.h"
15 #include "fw.h"
16 #include "led.h"
17 #include "sw.h"
18 #include "hw.h"
19 
20 u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset, u8 direct)
21 {
22 	struct rtl_priv *rtlpriv = rtl_priv(hw);
23 	u32 value;
24 
25 	rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC));
26 	rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct);
27 	udelay(10);
28 	value = rtl_read_dword(rtlpriv, REG_DBI_RDATA);
29 	return value;
30 }
31 
32 void rtl92de_write_dword_dbi(struct ieee80211_hw *hw,
33 			     u16 offset, u32 value, u8 direct)
34 {
35 	struct rtl_priv *rtlpriv = rtl_priv(hw);
36 
37 	rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000));
38 	rtl_write_dword(rtlpriv, REG_DBI_WDATA, value);
39 	rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct);
40 }
41 
42 static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
43 				      u8 set_bits, u8 clear_bits)
44 {
45 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
46 	struct rtl_priv *rtlpriv = rtl_priv(hw);
47 
48 	rtlpci->reg_bcn_ctrl_val |= set_bits;
49 	rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
50 	rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
51 }
52 
53 static void _rtl92de_stop_tx_beacon(struct ieee80211_hw *hw)
54 {
55 	struct rtl_priv *rtlpriv = rtl_priv(hw);
56 	u8 tmp1byte;
57 
58 	tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
59 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
60 	rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
61 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
62 	tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
63 	tmp1byte &= ~(BIT(0));
64 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
65 }
66 
67 static void _rtl92de_resume_tx_beacon(struct ieee80211_hw *hw)
68 {
69 	struct rtl_priv *rtlpriv = rtl_priv(hw);
70 	u8 tmp1byte;
71 
72 	tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
73 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
74 	rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
75 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
76 	tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
77 	tmp1byte |= BIT(0);
78 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
79 }
80 
81 static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw)
82 {
83 	_rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1));
84 }
85 
86 static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw)
87 {
88 	_rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0);
89 }
90 
91 void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
92 {
93 	struct rtl_priv *rtlpriv = rtl_priv(hw);
94 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
95 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
96 
97 	switch (variable) {
98 	case HW_VAR_RCR:
99 		*((u32 *) (val)) = rtlpci->receive_config;
100 		break;
101 	case HW_VAR_RF_STATE:
102 		*((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
103 		break;
104 	case HW_VAR_FWLPS_RF_ON:{
105 		enum rf_pwrstate rfstate;
106 		u32 val_rcr;
107 
108 		rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
109 					      (u8 *)(&rfstate));
110 		if (rfstate == ERFOFF) {
111 			*((bool *) (val)) = true;
112 		} else {
113 			val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
114 			val_rcr &= 0x00070000;
115 			if (val_rcr)
116 				*((bool *) (val)) = false;
117 			else
118 				*((bool *) (val)) = true;
119 		}
120 		break;
121 	}
122 	case HW_VAR_FW_PSMODE_STATUS:
123 		*((bool *) (val)) = ppsc->fw_current_inpsmode;
124 		break;
125 	case HW_VAR_CORRECT_TSF:{
126 		u64 tsf;
127 		u32 *ptsf_low = (u32 *)&tsf;
128 		u32 *ptsf_high = ((u32 *)&tsf) + 1;
129 
130 		*ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
131 		*ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
132 		*((u64 *) (val)) = tsf;
133 		break;
134 	}
135 	case HW_VAR_INT_MIGRATION:
136 		*((bool *)(val)) = rtlpriv->dm.interrupt_migration;
137 		break;
138 	case HW_VAR_INT_AC:
139 		*((bool *)(val)) = rtlpriv->dm.disable_tx_int;
140 		break;
141 	case HAL_DEF_WOWLAN:
142 		break;
143 	default:
144 		pr_err("switch case %#x not processed\n", variable);
145 		break;
146 	}
147 }
148 
149 void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
150 {
151 	struct rtl_priv *rtlpriv = rtl_priv(hw);
152 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
153 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
154 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
155 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
156 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
157 	u8 idx;
158 
159 	switch (variable) {
160 	case HW_VAR_ETHER_ADDR:
161 		for (idx = 0; idx < ETH_ALEN; idx++) {
162 			rtl_write_byte(rtlpriv, (REG_MACID + idx),
163 				       val[idx]);
164 		}
165 		break;
166 	case HW_VAR_BASIC_RATE: {
167 		u16 rate_cfg = ((u16 *) val)[0];
168 		u8 rate_index = 0;
169 
170 		rate_cfg = rate_cfg & 0x15f;
171 		if (mac->vendor == PEER_CISCO &&
172 		    ((rate_cfg & 0x150) == 0))
173 			rate_cfg |= 0x01;
174 		rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
175 		rtl_write_byte(rtlpriv, REG_RRSR + 1,
176 			       (rate_cfg >> 8) & 0xff);
177 		while (rate_cfg > 0x1) {
178 			rate_cfg = (rate_cfg >> 1);
179 			rate_index++;
180 		}
181 		if (rtlhal->fw_version > 0xe)
182 			rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
183 				       rate_index);
184 		break;
185 	}
186 	case HW_VAR_BSSID:
187 		for (idx = 0; idx < ETH_ALEN; idx++) {
188 			rtl_write_byte(rtlpriv, (REG_BSSID + idx),
189 				       val[idx]);
190 		}
191 		break;
192 	case HW_VAR_SIFS:
193 		rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
194 		rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
195 		rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
196 		rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
197 		if (!mac->ht_enable)
198 			rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
199 				       0x0e0e);
200 		else
201 			rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
202 				       *((u16 *) val));
203 		break;
204 	case HW_VAR_SLOT_TIME: {
205 		u8 e_aci;
206 
207 		RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
208 			 "HW_VAR_SLOT_TIME %x\n", val[0]);
209 		rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
210 		for (e_aci = 0; e_aci < AC_MAX; e_aci++)
211 			rtlpriv->cfg->ops->set_hw_reg(hw,
212 						      HW_VAR_AC_PARAM,
213 						      (&e_aci));
214 		break;
215 	}
216 	case HW_VAR_ACK_PREAMBLE: {
217 		u8 reg_tmp;
218 		u8 short_preamble = (bool) (*val);
219 
220 		reg_tmp = (mac->cur_40_prime_sc) << 5;
221 		if (short_preamble)
222 			reg_tmp |= 0x80;
223 		rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
224 		break;
225 	}
226 	case HW_VAR_AMPDU_MIN_SPACE: {
227 		u8 min_spacing_to_set;
228 		u8 sec_min_space;
229 
230 		min_spacing_to_set = *val;
231 		if (min_spacing_to_set <= 7) {
232 			sec_min_space = 0;
233 			if (min_spacing_to_set < sec_min_space)
234 				min_spacing_to_set = sec_min_space;
235 			mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
236 					      min_spacing_to_set);
237 			*val = min_spacing_to_set;
238 			RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
239 				 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
240 				 mac->min_space_cfg);
241 			rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
242 				       mac->min_space_cfg);
243 		}
244 		break;
245 	}
246 	case HW_VAR_SHORTGI_DENSITY: {
247 		u8 density_to_set;
248 
249 		density_to_set = *val;
250 		mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
251 		mac->min_space_cfg |= (density_to_set << 3);
252 		RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
253 			 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
254 			 mac->min_space_cfg);
255 		rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
256 			       mac->min_space_cfg);
257 		break;
258 	}
259 	case HW_VAR_AMPDU_FACTOR: {
260 		u8 factor_toset;
261 		u32 regtoset;
262 		u8 *ptmp_byte = NULL;
263 		u8 index;
264 
265 		if (rtlhal->macphymode == DUALMAC_DUALPHY)
266 			regtoset = 0xb9726641;
267 		else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
268 			regtoset = 0x66626641;
269 		else
270 			regtoset = 0xb972a841;
271 		factor_toset = *val;
272 		if (factor_toset <= 3) {
273 			factor_toset = (1 << (factor_toset + 2));
274 			if (factor_toset > 0xf)
275 				factor_toset = 0xf;
276 			for (index = 0; index < 4; index++) {
277 				ptmp_byte = (u8 *)(&regtoset) + index;
278 				if ((*ptmp_byte & 0xf0) >
279 				    (factor_toset << 4))
280 					*ptmp_byte = (*ptmp_byte & 0x0f)
281 						 | (factor_toset << 4);
282 				if ((*ptmp_byte & 0x0f) > factor_toset)
283 					*ptmp_byte = (*ptmp_byte & 0xf0)
284 						     | (factor_toset);
285 			}
286 			rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoset);
287 			RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
288 				 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
289 				 factor_toset);
290 		}
291 		break;
292 	}
293 	case HW_VAR_AC_PARAM: {
294 		u8 e_aci = *val;
295 		rtl92d_dm_init_edca_turbo(hw);
296 		if (rtlpci->acm_method != EACMWAY2_SW)
297 			rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
298 						      &e_aci);
299 		break;
300 	}
301 	case HW_VAR_ACM_CTRL: {
302 		u8 e_aci = *val;
303 		union aci_aifsn *p_aci_aifsn =
304 		    (union aci_aifsn *)(&(mac->ac[0].aifs));
305 		u8 acm = p_aci_aifsn->f.acm;
306 		u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
307 
308 		acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?  0x0 : 0x1);
309 		if (acm) {
310 			switch (e_aci) {
311 			case AC0_BE:
312 				acm_ctrl |= ACMHW_BEQEN;
313 				break;
314 			case AC2_VI:
315 				acm_ctrl |= ACMHW_VIQEN;
316 				break;
317 			case AC3_VO:
318 				acm_ctrl |= ACMHW_VOQEN;
319 				break;
320 			default:
321 				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
322 					 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
323 					 acm);
324 				break;
325 			}
326 		} else {
327 			switch (e_aci) {
328 			case AC0_BE:
329 				acm_ctrl &= (~ACMHW_BEQEN);
330 				break;
331 			case AC2_VI:
332 				acm_ctrl &= (~ACMHW_VIQEN);
333 				break;
334 			case AC3_VO:
335 				acm_ctrl &= (~ACMHW_VOQEN);
336 				break;
337 			default:
338 				pr_err("switch case %#x not processed\n",
339 				       e_aci);
340 				break;
341 			}
342 		}
343 		RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
344 			 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
345 			 acm_ctrl);
346 		rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
347 		break;
348 	}
349 	case HW_VAR_RCR:
350 		rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
351 		rtlpci->receive_config = ((u32 *) (val))[0];
352 		break;
353 	case HW_VAR_RETRY_LIMIT: {
354 		u8 retry_limit = val[0];
355 
356 		rtl_write_word(rtlpriv, REG_RL,
357 			       retry_limit << RETRY_LIMIT_SHORT_SHIFT |
358 			       retry_limit << RETRY_LIMIT_LONG_SHIFT);
359 		break;
360 	}
361 	case HW_VAR_DUAL_TSF_RST:
362 		rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
363 		break;
364 	case HW_VAR_EFUSE_BYTES:
365 		rtlefuse->efuse_usedbytes = *((u16 *) val);
366 		break;
367 	case HW_VAR_EFUSE_USAGE:
368 		rtlefuse->efuse_usedpercentage = *val;
369 		break;
370 	case HW_VAR_IO_CMD:
371 		rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val));
372 		break;
373 	case HW_VAR_WPA_CONFIG:
374 		rtl_write_byte(rtlpriv, REG_SECCFG, *val);
375 		break;
376 	case HW_VAR_SET_RPWM:
377 		rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (val));
378 		break;
379 	case HW_VAR_H2C_FW_PWRMODE:
380 		break;
381 	case HW_VAR_FW_PSMODE_STATUS:
382 		ppsc->fw_current_inpsmode = *((bool *) val);
383 		break;
384 	case HW_VAR_H2C_FW_JOINBSSRPT: {
385 		u8 mstatus = (*val);
386 		u8 tmp_regcr, tmp_reg422;
387 		bool recover = false;
388 
389 		if (mstatus == RT_MEDIA_CONNECT) {
390 			rtlpriv->cfg->ops->set_hw_reg(hw,
391 						      HW_VAR_AID, NULL);
392 			tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
393 			rtl_write_byte(rtlpriv, REG_CR + 1,
394 				       (tmp_regcr | BIT(0)));
395 			_rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
396 			_rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
397 			tmp_reg422 = rtl_read_byte(rtlpriv,
398 						 REG_FWHW_TXQ_CTRL + 2);
399 			if (tmp_reg422 & BIT(6))
400 				recover = true;
401 			rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
402 				       tmp_reg422 & (~BIT(6)));
403 			rtl92d_set_fw_rsvdpagepkt(hw, 0);
404 			_rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
405 			_rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
406 			if (recover)
407 				rtl_write_byte(rtlpriv,
408 					       REG_FWHW_TXQ_CTRL + 2,
409 					       tmp_reg422);
410 			rtl_write_byte(rtlpriv, REG_CR + 1,
411 				       (tmp_regcr & ~(BIT(0))));
412 		}
413 		rtl92d_set_fw_joinbss_report_cmd(hw, (*val));
414 		break;
415 	}
416 	case HW_VAR_AID: {
417 		u16 u2btmp;
418 		u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
419 		u2btmp &= 0xC000;
420 		rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
421 			       mac->assoc_id));
422 		break;
423 	}
424 	case HW_VAR_CORRECT_TSF: {
425 		u8 btype_ibss = val[0];
426 
427 		if (btype_ibss)
428 			_rtl92de_stop_tx_beacon(hw);
429 		_rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
430 		rtl_write_dword(rtlpriv, REG_TSFTR,
431 				(u32) (mac->tsf & 0xffffffff));
432 		rtl_write_dword(rtlpriv, REG_TSFTR + 4,
433 				(u32) ((mac->tsf >> 32) & 0xffffffff));
434 		_rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
435 		if (btype_ibss)
436 			_rtl92de_resume_tx_beacon(hw);
437 
438 		break;
439 	}
440 	case HW_VAR_INT_MIGRATION: {
441 		bool int_migration = *(bool *) (val);
442 
443 		if (int_migration) {
444 			/* Set interrupt migration timer and
445 			 * corresponding Tx/Rx counter.
446 			 * timer 25ns*0xfa0=100us for 0xf packets.
447 			 * 0x306:Rx, 0x307:Tx */
448 			rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0);
449 			rtlpriv->dm.interrupt_migration = int_migration;
450 		} else {
451 			/* Reset all interrupt migration settings. */
452 			rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
453 			rtlpriv->dm.interrupt_migration = int_migration;
454 		}
455 		break;
456 	}
457 	case HW_VAR_INT_AC: {
458 		bool disable_ac_int = *((bool *) val);
459 
460 		/* Disable four ACs interrupts. */
461 		if (disable_ac_int) {
462 			/* Disable VO, VI, BE and BK four AC interrupts
463 			 * to gain more efficient CPU utilization.
464 			 * When extremely highly Rx OK occurs,
465 			 * we will disable Tx interrupts.
466 			 */
467 			rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
468 						 RT_AC_INT_MASKS);
469 			rtlpriv->dm.disable_tx_int = disable_ac_int;
470 		/* Enable four ACs interrupts. */
471 		} else {
472 			rtlpriv->cfg->ops->update_interrupt_mask(hw,
473 						 RT_AC_INT_MASKS, 0);
474 			rtlpriv->dm.disable_tx_int = disable_ac_int;
475 		}
476 		break;
477 	}
478 	default:
479 		pr_err("switch case %#x not processed\n", variable);
480 		break;
481 	}
482 }
483 
484 static bool _rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
485 {
486 	struct rtl_priv *rtlpriv = rtl_priv(hw);
487 	bool status = true;
488 	long count = 0;
489 	u32 value = _LLT_INIT_ADDR(address) |
490 	    _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
491 
492 	rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
493 	do {
494 		value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
495 		if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
496 			break;
497 		if (count > POLLING_LLT_THRESHOLD) {
498 			pr_err("Failed to polling write LLT done at address %d!\n",
499 			       address);
500 			status = false;
501 			break;
502 		}
503 	} while (++count);
504 	return status;
505 }
506 
507 static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw)
508 {
509 	struct rtl_priv *rtlpriv = rtl_priv(hw);
510 	unsigned short i;
511 	u8 txpktbuf_bndy;
512 	u8 maxpage;
513 	bool status;
514 	u32 value32; /* High+low page number */
515 	u8 value8;	 /* normal page number */
516 
517 	if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
518 		maxpage = 255;
519 		txpktbuf_bndy = 246;
520 		value8 = 0;
521 		value32 = 0x80bf0d29;
522 	} else {
523 		maxpage = 127;
524 		txpktbuf_bndy = 123;
525 		value8 = 0;
526 		value32 = 0x80750005;
527 	}
528 
529 	/* Set reserved page for each queue */
530 	/* 11.  RQPN 0x200[31:0] = 0x80BD1C1C */
531 	/* load RQPN */
532 	rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
533 	rtl_write_dword(rtlpriv, REG_RQPN, value32);
534 
535 	/* 12.  TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */
536 	/* TXRKTBUG_PG_BNDY */
537 	rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
538 			(rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 |
539 			txpktbuf_bndy));
540 
541 	/* 13.  TDECTRL[15:8] 0x209[7:0] = 0xF6 */
542 	/* Beacon Head for TXDMA */
543 	rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
544 
545 	/* 14.  BCNQ_PGBNDY 0x424[7:0] =  0xF6 */
546 	/* BCNQ_PGBNDY */
547 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
548 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
549 
550 	/* 15.  WMAC_LBK_BF_HD 0x45D[7:0] =  0xF6 */
551 	/* WMAC_LBK_BF_HD */
552 	rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
553 
554 	/* Set Tx/Rx page size (Tx must be 128 Bytes, */
555 	/* Rx can be 64,128,256,512,1024 bytes) */
556 	/* 16.  PBP [7:0] = 0x11 */
557 	/* TRX page size */
558 	rtl_write_byte(rtlpriv, REG_PBP, 0x11);
559 
560 	/* 17.  DRV_INFO_SZ = 0x04 */
561 	rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
562 
563 	/* 18.  LLT_table_init(Adapter);  */
564 	for (i = 0; i < (txpktbuf_bndy - 1); i++) {
565 		status = _rtl92de_llt_write(hw, i, i + 1);
566 		if (true != status)
567 			return status;
568 	}
569 
570 	/* end of list */
571 	status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
572 	if (true != status)
573 		return status;
574 
575 	/* Make the other pages as ring buffer */
576 	/* This ring buffer is used as beacon buffer if we */
577 	/* config this MAC as two MAC transfer. */
578 	/* Otherwise used as local loopback buffer.  */
579 	for (i = txpktbuf_bndy; i < maxpage; i++) {
580 		status = _rtl92de_llt_write(hw, i, (i + 1));
581 		if (true != status)
582 			return status;
583 	}
584 
585 	/* Let last entry point to the start entry of ring buffer */
586 	status = _rtl92de_llt_write(hw, maxpage, txpktbuf_bndy);
587 	if (true != status)
588 		return status;
589 
590 	return true;
591 }
592 
593 static void _rtl92de_gen_refresh_led_state(struct ieee80211_hw *hw)
594 {
595 	struct rtl_priv *rtlpriv = rtl_priv(hw);
596 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
597 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
598 	struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
599 
600 	if (rtlpci->up_first_time)
601 		return;
602 	if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
603 		rtl92de_sw_led_on(hw, pled0);
604 	else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
605 		rtl92de_sw_led_on(hw, pled0);
606 	else
607 		rtl92de_sw_led_off(hw, pled0);
608 }
609 
610 static bool _rtl92de_init_mac(struct ieee80211_hw *hw)
611 {
612 	struct rtl_priv *rtlpriv = rtl_priv(hw);
613 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
614 	unsigned char bytetmp;
615 	unsigned short wordtmp;
616 	u16 retry;
617 
618 	rtl92d_phy_set_poweron(hw);
619 	/* Add for resume sequence of power domain according
620 	 * to power document V11. Chapter V.11....  */
621 	/* 0.   RSV_CTRL 0x1C[7:0] = 0x00  */
622 	/* unlock ISO/CLK/Power control register */
623 	rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
624 	rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05);
625 
626 	/* 1.   AFE_XTAL_CTRL [7:0] = 0x0F  enable XTAL */
627 	/* 2.   SPS0_CTRL 0x11[7:0] = 0x2b  enable SPS into PWM mode  */
628 	/* 3.   delay (1ms) this is not necessary when initially power on */
629 
630 	/* C.   Resume Sequence */
631 	/* a.   SPS0_CTRL 0x11[7:0] = 0x2b */
632 	rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
633 
634 	/* b.   AFE_XTAL_CTRL [7:0] = 0x0F */
635 	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
636 
637 	/* c.   DRV runs power on init flow */
638 
639 	/* auto enable WLAN */
640 	/* 4.   APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0   */
641 	/* Power On Reset for MAC Block */
642 	bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
643 	udelay(2);
644 	rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
645 	udelay(2);
646 
647 	/* 5.   Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */
648 	bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
649 	udelay(50);
650 	retry = 0;
651 	while ((bytetmp & BIT(0)) && retry < 1000) {
652 		retry++;
653 		bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
654 		udelay(50);
655 	}
656 
657 	/* Enable Radio off, GPIO, and LED function */
658 	/* 6.   APS_FSMCO 0x04[15:0] = 0x0012  when enable HWPDN */
659 	rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
660 
661 	/* release RF digital isolation  */
662 	/* 7.  SYS_ISO_CTRL 0x01[1]    = 0x0;  */
663 	/*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */
664 	rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
665 	udelay(2);
666 
667 	/* make sure that BB reset OK. */
668 	/* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */
669 
670 	/* Disable REG_CR before enable it to assure reset */
671 	rtl_write_word(rtlpriv, REG_CR, 0x0);
672 
673 	/* Release MAC IO register reset */
674 	rtl_write_word(rtlpriv, REG_CR, 0x2ff);
675 
676 	/* clear stopping tx/rx dma   */
677 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0);
678 
679 	/* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */
680 
681 	/* System init */
682 	/* 18.  LLT_table_init(Adapter);  */
683 	if (!_rtl92de_llt_table_init(hw))
684 		return false;
685 
686 	/* Clear interrupt and enable interrupt */
687 	/* 19.  HISR 0x124[31:0] = 0xffffffff;  */
688 	/*      HISRE 0x12C[7:0] = 0xFF */
689 	rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
690 	rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
691 
692 	/* 20.  HIMR 0x120[31:0] |= [enable INT mask bit map];  */
693 	/* 21.  HIMRE 0x128[7:0] = [enable INT mask bit map] */
694 	/* The IMR should be enabled later after all init sequence
695 	 * is finished. */
696 
697 	/* 22.  PCIE configuration space configuration */
698 	/* 23.  Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ),  */
699 	/*      and PCIe gated clock function is enabled.    */
700 	/* PCIE configuration space will be written after
701 	 * all init sequence.(Or by BIOS) */
702 
703 	rtl92d_phy_config_maccoexist_rfpage(hw);
704 
705 	/* THe below section is not related to power document Vxx . */
706 	/* This is only useful for driver and OS setting. */
707 	/* -------------------Software Relative Setting---------------------- */
708 	wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
709 	wordtmp &= 0xf;
710 	wordtmp |= 0xF771;
711 	rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
712 
713 	/* Reported Tx status from HW for rate adaptive. */
714 	/* This should be realtive to power on step 14. But in document V11  */
715 	/* still not contain the description.!!! */
716 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
717 
718 	/* Set Tx/Rx page size (Tx must be 128 Bytes,
719 	 * Rx can be 64,128,256,512,1024 bytes) */
720 	/* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */
721 
722 	/* Set RCR register */
723 	rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
724 	/* rtl_write_byte(rtlpriv,REG_RX_DRVINFO_SZ, 4); */
725 
726 	/*  Set TCR register */
727 	rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
728 
729 	/* disable earlymode */
730 	rtl_write_byte(rtlpriv, 0x4d0, 0x0);
731 
732 	/* Set TX/RX descriptor physical address(from OS API). */
733 	rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
734 			rtlpci->tx_ring[BEACON_QUEUE].dma);
735 	rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma);
736 	rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma);
737 	rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma);
738 	rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma);
739 	rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma);
740 	rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma);
741 	/* Set RX Desc Address */
742 	rtl_write_dword(rtlpriv, REG_RX_DESA,
743 			rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
744 
745 	/* if we want to support 64 bit DMA, we should set it here,
746 	 * but now we do not support 64 bit DMA*/
747 
748 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33);
749 
750 	/* Reset interrupt migration setting when initialization */
751 	rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
752 
753 	/* Reconsider when to do this operation after asking HWSD. */
754 	bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
755 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
756 	do {
757 		retry++;
758 		bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
759 	} while ((retry < 200) && !(bytetmp & BIT(7)));
760 
761 	/* After MACIO reset,we must refresh LED state. */
762 	_rtl92de_gen_refresh_led_state(hw);
763 
764 	/* Reset H2C protection register */
765 	rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
766 
767 	return true;
768 }
769 
770 static void _rtl92de_hw_configure(struct ieee80211_hw *hw)
771 {
772 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
773 	struct rtl_priv *rtlpriv = rtl_priv(hw);
774 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
775 	u8 reg_bw_opmode = BW_OPMODE_20MHZ;
776 	u32 reg_rrsr;
777 
778 	reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
779 	rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
780 	rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
781 	rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
782 	rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
783 	rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
784 	rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
785 	rtl_write_word(rtlpriv, REG_RL, 0x0707);
786 	rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
787 	rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
788 	rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
789 	rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
790 	rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
791 	rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
792 	/* Aggregation threshold */
793 	if (rtlhal->macphymode == DUALMAC_DUALPHY)
794 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641);
795 	else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
796 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641);
797 	else
798 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
799 	rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
800 	rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
801 	rtlpci->reg_bcn_ctrl_val = 0x1f;
802 	rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
803 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
804 	rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
805 	rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
806 	rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
807 	/* For throughput */
808 	rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666);
809 	/* ACKTO for IOT issue. */
810 	rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
811 	/* Set Spec SIFS (used in NAV) */
812 	rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
813 	rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
814 	/* Set SIFS for CCK */
815 	rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
816 	/* Set SIFS for OFDM */
817 	rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
818 	/* Set Multicast Address. */
819 	rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
820 	rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
821 	switch (rtlpriv->phy.rf_type) {
822 	case RF_1T2R:
823 	case RF_1T1R:
824 		rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
825 		break;
826 	case RF_2T2R:
827 	case RF_2T2R_GREEN:
828 		rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
829 		break;
830 	}
831 }
832 
833 static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw)
834 {
835 	struct rtl_priv *rtlpriv = rtl_priv(hw);
836 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
837 
838 	rtl_write_byte(rtlpriv, 0x34b, 0x93);
839 	rtl_write_word(rtlpriv, 0x350, 0x870c);
840 	rtl_write_byte(rtlpriv, 0x352, 0x1);
841 	if (ppsc->support_backdoor)
842 		rtl_write_byte(rtlpriv, 0x349, 0x1b);
843 	else
844 		rtl_write_byte(rtlpriv, 0x349, 0x03);
845 	rtl_write_word(rtlpriv, 0x350, 0x2718);
846 	rtl_write_byte(rtlpriv, 0x352, 0x1);
847 }
848 
849 void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw)
850 {
851 	struct rtl_priv *rtlpriv = rtl_priv(hw);
852 	u8 sec_reg_value;
853 
854 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
855 		 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
856 		 rtlpriv->sec.pairwise_enc_algorithm,
857 		 rtlpriv->sec.group_enc_algorithm);
858 	if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
859 		RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
860 			 "not open hw encryption\n");
861 		return;
862 	}
863 	sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
864 	if (rtlpriv->sec.use_defaultkey) {
865 		sec_reg_value |= SCR_TXUSEDK;
866 		sec_reg_value |= SCR_RXUSEDK;
867 	}
868 	sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
869 	rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
870 	RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
871 		 "The SECR-value %x\n", sec_reg_value);
872 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
873 }
874 
875 int rtl92de_hw_init(struct ieee80211_hw *hw)
876 {
877 	struct rtl_priv *rtlpriv = rtl_priv(hw);
878 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
879 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
880 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
881 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
882 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
883 	bool rtstatus = true;
884 	u8 tmp_u1b;
885 	int i;
886 	int err;
887 	unsigned long flags;
888 
889 	rtlpci->being_init_adapter = true;
890 	rtlpci->init_ready = false;
891 	spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);
892 	/* we should do iqk after disable/enable */
893 	rtl92d_phy_reset_iqk_result(hw);
894 	/* rtlpriv->intf_ops->disable_aspm(hw); */
895 	rtstatus = _rtl92de_init_mac(hw);
896 	if (!rtstatus) {
897 		pr_err("Init MAC failed\n");
898 		err = 1;
899 		spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
900 		return err;
901 	}
902 	err = rtl92d_download_fw(hw);
903 	spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
904 	if (err) {
905 		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
906 			 "Failed to download FW. Init HW without FW..\n");
907 		return 1;
908 	}
909 	rtlhal->last_hmeboxnum = 0;
910 	rtlpriv->psc.fw_current_inpsmode = false;
911 
912 	tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
913 	tmp_u1b = tmp_u1b | 0x30;
914 	rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
915 
916 	if (rtlhal->earlymode_enable) {
917 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
918 			 "EarlyMode Enabled!!!\n");
919 
920 		tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0);
921 		tmp_u1b = tmp_u1b | 0x1f;
922 		rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b);
923 
924 		rtl_write_byte(rtlpriv, 0x4d3, 0x80);
925 
926 		tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
927 		tmp_u1b = tmp_u1b | 0x40;
928 		rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
929 	}
930 
931 	if (mac->rdg_en) {
932 		rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff);
933 		rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
934 		rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
935 	}
936 
937 	rtl92d_phy_mac_config(hw);
938 	/* because last function modify RCR, so we update
939 	 * rcr var here, or TP will unstable for receive_config
940 	 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
941 	 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
942 	rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
943 	rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
944 
945 	rtl92d_phy_bb_config(hw);
946 
947 	rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
948 	/* set before initialize RF */
949 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
950 
951 	/* config RF */
952 	rtl92d_phy_rf_config(hw);
953 
954 	/* After read predefined TXT, we must set BB/MAC/RF
955 	 * register as our requirement */
956 	/* After load BB,RF params,we need do more for 92D. */
957 	rtl92d_update_bbrf_configuration(hw);
958 	/* set default value after initialize RF,  */
959 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
960 	rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
961 			RF_CHNLBW, RFREG_OFFSET_MASK);
962 	rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
963 			RF_CHNLBW, RFREG_OFFSET_MASK);
964 
965 	/*---- Set CCK and OFDM Block "ON"----*/
966 	if (rtlhal->current_bandtype == BAND_ON_2_4G)
967 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
968 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
969 	if (rtlhal->interfaceindex == 0) {
970 		/* RFPGA0_ANALOGPARAMETER2: cck clock select,
971 		 *  set to 20MHz by default */
972 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
973 			      BIT(11), 3);
974 	} else {
975 		/* Mac1 */
976 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(11) |
977 			      BIT(10), 3);
978 	}
979 
980 	_rtl92de_hw_configure(hw);
981 
982 	/* reset hw sec */
983 	rtl_cam_reset_all_entry(hw);
984 	rtl92de_enable_hw_security_config(hw);
985 
986 	/* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
987 	/* TX power index for different rate set. */
988 	rtl92d_phy_get_hw_reg_originalvalue(hw);
989 	rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
990 
991 	ppsc->rfpwr_state = ERFON;
992 
993 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
994 
995 	_rtl92de_enable_aspm_back_door(hw);
996 	/* rtlpriv->intf_ops->enable_aspm(hw); */
997 
998 	rtl92d_dm_init(hw);
999 	rtlpci->being_init_adapter = false;
1000 
1001 	if (ppsc->rfpwr_state == ERFON) {
1002 		rtl92d_phy_lc_calibrate(hw);
1003 		/* 5G and 2.4G must wait sometime to let RF LO ready */
1004 		if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1005 			u32 tmp_rega;
1006 			for (i = 0; i < 10000; i++) {
1007 				udelay(MAX_STALL_TIME);
1008 
1009 				tmp_rega = rtl_get_rfreg(hw,
1010 						  (enum radio_path)RF90_PATH_A,
1011 						  0x2a, MASKDWORD);
1012 
1013 				if (((tmp_rega & BIT(11)) == BIT(11)))
1014 					break;
1015 			}
1016 			/* check that loop was successful. If not, exit now */
1017 			if (i == 10000) {
1018 				rtlpci->init_ready = false;
1019 				return 1;
1020 			}
1021 		}
1022 	}
1023 	rtlpci->init_ready = true;
1024 	return err;
1025 }
1026 
1027 static enum version_8192d _rtl92de_read_chip_version(struct ieee80211_hw *hw)
1028 {
1029 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1030 	enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1031 	u32 value32;
1032 
1033 	value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1034 	if (!(value32 & 0x000f0000)) {
1035 		version = VERSION_TEST_CHIP_92D_SINGLEPHY;
1036 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n");
1037 	} else {
1038 		version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1039 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n");
1040 	}
1041 	return version;
1042 }
1043 
1044 static int _rtl92de_set_media_status(struct ieee80211_hw *hw,
1045 				     enum nl80211_iftype type)
1046 {
1047 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1048 	u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1049 	enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1050 	u8 bcnfunc_enable;
1051 
1052 	bt_msr &= 0xfc;
1053 
1054 	if (type == NL80211_IFTYPE_UNSPECIFIED ||
1055 	    type == NL80211_IFTYPE_STATION) {
1056 		_rtl92de_stop_tx_beacon(hw);
1057 		_rtl92de_enable_bcn_sub_func(hw);
1058 	} else if (type == NL80211_IFTYPE_ADHOC ||
1059 		type == NL80211_IFTYPE_AP) {
1060 		_rtl92de_resume_tx_beacon(hw);
1061 		_rtl92de_disable_bcn_sub_func(hw);
1062 	} else {
1063 		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1064 			 "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1065 			 type);
1066 	}
1067 	bcnfunc_enable = rtl_read_byte(rtlpriv, REG_BCN_CTRL);
1068 	switch (type) {
1069 	case NL80211_IFTYPE_UNSPECIFIED:
1070 		bt_msr |= MSR_NOLINK;
1071 		ledaction = LED_CTL_LINK;
1072 		bcnfunc_enable &= 0xF7;
1073 		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1074 			 "Set Network type to NO LINK!\n");
1075 		break;
1076 	case NL80211_IFTYPE_ADHOC:
1077 		bt_msr |= MSR_ADHOC;
1078 		bcnfunc_enable |= 0x08;
1079 		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1080 			 "Set Network type to Ad Hoc!\n");
1081 		break;
1082 	case NL80211_IFTYPE_STATION:
1083 		bt_msr |= MSR_INFRA;
1084 		ledaction = LED_CTL_LINK;
1085 		bcnfunc_enable &= 0xF7;
1086 		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1087 			 "Set Network type to STA!\n");
1088 		break;
1089 	case NL80211_IFTYPE_AP:
1090 		bt_msr |= MSR_AP;
1091 		bcnfunc_enable |= 0x08;
1092 		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1093 			 "Set Network type to AP!\n");
1094 		break;
1095 	default:
1096 		pr_err("Network type %d not supported!\n", type);
1097 		return 1;
1098 	}
1099 	rtl_write_byte(rtlpriv, MSR, bt_msr);
1100 	rtlpriv->cfg->ops->led_control(hw, ledaction);
1101 	if ((bt_msr & MSR_MASK) == MSR_AP)
1102 		rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1103 	else
1104 		rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1105 	return 0;
1106 }
1107 
1108 void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1109 {
1110 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1111 	u32 reg_rcr;
1112 
1113 	if (rtlpriv->psc.rfpwr_state != ERFON)
1114 		return;
1115 
1116 	rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1117 
1118 	if (check_bssid) {
1119 		reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1120 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1121 		_rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
1122 	} else if (!check_bssid) {
1123 		reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1124 		_rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
1125 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1126 	}
1127 }
1128 
1129 int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1130 {
1131 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1132 
1133 	if (_rtl92de_set_media_status(hw, type))
1134 		return -EOPNOTSUPP;
1135 
1136 	/* check bssid */
1137 	if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1138 		if (type != NL80211_IFTYPE_AP)
1139 			rtl92de_set_check_bssid(hw, true);
1140 	} else {
1141 		rtl92de_set_check_bssid(hw, false);
1142 	}
1143 	return 0;
1144 }
1145 
1146 /* do iqk or reload iqk */
1147 /* windows just rtl92d_phy_reload_iqk_setting in set channel,
1148  * but it's very strict for time sequence so we add
1149  * rtl92d_phy_reload_iqk_setting here */
1150 void rtl92d_linked_set_reg(struct ieee80211_hw *hw)
1151 {
1152 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1153 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1154 	u8 indexforchannel;
1155 	u8 channel = rtlphy->current_channel;
1156 
1157 	indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
1158 	if (!rtlphy->iqk_matrix[indexforchannel].iqk_done) {
1159 		RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG,
1160 			 "Do IQK for channel:%d\n", channel);
1161 		rtl92d_phy_iq_calibrate(hw);
1162 	}
1163 }
1164 
1165 /* don't set REG_EDCA_BE_PARAM here because
1166  * mac80211 will send pkt when scan */
1167 void rtl92de_set_qos(struct ieee80211_hw *hw, int aci)
1168 {
1169 	rtl92d_dm_init_edca_turbo(hw);
1170 }
1171 
1172 void rtl92de_enable_interrupt(struct ieee80211_hw *hw)
1173 {
1174 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1175 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1176 
1177 	rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1178 	rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1179 }
1180 
1181 void rtl92de_disable_interrupt(struct ieee80211_hw *hw)
1182 {
1183 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1184 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1185 
1186 	rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1187 	rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1188 	synchronize_irq(rtlpci->pdev->irq);
1189 }
1190 
1191 static void _rtl92de_poweroff_adapter(struct ieee80211_hw *hw)
1192 {
1193 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1194 	u8 u1b_tmp;
1195 	unsigned long flags;
1196 
1197 	rtlpriv->intf_ops->enable_aspm(hw);
1198 	rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1199 	rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0);
1200 	rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0);
1201 
1202 	/* 0x20:value 05-->04 */
1203 	rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1204 
1205 	/*  ==== Reset digital sequence   ====== */
1206 	rtl92d_firmware_selfreset(hw);
1207 
1208 	/* f.   SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */
1209 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1210 
1211 	/* g.   MCUFWDL 0x80[1:0]=0 reset MCU ready status */
1212 	rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1213 
1214 	/*  ==== Pull GPIO PIN to balance level and LED control ====== */
1215 
1216 	/* h.     GPIO_PIN_CTRL 0x44[31:0]=0x000  */
1217 	rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1218 
1219 	/* i.    Value = GPIO_PIN_CTRL[7:0] */
1220 	u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1221 
1222 	/* j.    GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */
1223 	/* write external PIN level  */
1224 	rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL,
1225 			0x00FF0000 | (u1b_tmp << 8));
1226 
1227 	/* k.   GPIO_MUXCFG 0x42 [15:0] = 0x0780 */
1228 	rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1229 
1230 	/* l.   LEDCFG 0x4C[15:0] = 0x8080 */
1231 	rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1232 
1233 	/*  ==== Disable analog sequence === */
1234 
1235 	/* m.   AFE_PLL_CTRL[7:0] = 0x80  disable PLL */
1236 	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1237 
1238 	/* n.   SPS0_CTRL 0x11[7:0] = 0x22  enter PFM mode */
1239 	rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1240 
1241 	/* o.   AFE_XTAL_CTRL 0x24[7:0] = 0x0E  disable XTAL, if No BT COEX */
1242 	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1243 
1244 	/* p.   RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */
1245 	rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1246 
1247 	/*  ==== interface into suspend === */
1248 
1249 	/* q.   APS_FSMCO[15:8] = 0x58 PCIe suspend mode */
1250 	/* According to power document V11, we need to set this */
1251 	/* value as 0x18. Otherwise, we may not L0s sometimes. */
1252 	/* This indluences power consumption. Bases on SD1's test, */
1253 	/* set as 0x00 do not affect power current. And if it */
1254 	/* is set as 0x18, they had ever met auto load fail problem. */
1255 	rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1256 
1257 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1258 		 "In PowerOff,reg0x%x=%X\n",
1259 		 REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL));
1260 	/* r.   Note: for PCIe interface, PON will not turn */
1261 	/* off m-bias and BandGap in PCIe suspend mode.  */
1262 
1263 	/* 0x17[7] 1b': power off in process  0b' : power off over */
1264 	if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
1265 		spin_lock_irqsave(&globalmutex_power, flags);
1266 		u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
1267 		u1b_tmp &= (~BIT(7));
1268 		rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp);
1269 		spin_unlock_irqrestore(&globalmutex_power, flags);
1270 	}
1271 
1272 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n");
1273 }
1274 
1275 void rtl92de_card_disable(struct ieee80211_hw *hw)
1276 {
1277 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1278 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1279 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1280 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1281 	enum nl80211_iftype opmode;
1282 
1283 	mac->link_state = MAC80211_NOLINK;
1284 	opmode = NL80211_IFTYPE_UNSPECIFIED;
1285 	_rtl92de_set_media_status(hw, opmode);
1286 
1287 	if (rtlpci->driver_is_goingto_unload ||
1288 	    ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1289 		rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1290 	RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1291 	/* Power sequence for each MAC. */
1292 	/* a. stop tx DMA  */
1293 	/* b. close RF */
1294 	/* c. clear rx buf */
1295 	/* d. stop rx DMA */
1296 	/* e.  reset MAC */
1297 
1298 	/* a. stop tx DMA */
1299 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1300 	udelay(50);
1301 
1302 	/* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
1303 
1304 	/* c. ========RF OFF sequence==========  */
1305 	/* 0x88c[23:20] = 0xf. */
1306 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1307 	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1308 
1309 	/* APSD_CTRL 0x600[7:0] = 0x40 */
1310 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1311 
1312 	/* Close antenna 0,0xc04,0xd04 */
1313 	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0);
1314 	rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0);
1315 
1316 	/*  SYS_FUNC_EN 0x02[7:0] = 0xE2   reset BB state machine */
1317 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1318 
1319 	/* Mac0 can not do Global reset. Mac1 can do. */
1320 	/* SYS_FUNC_EN 0x02[7:0] = 0xE0  reset BB state machine  */
1321 	if (rtlpriv->rtlhal.interfaceindex == 1)
1322 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1323 	udelay(50);
1324 
1325 	/* d.  stop tx/rx dma before disable REG_CR (0x100) to fix */
1326 	/* dma hang issue when disable/enable device.  */
1327 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
1328 	udelay(50);
1329 	rtl_write_byte(rtlpriv, REG_CR, 0x0);
1330 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n");
1331 	if (rtl92d_phy_check_poweroff(hw))
1332 		_rtl92de_poweroff_adapter(hw);
1333 	return;
1334 }
1335 
1336 void rtl92de_interrupt_recognized(struct ieee80211_hw *hw,
1337 				  struct rtl_int *intvec)
1338 {
1339 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1340 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1341 
1342 	intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1343 	rtl_write_dword(rtlpriv, ISR, intvec->inta);
1344 }
1345 
1346 void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw)
1347 {
1348 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1349 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1350 	u16 bcn_interval, atim_window;
1351 
1352 	bcn_interval = mac->beacon_interval;
1353 	atim_window = 2;
1354 	/*rtl92de_disable_interrupt(hw);  */
1355 	rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1356 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1357 	rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1358 	rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20);
1359 	if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
1360 		rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30);
1361 	else
1362 		rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20);
1363 	rtl_write_byte(rtlpriv, 0x606, 0x30);
1364 }
1365 
1366 void rtl92de_set_beacon_interval(struct ieee80211_hw *hw)
1367 {
1368 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1369 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1370 	u16 bcn_interval = mac->beacon_interval;
1371 
1372 	RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1373 		 "beacon_interval:%d\n", bcn_interval);
1374 	/* rtl92de_disable_interrupt(hw); */
1375 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1376 	/* rtl92de_enable_interrupt(hw); */
1377 }
1378 
1379 void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw,
1380 				   u32 add_msr, u32 rm_msr)
1381 {
1382 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1383 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1384 
1385 	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1386 		 add_msr, rm_msr);
1387 	if (add_msr)
1388 		rtlpci->irq_mask[0] |= add_msr;
1389 	if (rm_msr)
1390 		rtlpci->irq_mask[0] &= (~rm_msr);
1391 	rtl92de_disable_interrupt(hw);
1392 	rtl92de_enable_interrupt(hw);
1393 }
1394 
1395 static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo,
1396 				 u8 *rom_content, bool autoloadfail)
1397 {
1398 	u32 rfpath, eeaddr, group, offset1, offset2;
1399 	u8 i;
1400 
1401 	memset(pwrinfo, 0, sizeof(struct txpower_info));
1402 	if (autoloadfail) {
1403 		for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1404 			for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1405 				if (group < CHANNEL_GROUP_MAX_2G) {
1406 					pwrinfo->cck_index[rfpath][group] =
1407 					    EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1408 					pwrinfo->ht40_1sindex[rfpath][group] =
1409 					    EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1410 				} else {
1411 					pwrinfo->ht40_1sindex[rfpath][group] =
1412 					    EEPROM_DEFAULT_TXPOWERLEVEL_5G;
1413 				}
1414 				pwrinfo->ht40_2sindexdiff[rfpath][group] =
1415 				    EEPROM_DEFAULT_HT40_2SDIFF;
1416 				pwrinfo->ht20indexdiff[rfpath][group] =
1417 				    EEPROM_DEFAULT_HT20_DIFF;
1418 				pwrinfo->ofdmindexdiff[rfpath][group] =
1419 				    EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1420 				pwrinfo->ht40maxoffset[rfpath][group] =
1421 				    EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1422 				pwrinfo->ht20maxoffset[rfpath][group] =
1423 				    EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1424 			}
1425 		}
1426 		for (i = 0; i < 3; i++) {
1427 			pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1428 			pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1429 		}
1430 		return;
1431 	}
1432 
1433 	/* Maybe autoload OK,buf the tx power index value is not filled.
1434 	 * If we find it, we set it to default value. */
1435 	for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1436 		for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) {
1437 			eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3)
1438 				 + group;
1439 			pwrinfo->cck_index[rfpath][group] =
1440 					(rom_content[eeaddr] == 0xFF) ?
1441 					     (eeaddr > 0x7B ?
1442 					     EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1443 					     EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1444 					     rom_content[eeaddr];
1445 		}
1446 	}
1447 	for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1448 		for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1449 			offset1 = group / 3;
1450 			offset2 = group % 3;
1451 			eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) +
1452 			    offset2 + offset1 * 21;
1453 			pwrinfo->ht40_1sindex[rfpath][group] =
1454 			    (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ?
1455 					     EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1456 					     EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1457 						 rom_content[eeaddr];
1458 		}
1459 	}
1460 	/* These just for 92D efuse offset. */
1461 	for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1462 		for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1463 			int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G;
1464 
1465 			offset1 = group / 3;
1466 			offset2 = group % 3;
1467 
1468 			if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF)
1469 				pwrinfo->ht40_2sindexdiff[rfpath][group] =
1470 				    (rom_content[base1 +
1471 				     offset2 + offset1 * 21] >> (rfpath * 4))
1472 				     & 0xF;
1473 			else
1474 				pwrinfo->ht40_2sindexdiff[rfpath][group] =
1475 				    EEPROM_DEFAULT_HT40_2SDIFF;
1476 			if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2
1477 			    + offset1 * 21] != 0xFF)
1478 				pwrinfo->ht20indexdiff[rfpath][group] =
1479 				    (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G
1480 				    + offset2 + offset1 * 21] >> (rfpath * 4))
1481 				    & 0xF;
1482 			else
1483 				pwrinfo->ht20indexdiff[rfpath][group] =
1484 				    EEPROM_DEFAULT_HT20_DIFF;
1485 			if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2
1486 			    + offset1 * 21] != 0xFF)
1487 				pwrinfo->ofdmindexdiff[rfpath][group] =
1488 				    (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G
1489 				     + offset2 + offset1 * 21] >> (rfpath * 4))
1490 				     & 0xF;
1491 			else
1492 				pwrinfo->ofdmindexdiff[rfpath][group] =
1493 				    EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1494 			if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2
1495 			    + offset1 * 21] != 0xFF)
1496 				pwrinfo->ht40maxoffset[rfpath][group] =
1497 				    (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G
1498 				    + offset2 + offset1 * 21] >> (rfpath * 4))
1499 				    & 0xF;
1500 			else
1501 				pwrinfo->ht40maxoffset[rfpath][group] =
1502 				    EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1503 			if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2
1504 			    + offset1 * 21] != 0xFF)
1505 				pwrinfo->ht20maxoffset[rfpath][group] =
1506 				    (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G +
1507 				     offset2 + offset1 * 21] >> (rfpath * 4)) &
1508 				     0xF;
1509 			else
1510 				pwrinfo->ht20maxoffset[rfpath][group] =
1511 				    EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1512 		}
1513 	}
1514 	if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) {
1515 		/* 5GL */
1516 		pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F;
1517 		pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F;
1518 		/* 5GM */
1519 		pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F;
1520 		pwrinfo->tssi_b[1] =
1521 		    (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 |
1522 		    (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2;
1523 		/* 5GH */
1524 		pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] &
1525 				      0xF0) >> 4 |
1526 		    (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4;
1527 		pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] &
1528 				      0xFC) >> 2;
1529 	} else {
1530 		for (i = 0; i < 3; i++) {
1531 			pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1532 			pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1533 		}
1534 	}
1535 }
1536 
1537 static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw,
1538 				       bool autoload_fail, u8 *hwinfo)
1539 {
1540 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1541 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1542 	struct txpower_info pwrinfo;
1543 	u8 tempval[2], i, pwr, diff;
1544 	u32 ch, rfpath, group;
1545 
1546 	_rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail);
1547 	if (!autoload_fail) {
1548 		/* bit0~2 */
1549 		rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7);
1550 		rtlefuse->eeprom_thermalmeter =
1551 			 hwinfo[EEPROM_THERMAL_METER] & 0x1f;
1552 		rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K];
1553 		tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03;
1554 		tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2;
1555 		rtlefuse->txpwr_fromeprom = true;
1556 		if (IS_92D_D_CUT(rtlpriv->rtlhal.version) ||
1557 		    IS_92D_E_CUT(rtlpriv->rtlhal.version)) {
1558 			rtlefuse->internal_pa_5g[0] =
1559 				!((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6);
1560 			rtlefuse->internal_pa_5g[1] =
1561 				!((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6);
1562 			RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1563 				 "Is D cut,Internal PA0 %d Internal PA1 %d\n",
1564 				 rtlefuse->internal_pa_5g[0],
1565 				 rtlefuse->internal_pa_5g[1]);
1566 		}
1567 		rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6];
1568 		rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7];
1569 	} else {
1570 		rtlefuse->eeprom_regulatory = 0;
1571 		rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1572 		rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP;
1573 		tempval[0] = tempval[1] = 3;
1574 	}
1575 
1576 	/* Use default value to fill parameters if
1577 	 * efuse is not filled on some place. */
1578 
1579 	/* ThermalMeter from EEPROM */
1580 	if (rtlefuse->eeprom_thermalmeter < 0x06 ||
1581 	    rtlefuse->eeprom_thermalmeter > 0x1c)
1582 		rtlefuse->eeprom_thermalmeter = 0x12;
1583 	rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1584 
1585 	/* check XTAL_K */
1586 	if (rtlefuse->crystalcap == 0xFF)
1587 		rtlefuse->crystalcap = 0;
1588 	if (rtlefuse->eeprom_regulatory > 3)
1589 		rtlefuse->eeprom_regulatory = 0;
1590 
1591 	for (i = 0; i < 2; i++) {
1592 		switch (tempval[i]) {
1593 		case 0:
1594 			tempval[i] = 5;
1595 			break;
1596 		case 1:
1597 			tempval[i] = 4;
1598 			break;
1599 		case 2:
1600 			tempval[i] = 3;
1601 			break;
1602 		case 3:
1603 		default:
1604 			tempval[i] = 0;
1605 			break;
1606 		}
1607 	}
1608 
1609 	rtlefuse->delta_iqk = tempval[0];
1610 	if (tempval[1] > 0)
1611 		rtlefuse->delta_lck = tempval[1] - 1;
1612 	if (rtlefuse->eeprom_c9 == 0xFF)
1613 		rtlefuse->eeprom_c9 = 0x00;
1614 	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1615 		 "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1616 	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1617 		 "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1618 	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1619 		 "CrystalCap = 0x%x\n", rtlefuse->crystalcap);
1620 	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1621 		 "Delta_IQK = 0x%x Delta_LCK = 0x%x\n",
1622 		 rtlefuse->delta_iqk, rtlefuse->delta_lck);
1623 
1624 	for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1625 		for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1626 			group = rtl92d_get_chnlgroup_fromarray((u8) ch);
1627 			if (ch < CHANNEL_MAX_NUMBER_2G)
1628 				rtlefuse->txpwrlevel_cck[rfpath][ch] =
1629 				    pwrinfo.cck_index[rfpath][group];
1630 			rtlefuse->txpwrlevel_ht40_1s[rfpath][ch] =
1631 				    pwrinfo.ht40_1sindex[rfpath][group];
1632 			rtlefuse->txpwr_ht20diff[rfpath][ch] =
1633 				    pwrinfo.ht20indexdiff[rfpath][group];
1634 			rtlefuse->txpwr_legacyhtdiff[rfpath][ch] =
1635 				    pwrinfo.ofdmindexdiff[rfpath][group];
1636 			rtlefuse->pwrgroup_ht20[rfpath][ch] =
1637 				    pwrinfo.ht20maxoffset[rfpath][group];
1638 			rtlefuse->pwrgroup_ht40[rfpath][ch] =
1639 				    pwrinfo.ht40maxoffset[rfpath][group];
1640 			pwr = pwrinfo.ht40_1sindex[rfpath][group];
1641 			diff = pwrinfo.ht40_2sindexdiff[rfpath][group];
1642 			rtlefuse->txpwrlevel_ht40_2s[rfpath][ch] =
1643 				    (pwr > diff) ? (pwr - diff) : 0;
1644 		}
1645 	}
1646 }
1647 
1648 static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw,
1649 					       u8 *content)
1650 {
1651 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1652 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1653 	u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION];
1654 
1655 	if (macphy_crvalue & BIT(3)) {
1656 		rtlhal->macphymode = SINGLEMAC_SINGLEPHY;
1657 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1658 			 "MacPhyMode SINGLEMAC_SINGLEPHY\n");
1659 	} else {
1660 		rtlhal->macphymode = DUALMAC_DUALPHY;
1661 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1662 			 "MacPhyMode DUALMAC_DUALPHY\n");
1663 	}
1664 }
1665 
1666 static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw,
1667 						  u8 *content)
1668 {
1669 	_rtl92de_read_macphymode_from_prom(hw, content);
1670 	rtl92d_phy_config_macphymode(hw);
1671 	rtl92d_phy_config_macphymode_info(hw);
1672 }
1673 
1674 static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw)
1675 {
1676 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1677 	enum version_8192d chipver = rtlpriv->rtlhal.version;
1678 	u8 cutvalue[2];
1679 	u16 chipvalue;
1680 
1681 	rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H,
1682 					   &cutvalue[1]);
1683 	rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L,
1684 					   &cutvalue[0]);
1685 	chipvalue = (cutvalue[1] << 8) | cutvalue[0];
1686 	switch (chipvalue) {
1687 	case 0xAA55:
1688 		chipver |= CHIP_92D_C_CUT;
1689 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n");
1690 		break;
1691 	case 0x9966:
1692 		chipver |= CHIP_92D_D_CUT;
1693 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n");
1694 		break;
1695 	case 0xCC33:
1696 		chipver |= CHIP_92D_E_CUT;
1697 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n");
1698 		break;
1699 	default:
1700 		chipver |= CHIP_92D_D_CUT;
1701 		pr_err("Unknown CUT!\n");
1702 		break;
1703 	}
1704 	rtlpriv->rtlhal.version = chipver;
1705 }
1706 
1707 static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw)
1708 {
1709 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1710 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1711 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1712 	int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1713 			EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D,
1714 			EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1715 			COUNTRY_CODE_WORLD_WIDE_13};
1716 	int i;
1717 	u16 usvalue;
1718 	u8 *hwinfo;
1719 
1720 	hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1721 	if (!hwinfo)
1722 		return;
1723 
1724 	if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1725 		goto exit;
1726 
1727 	_rtl92de_efuse_update_chip_version(hw);
1728 	_rtl92de_read_macphymode_and_bandtype(hw, hwinfo);
1729 
1730 	/* Read Permanent MAC address for 2nd interface */
1731 	if (rtlhal->interfaceindex != 0) {
1732 		for (i = 0; i < 6; i += 2) {
1733 			usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i];
1734 			*((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1735 		}
1736 	}
1737 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR,
1738 				      rtlefuse->dev_addr);
1739 	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1740 	_rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo);
1741 
1742 	/* Read Channel Plan */
1743 	switch (rtlhal->bandset) {
1744 	case BAND_ON_2_4G:
1745 		rtlefuse->channel_plan = COUNTRY_CODE_TELEC;
1746 		break;
1747 	case BAND_ON_5G:
1748 		rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1749 		break;
1750 	case BAND_ON_BOTH:
1751 		rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1752 		break;
1753 	default:
1754 		rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1755 		break;
1756 	}
1757 	rtlefuse->txpwr_fromeprom = true;
1758 exit:
1759 	kfree(hwinfo);
1760 }
1761 
1762 void rtl92de_read_eeprom_info(struct ieee80211_hw *hw)
1763 {
1764 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1765 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1766 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1767 	u8 tmp_u1b;
1768 
1769 	rtlhal->version = _rtl92de_read_chip_version(hw);
1770 	tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1771 	rtlefuse->autoload_status = tmp_u1b;
1772 	if (tmp_u1b & BIT(4)) {
1773 		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1774 		rtlefuse->epromtype = EEPROM_93C46;
1775 	} else {
1776 		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1777 		rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1778 	}
1779 	if (tmp_u1b & BIT(5)) {
1780 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1781 
1782 		rtlefuse->autoload_failflag = false;
1783 		_rtl92de_read_adapter_info(hw);
1784 	} else {
1785 		pr_err("Autoload ERR!!\n");
1786 	}
1787 	return;
1788 }
1789 
1790 static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw,
1791 					  struct ieee80211_sta *sta)
1792 {
1793 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1794 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1795 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1796 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1797 	u32 ratr_value;
1798 	u8 ratr_index = 0;
1799 	u8 nmode = mac->ht_enable;
1800 	u8 mimo_ps = IEEE80211_SMPS_OFF;
1801 	u16 shortgi_rate;
1802 	u32 tmp_ratr_value;
1803 	u8 curtxbw_40mhz = mac->bw_40;
1804 	u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1805 							1 : 0;
1806 	u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1807 							1 : 0;
1808 	enum wireless_mode wirelessmode = mac->mode;
1809 
1810 	if (rtlhal->current_bandtype == BAND_ON_5G)
1811 		ratr_value = sta->supp_rates[1] << 4;
1812 	else
1813 		ratr_value = sta->supp_rates[0];
1814 	ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1815 		       sta->ht_cap.mcs.rx_mask[0] << 12);
1816 	switch (wirelessmode) {
1817 	case WIRELESS_MODE_A:
1818 		ratr_value &= 0x00000FF0;
1819 		break;
1820 	case WIRELESS_MODE_B:
1821 		if (ratr_value & 0x0000000c)
1822 			ratr_value &= 0x0000000d;
1823 		else
1824 			ratr_value &= 0x0000000f;
1825 		break;
1826 	case WIRELESS_MODE_G:
1827 		ratr_value &= 0x00000FF5;
1828 		break;
1829 	case WIRELESS_MODE_N_24G:
1830 	case WIRELESS_MODE_N_5G:
1831 		nmode = 1;
1832 		if (mimo_ps == IEEE80211_SMPS_STATIC) {
1833 			ratr_value &= 0x0007F005;
1834 		} else {
1835 			u32 ratr_mask;
1836 
1837 			if (get_rf_type(rtlphy) == RF_1T2R ||
1838 			    get_rf_type(rtlphy) == RF_1T1R) {
1839 				ratr_mask = 0x000ff005;
1840 			} else {
1841 				ratr_mask = 0x0f0ff005;
1842 			}
1843 
1844 			ratr_value &= ratr_mask;
1845 		}
1846 		break;
1847 	default:
1848 		if (rtlphy->rf_type == RF_1T2R)
1849 			ratr_value &= 0x000ff0ff;
1850 		else
1851 			ratr_value &= 0x0f0ff0ff;
1852 
1853 		break;
1854 	}
1855 	ratr_value &= 0x0FFFFFFF;
1856 	if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
1857 	    (!curtxbw_40mhz && curshortgi_20mhz))) {
1858 		ratr_value |= 0x10000000;
1859 		tmp_ratr_value = (ratr_value >> 12);
1860 		for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1861 			if ((1 << shortgi_rate) & tmp_ratr_value)
1862 				break;
1863 		}
1864 		shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1865 		    (shortgi_rate << 4) | (shortgi_rate);
1866 	}
1867 	rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1868 	RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1869 		 rtl_read_dword(rtlpriv, REG_ARFR0));
1870 }
1871 
1872 static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw,
1873 		struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
1874 {
1875 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1876 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1877 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1878 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1879 	struct rtl_sta_info *sta_entry = NULL;
1880 	u32 ratr_bitmap;
1881 	u8 ratr_index;
1882 	u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
1883 	u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1884 							1 : 0;
1885 	u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1886 							1 : 0;
1887 	enum wireless_mode wirelessmode = 0;
1888 	bool shortgi = false;
1889 	u32 value[2];
1890 	u8 macid = 0;
1891 	u8 mimo_ps = IEEE80211_SMPS_OFF;
1892 
1893 	sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1894 	mimo_ps = sta_entry->mimo_ps;
1895 	wirelessmode = sta_entry->wireless_mode;
1896 	if (mac->opmode == NL80211_IFTYPE_STATION)
1897 		curtxbw_40mhz = mac->bw_40;
1898 	else if (mac->opmode == NL80211_IFTYPE_AP ||
1899 		mac->opmode == NL80211_IFTYPE_ADHOC)
1900 		macid = sta->aid + 1;
1901 
1902 	if (rtlhal->current_bandtype == BAND_ON_5G)
1903 		ratr_bitmap = sta->supp_rates[1] << 4;
1904 	else
1905 		ratr_bitmap = sta->supp_rates[0];
1906 	ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1907 			sta->ht_cap.mcs.rx_mask[0] << 12);
1908 	switch (wirelessmode) {
1909 	case WIRELESS_MODE_B:
1910 		ratr_index = RATR_INX_WIRELESS_B;
1911 		if (ratr_bitmap & 0x0000000c)
1912 			ratr_bitmap &= 0x0000000d;
1913 		else
1914 			ratr_bitmap &= 0x0000000f;
1915 		break;
1916 	case WIRELESS_MODE_G:
1917 		ratr_index = RATR_INX_WIRELESS_GB;
1918 
1919 		if (rssi_level == 1)
1920 			ratr_bitmap &= 0x00000f00;
1921 		else if (rssi_level == 2)
1922 			ratr_bitmap &= 0x00000ff0;
1923 		else
1924 			ratr_bitmap &= 0x00000ff5;
1925 		break;
1926 	case WIRELESS_MODE_A:
1927 		ratr_index = RATR_INX_WIRELESS_G;
1928 		ratr_bitmap &= 0x00000ff0;
1929 		break;
1930 	case WIRELESS_MODE_N_24G:
1931 	case WIRELESS_MODE_N_5G:
1932 		if (wirelessmode == WIRELESS_MODE_N_24G)
1933 			ratr_index = RATR_INX_WIRELESS_NGB;
1934 		else
1935 			ratr_index = RATR_INX_WIRELESS_NG;
1936 		if (mimo_ps == IEEE80211_SMPS_STATIC) {
1937 			if (rssi_level == 1)
1938 				ratr_bitmap &= 0x00070000;
1939 			else if (rssi_level == 2)
1940 				ratr_bitmap &= 0x0007f000;
1941 			else
1942 				ratr_bitmap &= 0x0007f005;
1943 		} else {
1944 			if (rtlphy->rf_type == RF_1T2R ||
1945 			    rtlphy->rf_type == RF_1T1R) {
1946 				if (curtxbw_40mhz) {
1947 					if (rssi_level == 1)
1948 						ratr_bitmap &= 0x000f0000;
1949 					else if (rssi_level == 2)
1950 						ratr_bitmap &= 0x000ff000;
1951 					else
1952 						ratr_bitmap &= 0x000ff015;
1953 				} else {
1954 					if (rssi_level == 1)
1955 						ratr_bitmap &= 0x000f0000;
1956 					else if (rssi_level == 2)
1957 						ratr_bitmap &= 0x000ff000;
1958 					else
1959 						ratr_bitmap &= 0x000ff005;
1960 				}
1961 			} else {
1962 				if (curtxbw_40mhz) {
1963 					if (rssi_level == 1)
1964 						ratr_bitmap &= 0x0f0f0000;
1965 					else if (rssi_level == 2)
1966 						ratr_bitmap &= 0x0f0ff000;
1967 					else
1968 						ratr_bitmap &= 0x0f0ff015;
1969 				} else {
1970 					if (rssi_level == 1)
1971 						ratr_bitmap &= 0x0f0f0000;
1972 					else if (rssi_level == 2)
1973 						ratr_bitmap &= 0x0f0ff000;
1974 					else
1975 						ratr_bitmap &= 0x0f0ff005;
1976 				}
1977 			}
1978 		}
1979 		if ((curtxbw_40mhz && curshortgi_40mhz) ||
1980 		    (!curtxbw_40mhz && curshortgi_20mhz)) {
1981 
1982 			if (macid == 0)
1983 				shortgi = true;
1984 			else if (macid == 1)
1985 				shortgi = false;
1986 		}
1987 		break;
1988 	default:
1989 		ratr_index = RATR_INX_WIRELESS_NGB;
1990 
1991 		if (rtlphy->rf_type == RF_1T2R)
1992 			ratr_bitmap &= 0x000ff0ff;
1993 		else
1994 			ratr_bitmap &= 0x0f0ff0ff;
1995 		break;
1996 	}
1997 
1998 	value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28);
1999 	value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2000 	RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2001 		 "ratr_bitmap :%x value0:%x value1:%x\n",
2002 		 ratr_bitmap, value[0], value[1]);
2003 	rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value);
2004 	if (macid != 0)
2005 		sta_entry->ratr_index = ratr_index;
2006 }
2007 
2008 void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw,
2009 		struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
2010 {
2011 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2012 
2013 	if (rtlpriv->dm.useramask)
2014 		rtl92de_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2015 	else
2016 		rtl92de_update_hal_rate_table(hw, sta);
2017 }
2018 
2019 void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw)
2020 {
2021 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2022 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2023 	u16 sifs_timer;
2024 
2025 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2026 				      &mac->slot_time);
2027 	if (!mac->ht_enable)
2028 		sifs_timer = 0x0a0a;
2029 	else
2030 		sifs_timer = 0x1010;
2031 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2032 }
2033 
2034 bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2035 {
2036 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2037 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2038 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2039 	enum rf_pwrstate e_rfpowerstate_toset;
2040 	u8 u1tmp;
2041 	bool actuallyset = false;
2042 	unsigned long flag;
2043 
2044 	if (rtlpci->being_init_adapter)
2045 		return false;
2046 	if (ppsc->swrf_processing)
2047 		return false;
2048 	spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2049 	if (ppsc->rfchange_inprogress) {
2050 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2051 		return false;
2052 	} else {
2053 		ppsc->rfchange_inprogress = true;
2054 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2055 	}
2056 	rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2057 			  REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2058 	u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2059 	e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2060 	if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2061 		RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2062 			 "GPIOChangeRF  - HW Radio ON, RF ON\n");
2063 		e_rfpowerstate_toset = ERFON;
2064 		ppsc->hwradiooff = false;
2065 		actuallyset = true;
2066 	} else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2067 		RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2068 			 "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2069 		e_rfpowerstate_toset = ERFOFF;
2070 		ppsc->hwradiooff = true;
2071 		actuallyset = true;
2072 	}
2073 	if (actuallyset) {
2074 		spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2075 		ppsc->rfchange_inprogress = false;
2076 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2077 	} else {
2078 		if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2079 			RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2080 		spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2081 		ppsc->rfchange_inprogress = false;
2082 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2083 	}
2084 	*valid = 1;
2085 	return !ppsc->hwradiooff;
2086 }
2087 
2088 void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index,
2089 		     u8 *p_macaddr, bool is_group, u8 enc_algo,
2090 		     bool is_wepkey, bool clear_all)
2091 {
2092 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2093 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2094 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2095 	u8 *macaddr = p_macaddr;
2096 	u32 entry_id;
2097 	bool is_pairwise = false;
2098 	static u8 cam_const_addr[4][6] = {
2099 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2100 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2101 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2102 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2103 	};
2104 	static u8 cam_const_broad[] = {
2105 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2106 	};
2107 
2108 	if (clear_all) {
2109 		u8 idx;
2110 		u8 cam_offset = 0;
2111 		u8 clear_number = 5;
2112 		RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2113 		for (idx = 0; idx < clear_number; idx++) {
2114 			rtl_cam_mark_invalid(hw, cam_offset + idx);
2115 			rtl_cam_empty_entry(hw, cam_offset + idx);
2116 
2117 			if (idx < 5) {
2118 				memset(rtlpriv->sec.key_buf[idx], 0,
2119 				       MAX_KEY_LEN);
2120 				rtlpriv->sec.key_len[idx] = 0;
2121 			}
2122 		}
2123 	} else {
2124 		switch (enc_algo) {
2125 		case WEP40_ENCRYPTION:
2126 			enc_algo = CAM_WEP40;
2127 			break;
2128 		case WEP104_ENCRYPTION:
2129 			enc_algo = CAM_WEP104;
2130 			break;
2131 		case TKIP_ENCRYPTION:
2132 			enc_algo = CAM_TKIP;
2133 			break;
2134 		case AESCCMP_ENCRYPTION:
2135 			enc_algo = CAM_AES;
2136 			break;
2137 		default:
2138 			pr_err("switch case %#x not processed\n",
2139 			       enc_algo);
2140 			enc_algo = CAM_TKIP;
2141 			break;
2142 		}
2143 		if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2144 			macaddr = cam_const_addr[key_index];
2145 			entry_id = key_index;
2146 		} else {
2147 			if (is_group) {
2148 				macaddr = cam_const_broad;
2149 				entry_id = key_index;
2150 			} else {
2151 				if (mac->opmode == NL80211_IFTYPE_AP) {
2152 					entry_id = rtl_cam_get_free_entry(hw,
2153 								 p_macaddr);
2154 					if (entry_id >=  TOTAL_CAM_ENTRY) {
2155 						pr_err("Can not find free hw security cam entry\n");
2156 						return;
2157 					}
2158 				} else {
2159 					entry_id = CAM_PAIRWISE_KEY_POSITION;
2160 				}
2161 				key_index = PAIRWISE_KEYIDX;
2162 				is_pairwise = true;
2163 			}
2164 		}
2165 		if (rtlpriv->sec.key_len[key_index] == 0) {
2166 			RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2167 				 "delete one entry, entry_id is %d\n",
2168 				 entry_id);
2169 			if (mac->opmode == NL80211_IFTYPE_AP)
2170 				rtl_cam_del_entry(hw, p_macaddr);
2171 			rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2172 		} else {
2173 			RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2174 				 "The insert KEY length is %d\n",
2175 				 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2176 			RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2177 				 "The insert KEY is %x %x\n",
2178 				 rtlpriv->sec.key_buf[0][0],
2179 				 rtlpriv->sec.key_buf[0][1]);
2180 			RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2181 				 "add one entry\n");
2182 			if (is_pairwise) {
2183 				RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2184 					      "Pairwise Key content",
2185 					      rtlpriv->sec.pairwise_key,
2186 					      rtlpriv->
2187 					      sec.key_len[PAIRWISE_KEYIDX]);
2188 				RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2189 					 "set Pairwise key\n");
2190 				rtl_cam_add_one_entry(hw, macaddr, key_index,
2191 						      entry_id, enc_algo,
2192 						      CAM_CONFIG_NO_USEDK,
2193 						      rtlpriv->
2194 						      sec.key_buf[key_index]);
2195 			} else {
2196 				RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2197 					 "set group key\n");
2198 				if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2199 					rtl_cam_add_one_entry(hw,
2200 						rtlefuse->dev_addr,
2201 						PAIRWISE_KEYIDX,
2202 						CAM_PAIRWISE_KEY_POSITION,
2203 						enc_algo, CAM_CONFIG_NO_USEDK,
2204 						rtlpriv->sec.key_buf[entry_id]);
2205 				}
2206 				rtl_cam_add_one_entry(hw, macaddr, key_index,
2207 						entry_id, enc_algo,
2208 						CAM_CONFIG_NO_USEDK,
2209 						rtlpriv->sec.key_buf
2210 						[entry_id]);
2211 			}
2212 		}
2213 	}
2214 }
2215 
2216 void rtl92de_suspend(struct ieee80211_hw *hw)
2217 {
2218 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2219 
2220 	rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv,
2221 		REG_MAC_PHY_CTRL_NORMAL);
2222 }
2223 
2224 void rtl92de_resume(struct ieee80211_hw *hw)
2225 {
2226 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2227 
2228 	rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL,
2229 		       rtlpriv->rtlhal.macphyctl_reg);
2230 }
2231