1 /******************************************************************************
2  *
3  * Copyright(c) 2009-2012  Realtek Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * The full GNU General Public License is included in this distribution in the
15  * file called LICENSE.
16  *
17  * Contact Information:
18  * wlanfae <wlanfae@realtek.com>
19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20  * Hsinchu 300, Taiwan.
21  *
22  * Larry Finger <Larry.Finger@lwfinger.net>
23  *
24  *****************************************************************************/
25 
26 #include "../wifi.h"
27 #include "../efuse.h"
28 #include "../base.h"
29 #include "../regd.h"
30 #include "../cam.h"
31 #include "../ps.h"
32 #include "../pci.h"
33 #include "reg.h"
34 #include "def.h"
35 #include "phy.h"
36 #include "dm.h"
37 #include "fw.h"
38 #include "led.h"
39 #include "sw.h"
40 #include "hw.h"
41 
42 u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset, u8 direct)
43 {
44 	struct rtl_priv *rtlpriv = rtl_priv(hw);
45 	u32 value;
46 
47 	rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC));
48 	rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct);
49 	udelay(10);
50 	value = rtl_read_dword(rtlpriv, REG_DBI_RDATA);
51 	return value;
52 }
53 
54 void rtl92de_write_dword_dbi(struct ieee80211_hw *hw,
55 			     u16 offset, u32 value, u8 direct)
56 {
57 	struct rtl_priv *rtlpriv = rtl_priv(hw);
58 
59 	rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000));
60 	rtl_write_dword(rtlpriv, REG_DBI_WDATA, value);
61 	rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct);
62 }
63 
64 static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
65 				      u8 set_bits, u8 clear_bits)
66 {
67 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
68 	struct rtl_priv *rtlpriv = rtl_priv(hw);
69 
70 	rtlpci->reg_bcn_ctrl_val |= set_bits;
71 	rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
72 	rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
73 }
74 
75 static void _rtl92de_stop_tx_beacon(struct ieee80211_hw *hw)
76 {
77 	struct rtl_priv *rtlpriv = rtl_priv(hw);
78 	u8 tmp1byte;
79 
80 	tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
81 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
82 	rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
83 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
84 	tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
85 	tmp1byte &= ~(BIT(0));
86 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
87 }
88 
89 static void _rtl92de_resume_tx_beacon(struct ieee80211_hw *hw)
90 {
91 	struct rtl_priv *rtlpriv = rtl_priv(hw);
92 	u8 tmp1byte;
93 
94 	tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
95 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
96 	rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
97 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
98 	tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
99 	tmp1byte |= BIT(0);
100 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
101 }
102 
103 static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw)
104 {
105 	_rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1));
106 }
107 
108 static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw)
109 {
110 	_rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0);
111 }
112 
113 void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
114 {
115 	struct rtl_priv *rtlpriv = rtl_priv(hw);
116 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
117 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
118 
119 	switch (variable) {
120 	case HW_VAR_RCR:
121 		*((u32 *) (val)) = rtlpci->receive_config;
122 		break;
123 	case HW_VAR_RF_STATE:
124 		*((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
125 		break;
126 	case HW_VAR_FWLPS_RF_ON:{
127 		enum rf_pwrstate rfState;
128 		u32 val_rcr;
129 
130 		rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
131 					      (u8 *) (&rfState));
132 		if (rfState == ERFOFF) {
133 			*((bool *) (val)) = true;
134 		} else {
135 			val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
136 			val_rcr &= 0x00070000;
137 			if (val_rcr)
138 				*((bool *) (val)) = false;
139 			else
140 				*((bool *) (val)) = true;
141 		}
142 		break;
143 	}
144 	case HW_VAR_FW_PSMODE_STATUS:
145 		*((bool *) (val)) = ppsc->fw_current_inpsmode;
146 		break;
147 	case HW_VAR_CORRECT_TSF:{
148 		u64 tsf;
149 		u32 *ptsf_low = (u32 *)&tsf;
150 		u32 *ptsf_high = ((u32 *)&tsf) + 1;
151 
152 		*ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
153 		*ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
154 		*((u64 *) (val)) = tsf;
155 		break;
156 	}
157 	case HW_VAR_INT_MIGRATION:
158 		*((bool *)(val)) = rtlpriv->dm.interrupt_migration;
159 		break;
160 	case HW_VAR_INT_AC:
161 		*((bool *)(val)) = rtlpriv->dm.disable_tx_int;
162 		break;
163 	case HAL_DEF_WOWLAN:
164 		break;
165 	default:
166 		pr_err("switch case %#x not processed\n", variable);
167 		break;
168 	}
169 }
170 
171 void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
172 {
173 	struct rtl_priv *rtlpriv = rtl_priv(hw);
174 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
175 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
176 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
177 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
178 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
179 	u8 idx;
180 
181 	switch (variable) {
182 	case HW_VAR_ETHER_ADDR:
183 		for (idx = 0; idx < ETH_ALEN; idx++) {
184 			rtl_write_byte(rtlpriv, (REG_MACID + idx),
185 				       val[idx]);
186 		}
187 		break;
188 	case HW_VAR_BASIC_RATE: {
189 		u16 rate_cfg = ((u16 *) val)[0];
190 		u8 rate_index = 0;
191 
192 		rate_cfg = rate_cfg & 0x15f;
193 		if (mac->vendor == PEER_CISCO &&
194 		    ((rate_cfg & 0x150) == 0))
195 			rate_cfg |= 0x01;
196 		rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
197 		rtl_write_byte(rtlpriv, REG_RRSR + 1,
198 			       (rate_cfg >> 8) & 0xff);
199 		while (rate_cfg > 0x1) {
200 			rate_cfg = (rate_cfg >> 1);
201 			rate_index++;
202 		}
203 		if (rtlhal->fw_version > 0xe)
204 			rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
205 				       rate_index);
206 		break;
207 	}
208 	case HW_VAR_BSSID:
209 		for (idx = 0; idx < ETH_ALEN; idx++) {
210 			rtl_write_byte(rtlpriv, (REG_BSSID + idx),
211 				       val[idx]);
212 		}
213 		break;
214 	case HW_VAR_SIFS:
215 		rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
216 		rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
217 		rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
218 		rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
219 		if (!mac->ht_enable)
220 			rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
221 				       0x0e0e);
222 		else
223 			rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
224 				       *((u16 *) val));
225 		break;
226 	case HW_VAR_SLOT_TIME: {
227 		u8 e_aci;
228 
229 		RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
230 			 "HW_VAR_SLOT_TIME %x\n", val[0]);
231 		rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
232 		for (e_aci = 0; e_aci < AC_MAX; e_aci++)
233 			rtlpriv->cfg->ops->set_hw_reg(hw,
234 						      HW_VAR_AC_PARAM,
235 						      (&e_aci));
236 		break;
237 	}
238 	case HW_VAR_ACK_PREAMBLE: {
239 		u8 reg_tmp;
240 		u8 short_preamble = (bool) (*val);
241 
242 		reg_tmp = (mac->cur_40_prime_sc) << 5;
243 		if (short_preamble)
244 			reg_tmp |= 0x80;
245 		rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
246 		break;
247 	}
248 	case HW_VAR_AMPDU_MIN_SPACE: {
249 		u8 min_spacing_to_set;
250 		u8 sec_min_space;
251 
252 		min_spacing_to_set = *val;
253 		if (min_spacing_to_set <= 7) {
254 			sec_min_space = 0;
255 			if (min_spacing_to_set < sec_min_space)
256 				min_spacing_to_set = sec_min_space;
257 			mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
258 					      min_spacing_to_set);
259 			*val = min_spacing_to_set;
260 			RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
261 				 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
262 				 mac->min_space_cfg);
263 			rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
264 				       mac->min_space_cfg);
265 		}
266 		break;
267 	}
268 	case HW_VAR_SHORTGI_DENSITY: {
269 		u8 density_to_set;
270 
271 		density_to_set = *val;
272 		mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
273 		mac->min_space_cfg |= (density_to_set << 3);
274 		RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
275 			 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
276 			 mac->min_space_cfg);
277 		rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
278 			       mac->min_space_cfg);
279 		break;
280 	}
281 	case HW_VAR_AMPDU_FACTOR: {
282 		u8 factor_toset;
283 		u32 regtoSet;
284 		u8 *ptmp_byte = NULL;
285 		u8 index;
286 
287 		if (rtlhal->macphymode == DUALMAC_DUALPHY)
288 			regtoSet = 0xb9726641;
289 		else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
290 			regtoSet = 0x66626641;
291 		else
292 			regtoSet = 0xb972a841;
293 		factor_toset = *val;
294 		if (factor_toset <= 3) {
295 			factor_toset = (1 << (factor_toset + 2));
296 			if (factor_toset > 0xf)
297 				factor_toset = 0xf;
298 			for (index = 0; index < 4; index++) {
299 				ptmp_byte = (u8 *) (&regtoSet) + index;
300 				if ((*ptmp_byte & 0xf0) >
301 				    (factor_toset << 4))
302 					*ptmp_byte = (*ptmp_byte & 0x0f)
303 						 | (factor_toset << 4);
304 				if ((*ptmp_byte & 0x0f) > factor_toset)
305 					*ptmp_byte = (*ptmp_byte & 0xf0)
306 						     | (factor_toset);
307 			}
308 			rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoSet);
309 			RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
310 				 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
311 				 factor_toset);
312 		}
313 		break;
314 	}
315 	case HW_VAR_AC_PARAM: {
316 		u8 e_aci = *val;
317 		rtl92d_dm_init_edca_turbo(hw);
318 		if (rtlpci->acm_method != EACMWAY2_SW)
319 			rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
320 						      &e_aci);
321 		break;
322 	}
323 	case HW_VAR_ACM_CTRL: {
324 		u8 e_aci = *val;
325 		union aci_aifsn *p_aci_aifsn =
326 		    (union aci_aifsn *)(&(mac->ac[0].aifs));
327 		u8 acm = p_aci_aifsn->f.acm;
328 		u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
329 
330 		acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?  0x0 : 0x1);
331 		if (acm) {
332 			switch (e_aci) {
333 			case AC0_BE:
334 				acm_ctrl |= ACMHW_BEQEN;
335 				break;
336 			case AC2_VI:
337 				acm_ctrl |= ACMHW_VIQEN;
338 				break;
339 			case AC3_VO:
340 				acm_ctrl |= ACMHW_VOQEN;
341 				break;
342 			default:
343 				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
344 					 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
345 					 acm);
346 				break;
347 			}
348 		} else {
349 			switch (e_aci) {
350 			case AC0_BE:
351 				acm_ctrl &= (~ACMHW_BEQEN);
352 				break;
353 			case AC2_VI:
354 				acm_ctrl &= (~ACMHW_VIQEN);
355 				break;
356 			case AC3_VO:
357 				acm_ctrl &= (~ACMHW_VOQEN);
358 				break;
359 			default:
360 				pr_err("switch case %#x not processed\n",
361 				       e_aci);
362 				break;
363 			}
364 		}
365 		RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
366 			 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
367 			 acm_ctrl);
368 		rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
369 		break;
370 	}
371 	case HW_VAR_RCR:
372 		rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
373 		rtlpci->receive_config = ((u32 *) (val))[0];
374 		break;
375 	case HW_VAR_RETRY_LIMIT: {
376 		u8 retry_limit = val[0];
377 
378 		rtl_write_word(rtlpriv, REG_RL,
379 			       retry_limit << RETRY_LIMIT_SHORT_SHIFT |
380 			       retry_limit << RETRY_LIMIT_LONG_SHIFT);
381 		break;
382 	}
383 	case HW_VAR_DUAL_TSF_RST:
384 		rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
385 		break;
386 	case HW_VAR_EFUSE_BYTES:
387 		rtlefuse->efuse_usedbytes = *((u16 *) val);
388 		break;
389 	case HW_VAR_EFUSE_USAGE:
390 		rtlefuse->efuse_usedpercentage = *val;
391 		break;
392 	case HW_VAR_IO_CMD:
393 		rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val));
394 		break;
395 	case HW_VAR_WPA_CONFIG:
396 		rtl_write_byte(rtlpriv, REG_SECCFG, *val);
397 		break;
398 	case HW_VAR_SET_RPWM:
399 		rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (val));
400 		break;
401 	case HW_VAR_H2C_FW_PWRMODE:
402 		break;
403 	case HW_VAR_FW_PSMODE_STATUS:
404 		ppsc->fw_current_inpsmode = *((bool *) val);
405 		break;
406 	case HW_VAR_H2C_FW_JOINBSSRPT: {
407 		u8 mstatus = (*val);
408 		u8 tmp_regcr, tmp_reg422;
409 		bool recover = false;
410 
411 		if (mstatus == RT_MEDIA_CONNECT) {
412 			rtlpriv->cfg->ops->set_hw_reg(hw,
413 						      HW_VAR_AID, NULL);
414 			tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
415 			rtl_write_byte(rtlpriv, REG_CR + 1,
416 				       (tmp_regcr | BIT(0)));
417 			_rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
418 			_rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
419 			tmp_reg422 = rtl_read_byte(rtlpriv,
420 						 REG_FWHW_TXQ_CTRL + 2);
421 			if (tmp_reg422 & BIT(6))
422 				recover = true;
423 			rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
424 				       tmp_reg422 & (~BIT(6)));
425 			rtl92d_set_fw_rsvdpagepkt(hw, 0);
426 			_rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
427 			_rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
428 			if (recover)
429 				rtl_write_byte(rtlpriv,
430 					       REG_FWHW_TXQ_CTRL + 2,
431 					       tmp_reg422);
432 			rtl_write_byte(rtlpriv, REG_CR + 1,
433 				       (tmp_regcr & ~(BIT(0))));
434 		}
435 		rtl92d_set_fw_joinbss_report_cmd(hw, (*val));
436 		break;
437 	}
438 	case HW_VAR_AID: {
439 		u16 u2btmp;
440 		u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
441 		u2btmp &= 0xC000;
442 		rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
443 			       mac->assoc_id));
444 		break;
445 	}
446 	case HW_VAR_CORRECT_TSF: {
447 		u8 btype_ibss = val[0];
448 
449 		if (btype_ibss)
450 			_rtl92de_stop_tx_beacon(hw);
451 		_rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
452 		rtl_write_dword(rtlpriv, REG_TSFTR,
453 				(u32) (mac->tsf & 0xffffffff));
454 		rtl_write_dword(rtlpriv, REG_TSFTR + 4,
455 				(u32) ((mac->tsf >> 32) & 0xffffffff));
456 		_rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
457 		if (btype_ibss)
458 			_rtl92de_resume_tx_beacon(hw);
459 
460 		break;
461 	}
462 	case HW_VAR_INT_MIGRATION: {
463 		bool int_migration = *(bool *) (val);
464 
465 		if (int_migration) {
466 			/* Set interrupt migration timer and
467 			 * corresponding Tx/Rx counter.
468 			 * timer 25ns*0xfa0=100us for 0xf packets.
469 			 * 0x306:Rx, 0x307:Tx */
470 			rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0);
471 			rtlpriv->dm.interrupt_migration = int_migration;
472 		} else {
473 			/* Reset all interrupt migration settings. */
474 			rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
475 			rtlpriv->dm.interrupt_migration = int_migration;
476 		}
477 		break;
478 	}
479 	case HW_VAR_INT_AC: {
480 		bool disable_ac_int = *((bool *) val);
481 
482 		/* Disable four ACs interrupts. */
483 		if (disable_ac_int) {
484 			/* Disable VO, VI, BE and BK four AC interrupts
485 			 * to gain more efficient CPU utilization.
486 			 * When extremely highly Rx OK occurs,
487 			 * we will disable Tx interrupts.
488 			 */
489 			rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
490 						 RT_AC_INT_MASKS);
491 			rtlpriv->dm.disable_tx_int = disable_ac_int;
492 		/* Enable four ACs interrupts. */
493 		} else {
494 			rtlpriv->cfg->ops->update_interrupt_mask(hw,
495 						 RT_AC_INT_MASKS, 0);
496 			rtlpriv->dm.disable_tx_int = disable_ac_int;
497 		}
498 		break;
499 	}
500 	default:
501 		pr_err("switch case %#x not processed\n", variable);
502 		break;
503 	}
504 }
505 
506 static bool _rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
507 {
508 	struct rtl_priv *rtlpriv = rtl_priv(hw);
509 	bool status = true;
510 	long count = 0;
511 	u32 value = _LLT_INIT_ADDR(address) |
512 	    _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
513 
514 	rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
515 	do {
516 		value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
517 		if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
518 			break;
519 		if (count > POLLING_LLT_THRESHOLD) {
520 			pr_err("Failed to polling write LLT done at address %d!\n",
521 			       address);
522 			status = false;
523 			break;
524 		}
525 	} while (++count);
526 	return status;
527 }
528 
529 static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw)
530 {
531 	struct rtl_priv *rtlpriv = rtl_priv(hw);
532 	unsigned short i;
533 	u8 txpktbuf_bndy;
534 	u8 maxPage;
535 	bool status;
536 	u32 value32; /* High+low page number */
537 	u8 value8;	 /* normal page number */
538 
539 	if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
540 		maxPage = 255;
541 		txpktbuf_bndy = 246;
542 		value8 = 0;
543 		value32 = 0x80bf0d29;
544 	} else {
545 		maxPage = 127;
546 		txpktbuf_bndy = 123;
547 		value8 = 0;
548 		value32 = 0x80750005;
549 	}
550 
551 	/* Set reserved page for each queue */
552 	/* 11.  RQPN 0x200[31:0] = 0x80BD1C1C */
553 	/* load RQPN */
554 	rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
555 	rtl_write_dword(rtlpriv, REG_RQPN, value32);
556 
557 	/* 12.  TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */
558 	/* TXRKTBUG_PG_BNDY */
559 	rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
560 			(rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 |
561 			txpktbuf_bndy));
562 
563 	/* 13.  TDECTRL[15:8] 0x209[7:0] = 0xF6 */
564 	/* Beacon Head for TXDMA */
565 	rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
566 
567 	/* 14.  BCNQ_PGBNDY 0x424[7:0] =  0xF6 */
568 	/* BCNQ_PGBNDY */
569 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
570 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
571 
572 	/* 15.  WMAC_LBK_BF_HD 0x45D[7:0] =  0xF6 */
573 	/* WMAC_LBK_BF_HD */
574 	rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
575 
576 	/* Set Tx/Rx page size (Tx must be 128 Bytes, */
577 	/* Rx can be 64,128,256,512,1024 bytes) */
578 	/* 16.  PBP [7:0] = 0x11 */
579 	/* TRX page size */
580 	rtl_write_byte(rtlpriv, REG_PBP, 0x11);
581 
582 	/* 17.  DRV_INFO_SZ = 0x04 */
583 	rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
584 
585 	/* 18.  LLT_table_init(Adapter);  */
586 	for (i = 0; i < (txpktbuf_bndy - 1); i++) {
587 		status = _rtl92de_llt_write(hw, i, i + 1);
588 		if (true != status)
589 			return status;
590 	}
591 
592 	/* end of list */
593 	status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
594 	if (true != status)
595 		return status;
596 
597 	/* Make the other pages as ring buffer */
598 	/* This ring buffer is used as beacon buffer if we */
599 	/* config this MAC as two MAC transfer. */
600 	/* Otherwise used as local loopback buffer.  */
601 	for (i = txpktbuf_bndy; i < maxPage; i++) {
602 		status = _rtl92de_llt_write(hw, i, (i + 1));
603 		if (true != status)
604 			return status;
605 	}
606 
607 	/* Let last entry point to the start entry of ring buffer */
608 	status = _rtl92de_llt_write(hw, maxPage, txpktbuf_bndy);
609 	if (true != status)
610 		return status;
611 
612 	return true;
613 }
614 
615 static void _rtl92de_gen_refresh_led_state(struct ieee80211_hw *hw)
616 {
617 	struct rtl_priv *rtlpriv = rtl_priv(hw);
618 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
619 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
620 	struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
621 
622 	if (rtlpci->up_first_time)
623 		return;
624 	if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
625 		rtl92de_sw_led_on(hw, pled0);
626 	else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
627 		rtl92de_sw_led_on(hw, pled0);
628 	else
629 		rtl92de_sw_led_off(hw, pled0);
630 }
631 
632 static bool _rtl92de_init_mac(struct ieee80211_hw *hw)
633 {
634 	struct rtl_priv *rtlpriv = rtl_priv(hw);
635 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
636 	unsigned char bytetmp;
637 	unsigned short wordtmp;
638 	u16 retry;
639 
640 	rtl92d_phy_set_poweron(hw);
641 	/* Add for resume sequence of power domain according
642 	 * to power document V11. Chapter V.11....  */
643 	/* 0.   RSV_CTRL 0x1C[7:0] = 0x00  */
644 	/* unlock ISO/CLK/Power control register */
645 	rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
646 	rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05);
647 
648 	/* 1.   AFE_XTAL_CTRL [7:0] = 0x0F  enable XTAL */
649 	/* 2.   SPS0_CTRL 0x11[7:0] = 0x2b  enable SPS into PWM mode  */
650 	/* 3.   delay (1ms) this is not necessary when initially power on */
651 
652 	/* C.   Resume Sequence */
653 	/* a.   SPS0_CTRL 0x11[7:0] = 0x2b */
654 	rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
655 
656 	/* b.   AFE_XTAL_CTRL [7:0] = 0x0F */
657 	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
658 
659 	/* c.   DRV runs power on init flow */
660 
661 	/* auto enable WLAN */
662 	/* 4.   APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0   */
663 	/* Power On Reset for MAC Block */
664 	bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
665 	udelay(2);
666 	rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
667 	udelay(2);
668 
669 	/* 5.   Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */
670 	bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
671 	udelay(50);
672 	retry = 0;
673 	while ((bytetmp & BIT(0)) && retry < 1000) {
674 		retry++;
675 		bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
676 		udelay(50);
677 	}
678 
679 	/* Enable Radio off, GPIO, and LED function */
680 	/* 6.   APS_FSMCO 0x04[15:0] = 0x0012  when enable HWPDN */
681 	rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
682 
683 	/* release RF digital isolation  */
684 	/* 7.  SYS_ISO_CTRL 0x01[1]    = 0x0;  */
685 	/*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */
686 	rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
687 	udelay(2);
688 
689 	/* make sure that BB reset OK. */
690 	/* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */
691 
692 	/* Disable REG_CR before enable it to assure reset */
693 	rtl_write_word(rtlpriv, REG_CR, 0x0);
694 
695 	/* Release MAC IO register reset */
696 	rtl_write_word(rtlpriv, REG_CR, 0x2ff);
697 
698 	/* clear stopping tx/rx dma   */
699 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0);
700 
701 	/* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */
702 
703 	/* System init */
704 	/* 18.  LLT_table_init(Adapter);  */
705 	if (!_rtl92de_llt_table_init(hw))
706 		return false;
707 
708 	/* Clear interrupt and enable interrupt */
709 	/* 19.  HISR 0x124[31:0] = 0xffffffff;  */
710 	/*      HISRE 0x12C[7:0] = 0xFF */
711 	rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
712 	rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
713 
714 	/* 20.  HIMR 0x120[31:0] |= [enable INT mask bit map];  */
715 	/* 21.  HIMRE 0x128[7:0] = [enable INT mask bit map] */
716 	/* The IMR should be enabled later after all init sequence
717 	 * is finished. */
718 
719 	/* 22.  PCIE configuration space configuration */
720 	/* 23.  Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ),  */
721 	/*      and PCIe gated clock function is enabled.    */
722 	/* PCIE configuration space will be written after
723 	 * all init sequence.(Or by BIOS) */
724 
725 	rtl92d_phy_config_maccoexist_rfpage(hw);
726 
727 	/* THe below section is not related to power document Vxx . */
728 	/* This is only useful for driver and OS setting. */
729 	/* -------------------Software Relative Setting---------------------- */
730 	wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
731 	wordtmp &= 0xf;
732 	wordtmp |= 0xF771;
733 	rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
734 
735 	/* Reported Tx status from HW for rate adaptive. */
736 	/* This should be realtive to power on step 14. But in document V11  */
737 	/* still not contain the description.!!! */
738 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
739 
740 	/* Set Tx/Rx page size (Tx must be 128 Bytes,
741 	 * Rx can be 64,128,256,512,1024 bytes) */
742 	/* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */
743 
744 	/* Set RCR register */
745 	rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
746 	/* rtl_write_byte(rtlpriv,REG_RX_DRVINFO_SZ, 4); */
747 
748 	/*  Set TCR register */
749 	rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
750 
751 	/* disable earlymode */
752 	rtl_write_byte(rtlpriv, 0x4d0, 0x0);
753 
754 	/* Set TX/RX descriptor physical address(from OS API). */
755 	rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
756 			rtlpci->tx_ring[BEACON_QUEUE].dma);
757 	rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma);
758 	rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma);
759 	rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma);
760 	rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma);
761 	rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma);
762 	rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma);
763 	/* Set RX Desc Address */
764 	rtl_write_dword(rtlpriv, REG_RX_DESA,
765 			rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
766 
767 	/* if we want to support 64 bit DMA, we should set it here,
768 	 * but now we do not support 64 bit DMA*/
769 
770 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33);
771 
772 	/* Reset interrupt migration setting when initialization */
773 	rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
774 
775 	/* Reconsider when to do this operation after asking HWSD. */
776 	bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
777 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
778 	do {
779 		retry++;
780 		bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
781 	} while ((retry < 200) && !(bytetmp & BIT(7)));
782 
783 	/* After MACIO reset,we must refresh LED state. */
784 	_rtl92de_gen_refresh_led_state(hw);
785 
786 	/* Reset H2C protection register */
787 	rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
788 
789 	return true;
790 }
791 
792 static void _rtl92de_hw_configure(struct ieee80211_hw *hw)
793 {
794 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
795 	struct rtl_priv *rtlpriv = rtl_priv(hw);
796 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
797 	u8 reg_bw_opmode = BW_OPMODE_20MHZ;
798 	u32 reg_rrsr;
799 
800 	reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
801 	rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
802 	rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
803 	rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
804 	rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
805 	rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
806 	rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
807 	rtl_write_word(rtlpriv, REG_RL, 0x0707);
808 	rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
809 	rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
810 	rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
811 	rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
812 	rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
813 	rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
814 	/* Aggregation threshold */
815 	if (rtlhal->macphymode == DUALMAC_DUALPHY)
816 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641);
817 	else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
818 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641);
819 	else
820 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
821 	rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
822 	rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
823 	rtlpci->reg_bcn_ctrl_val = 0x1f;
824 	rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
825 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
826 	rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
827 	rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
828 	rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
829 	/* For throughput */
830 	rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666);
831 	/* ACKTO for IOT issue. */
832 	rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
833 	/* Set Spec SIFS (used in NAV) */
834 	rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
835 	rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
836 	/* Set SIFS for CCK */
837 	rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
838 	/* Set SIFS for OFDM */
839 	rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
840 	/* Set Multicast Address. */
841 	rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
842 	rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
843 	switch (rtlpriv->phy.rf_type) {
844 	case RF_1T2R:
845 	case RF_1T1R:
846 		rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
847 		break;
848 	case RF_2T2R:
849 	case RF_2T2R_GREEN:
850 		rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
851 		break;
852 	}
853 }
854 
855 static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw)
856 {
857 	struct rtl_priv *rtlpriv = rtl_priv(hw);
858 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
859 
860 	rtl_write_byte(rtlpriv, 0x34b, 0x93);
861 	rtl_write_word(rtlpriv, 0x350, 0x870c);
862 	rtl_write_byte(rtlpriv, 0x352, 0x1);
863 	if (ppsc->support_backdoor)
864 		rtl_write_byte(rtlpriv, 0x349, 0x1b);
865 	else
866 		rtl_write_byte(rtlpriv, 0x349, 0x03);
867 	rtl_write_word(rtlpriv, 0x350, 0x2718);
868 	rtl_write_byte(rtlpriv, 0x352, 0x1);
869 }
870 
871 void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw)
872 {
873 	struct rtl_priv *rtlpriv = rtl_priv(hw);
874 	u8 sec_reg_value;
875 
876 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
877 		 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
878 		 rtlpriv->sec.pairwise_enc_algorithm,
879 		 rtlpriv->sec.group_enc_algorithm);
880 	if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
881 		RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
882 			 "not open hw encryption\n");
883 		return;
884 	}
885 	sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
886 	if (rtlpriv->sec.use_defaultkey) {
887 		sec_reg_value |= SCR_TXUSEDK;
888 		sec_reg_value |= SCR_RXUSEDK;
889 	}
890 	sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
891 	rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
892 	RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
893 		 "The SECR-value %x\n", sec_reg_value);
894 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
895 }
896 
897 int rtl92de_hw_init(struct ieee80211_hw *hw)
898 {
899 	struct rtl_priv *rtlpriv = rtl_priv(hw);
900 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
901 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
902 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
903 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
904 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
905 	bool rtstatus = true;
906 	u8 tmp_u1b;
907 	int i;
908 	int err;
909 	unsigned long flags;
910 
911 	rtlpci->being_init_adapter = true;
912 	rtlpci->init_ready = false;
913 	spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);
914 	/* we should do iqk after disable/enable */
915 	rtl92d_phy_reset_iqk_result(hw);
916 	/* rtlpriv->intf_ops->disable_aspm(hw); */
917 	rtstatus = _rtl92de_init_mac(hw);
918 	if (!rtstatus) {
919 		pr_err("Init MAC failed\n");
920 		err = 1;
921 		spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
922 		return err;
923 	}
924 	err = rtl92d_download_fw(hw);
925 	spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
926 	if (err) {
927 		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
928 			 "Failed to download FW. Init HW without FW..\n");
929 		return 1;
930 	}
931 	rtlhal->last_hmeboxnum = 0;
932 	rtlpriv->psc.fw_current_inpsmode = false;
933 
934 	tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
935 	tmp_u1b = tmp_u1b | 0x30;
936 	rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
937 
938 	if (rtlhal->earlymode_enable) {
939 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
940 			 "EarlyMode Enabled!!!\n");
941 
942 		tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0);
943 		tmp_u1b = tmp_u1b | 0x1f;
944 		rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b);
945 
946 		rtl_write_byte(rtlpriv, 0x4d3, 0x80);
947 
948 		tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
949 		tmp_u1b = tmp_u1b | 0x40;
950 		rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
951 	}
952 
953 	if (mac->rdg_en) {
954 		rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff);
955 		rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
956 		rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
957 	}
958 
959 	rtl92d_phy_mac_config(hw);
960 	/* because last function modify RCR, so we update
961 	 * rcr var here, or TP will unstable for receive_config
962 	 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
963 	 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
964 	rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
965 	rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
966 
967 	rtl92d_phy_bb_config(hw);
968 
969 	rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
970 	/* set before initialize RF */
971 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
972 
973 	/* config RF */
974 	rtl92d_phy_rf_config(hw);
975 
976 	/* After read predefined TXT, we must set BB/MAC/RF
977 	 * register as our requirement */
978 	/* After load BB,RF params,we need do more for 92D. */
979 	rtl92d_update_bbrf_configuration(hw);
980 	/* set default value after initialize RF,  */
981 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
982 	rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
983 			RF_CHNLBW, RFREG_OFFSET_MASK);
984 	rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
985 			RF_CHNLBW, RFREG_OFFSET_MASK);
986 
987 	/*---- Set CCK and OFDM Block "ON"----*/
988 	if (rtlhal->current_bandtype == BAND_ON_2_4G)
989 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
990 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
991 	if (rtlhal->interfaceindex == 0) {
992 		/* RFPGA0_ANALOGPARAMETER2: cck clock select,
993 		 *  set to 20MHz by default */
994 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
995 			      BIT(11), 3);
996 	} else {
997 		/* Mac1 */
998 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(11) |
999 			      BIT(10), 3);
1000 	}
1001 
1002 	_rtl92de_hw_configure(hw);
1003 
1004 	/* reset hw sec */
1005 	rtl_cam_reset_all_entry(hw);
1006 	rtl92de_enable_hw_security_config(hw);
1007 
1008 	/* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1009 	/* TX power index for different rate set. */
1010 	rtl92d_phy_get_hw_reg_originalvalue(hw);
1011 	rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
1012 
1013 	ppsc->rfpwr_state = ERFON;
1014 
1015 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1016 
1017 	_rtl92de_enable_aspm_back_door(hw);
1018 	/* rtlpriv->intf_ops->enable_aspm(hw); */
1019 
1020 	rtl92d_dm_init(hw);
1021 	rtlpci->being_init_adapter = false;
1022 
1023 	if (ppsc->rfpwr_state == ERFON) {
1024 		rtl92d_phy_lc_calibrate(hw);
1025 		/* 5G and 2.4G must wait sometime to let RF LO ready */
1026 		if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1027 			u32 tmp_rega;
1028 			for (i = 0; i < 10000; i++) {
1029 				udelay(MAX_STALL_TIME);
1030 
1031 				tmp_rega = rtl_get_rfreg(hw,
1032 						  (enum radio_path)RF90_PATH_A,
1033 						  0x2a, MASKDWORD);
1034 
1035 				if (((tmp_rega & BIT(11)) == BIT(11)))
1036 					break;
1037 			}
1038 			/* check that loop was successful. If not, exit now */
1039 			if (i == 10000) {
1040 				rtlpci->init_ready = false;
1041 				return 1;
1042 			}
1043 		}
1044 	}
1045 	rtlpci->init_ready = true;
1046 	return err;
1047 }
1048 
1049 static enum version_8192d _rtl92de_read_chip_version(struct ieee80211_hw *hw)
1050 {
1051 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1052 	enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1053 	u32 value32;
1054 
1055 	value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1056 	if (!(value32 & 0x000f0000)) {
1057 		version = VERSION_TEST_CHIP_92D_SINGLEPHY;
1058 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n");
1059 	} else {
1060 		version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1061 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n");
1062 	}
1063 	return version;
1064 }
1065 
1066 static int _rtl92de_set_media_status(struct ieee80211_hw *hw,
1067 				     enum nl80211_iftype type)
1068 {
1069 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1070 	u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1071 	enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1072 	u8 bcnfunc_enable;
1073 
1074 	bt_msr &= 0xfc;
1075 
1076 	if (type == NL80211_IFTYPE_UNSPECIFIED ||
1077 	    type == NL80211_IFTYPE_STATION) {
1078 		_rtl92de_stop_tx_beacon(hw);
1079 		_rtl92de_enable_bcn_sub_func(hw);
1080 	} else if (type == NL80211_IFTYPE_ADHOC ||
1081 		type == NL80211_IFTYPE_AP) {
1082 		_rtl92de_resume_tx_beacon(hw);
1083 		_rtl92de_disable_bcn_sub_func(hw);
1084 	} else {
1085 		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1086 			 "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1087 			 type);
1088 	}
1089 	bcnfunc_enable = rtl_read_byte(rtlpriv, REG_BCN_CTRL);
1090 	switch (type) {
1091 	case NL80211_IFTYPE_UNSPECIFIED:
1092 		bt_msr |= MSR_NOLINK;
1093 		ledaction = LED_CTL_LINK;
1094 		bcnfunc_enable &= 0xF7;
1095 		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1096 			 "Set Network type to NO LINK!\n");
1097 		break;
1098 	case NL80211_IFTYPE_ADHOC:
1099 		bt_msr |= MSR_ADHOC;
1100 		bcnfunc_enable |= 0x08;
1101 		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1102 			 "Set Network type to Ad Hoc!\n");
1103 		break;
1104 	case NL80211_IFTYPE_STATION:
1105 		bt_msr |= MSR_INFRA;
1106 		ledaction = LED_CTL_LINK;
1107 		bcnfunc_enable &= 0xF7;
1108 		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1109 			 "Set Network type to STA!\n");
1110 		break;
1111 	case NL80211_IFTYPE_AP:
1112 		bt_msr |= MSR_AP;
1113 		bcnfunc_enable |= 0x08;
1114 		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1115 			 "Set Network type to AP!\n");
1116 		break;
1117 	default:
1118 		pr_err("Network type %d not supported!\n", type);
1119 		return 1;
1120 	}
1121 	rtl_write_byte(rtlpriv, MSR, bt_msr);
1122 	rtlpriv->cfg->ops->led_control(hw, ledaction);
1123 	if ((bt_msr & MSR_MASK) == MSR_AP)
1124 		rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1125 	else
1126 		rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1127 	return 0;
1128 }
1129 
1130 void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1131 {
1132 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1133 	u32 reg_rcr;
1134 
1135 	if (rtlpriv->psc.rfpwr_state != ERFON)
1136 		return;
1137 
1138 	rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1139 
1140 	if (check_bssid) {
1141 		reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1142 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1143 		_rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
1144 	} else if (!check_bssid) {
1145 		reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1146 		_rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
1147 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1148 	}
1149 }
1150 
1151 int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1152 {
1153 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1154 
1155 	if (_rtl92de_set_media_status(hw, type))
1156 		return -EOPNOTSUPP;
1157 
1158 	/* check bssid */
1159 	if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1160 		if (type != NL80211_IFTYPE_AP)
1161 			rtl92de_set_check_bssid(hw, true);
1162 	} else {
1163 		rtl92de_set_check_bssid(hw, false);
1164 	}
1165 	return 0;
1166 }
1167 
1168 /* do iqk or reload iqk */
1169 /* windows just rtl92d_phy_reload_iqk_setting in set channel,
1170  * but it's very strict for time sequence so we add
1171  * rtl92d_phy_reload_iqk_setting here */
1172 void rtl92d_linked_set_reg(struct ieee80211_hw *hw)
1173 {
1174 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1175 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1176 	u8 indexforchannel;
1177 	u8 channel = rtlphy->current_channel;
1178 
1179 	indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
1180 	if (!rtlphy->iqk_matrix[indexforchannel].iqk_done) {
1181 		RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG,
1182 			 "Do IQK for channel:%d\n", channel);
1183 		rtl92d_phy_iq_calibrate(hw);
1184 	}
1185 }
1186 
1187 /* don't set REG_EDCA_BE_PARAM here because
1188  * mac80211 will send pkt when scan */
1189 void rtl92de_set_qos(struct ieee80211_hw *hw, int aci)
1190 {
1191 	rtl92d_dm_init_edca_turbo(hw);
1192 }
1193 
1194 void rtl92de_enable_interrupt(struct ieee80211_hw *hw)
1195 {
1196 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1197 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1198 
1199 	rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1200 	rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1201 }
1202 
1203 void rtl92de_disable_interrupt(struct ieee80211_hw *hw)
1204 {
1205 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1206 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1207 
1208 	rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1209 	rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1210 	synchronize_irq(rtlpci->pdev->irq);
1211 }
1212 
1213 static void _rtl92de_poweroff_adapter(struct ieee80211_hw *hw)
1214 {
1215 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1216 	u8 u1b_tmp;
1217 	unsigned long flags;
1218 
1219 	rtlpriv->intf_ops->enable_aspm(hw);
1220 	rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1221 	rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0);
1222 	rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0);
1223 
1224 	/* 0x20:value 05-->04 */
1225 	rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1226 
1227 	/*  ==== Reset digital sequence   ====== */
1228 	rtl92d_firmware_selfreset(hw);
1229 
1230 	/* f.   SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */
1231 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1232 
1233 	/* g.   MCUFWDL 0x80[1:0]=0 reset MCU ready status */
1234 	rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1235 
1236 	/*  ==== Pull GPIO PIN to balance level and LED control ====== */
1237 
1238 	/* h.     GPIO_PIN_CTRL 0x44[31:0]=0x000  */
1239 	rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1240 
1241 	/* i.    Value = GPIO_PIN_CTRL[7:0] */
1242 	u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1243 
1244 	/* j.    GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */
1245 	/* write external PIN level  */
1246 	rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL,
1247 			0x00FF0000 | (u1b_tmp << 8));
1248 
1249 	/* k.   GPIO_MUXCFG 0x42 [15:0] = 0x0780 */
1250 	rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1251 
1252 	/* l.   LEDCFG 0x4C[15:0] = 0x8080 */
1253 	rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1254 
1255 	/*  ==== Disable analog sequence === */
1256 
1257 	/* m.   AFE_PLL_CTRL[7:0] = 0x80  disable PLL */
1258 	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1259 
1260 	/* n.   SPS0_CTRL 0x11[7:0] = 0x22  enter PFM mode */
1261 	rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1262 
1263 	/* o.   AFE_XTAL_CTRL 0x24[7:0] = 0x0E  disable XTAL, if No BT COEX */
1264 	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1265 
1266 	/* p.   RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */
1267 	rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1268 
1269 	/*  ==== interface into suspend === */
1270 
1271 	/* q.   APS_FSMCO[15:8] = 0x58 PCIe suspend mode */
1272 	/* According to power document V11, we need to set this */
1273 	/* value as 0x18. Otherwise, we may not L0s sometimes. */
1274 	/* This indluences power consumption. Bases on SD1's test, */
1275 	/* set as 0x00 do not affect power current. And if it */
1276 	/* is set as 0x18, they had ever met auto load fail problem. */
1277 	rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1278 
1279 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1280 		 "In PowerOff,reg0x%x=%X\n",
1281 		 REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL));
1282 	/* r.   Note: for PCIe interface, PON will not turn */
1283 	/* off m-bias and BandGap in PCIe suspend mode.  */
1284 
1285 	/* 0x17[7] 1b': power off in process  0b' : power off over */
1286 	if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
1287 		spin_lock_irqsave(&globalmutex_power, flags);
1288 		u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
1289 		u1b_tmp &= (~BIT(7));
1290 		rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp);
1291 		spin_unlock_irqrestore(&globalmutex_power, flags);
1292 	}
1293 
1294 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n");
1295 }
1296 
1297 void rtl92de_card_disable(struct ieee80211_hw *hw)
1298 {
1299 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1300 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1301 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1302 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1303 	enum nl80211_iftype opmode;
1304 
1305 	mac->link_state = MAC80211_NOLINK;
1306 	opmode = NL80211_IFTYPE_UNSPECIFIED;
1307 	_rtl92de_set_media_status(hw, opmode);
1308 
1309 	if (rtlpci->driver_is_goingto_unload ||
1310 	    ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1311 		rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1312 	RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1313 	/* Power sequence for each MAC. */
1314 	/* a. stop tx DMA  */
1315 	/* b. close RF */
1316 	/* c. clear rx buf */
1317 	/* d. stop rx DMA */
1318 	/* e.  reset MAC */
1319 
1320 	/* a. stop tx DMA */
1321 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1322 	udelay(50);
1323 
1324 	/* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
1325 
1326 	/* c. ========RF OFF sequence==========  */
1327 	/* 0x88c[23:20] = 0xf. */
1328 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1329 	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1330 
1331 	/* APSD_CTRL 0x600[7:0] = 0x40 */
1332 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1333 
1334 	/* Close antenna 0,0xc04,0xd04 */
1335 	rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0);
1336 	rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0);
1337 
1338 	/*  SYS_FUNC_EN 0x02[7:0] = 0xE2   reset BB state machine */
1339 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1340 
1341 	/* Mac0 can not do Global reset. Mac1 can do. */
1342 	/* SYS_FUNC_EN 0x02[7:0] = 0xE0  reset BB state machine  */
1343 	if (rtlpriv->rtlhal.interfaceindex == 1)
1344 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1345 	udelay(50);
1346 
1347 	/* d.  stop tx/rx dma before disable REG_CR (0x100) to fix */
1348 	/* dma hang issue when disable/enable device.  */
1349 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
1350 	udelay(50);
1351 	rtl_write_byte(rtlpriv, REG_CR, 0x0);
1352 	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n");
1353 	if (rtl92d_phy_check_poweroff(hw))
1354 		_rtl92de_poweroff_adapter(hw);
1355 	return;
1356 }
1357 
1358 void rtl92de_interrupt_recognized(struct ieee80211_hw *hw,
1359 				  u32 *p_inta, u32 *p_intb)
1360 {
1361 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1362 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1363 
1364 	*p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1365 	rtl_write_dword(rtlpriv, ISR, *p_inta);
1366 
1367 	/*
1368 	 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1369 	 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1370 	 */
1371 }
1372 
1373 void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw)
1374 {
1375 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1376 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1377 	u16 bcn_interval, atim_window;
1378 
1379 	bcn_interval = mac->beacon_interval;
1380 	atim_window = 2;
1381 	/*rtl92de_disable_interrupt(hw);  */
1382 	rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1383 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1384 	rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1385 	rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20);
1386 	if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
1387 		rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30);
1388 	else
1389 		rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20);
1390 	rtl_write_byte(rtlpriv, 0x606, 0x30);
1391 }
1392 
1393 void rtl92de_set_beacon_interval(struct ieee80211_hw *hw)
1394 {
1395 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1396 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1397 	u16 bcn_interval = mac->beacon_interval;
1398 
1399 	RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1400 		 "beacon_interval:%d\n", bcn_interval);
1401 	/* rtl92de_disable_interrupt(hw); */
1402 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1403 	/* rtl92de_enable_interrupt(hw); */
1404 }
1405 
1406 void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw,
1407 				   u32 add_msr, u32 rm_msr)
1408 {
1409 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1410 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1411 
1412 	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1413 		 add_msr, rm_msr);
1414 	if (add_msr)
1415 		rtlpci->irq_mask[0] |= add_msr;
1416 	if (rm_msr)
1417 		rtlpci->irq_mask[0] &= (~rm_msr);
1418 	rtl92de_disable_interrupt(hw);
1419 	rtl92de_enable_interrupt(hw);
1420 }
1421 
1422 static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo,
1423 				 u8 *rom_content, bool autoLoadfail)
1424 {
1425 	u32 rfpath, eeaddr, group, offset1, offset2;
1426 	u8 i;
1427 
1428 	memset(pwrinfo, 0, sizeof(struct txpower_info));
1429 	if (autoLoadfail) {
1430 		for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1431 			for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1432 				if (group < CHANNEL_GROUP_MAX_2G) {
1433 					pwrinfo->cck_index[rfpath][group] =
1434 					    EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1435 					pwrinfo->ht40_1sindex[rfpath][group] =
1436 					    EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1437 				} else {
1438 					pwrinfo->ht40_1sindex[rfpath][group] =
1439 					    EEPROM_DEFAULT_TXPOWERLEVEL_5G;
1440 				}
1441 				pwrinfo->ht40_2sindexdiff[rfpath][group] =
1442 				    EEPROM_DEFAULT_HT40_2SDIFF;
1443 				pwrinfo->ht20indexdiff[rfpath][group] =
1444 				    EEPROM_DEFAULT_HT20_DIFF;
1445 				pwrinfo->ofdmindexdiff[rfpath][group] =
1446 				    EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1447 				pwrinfo->ht40maxoffset[rfpath][group] =
1448 				    EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1449 				pwrinfo->ht20maxoffset[rfpath][group] =
1450 				    EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1451 			}
1452 		}
1453 		for (i = 0; i < 3; i++) {
1454 			pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1455 			pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1456 		}
1457 		return;
1458 	}
1459 
1460 	/* Maybe autoload OK,buf the tx power index value is not filled.
1461 	 * If we find it, we set it to default value. */
1462 	for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1463 		for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) {
1464 			eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3)
1465 				 + group;
1466 			pwrinfo->cck_index[rfpath][group] =
1467 					(rom_content[eeaddr] == 0xFF) ?
1468 					     (eeaddr > 0x7B ?
1469 					     EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1470 					     EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1471 					     rom_content[eeaddr];
1472 		}
1473 	}
1474 	for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1475 		for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1476 			offset1 = group / 3;
1477 			offset2 = group % 3;
1478 			eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) +
1479 			    offset2 + offset1 * 21;
1480 			pwrinfo->ht40_1sindex[rfpath][group] =
1481 			    (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ?
1482 					     EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1483 					     EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1484 						 rom_content[eeaddr];
1485 		}
1486 	}
1487 	/* These just for 92D efuse offset. */
1488 	for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1489 		for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1490 			int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G;
1491 
1492 			offset1 = group / 3;
1493 			offset2 = group % 3;
1494 
1495 			if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF)
1496 				pwrinfo->ht40_2sindexdiff[rfpath][group] =
1497 				    (rom_content[base1 +
1498 				     offset2 + offset1 * 21] >> (rfpath * 4))
1499 				     & 0xF;
1500 			else
1501 				pwrinfo->ht40_2sindexdiff[rfpath][group] =
1502 				    EEPROM_DEFAULT_HT40_2SDIFF;
1503 			if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2
1504 			    + offset1 * 21] != 0xFF)
1505 				pwrinfo->ht20indexdiff[rfpath][group] =
1506 				    (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G
1507 				    + offset2 + offset1 * 21] >> (rfpath * 4))
1508 				    & 0xF;
1509 			else
1510 				pwrinfo->ht20indexdiff[rfpath][group] =
1511 				    EEPROM_DEFAULT_HT20_DIFF;
1512 			if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2
1513 			    + offset1 * 21] != 0xFF)
1514 				pwrinfo->ofdmindexdiff[rfpath][group] =
1515 				    (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G
1516 				     + offset2 + offset1 * 21] >> (rfpath * 4))
1517 				     & 0xF;
1518 			else
1519 				pwrinfo->ofdmindexdiff[rfpath][group] =
1520 				    EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1521 			if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2
1522 			    + offset1 * 21] != 0xFF)
1523 				pwrinfo->ht40maxoffset[rfpath][group] =
1524 				    (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G
1525 				    + offset2 + offset1 * 21] >> (rfpath * 4))
1526 				    & 0xF;
1527 			else
1528 				pwrinfo->ht40maxoffset[rfpath][group] =
1529 				    EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1530 			if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2
1531 			    + offset1 * 21] != 0xFF)
1532 				pwrinfo->ht20maxoffset[rfpath][group] =
1533 				    (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G +
1534 				     offset2 + offset1 * 21] >> (rfpath * 4)) &
1535 				     0xF;
1536 			else
1537 				pwrinfo->ht20maxoffset[rfpath][group] =
1538 				    EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1539 		}
1540 	}
1541 	if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) {
1542 		/* 5GL */
1543 		pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F;
1544 		pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F;
1545 		/* 5GM */
1546 		pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F;
1547 		pwrinfo->tssi_b[1] =
1548 		    (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 |
1549 		    (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2;
1550 		/* 5GH */
1551 		pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] &
1552 				      0xF0) >> 4 |
1553 		    (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4;
1554 		pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] &
1555 				      0xFC) >> 2;
1556 	} else {
1557 		for (i = 0; i < 3; i++) {
1558 			pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1559 			pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1560 		}
1561 	}
1562 }
1563 
1564 static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw,
1565 				       bool autoload_fail, u8 *hwinfo)
1566 {
1567 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1568 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1569 	struct txpower_info pwrinfo;
1570 	u8 tempval[2], i, pwr, diff;
1571 	u32 ch, rfPath, group;
1572 
1573 	_rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail);
1574 	if (!autoload_fail) {
1575 		/* bit0~2 */
1576 		rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7);
1577 		rtlefuse->eeprom_thermalmeter =
1578 			 hwinfo[EEPROM_THERMAL_METER] & 0x1f;
1579 		rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K];
1580 		tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03;
1581 		tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2;
1582 		rtlefuse->txpwr_fromeprom = true;
1583 		if (IS_92D_D_CUT(rtlpriv->rtlhal.version) ||
1584 		    IS_92D_E_CUT(rtlpriv->rtlhal.version)) {
1585 			rtlefuse->internal_pa_5g[0] =
1586 				!((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6);
1587 			rtlefuse->internal_pa_5g[1] =
1588 				!((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6);
1589 			RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1590 				 "Is D cut,Internal PA0 %d Internal PA1 %d\n",
1591 				 rtlefuse->internal_pa_5g[0],
1592 				 rtlefuse->internal_pa_5g[1]);
1593 		}
1594 		rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6];
1595 		rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7];
1596 	} else {
1597 		rtlefuse->eeprom_regulatory = 0;
1598 		rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1599 		rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP;
1600 		tempval[0] = tempval[1] = 3;
1601 	}
1602 
1603 	/* Use default value to fill parameters if
1604 	 * efuse is not filled on some place. */
1605 
1606 	/* ThermalMeter from EEPROM */
1607 	if (rtlefuse->eeprom_thermalmeter < 0x06 ||
1608 	    rtlefuse->eeprom_thermalmeter > 0x1c)
1609 		rtlefuse->eeprom_thermalmeter = 0x12;
1610 	rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1611 
1612 	/* check XTAL_K */
1613 	if (rtlefuse->crystalcap == 0xFF)
1614 		rtlefuse->crystalcap = 0;
1615 	if (rtlefuse->eeprom_regulatory > 3)
1616 		rtlefuse->eeprom_regulatory = 0;
1617 
1618 	for (i = 0; i < 2; i++) {
1619 		switch (tempval[i]) {
1620 		case 0:
1621 			tempval[i] = 5;
1622 			break;
1623 		case 1:
1624 			tempval[i] = 4;
1625 			break;
1626 		case 2:
1627 			tempval[i] = 3;
1628 			break;
1629 		case 3:
1630 		default:
1631 			tempval[i] = 0;
1632 			break;
1633 		}
1634 	}
1635 
1636 	rtlefuse->delta_iqk = tempval[0];
1637 	if (tempval[1] > 0)
1638 		rtlefuse->delta_lck = tempval[1] - 1;
1639 	if (rtlefuse->eeprom_c9 == 0xFF)
1640 		rtlefuse->eeprom_c9 = 0x00;
1641 	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1642 		 "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1643 	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1644 		 "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1645 	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1646 		 "CrystalCap = 0x%x\n", rtlefuse->crystalcap);
1647 	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1648 		 "Delta_IQK = 0x%x Delta_LCK = 0x%x\n",
1649 		 rtlefuse->delta_iqk, rtlefuse->delta_lck);
1650 
1651 	for (rfPath = 0; rfPath < RF6052_MAX_PATH; rfPath++) {
1652 		for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1653 			group = rtl92d_get_chnlgroup_fromarray((u8) ch);
1654 			if (ch < CHANNEL_MAX_NUMBER_2G)
1655 				rtlefuse->txpwrlevel_cck[rfPath][ch] =
1656 				    pwrinfo.cck_index[rfPath][group];
1657 			rtlefuse->txpwrlevel_ht40_1s[rfPath][ch] =
1658 				    pwrinfo.ht40_1sindex[rfPath][group];
1659 			rtlefuse->txpwr_ht20diff[rfPath][ch] =
1660 				    pwrinfo.ht20indexdiff[rfPath][group];
1661 			rtlefuse->txpwr_legacyhtdiff[rfPath][ch] =
1662 				    pwrinfo.ofdmindexdiff[rfPath][group];
1663 			rtlefuse->pwrgroup_ht20[rfPath][ch] =
1664 				    pwrinfo.ht20maxoffset[rfPath][group];
1665 			rtlefuse->pwrgroup_ht40[rfPath][ch] =
1666 				    pwrinfo.ht40maxoffset[rfPath][group];
1667 			pwr = pwrinfo.ht40_1sindex[rfPath][group];
1668 			diff = pwrinfo.ht40_2sindexdiff[rfPath][group];
1669 			rtlefuse->txpwrlevel_ht40_2s[rfPath][ch] =
1670 				    (pwr > diff) ? (pwr - diff) : 0;
1671 		}
1672 	}
1673 }
1674 
1675 static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw,
1676 					       u8 *content)
1677 {
1678 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1679 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1680 	u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION];
1681 
1682 	if (macphy_crvalue & BIT(3)) {
1683 		rtlhal->macphymode = SINGLEMAC_SINGLEPHY;
1684 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1685 			 "MacPhyMode SINGLEMAC_SINGLEPHY\n");
1686 	} else {
1687 		rtlhal->macphymode = DUALMAC_DUALPHY;
1688 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1689 			 "MacPhyMode DUALMAC_DUALPHY\n");
1690 	}
1691 }
1692 
1693 static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw,
1694 						  u8 *content)
1695 {
1696 	_rtl92de_read_macphymode_from_prom(hw, content);
1697 	rtl92d_phy_config_macphymode(hw);
1698 	rtl92d_phy_config_macphymode_info(hw);
1699 }
1700 
1701 static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw)
1702 {
1703 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1704 	enum version_8192d chipver = rtlpriv->rtlhal.version;
1705 	u8 cutvalue[2];
1706 	u16 chipvalue;
1707 
1708 	rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H,
1709 					   &cutvalue[1]);
1710 	rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L,
1711 					   &cutvalue[0]);
1712 	chipvalue = (cutvalue[1] << 8) | cutvalue[0];
1713 	switch (chipvalue) {
1714 	case 0xAA55:
1715 		chipver |= CHIP_92D_C_CUT;
1716 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n");
1717 		break;
1718 	case 0x9966:
1719 		chipver |= CHIP_92D_D_CUT;
1720 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n");
1721 		break;
1722 	case 0xCC33:
1723 		chipver |= CHIP_92D_E_CUT;
1724 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n");
1725 		break;
1726 	default:
1727 		chipver |= CHIP_92D_D_CUT;
1728 		pr_err("Unknown CUT!\n");
1729 		break;
1730 	}
1731 	rtlpriv->rtlhal.version = chipver;
1732 }
1733 
1734 static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw)
1735 {
1736 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1737 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1738 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1739 	int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1740 			EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D,
1741 			EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1742 			COUNTRY_CODE_WORLD_WIDE_13};
1743 	int i;
1744 	u16 usvalue;
1745 	u8 *hwinfo;
1746 
1747 	hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1748 	if (!hwinfo)
1749 		return;
1750 
1751 	if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1752 		goto exit;
1753 
1754 	_rtl92de_efuse_update_chip_version(hw);
1755 	_rtl92de_read_macphymode_and_bandtype(hw, hwinfo);
1756 
1757 	/* Read Permanent MAC address for 2nd interface */
1758 	if (rtlhal->interfaceindex != 0) {
1759 		for (i = 0; i < 6; i += 2) {
1760 			usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i];
1761 			*((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1762 		}
1763 	}
1764 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR,
1765 				      rtlefuse->dev_addr);
1766 	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1767 	_rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo);
1768 
1769 	/* Read Channel Plan */
1770 	switch (rtlhal->bandset) {
1771 	case BAND_ON_2_4G:
1772 		rtlefuse->channel_plan = COUNTRY_CODE_TELEC;
1773 		break;
1774 	case BAND_ON_5G:
1775 		rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1776 		break;
1777 	case BAND_ON_BOTH:
1778 		rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1779 		break;
1780 	default:
1781 		rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1782 		break;
1783 	}
1784 	rtlefuse->txpwr_fromeprom = true;
1785 exit:
1786 	kfree(hwinfo);
1787 }
1788 
1789 void rtl92de_read_eeprom_info(struct ieee80211_hw *hw)
1790 {
1791 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1792 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1793 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1794 	u8 tmp_u1b;
1795 
1796 	rtlhal->version = _rtl92de_read_chip_version(hw);
1797 	tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1798 	rtlefuse->autoload_status = tmp_u1b;
1799 	if (tmp_u1b & BIT(4)) {
1800 		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1801 		rtlefuse->epromtype = EEPROM_93C46;
1802 	} else {
1803 		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1804 		rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1805 	}
1806 	if (tmp_u1b & BIT(5)) {
1807 		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1808 
1809 		rtlefuse->autoload_failflag = false;
1810 		_rtl92de_read_adapter_info(hw);
1811 	} else {
1812 		pr_err("Autoload ERR!!\n");
1813 	}
1814 	return;
1815 }
1816 
1817 static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw,
1818 					  struct ieee80211_sta *sta)
1819 {
1820 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1821 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1822 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1823 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1824 	u32 ratr_value;
1825 	u8 ratr_index = 0;
1826 	u8 nmode = mac->ht_enable;
1827 	u8 mimo_ps = IEEE80211_SMPS_OFF;
1828 	u16 shortgi_rate;
1829 	u32 tmp_ratr_value;
1830 	u8 curtxbw_40mhz = mac->bw_40;
1831 	u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1832 							1 : 0;
1833 	u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1834 							1 : 0;
1835 	enum wireless_mode wirelessmode = mac->mode;
1836 
1837 	if (rtlhal->current_bandtype == BAND_ON_5G)
1838 		ratr_value = sta->supp_rates[1] << 4;
1839 	else
1840 		ratr_value = sta->supp_rates[0];
1841 	ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1842 		       sta->ht_cap.mcs.rx_mask[0] << 12);
1843 	switch (wirelessmode) {
1844 	case WIRELESS_MODE_A:
1845 		ratr_value &= 0x00000FF0;
1846 		break;
1847 	case WIRELESS_MODE_B:
1848 		if (ratr_value & 0x0000000c)
1849 			ratr_value &= 0x0000000d;
1850 		else
1851 			ratr_value &= 0x0000000f;
1852 		break;
1853 	case WIRELESS_MODE_G:
1854 		ratr_value &= 0x00000FF5;
1855 		break;
1856 	case WIRELESS_MODE_N_24G:
1857 	case WIRELESS_MODE_N_5G:
1858 		nmode = 1;
1859 		if (mimo_ps == IEEE80211_SMPS_STATIC) {
1860 			ratr_value &= 0x0007F005;
1861 		} else {
1862 			u32 ratr_mask;
1863 
1864 			if (get_rf_type(rtlphy) == RF_1T2R ||
1865 			    get_rf_type(rtlphy) == RF_1T1R) {
1866 				ratr_mask = 0x000ff005;
1867 			} else {
1868 				ratr_mask = 0x0f0ff005;
1869 			}
1870 
1871 			ratr_value &= ratr_mask;
1872 		}
1873 		break;
1874 	default:
1875 		if (rtlphy->rf_type == RF_1T2R)
1876 			ratr_value &= 0x000ff0ff;
1877 		else
1878 			ratr_value &= 0x0f0ff0ff;
1879 
1880 		break;
1881 	}
1882 	ratr_value &= 0x0FFFFFFF;
1883 	if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
1884 	    (!curtxbw_40mhz && curshortgi_20mhz))) {
1885 		ratr_value |= 0x10000000;
1886 		tmp_ratr_value = (ratr_value >> 12);
1887 		for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1888 			if ((1 << shortgi_rate) & tmp_ratr_value)
1889 				break;
1890 		}
1891 		shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1892 		    (shortgi_rate << 4) | (shortgi_rate);
1893 	}
1894 	rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1895 	RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1896 		 rtl_read_dword(rtlpriv, REG_ARFR0));
1897 }
1898 
1899 static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw,
1900 		struct ieee80211_sta *sta, u8 rssi_level)
1901 {
1902 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1903 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1904 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1905 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1906 	struct rtl_sta_info *sta_entry = NULL;
1907 	u32 ratr_bitmap;
1908 	u8 ratr_index;
1909 	u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
1910 	u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1911 							1 : 0;
1912 	u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1913 							1 : 0;
1914 	enum wireless_mode wirelessmode = 0;
1915 	bool shortgi = false;
1916 	u32 value[2];
1917 	u8 macid = 0;
1918 	u8 mimo_ps = IEEE80211_SMPS_OFF;
1919 
1920 	sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1921 	mimo_ps = sta_entry->mimo_ps;
1922 	wirelessmode = sta_entry->wireless_mode;
1923 	if (mac->opmode == NL80211_IFTYPE_STATION)
1924 		curtxbw_40mhz = mac->bw_40;
1925 	else if (mac->opmode == NL80211_IFTYPE_AP ||
1926 		mac->opmode == NL80211_IFTYPE_ADHOC)
1927 		macid = sta->aid + 1;
1928 
1929 	if (rtlhal->current_bandtype == BAND_ON_5G)
1930 		ratr_bitmap = sta->supp_rates[1] << 4;
1931 	else
1932 		ratr_bitmap = sta->supp_rates[0];
1933 	ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1934 			sta->ht_cap.mcs.rx_mask[0] << 12);
1935 	switch (wirelessmode) {
1936 	case WIRELESS_MODE_B:
1937 		ratr_index = RATR_INX_WIRELESS_B;
1938 		if (ratr_bitmap & 0x0000000c)
1939 			ratr_bitmap &= 0x0000000d;
1940 		else
1941 			ratr_bitmap &= 0x0000000f;
1942 		break;
1943 	case WIRELESS_MODE_G:
1944 		ratr_index = RATR_INX_WIRELESS_GB;
1945 
1946 		if (rssi_level == 1)
1947 			ratr_bitmap &= 0x00000f00;
1948 		else if (rssi_level == 2)
1949 			ratr_bitmap &= 0x00000ff0;
1950 		else
1951 			ratr_bitmap &= 0x00000ff5;
1952 		break;
1953 	case WIRELESS_MODE_A:
1954 		ratr_index = RATR_INX_WIRELESS_G;
1955 		ratr_bitmap &= 0x00000ff0;
1956 		break;
1957 	case WIRELESS_MODE_N_24G:
1958 	case WIRELESS_MODE_N_5G:
1959 		if (wirelessmode == WIRELESS_MODE_N_24G)
1960 			ratr_index = RATR_INX_WIRELESS_NGB;
1961 		else
1962 			ratr_index = RATR_INX_WIRELESS_NG;
1963 		if (mimo_ps == IEEE80211_SMPS_STATIC) {
1964 			if (rssi_level == 1)
1965 				ratr_bitmap &= 0x00070000;
1966 			else if (rssi_level == 2)
1967 				ratr_bitmap &= 0x0007f000;
1968 			else
1969 				ratr_bitmap &= 0x0007f005;
1970 		} else {
1971 			if (rtlphy->rf_type == RF_1T2R ||
1972 			    rtlphy->rf_type == RF_1T1R) {
1973 				if (curtxbw_40mhz) {
1974 					if (rssi_level == 1)
1975 						ratr_bitmap &= 0x000f0000;
1976 					else if (rssi_level == 2)
1977 						ratr_bitmap &= 0x000ff000;
1978 					else
1979 						ratr_bitmap &= 0x000ff015;
1980 				} else {
1981 					if (rssi_level == 1)
1982 						ratr_bitmap &= 0x000f0000;
1983 					else if (rssi_level == 2)
1984 						ratr_bitmap &= 0x000ff000;
1985 					else
1986 						ratr_bitmap &= 0x000ff005;
1987 				}
1988 			} else {
1989 				if (curtxbw_40mhz) {
1990 					if (rssi_level == 1)
1991 						ratr_bitmap &= 0x0f0f0000;
1992 					else if (rssi_level == 2)
1993 						ratr_bitmap &= 0x0f0ff000;
1994 					else
1995 						ratr_bitmap &= 0x0f0ff015;
1996 				} else {
1997 					if (rssi_level == 1)
1998 						ratr_bitmap &= 0x0f0f0000;
1999 					else if (rssi_level == 2)
2000 						ratr_bitmap &= 0x0f0ff000;
2001 					else
2002 						ratr_bitmap &= 0x0f0ff005;
2003 				}
2004 			}
2005 		}
2006 		if ((curtxbw_40mhz && curshortgi_40mhz) ||
2007 		    (!curtxbw_40mhz && curshortgi_20mhz)) {
2008 
2009 			if (macid == 0)
2010 				shortgi = true;
2011 			else if (macid == 1)
2012 				shortgi = false;
2013 		}
2014 		break;
2015 	default:
2016 		ratr_index = RATR_INX_WIRELESS_NGB;
2017 
2018 		if (rtlphy->rf_type == RF_1T2R)
2019 			ratr_bitmap &= 0x000ff0ff;
2020 		else
2021 			ratr_bitmap &= 0x0f0ff0ff;
2022 		break;
2023 	}
2024 
2025 	value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28);
2026 	value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2027 	RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2028 		 "ratr_bitmap :%x value0:%x value1:%x\n",
2029 		 ratr_bitmap, value[0], value[1]);
2030 	rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value);
2031 	if (macid != 0)
2032 		sta_entry->ratr_index = ratr_index;
2033 }
2034 
2035 void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw,
2036 		struct ieee80211_sta *sta, u8 rssi_level)
2037 {
2038 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2039 
2040 	if (rtlpriv->dm.useramask)
2041 		rtl92de_update_hal_rate_mask(hw, sta, rssi_level);
2042 	else
2043 		rtl92de_update_hal_rate_table(hw, sta);
2044 }
2045 
2046 void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw)
2047 {
2048 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2049 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2050 	u16 sifs_timer;
2051 
2052 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2053 				      &mac->slot_time);
2054 	if (!mac->ht_enable)
2055 		sifs_timer = 0x0a0a;
2056 	else
2057 		sifs_timer = 0x1010;
2058 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2059 }
2060 
2061 bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2062 {
2063 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2064 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2065 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2066 	enum rf_pwrstate e_rfpowerstate_toset;
2067 	u8 u1tmp;
2068 	bool actuallyset = false;
2069 	unsigned long flag;
2070 
2071 	if (rtlpci->being_init_adapter)
2072 		return false;
2073 	if (ppsc->swrf_processing)
2074 		return false;
2075 	spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2076 	if (ppsc->rfchange_inprogress) {
2077 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2078 		return false;
2079 	} else {
2080 		ppsc->rfchange_inprogress = true;
2081 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2082 	}
2083 	rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2084 			  REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2085 	u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2086 	e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2087 	if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2088 		RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2089 			 "GPIOChangeRF  - HW Radio ON, RF ON\n");
2090 		e_rfpowerstate_toset = ERFON;
2091 		ppsc->hwradiooff = false;
2092 		actuallyset = true;
2093 	} else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2094 		RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2095 			 "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2096 		e_rfpowerstate_toset = ERFOFF;
2097 		ppsc->hwradiooff = true;
2098 		actuallyset = true;
2099 	}
2100 	if (actuallyset) {
2101 		spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2102 		ppsc->rfchange_inprogress = false;
2103 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2104 	} else {
2105 		if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2106 			RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2107 		spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2108 		ppsc->rfchange_inprogress = false;
2109 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2110 	}
2111 	*valid = 1;
2112 	return !ppsc->hwradiooff;
2113 }
2114 
2115 void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index,
2116 		     u8 *p_macaddr, bool is_group, u8 enc_algo,
2117 		     bool is_wepkey, bool clear_all)
2118 {
2119 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2120 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2121 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2122 	u8 *macaddr = p_macaddr;
2123 	u32 entry_id;
2124 	bool is_pairwise = false;
2125 	static u8 cam_const_addr[4][6] = {
2126 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2127 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2128 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2129 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2130 	};
2131 	static u8 cam_const_broad[] = {
2132 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2133 	};
2134 
2135 	if (clear_all) {
2136 		u8 idx;
2137 		u8 cam_offset = 0;
2138 		u8 clear_number = 5;
2139 		RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2140 		for (idx = 0; idx < clear_number; idx++) {
2141 			rtl_cam_mark_invalid(hw, cam_offset + idx);
2142 			rtl_cam_empty_entry(hw, cam_offset + idx);
2143 
2144 			if (idx < 5) {
2145 				memset(rtlpriv->sec.key_buf[idx], 0,
2146 				       MAX_KEY_LEN);
2147 				rtlpriv->sec.key_len[idx] = 0;
2148 			}
2149 		}
2150 	} else {
2151 		switch (enc_algo) {
2152 		case WEP40_ENCRYPTION:
2153 			enc_algo = CAM_WEP40;
2154 			break;
2155 		case WEP104_ENCRYPTION:
2156 			enc_algo = CAM_WEP104;
2157 			break;
2158 		case TKIP_ENCRYPTION:
2159 			enc_algo = CAM_TKIP;
2160 			break;
2161 		case AESCCMP_ENCRYPTION:
2162 			enc_algo = CAM_AES;
2163 			break;
2164 		default:
2165 			pr_err("switch case %#x not processed\n",
2166 			       enc_algo);
2167 			enc_algo = CAM_TKIP;
2168 			break;
2169 		}
2170 		if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2171 			macaddr = cam_const_addr[key_index];
2172 			entry_id = key_index;
2173 		} else {
2174 			if (is_group) {
2175 				macaddr = cam_const_broad;
2176 				entry_id = key_index;
2177 			} else {
2178 				if (mac->opmode == NL80211_IFTYPE_AP) {
2179 					entry_id = rtl_cam_get_free_entry(hw,
2180 								 p_macaddr);
2181 					if (entry_id >=  TOTAL_CAM_ENTRY) {
2182 						pr_err("Can not find free hw security cam entry\n");
2183 						return;
2184 					}
2185 				} else {
2186 					entry_id = CAM_PAIRWISE_KEY_POSITION;
2187 				}
2188 				key_index = PAIRWISE_KEYIDX;
2189 				is_pairwise = true;
2190 			}
2191 		}
2192 		if (rtlpriv->sec.key_len[key_index] == 0) {
2193 			RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2194 				 "delete one entry, entry_id is %d\n",
2195 				 entry_id);
2196 			if (mac->opmode == NL80211_IFTYPE_AP)
2197 				rtl_cam_del_entry(hw, p_macaddr);
2198 			rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2199 		} else {
2200 			RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2201 				 "The insert KEY length is %d\n",
2202 				 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2203 			RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2204 				 "The insert KEY is %x %x\n",
2205 				 rtlpriv->sec.key_buf[0][0],
2206 				 rtlpriv->sec.key_buf[0][1]);
2207 			RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2208 				 "add one entry\n");
2209 			if (is_pairwise) {
2210 				RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2211 					      "Pairwise Key content",
2212 					      rtlpriv->sec.pairwise_key,
2213 					      rtlpriv->
2214 					      sec.key_len[PAIRWISE_KEYIDX]);
2215 				RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2216 					 "set Pairwise key\n");
2217 				rtl_cam_add_one_entry(hw, macaddr, key_index,
2218 						      entry_id, enc_algo,
2219 						      CAM_CONFIG_NO_USEDK,
2220 						      rtlpriv->
2221 						      sec.key_buf[key_index]);
2222 			} else {
2223 				RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2224 					 "set group key\n");
2225 				if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2226 					rtl_cam_add_one_entry(hw,
2227 						rtlefuse->dev_addr,
2228 						PAIRWISE_KEYIDX,
2229 						CAM_PAIRWISE_KEY_POSITION,
2230 						enc_algo, CAM_CONFIG_NO_USEDK,
2231 						rtlpriv->sec.key_buf[entry_id]);
2232 				}
2233 				rtl_cam_add_one_entry(hw, macaddr, key_index,
2234 						entry_id, enc_algo,
2235 						CAM_CONFIG_NO_USEDK,
2236 						rtlpriv->sec.key_buf
2237 						[entry_id]);
2238 			}
2239 		}
2240 	}
2241 }
2242 
2243 void rtl92de_suspend(struct ieee80211_hw *hw)
2244 {
2245 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2246 
2247 	rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv,
2248 		REG_MAC_PHY_CTRL_NORMAL);
2249 }
2250 
2251 void rtl92de_resume(struct ieee80211_hw *hw)
2252 {
2253 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2254 
2255 	rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL,
2256 		       rtlpriv->rtlhal.macphyctl_reg);
2257 }
2258