1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../regd.h" 30 #include "../cam.h" 31 #include "../ps.h" 32 #include "../pci.h" 33 #include "reg.h" 34 #include "def.h" 35 #include "phy.h" 36 #include "dm.h" 37 #include "fw.h" 38 #include "led.h" 39 #include "sw.h" 40 #include "hw.h" 41 42 u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset, u8 direct) 43 { 44 struct rtl_priv *rtlpriv = rtl_priv(hw); 45 u32 value; 46 47 rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC)); 48 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct); 49 udelay(10); 50 value = rtl_read_dword(rtlpriv, REG_DBI_RDATA); 51 return value; 52 } 53 54 void rtl92de_write_dword_dbi(struct ieee80211_hw *hw, 55 u16 offset, u32 value, u8 direct) 56 { 57 struct rtl_priv *rtlpriv = rtl_priv(hw); 58 59 rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000)); 60 rtl_write_dword(rtlpriv, REG_DBI_WDATA, value); 61 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct); 62 } 63 64 static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 65 u8 set_bits, u8 clear_bits) 66 { 67 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 68 struct rtl_priv *rtlpriv = rtl_priv(hw); 69 70 rtlpci->reg_bcn_ctrl_val |= set_bits; 71 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 72 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); 73 } 74 75 static void _rtl92de_stop_tx_beacon(struct ieee80211_hw *hw) 76 { 77 struct rtl_priv *rtlpriv = rtl_priv(hw); 78 u8 tmp1byte; 79 80 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 81 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 82 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); 83 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 84 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 85 tmp1byte &= ~(BIT(0)); 86 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 87 } 88 89 static void _rtl92de_resume_tx_beacon(struct ieee80211_hw *hw) 90 { 91 struct rtl_priv *rtlpriv = rtl_priv(hw); 92 u8 tmp1byte; 93 94 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 95 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 96 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); 97 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 98 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 99 tmp1byte |= BIT(0); 100 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 101 } 102 103 static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw) 104 { 105 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1)); 106 } 107 108 static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw) 109 { 110 _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0); 111 } 112 113 void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 114 { 115 struct rtl_priv *rtlpriv = rtl_priv(hw); 116 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 117 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 118 119 switch (variable) { 120 case HW_VAR_RCR: 121 *((u32 *) (val)) = rtlpci->receive_config; 122 break; 123 case HW_VAR_RF_STATE: 124 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 125 break; 126 case HW_VAR_FWLPS_RF_ON:{ 127 enum rf_pwrstate rfState; 128 u32 val_rcr; 129 130 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, 131 (u8 *) (&rfState)); 132 if (rfState == ERFOFF) { 133 *((bool *) (val)) = true; 134 } else { 135 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 136 val_rcr &= 0x00070000; 137 if (val_rcr) 138 *((bool *) (val)) = false; 139 else 140 *((bool *) (val)) = true; 141 } 142 break; 143 } 144 case HW_VAR_FW_PSMODE_STATUS: 145 *((bool *) (val)) = ppsc->fw_current_inpsmode; 146 break; 147 case HW_VAR_CORRECT_TSF:{ 148 u64 tsf; 149 u32 *ptsf_low = (u32 *)&tsf; 150 u32 *ptsf_high = ((u32 *)&tsf) + 1; 151 152 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 153 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 154 *((u64 *) (val)) = tsf; 155 break; 156 } 157 case HW_VAR_INT_MIGRATION: 158 *((bool *)(val)) = rtlpriv->dm.interrupt_migration; 159 break; 160 case HW_VAR_INT_AC: 161 *((bool *)(val)) = rtlpriv->dm.disable_tx_int; 162 break; 163 case HAL_DEF_WOWLAN: 164 break; 165 default: 166 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 167 "switch case %#x not processed\n", variable); 168 break; 169 } 170 } 171 172 void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 173 { 174 struct rtl_priv *rtlpriv = rtl_priv(hw); 175 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 176 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 177 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 178 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 179 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 180 u8 idx; 181 182 switch (variable) { 183 case HW_VAR_ETHER_ADDR: 184 for (idx = 0; idx < ETH_ALEN; idx++) { 185 rtl_write_byte(rtlpriv, (REG_MACID + idx), 186 val[idx]); 187 } 188 break; 189 case HW_VAR_BASIC_RATE: { 190 u16 rate_cfg = ((u16 *) val)[0]; 191 u8 rate_index = 0; 192 193 rate_cfg = rate_cfg & 0x15f; 194 if (mac->vendor == PEER_CISCO && 195 ((rate_cfg & 0x150) == 0)) 196 rate_cfg |= 0x01; 197 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); 198 rtl_write_byte(rtlpriv, REG_RRSR + 1, 199 (rate_cfg >> 8) & 0xff); 200 while (rate_cfg > 0x1) { 201 rate_cfg = (rate_cfg >> 1); 202 rate_index++; 203 } 204 if (rtlhal->fw_version > 0xe) 205 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 206 rate_index); 207 break; 208 } 209 case HW_VAR_BSSID: 210 for (idx = 0; idx < ETH_ALEN; idx++) { 211 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 212 val[idx]); 213 } 214 break; 215 case HW_VAR_SIFS: 216 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 217 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); 218 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 219 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 220 if (!mac->ht_enable) 221 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 222 0x0e0e); 223 else 224 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 225 *((u16 *) val)); 226 break; 227 case HW_VAR_SLOT_TIME: { 228 u8 e_aci; 229 230 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 231 "HW_VAR_SLOT_TIME %x\n", val[0]); 232 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 233 for (e_aci = 0; e_aci < AC_MAX; e_aci++) 234 rtlpriv->cfg->ops->set_hw_reg(hw, 235 HW_VAR_AC_PARAM, 236 (&e_aci)); 237 break; 238 } 239 case HW_VAR_ACK_PREAMBLE: { 240 u8 reg_tmp; 241 u8 short_preamble = (bool) (*val); 242 243 reg_tmp = (mac->cur_40_prime_sc) << 5; 244 if (short_preamble) 245 reg_tmp |= 0x80; 246 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 247 break; 248 } 249 case HW_VAR_AMPDU_MIN_SPACE: { 250 u8 min_spacing_to_set; 251 u8 sec_min_space; 252 253 min_spacing_to_set = *val; 254 if (min_spacing_to_set <= 7) { 255 sec_min_space = 0; 256 if (min_spacing_to_set < sec_min_space) 257 min_spacing_to_set = sec_min_space; 258 mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) | 259 min_spacing_to_set); 260 *val = min_spacing_to_set; 261 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 262 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 263 mac->min_space_cfg); 264 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 265 mac->min_space_cfg); 266 } 267 break; 268 } 269 case HW_VAR_SHORTGI_DENSITY: { 270 u8 density_to_set; 271 272 density_to_set = *val; 273 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg; 274 mac->min_space_cfg |= (density_to_set << 3); 275 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 276 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 277 mac->min_space_cfg); 278 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 279 mac->min_space_cfg); 280 break; 281 } 282 case HW_VAR_AMPDU_FACTOR: { 283 u8 factor_toset; 284 u32 regtoSet; 285 u8 *ptmp_byte = NULL; 286 u8 index; 287 288 if (rtlhal->macphymode == DUALMAC_DUALPHY) 289 regtoSet = 0xb9726641; 290 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY) 291 regtoSet = 0x66626641; 292 else 293 regtoSet = 0xb972a841; 294 factor_toset = *val; 295 if (factor_toset <= 3) { 296 factor_toset = (1 << (factor_toset + 2)); 297 if (factor_toset > 0xf) 298 factor_toset = 0xf; 299 for (index = 0; index < 4; index++) { 300 ptmp_byte = (u8 *) (®toSet) + index; 301 if ((*ptmp_byte & 0xf0) > 302 (factor_toset << 4)) 303 *ptmp_byte = (*ptmp_byte & 0x0f) 304 | (factor_toset << 4); 305 if ((*ptmp_byte & 0x0f) > factor_toset) 306 *ptmp_byte = (*ptmp_byte & 0xf0) 307 | (factor_toset); 308 } 309 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoSet); 310 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 311 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 312 factor_toset); 313 } 314 break; 315 } 316 case HW_VAR_AC_PARAM: { 317 u8 e_aci = *val; 318 rtl92d_dm_init_edca_turbo(hw); 319 if (rtlpci->acm_method != EACMWAY2_SW) 320 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL, 321 &e_aci); 322 break; 323 } 324 case HW_VAR_ACM_CTRL: { 325 u8 e_aci = *val; 326 union aci_aifsn *p_aci_aifsn = 327 (union aci_aifsn *)(&(mac->ac[0].aifs)); 328 u8 acm = p_aci_aifsn->f.acm; 329 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 330 331 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 332 if (acm) { 333 switch (e_aci) { 334 case AC0_BE: 335 acm_ctrl |= ACMHW_BEQEN; 336 break; 337 case AC2_VI: 338 acm_ctrl |= ACMHW_VIQEN; 339 break; 340 case AC3_VO: 341 acm_ctrl |= ACMHW_VOQEN; 342 break; 343 default: 344 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 345 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 346 acm); 347 break; 348 } 349 } else { 350 switch (e_aci) { 351 case AC0_BE: 352 acm_ctrl &= (~ACMHW_BEQEN); 353 break; 354 case AC2_VI: 355 acm_ctrl &= (~ACMHW_VIQEN); 356 break; 357 case AC3_VO: 358 acm_ctrl &= (~ACMHW_VOQEN); 359 break; 360 default: 361 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 362 "switch case %#x not processed\n", 363 e_aci); 364 break; 365 } 366 } 367 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 368 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 369 acm_ctrl); 370 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 371 break; 372 } 373 case HW_VAR_RCR: 374 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); 375 rtlpci->receive_config = ((u32 *) (val))[0]; 376 break; 377 case HW_VAR_RETRY_LIMIT: { 378 u8 retry_limit = val[0]; 379 380 rtl_write_word(rtlpriv, REG_RL, 381 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 382 retry_limit << RETRY_LIMIT_LONG_SHIFT); 383 break; 384 } 385 case HW_VAR_DUAL_TSF_RST: 386 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 387 break; 388 case HW_VAR_EFUSE_BYTES: 389 rtlefuse->efuse_usedbytes = *((u16 *) val); 390 break; 391 case HW_VAR_EFUSE_USAGE: 392 rtlefuse->efuse_usedpercentage = *val; 393 break; 394 case HW_VAR_IO_CMD: 395 rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val)); 396 break; 397 case HW_VAR_WPA_CONFIG: 398 rtl_write_byte(rtlpriv, REG_SECCFG, *val); 399 break; 400 case HW_VAR_SET_RPWM: 401 rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (val)); 402 break; 403 case HW_VAR_H2C_FW_PWRMODE: 404 break; 405 case HW_VAR_FW_PSMODE_STATUS: 406 ppsc->fw_current_inpsmode = *((bool *) val); 407 break; 408 case HW_VAR_H2C_FW_JOINBSSRPT: { 409 u8 mstatus = (*val); 410 u8 tmp_regcr, tmp_reg422; 411 bool recover = false; 412 413 if (mstatus == RT_MEDIA_CONNECT) { 414 rtlpriv->cfg->ops->set_hw_reg(hw, 415 HW_VAR_AID, NULL); 416 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 417 rtl_write_byte(rtlpriv, REG_CR + 1, 418 (tmp_regcr | BIT(0))); 419 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3)); 420 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0); 421 tmp_reg422 = rtl_read_byte(rtlpriv, 422 REG_FWHW_TXQ_CTRL + 2); 423 if (tmp_reg422 & BIT(6)) 424 recover = true; 425 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 426 tmp_reg422 & (~BIT(6))); 427 rtl92d_set_fw_rsvdpagepkt(hw, 0); 428 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0); 429 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4)); 430 if (recover) 431 rtl_write_byte(rtlpriv, 432 REG_FWHW_TXQ_CTRL + 2, 433 tmp_reg422); 434 rtl_write_byte(rtlpriv, REG_CR + 1, 435 (tmp_regcr & ~(BIT(0)))); 436 } 437 rtl92d_set_fw_joinbss_report_cmd(hw, (*val)); 438 break; 439 } 440 case HW_VAR_AID: { 441 u16 u2btmp; 442 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 443 u2btmp &= 0xC000; 444 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | 445 mac->assoc_id)); 446 break; 447 } 448 case HW_VAR_CORRECT_TSF: { 449 u8 btype_ibss = val[0]; 450 451 if (btype_ibss) 452 _rtl92de_stop_tx_beacon(hw); 453 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3)); 454 rtl_write_dword(rtlpriv, REG_TSFTR, 455 (u32) (mac->tsf & 0xffffffff)); 456 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 457 (u32) ((mac->tsf >> 32) & 0xffffffff)); 458 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0); 459 if (btype_ibss) 460 _rtl92de_resume_tx_beacon(hw); 461 462 break; 463 } 464 case HW_VAR_INT_MIGRATION: { 465 bool int_migration = *(bool *) (val); 466 467 if (int_migration) { 468 /* Set interrupt migration timer and 469 * corresponding Tx/Rx counter. 470 * timer 25ns*0xfa0=100us for 0xf packets. 471 * 0x306:Rx, 0x307:Tx */ 472 rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0); 473 rtlpriv->dm.interrupt_migration = int_migration; 474 } else { 475 /* Reset all interrupt migration settings. */ 476 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 477 rtlpriv->dm.interrupt_migration = int_migration; 478 } 479 break; 480 } 481 case HW_VAR_INT_AC: { 482 bool disable_ac_int = *((bool *) val); 483 484 /* Disable four ACs interrupts. */ 485 if (disable_ac_int) { 486 /* Disable VO, VI, BE and BK four AC interrupts 487 * to gain more efficient CPU utilization. 488 * When extremely highly Rx OK occurs, 489 * we will disable Tx interrupts. 490 */ 491 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0, 492 RT_AC_INT_MASKS); 493 rtlpriv->dm.disable_tx_int = disable_ac_int; 494 /* Enable four ACs interrupts. */ 495 } else { 496 rtlpriv->cfg->ops->update_interrupt_mask(hw, 497 RT_AC_INT_MASKS, 0); 498 rtlpriv->dm.disable_tx_int = disable_ac_int; 499 } 500 break; 501 } 502 default: 503 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 504 "switch case %#x not processed\n", variable); 505 break; 506 } 507 } 508 509 static bool _rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 510 { 511 struct rtl_priv *rtlpriv = rtl_priv(hw); 512 bool status = true; 513 long count = 0; 514 u32 value = _LLT_INIT_ADDR(address) | 515 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); 516 517 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 518 do { 519 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 520 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 521 break; 522 if (count > POLLING_LLT_THRESHOLD) { 523 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 524 "Failed to polling write LLT done at address %d!\n", 525 address); 526 status = false; 527 break; 528 } 529 } while (++count); 530 return status; 531 } 532 533 static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw) 534 { 535 struct rtl_priv *rtlpriv = rtl_priv(hw); 536 unsigned short i; 537 u8 txpktbuf_bndy; 538 u8 maxPage; 539 bool status; 540 u32 value32; /* High+low page number */ 541 u8 value8; /* normal page number */ 542 543 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) { 544 maxPage = 255; 545 txpktbuf_bndy = 246; 546 value8 = 0; 547 value32 = 0x80bf0d29; 548 } else { 549 maxPage = 127; 550 txpktbuf_bndy = 123; 551 value8 = 0; 552 value32 = 0x80750005; 553 } 554 555 /* Set reserved page for each queue */ 556 /* 11. RQPN 0x200[31:0] = 0x80BD1C1C */ 557 /* load RQPN */ 558 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); 559 rtl_write_dword(rtlpriv, REG_RQPN, value32); 560 561 /* 12. TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */ 562 /* TXRKTBUG_PG_BNDY */ 563 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, 564 (rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 | 565 txpktbuf_bndy)); 566 567 /* 13. TDECTRL[15:8] 0x209[7:0] = 0xF6 */ 568 /* Beacon Head for TXDMA */ 569 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 570 571 /* 14. BCNQ_PGBNDY 0x424[7:0] = 0xF6 */ 572 /* BCNQ_PGBNDY */ 573 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 574 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 575 576 /* 15. WMAC_LBK_BF_HD 0x45D[7:0] = 0xF6 */ 577 /* WMAC_LBK_BF_HD */ 578 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); 579 580 /* Set Tx/Rx page size (Tx must be 128 Bytes, */ 581 /* Rx can be 64,128,256,512,1024 bytes) */ 582 /* 16. PBP [7:0] = 0x11 */ 583 /* TRX page size */ 584 rtl_write_byte(rtlpriv, REG_PBP, 0x11); 585 586 /* 17. DRV_INFO_SZ = 0x04 */ 587 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 588 589 /* 18. LLT_table_init(Adapter); */ 590 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 591 status = _rtl92de_llt_write(hw, i, i + 1); 592 if (true != status) 593 return status; 594 } 595 596 /* end of list */ 597 status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 598 if (true != status) 599 return status; 600 601 /* Make the other pages as ring buffer */ 602 /* This ring buffer is used as beacon buffer if we */ 603 /* config this MAC as two MAC transfer. */ 604 /* Otherwise used as local loopback buffer. */ 605 for (i = txpktbuf_bndy; i < maxPage; i++) { 606 status = _rtl92de_llt_write(hw, i, (i + 1)); 607 if (true != status) 608 return status; 609 } 610 611 /* Let last entry point to the start entry of ring buffer */ 612 status = _rtl92de_llt_write(hw, maxPage, txpktbuf_bndy); 613 if (true != status) 614 return status; 615 616 return true; 617 } 618 619 static void _rtl92de_gen_refresh_led_state(struct ieee80211_hw *hw) 620 { 621 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 622 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 623 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 624 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0); 625 626 if (rtlpci->up_first_time) 627 return; 628 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 629 rtl92de_sw_led_on(hw, pLed0); 630 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 631 rtl92de_sw_led_on(hw, pLed0); 632 else 633 rtl92de_sw_led_off(hw, pLed0); 634 } 635 636 static bool _rtl92de_init_mac(struct ieee80211_hw *hw) 637 { 638 struct rtl_priv *rtlpriv = rtl_priv(hw); 639 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 640 unsigned char bytetmp; 641 unsigned short wordtmp; 642 u16 retry; 643 644 rtl92d_phy_set_poweron(hw); 645 /* Add for resume sequence of power domain according 646 * to power document V11. Chapter V.11.... */ 647 /* 0. RSV_CTRL 0x1C[7:0] = 0x00 */ 648 /* unlock ISO/CLK/Power control register */ 649 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 650 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05); 651 652 /* 1. AFE_XTAL_CTRL [7:0] = 0x0F enable XTAL */ 653 /* 2. SPS0_CTRL 0x11[7:0] = 0x2b enable SPS into PWM mode */ 654 /* 3. delay (1ms) this is not necessary when initially power on */ 655 656 /* C. Resume Sequence */ 657 /* a. SPS0_CTRL 0x11[7:0] = 0x2b */ 658 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 659 660 /* b. AFE_XTAL_CTRL [7:0] = 0x0F */ 661 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F); 662 663 /* c. DRV runs power on init flow */ 664 665 /* auto enable WLAN */ 666 /* 4. APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0 */ 667 /* Power On Reset for MAC Block */ 668 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0); 669 udelay(2); 670 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); 671 udelay(2); 672 673 /* 5. Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */ 674 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); 675 udelay(50); 676 retry = 0; 677 while ((bytetmp & BIT(0)) && retry < 1000) { 678 retry++; 679 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); 680 udelay(50); 681 } 682 683 /* Enable Radio off, GPIO, and LED function */ 684 /* 6. APS_FSMCO 0x04[15:0] = 0x0012 when enable HWPDN */ 685 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012); 686 687 /* release RF digital isolation */ 688 /* 7. SYS_ISO_CTRL 0x01[1] = 0x0; */ 689 /*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */ 690 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82); 691 udelay(2); 692 693 /* make sure that BB reset OK. */ 694 /* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */ 695 696 /* Disable REG_CR before enable it to assure reset */ 697 rtl_write_word(rtlpriv, REG_CR, 0x0); 698 699 /* Release MAC IO register reset */ 700 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 701 702 /* clear stopping tx/rx dma */ 703 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0); 704 705 /* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */ 706 707 /* System init */ 708 /* 18. LLT_table_init(Adapter); */ 709 if (!_rtl92de_llt_table_init(hw)) 710 return false; 711 712 /* Clear interrupt and enable interrupt */ 713 /* 19. HISR 0x124[31:0] = 0xffffffff; */ 714 /* HISRE 0x12C[7:0] = 0xFF */ 715 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 716 rtl_write_byte(rtlpriv, REG_HISRE, 0xff); 717 718 /* 20. HIMR 0x120[31:0] |= [enable INT mask bit map]; */ 719 /* 21. HIMRE 0x128[7:0] = [enable INT mask bit map] */ 720 /* The IMR should be enabled later after all init sequence 721 * is finished. */ 722 723 /* 22. PCIE configuration space configuration */ 724 /* 23. Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ), */ 725 /* and PCIe gated clock function is enabled. */ 726 /* PCIE configuration space will be written after 727 * all init sequence.(Or by BIOS) */ 728 729 rtl92d_phy_config_maccoexist_rfpage(hw); 730 731 /* THe below section is not related to power document Vxx . */ 732 /* This is only useful for driver and OS setting. */ 733 /* -------------------Software Relative Setting---------------------- */ 734 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 735 wordtmp &= 0xf; 736 wordtmp |= 0xF771; 737 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 738 739 /* Reported Tx status from HW for rate adaptive. */ 740 /* This should be realtive to power on step 14. But in document V11 */ 741 /* still not contain the description.!!! */ 742 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 743 744 /* Set Tx/Rx page size (Tx must be 128 Bytes, 745 * Rx can be 64,128,256,512,1024 bytes) */ 746 /* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */ 747 748 /* Set RCR register */ 749 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 750 /* rtl_write_byte(rtlpriv,REG_RX_DRVINFO_SZ, 4); */ 751 752 /* Set TCR register */ 753 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); 754 755 /* disable earlymode */ 756 rtl_write_byte(rtlpriv, 0x4d0, 0x0); 757 758 /* Set TX/RX descriptor physical address(from OS API). */ 759 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 760 rtlpci->tx_ring[BEACON_QUEUE].dma); 761 rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma); 762 rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma); 763 rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma); 764 rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma); 765 rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma); 766 rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma); 767 /* Set RX Desc Address */ 768 rtl_write_dword(rtlpriv, REG_RX_DESA, 769 rtlpci->rx_ring[RX_MPDU_QUEUE].dma); 770 771 /* if we want to support 64 bit DMA, we should set it here, 772 * but now we do not support 64 bit DMA*/ 773 774 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33); 775 776 /* Reset interrupt migration setting when initialization */ 777 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 778 779 /* Reconsider when to do this operation after asking HWSD. */ 780 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 781 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); 782 do { 783 retry++; 784 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 785 } while ((retry < 200) && !(bytetmp & BIT(7))); 786 787 /* After MACIO reset,we must refresh LED state. */ 788 _rtl92de_gen_refresh_led_state(hw); 789 790 /* Reset H2C protection register */ 791 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); 792 793 return true; 794 } 795 796 static void _rtl92de_hw_configure(struct ieee80211_hw *hw) 797 { 798 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 799 struct rtl_priv *rtlpriv = rtl_priv(hw); 800 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 801 u8 reg_bw_opmode = BW_OPMODE_20MHZ; 802 u32 reg_rrsr; 803 804 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 805 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); 806 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 807 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr); 808 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 809 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); 810 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); 811 rtl_write_word(rtlpriv, REG_RL, 0x0707); 812 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); 813 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 814 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 815 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 816 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 817 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 818 /* Aggregation threshold */ 819 if (rtlhal->macphymode == DUALMAC_DUALPHY) 820 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641); 821 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY) 822 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641); 823 else 824 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); 825 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); 826 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); 827 rtlpci->reg_bcn_ctrl_val = 0x1f; 828 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 829 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 830 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); 831 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 832 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 833 /* For throughput */ 834 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666); 835 /* ACKTO for IOT issue. */ 836 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); 837 /* Set Spec SIFS (used in NAV) */ 838 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); 839 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); 840 /* Set SIFS for CCK */ 841 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); 842 /* Set SIFS for OFDM */ 843 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); 844 /* Set Multicast Address. */ 845 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); 846 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); 847 switch (rtlpriv->phy.rf_type) { 848 case RF_1T2R: 849 case RF_1T1R: 850 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3); 851 break; 852 case RF_2T2R: 853 case RF_2T2R_GREEN: 854 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3); 855 break; 856 } 857 } 858 859 static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw) 860 { 861 struct rtl_priv *rtlpriv = rtl_priv(hw); 862 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 863 864 rtl_write_byte(rtlpriv, 0x34b, 0x93); 865 rtl_write_word(rtlpriv, 0x350, 0x870c); 866 rtl_write_byte(rtlpriv, 0x352, 0x1); 867 if (ppsc->support_backdoor) 868 rtl_write_byte(rtlpriv, 0x349, 0x1b); 869 else 870 rtl_write_byte(rtlpriv, 0x349, 0x03); 871 rtl_write_word(rtlpriv, 0x350, 0x2718); 872 rtl_write_byte(rtlpriv, 0x352, 0x1); 873 } 874 875 void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw) 876 { 877 struct rtl_priv *rtlpriv = rtl_priv(hw); 878 u8 sec_reg_value; 879 880 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 881 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 882 rtlpriv->sec.pairwise_enc_algorithm, 883 rtlpriv->sec.group_enc_algorithm); 884 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 885 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 886 "not open hw encryption\n"); 887 return; 888 } 889 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE; 890 if (rtlpriv->sec.use_defaultkey) { 891 sec_reg_value |= SCR_TXUSEDK; 892 sec_reg_value |= SCR_RXUSEDK; 893 } 894 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 895 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 896 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 897 "The SECR-value %x\n", sec_reg_value); 898 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 899 } 900 901 int rtl92de_hw_init(struct ieee80211_hw *hw) 902 { 903 struct rtl_priv *rtlpriv = rtl_priv(hw); 904 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 905 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 906 struct rtl_phy *rtlphy = &(rtlpriv->phy); 907 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 908 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 909 bool rtstatus = true; 910 u8 tmp_u1b; 911 int i; 912 int err; 913 unsigned long flags; 914 915 rtlpci->being_init_adapter = true; 916 rtlpci->init_ready = false; 917 spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags); 918 /* we should do iqk after disable/enable */ 919 rtl92d_phy_reset_iqk_result(hw); 920 /* rtlpriv->intf_ops->disable_aspm(hw); */ 921 rtstatus = _rtl92de_init_mac(hw); 922 if (!rtstatus) { 923 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n"); 924 err = 1; 925 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags); 926 return err; 927 } 928 err = rtl92d_download_fw(hw); 929 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags); 930 if (err) { 931 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 932 "Failed to download FW. Init HW without FW..\n"); 933 return 1; 934 } 935 rtlhal->last_hmeboxnum = 0; 936 rtlpriv->psc.fw_current_inpsmode = false; 937 938 tmp_u1b = rtl_read_byte(rtlpriv, 0x605); 939 tmp_u1b = tmp_u1b | 0x30; 940 rtl_write_byte(rtlpriv, 0x605, tmp_u1b); 941 942 if (rtlhal->earlymode_enable) { 943 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 944 "EarlyMode Enabled!!!\n"); 945 946 tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0); 947 tmp_u1b = tmp_u1b | 0x1f; 948 rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b); 949 950 rtl_write_byte(rtlpriv, 0x4d3, 0x80); 951 952 tmp_u1b = rtl_read_byte(rtlpriv, 0x605); 953 tmp_u1b = tmp_u1b | 0x40; 954 rtl_write_byte(rtlpriv, 0x605, tmp_u1b); 955 } 956 957 if (mac->rdg_en) { 958 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff); 959 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200); 960 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05); 961 } 962 963 rtl92d_phy_mac_config(hw); 964 /* because last function modify RCR, so we update 965 * rcr var here, or TP will unstable for receive_config 966 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 967 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/ 968 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); 969 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 970 971 rtl92d_phy_bb_config(hw); 972 973 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 974 /* set before initialize RF */ 975 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); 976 977 /* config RF */ 978 rtl92d_phy_rf_config(hw); 979 980 /* After read predefined TXT, we must set BB/MAC/RF 981 * register as our requirement */ 982 /* After load BB,RF params,we need do more for 92D. */ 983 rtl92d_update_bbrf_configuration(hw); 984 /* set default value after initialize RF, */ 985 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); 986 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 987 RF_CHNLBW, RFREG_OFFSET_MASK); 988 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 989 RF_CHNLBW, RFREG_OFFSET_MASK); 990 991 /*---- Set CCK and OFDM Block "ON"----*/ 992 if (rtlhal->current_bandtype == BAND_ON_2_4G) 993 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 994 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 995 if (rtlhal->interfaceindex == 0) { 996 /* RFPGA0_ANALOGPARAMETER2: cck clock select, 997 * set to 20MHz by default */ 998 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | 999 BIT(11), 3); 1000 } else { 1001 /* Mac1 */ 1002 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(11) | 1003 BIT(10), 3); 1004 } 1005 1006 _rtl92de_hw_configure(hw); 1007 1008 /* reset hw sec */ 1009 rtl_cam_reset_all_entry(hw); 1010 rtl92de_enable_hw_security_config(hw); 1011 1012 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */ 1013 /* TX power index for different rate set. */ 1014 rtl92d_phy_get_hw_reg_originalvalue(hw); 1015 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel); 1016 1017 ppsc->rfpwr_state = ERFON; 1018 1019 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1020 1021 _rtl92de_enable_aspm_back_door(hw); 1022 /* rtlpriv->intf_ops->enable_aspm(hw); */ 1023 1024 rtl92d_dm_init(hw); 1025 rtlpci->being_init_adapter = false; 1026 1027 if (ppsc->rfpwr_state == ERFON) { 1028 rtl92d_phy_lc_calibrate(hw); 1029 /* 5G and 2.4G must wait sometime to let RF LO ready */ 1030 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 1031 u32 tmp_rega; 1032 for (i = 0; i < 10000; i++) { 1033 udelay(MAX_STALL_TIME); 1034 1035 tmp_rega = rtl_get_rfreg(hw, 1036 (enum radio_path)RF90_PATH_A, 1037 0x2a, MASKDWORD); 1038 1039 if (((tmp_rega & BIT(11)) == BIT(11))) 1040 break; 1041 } 1042 /* check that loop was successful. If not, exit now */ 1043 if (i == 10000) { 1044 rtlpci->init_ready = false; 1045 return 1; 1046 } 1047 } 1048 } 1049 rtlpci->init_ready = true; 1050 return err; 1051 } 1052 1053 static enum version_8192d _rtl92de_read_chip_version(struct ieee80211_hw *hw) 1054 { 1055 struct rtl_priv *rtlpriv = rtl_priv(hw); 1056 enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY; 1057 u32 value32; 1058 1059 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 1060 if (!(value32 & 0x000f0000)) { 1061 version = VERSION_TEST_CHIP_92D_SINGLEPHY; 1062 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n"); 1063 } else { 1064 version = VERSION_NORMAL_CHIP_92D_SINGLEPHY; 1065 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n"); 1066 } 1067 return version; 1068 } 1069 1070 static int _rtl92de_set_media_status(struct ieee80211_hw *hw, 1071 enum nl80211_iftype type) 1072 { 1073 struct rtl_priv *rtlpriv = rtl_priv(hw); 1074 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1075 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1076 u8 bcnfunc_enable; 1077 1078 bt_msr &= 0xfc; 1079 1080 if (type == NL80211_IFTYPE_UNSPECIFIED || 1081 type == NL80211_IFTYPE_STATION) { 1082 _rtl92de_stop_tx_beacon(hw); 1083 _rtl92de_enable_bcn_sub_func(hw); 1084 } else if (type == NL80211_IFTYPE_ADHOC || 1085 type == NL80211_IFTYPE_AP) { 1086 _rtl92de_resume_tx_beacon(hw); 1087 _rtl92de_disable_bcn_sub_func(hw); 1088 } else { 1089 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1090 "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n", 1091 type); 1092 } 1093 bcnfunc_enable = rtl_read_byte(rtlpriv, REG_BCN_CTRL); 1094 switch (type) { 1095 case NL80211_IFTYPE_UNSPECIFIED: 1096 bt_msr |= MSR_NOLINK; 1097 ledaction = LED_CTL_LINK; 1098 bcnfunc_enable &= 0xF7; 1099 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1100 "Set Network type to NO LINK!\n"); 1101 break; 1102 case NL80211_IFTYPE_ADHOC: 1103 bt_msr |= MSR_ADHOC; 1104 bcnfunc_enable |= 0x08; 1105 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1106 "Set Network type to Ad Hoc!\n"); 1107 break; 1108 case NL80211_IFTYPE_STATION: 1109 bt_msr |= MSR_INFRA; 1110 ledaction = LED_CTL_LINK; 1111 bcnfunc_enable &= 0xF7; 1112 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1113 "Set Network type to STA!\n"); 1114 break; 1115 case NL80211_IFTYPE_AP: 1116 bt_msr |= MSR_AP; 1117 bcnfunc_enable |= 0x08; 1118 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1119 "Set Network type to AP!\n"); 1120 break; 1121 default: 1122 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1123 "Network type %d not supported!\n", type); 1124 return 1; 1125 break; 1126 1127 } 1128 rtl_write_byte(rtlpriv, MSR, bt_msr); 1129 rtlpriv->cfg->ops->led_control(hw, ledaction); 1130 if ((bt_msr & MSR_MASK) == MSR_AP) 1131 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1132 else 1133 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1134 return 0; 1135 } 1136 1137 void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1138 { 1139 struct rtl_priv *rtlpriv = rtl_priv(hw); 1140 u32 reg_rcr; 1141 1142 if (rtlpriv->psc.rfpwr_state != ERFON) 1143 return; 1144 1145 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1146 1147 if (check_bssid) { 1148 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1149 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1150 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1151 } else if (!check_bssid) { 1152 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1153 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0); 1154 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1155 } 1156 } 1157 1158 int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1159 { 1160 struct rtl_priv *rtlpriv = rtl_priv(hw); 1161 1162 if (_rtl92de_set_media_status(hw, type)) 1163 return -EOPNOTSUPP; 1164 1165 /* check bssid */ 1166 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1167 if (type != NL80211_IFTYPE_AP) 1168 rtl92de_set_check_bssid(hw, true); 1169 } else { 1170 rtl92de_set_check_bssid(hw, false); 1171 } 1172 return 0; 1173 } 1174 1175 /* do iqk or reload iqk */ 1176 /* windows just rtl92d_phy_reload_iqk_setting in set channel, 1177 * but it's very strict for time sequence so we add 1178 * rtl92d_phy_reload_iqk_setting here */ 1179 void rtl92d_linked_set_reg(struct ieee80211_hw *hw) 1180 { 1181 struct rtl_priv *rtlpriv = rtl_priv(hw); 1182 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1183 u8 indexforchannel; 1184 u8 channel = rtlphy->current_channel; 1185 1186 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel); 1187 if (!rtlphy->iqk_matrix[indexforchannel].iqk_done) { 1188 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG, 1189 "Do IQK for channel:%d\n", channel); 1190 rtl92d_phy_iq_calibrate(hw); 1191 } 1192 } 1193 1194 /* don't set REG_EDCA_BE_PARAM here because 1195 * mac80211 will send pkt when scan */ 1196 void rtl92de_set_qos(struct ieee80211_hw *hw, int aci) 1197 { 1198 rtl92d_dm_init_edca_turbo(hw); 1199 } 1200 1201 void rtl92de_enable_interrupt(struct ieee80211_hw *hw) 1202 { 1203 struct rtl_priv *rtlpriv = rtl_priv(hw); 1204 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1205 1206 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); 1207 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); 1208 } 1209 1210 void rtl92de_disable_interrupt(struct ieee80211_hw *hw) 1211 { 1212 struct rtl_priv *rtlpriv = rtl_priv(hw); 1213 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1214 1215 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); 1216 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); 1217 synchronize_irq(rtlpci->pdev->irq); 1218 } 1219 1220 static void _rtl92de_poweroff_adapter(struct ieee80211_hw *hw) 1221 { 1222 struct rtl_priv *rtlpriv = rtl_priv(hw); 1223 u8 u1b_tmp; 1224 unsigned long flags; 1225 1226 rtlpriv->intf_ops->enable_aspm(hw); 1227 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); 1228 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0); 1229 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0); 1230 1231 /* 0x20:value 05-->04 */ 1232 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04); 1233 1234 /* ==== Reset digital sequence ====== */ 1235 rtl92d_firmware_selfreset(hw); 1236 1237 /* f. SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */ 1238 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51); 1239 1240 /* g. MCUFWDL 0x80[1:0]=0 reset MCU ready status */ 1241 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1242 1243 /* ==== Pull GPIO PIN to balance level and LED control ====== */ 1244 1245 /* h. GPIO_PIN_CTRL 0x44[31:0]=0x000 */ 1246 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000); 1247 1248 /* i. Value = GPIO_PIN_CTRL[7:0] */ 1249 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL); 1250 1251 /* j. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */ 1252 /* write external PIN level */ 1253 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 1254 0x00FF0000 | (u1b_tmp << 8)); 1255 1256 /* k. GPIO_MUXCFG 0x42 [15:0] = 0x0780 */ 1257 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790); 1258 1259 /* l. LEDCFG 0x4C[15:0] = 0x8080 */ 1260 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); 1261 1262 /* ==== Disable analog sequence === */ 1263 1264 /* m. AFE_PLL_CTRL[7:0] = 0x80 disable PLL */ 1265 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); 1266 1267 /* n. SPS0_CTRL 0x11[7:0] = 0x22 enter PFM mode */ 1268 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); 1269 1270 /* o. AFE_XTAL_CTRL 0x24[7:0] = 0x0E disable XTAL, if No BT COEX */ 1271 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e); 1272 1273 /* p. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */ 1274 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); 1275 1276 /* ==== interface into suspend === */ 1277 1278 /* q. APS_FSMCO[15:8] = 0x58 PCIe suspend mode */ 1279 /* According to power document V11, we need to set this */ 1280 /* value as 0x18. Otherwise, we may not L0s sometimes. */ 1281 /* This indluences power consumption. Bases on SD1's test, */ 1282 /* set as 0x00 do not affect power current. And if it */ 1283 /* is set as 0x18, they had ever met auto load fail problem. */ 1284 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10); 1285 1286 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1287 "In PowerOff,reg0x%x=%X\n", 1288 REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL)); 1289 /* r. Note: for PCIe interface, PON will not turn */ 1290 /* off m-bias and BandGap in PCIe suspend mode. */ 1291 1292 /* 0x17[7] 1b': power off in process 0b' : power off over */ 1293 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) { 1294 spin_lock_irqsave(&globalmutex_power, flags); 1295 u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); 1296 u1b_tmp &= (~BIT(7)); 1297 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp); 1298 spin_unlock_irqrestore(&globalmutex_power, flags); 1299 } 1300 1301 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n"); 1302 } 1303 1304 void rtl92de_card_disable(struct ieee80211_hw *hw) 1305 { 1306 struct rtl_priv *rtlpriv = rtl_priv(hw); 1307 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1308 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1309 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1310 enum nl80211_iftype opmode; 1311 1312 mac->link_state = MAC80211_NOLINK; 1313 opmode = NL80211_IFTYPE_UNSPECIFIED; 1314 _rtl92de_set_media_status(hw, opmode); 1315 1316 if (rtlpci->driver_is_goingto_unload || 1317 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1318 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1319 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1320 /* Power sequence for each MAC. */ 1321 /* a. stop tx DMA */ 1322 /* b. close RF */ 1323 /* c. clear rx buf */ 1324 /* d. stop rx DMA */ 1325 /* e. reset MAC */ 1326 1327 /* a. stop tx DMA */ 1328 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE); 1329 udelay(50); 1330 1331 /* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ 1332 1333 /* c. ========RF OFF sequence========== */ 1334 /* 0x88c[23:20] = 0xf. */ 1335 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); 1336 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 1337 1338 /* APSD_CTRL 0x600[7:0] = 0x40 */ 1339 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 1340 1341 /* Close antenna 0,0xc04,0xd04 */ 1342 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0); 1343 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0); 1344 1345 /* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */ 1346 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 1347 1348 /* Mac0 can not do Global reset. Mac1 can do. */ 1349 /* SYS_FUNC_EN 0x02[7:0] = 0xE0 reset BB state machine */ 1350 if (rtlpriv->rtlhal.interfaceindex == 1) 1351 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0); 1352 udelay(50); 1353 1354 /* d. stop tx/rx dma before disable REG_CR (0x100) to fix */ 1355 /* dma hang issue when disable/enable device. */ 1356 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff); 1357 udelay(50); 1358 rtl_write_byte(rtlpriv, REG_CR, 0x0); 1359 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n"); 1360 if (rtl92d_phy_check_poweroff(hw)) 1361 _rtl92de_poweroff_adapter(hw); 1362 return; 1363 } 1364 1365 void rtl92de_interrupt_recognized(struct ieee80211_hw *hw, 1366 u32 *p_inta, u32 *p_intb) 1367 { 1368 struct rtl_priv *rtlpriv = rtl_priv(hw); 1369 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1370 1371 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 1372 rtl_write_dword(rtlpriv, ISR, *p_inta); 1373 1374 /* 1375 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; 1376 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb); 1377 */ 1378 } 1379 1380 void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw) 1381 { 1382 struct rtl_priv *rtlpriv = rtl_priv(hw); 1383 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1384 u16 bcn_interval, atim_window; 1385 1386 bcn_interval = mac->beacon_interval; 1387 atim_window = 2; 1388 /*rtl92de_disable_interrupt(hw); */ 1389 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1390 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1391 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 1392 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20); 1393 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) 1394 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30); 1395 else 1396 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20); 1397 rtl_write_byte(rtlpriv, 0x606, 0x30); 1398 } 1399 1400 void rtl92de_set_beacon_interval(struct ieee80211_hw *hw) 1401 { 1402 struct rtl_priv *rtlpriv = rtl_priv(hw); 1403 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1404 u16 bcn_interval = mac->beacon_interval; 1405 1406 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, 1407 "beacon_interval:%d\n", bcn_interval); 1408 /* rtl92de_disable_interrupt(hw); */ 1409 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1410 /* rtl92de_enable_interrupt(hw); */ 1411 } 1412 1413 void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw, 1414 u32 add_msr, u32 rm_msr) 1415 { 1416 struct rtl_priv *rtlpriv = rtl_priv(hw); 1417 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1418 1419 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n", 1420 add_msr, rm_msr); 1421 if (add_msr) 1422 rtlpci->irq_mask[0] |= add_msr; 1423 if (rm_msr) 1424 rtlpci->irq_mask[0] &= (~rm_msr); 1425 rtl92de_disable_interrupt(hw); 1426 rtl92de_enable_interrupt(hw); 1427 } 1428 1429 static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo, 1430 u8 *rom_content, bool autoLoadfail) 1431 { 1432 u32 rfpath, eeaddr, group, offset1, offset2; 1433 u8 i; 1434 1435 memset(pwrinfo, 0, sizeof(struct txpower_info)); 1436 if (autoLoadfail) { 1437 for (group = 0; group < CHANNEL_GROUP_MAX; group++) { 1438 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { 1439 if (group < CHANNEL_GROUP_MAX_2G) { 1440 pwrinfo->cck_index[rfpath][group] = 1441 EEPROM_DEFAULT_TXPOWERLEVEL_2G; 1442 pwrinfo->ht40_1sindex[rfpath][group] = 1443 EEPROM_DEFAULT_TXPOWERLEVEL_2G; 1444 } else { 1445 pwrinfo->ht40_1sindex[rfpath][group] = 1446 EEPROM_DEFAULT_TXPOWERLEVEL_5G; 1447 } 1448 pwrinfo->ht40_2sindexdiff[rfpath][group] = 1449 EEPROM_DEFAULT_HT40_2SDIFF; 1450 pwrinfo->ht20indexdiff[rfpath][group] = 1451 EEPROM_DEFAULT_HT20_DIFF; 1452 pwrinfo->ofdmindexdiff[rfpath][group] = 1453 EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 1454 pwrinfo->ht40maxoffset[rfpath][group] = 1455 EEPROM_DEFAULT_HT40_PWRMAXOFFSET; 1456 pwrinfo->ht20maxoffset[rfpath][group] = 1457 EEPROM_DEFAULT_HT20_PWRMAXOFFSET; 1458 } 1459 } 1460 for (i = 0; i < 3; i++) { 1461 pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI; 1462 pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI; 1463 } 1464 return; 1465 } 1466 1467 /* Maybe autoload OK,buf the tx power index value is not filled. 1468 * If we find it, we set it to default value. */ 1469 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { 1470 for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) { 1471 eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3) 1472 + group; 1473 pwrinfo->cck_index[rfpath][group] = 1474 (rom_content[eeaddr] == 0xFF) ? 1475 (eeaddr > 0x7B ? 1476 EEPROM_DEFAULT_TXPOWERLEVEL_5G : 1477 EEPROM_DEFAULT_TXPOWERLEVEL_2G) : 1478 rom_content[eeaddr]; 1479 } 1480 } 1481 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { 1482 for (group = 0; group < CHANNEL_GROUP_MAX; group++) { 1483 offset1 = group / 3; 1484 offset2 = group % 3; 1485 eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) + 1486 offset2 + offset1 * 21; 1487 pwrinfo->ht40_1sindex[rfpath][group] = 1488 (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ? 1489 EEPROM_DEFAULT_TXPOWERLEVEL_5G : 1490 EEPROM_DEFAULT_TXPOWERLEVEL_2G) : 1491 rom_content[eeaddr]; 1492 } 1493 } 1494 /* These just for 92D efuse offset. */ 1495 for (group = 0; group < CHANNEL_GROUP_MAX; group++) { 1496 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { 1497 int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G; 1498 1499 offset1 = group / 3; 1500 offset2 = group % 3; 1501 1502 if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF) 1503 pwrinfo->ht40_2sindexdiff[rfpath][group] = 1504 (rom_content[base1 + 1505 offset2 + offset1 * 21] >> (rfpath * 4)) 1506 & 0xF; 1507 else 1508 pwrinfo->ht40_2sindexdiff[rfpath][group] = 1509 EEPROM_DEFAULT_HT40_2SDIFF; 1510 if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2 1511 + offset1 * 21] != 0xFF) 1512 pwrinfo->ht20indexdiff[rfpath][group] = 1513 (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G 1514 + offset2 + offset1 * 21] >> (rfpath * 4)) 1515 & 0xF; 1516 else 1517 pwrinfo->ht20indexdiff[rfpath][group] = 1518 EEPROM_DEFAULT_HT20_DIFF; 1519 if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2 1520 + offset1 * 21] != 0xFF) 1521 pwrinfo->ofdmindexdiff[rfpath][group] = 1522 (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G 1523 + offset2 + offset1 * 21] >> (rfpath * 4)) 1524 & 0xF; 1525 else 1526 pwrinfo->ofdmindexdiff[rfpath][group] = 1527 EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 1528 if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2 1529 + offset1 * 21] != 0xFF) 1530 pwrinfo->ht40maxoffset[rfpath][group] = 1531 (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G 1532 + offset2 + offset1 * 21] >> (rfpath * 4)) 1533 & 0xF; 1534 else 1535 pwrinfo->ht40maxoffset[rfpath][group] = 1536 EEPROM_DEFAULT_HT40_PWRMAXOFFSET; 1537 if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2 1538 + offset1 * 21] != 0xFF) 1539 pwrinfo->ht20maxoffset[rfpath][group] = 1540 (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + 1541 offset2 + offset1 * 21] >> (rfpath * 4)) & 1542 0xF; 1543 else 1544 pwrinfo->ht20maxoffset[rfpath][group] = 1545 EEPROM_DEFAULT_HT20_PWRMAXOFFSET; 1546 } 1547 } 1548 if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) { 1549 /* 5GL */ 1550 pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F; 1551 pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F; 1552 /* 5GM */ 1553 pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F; 1554 pwrinfo->tssi_b[1] = 1555 (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 | 1556 (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2; 1557 /* 5GH */ 1558 pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] & 1559 0xF0) >> 4 | 1560 (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4; 1561 pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] & 1562 0xFC) >> 2; 1563 } else { 1564 for (i = 0; i < 3; i++) { 1565 pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI; 1566 pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI; 1567 } 1568 } 1569 } 1570 1571 static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw, 1572 bool autoload_fail, u8 *hwinfo) 1573 { 1574 struct rtl_priv *rtlpriv = rtl_priv(hw); 1575 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1576 struct txpower_info pwrinfo; 1577 u8 tempval[2], i, pwr, diff; 1578 u32 ch, rfPath, group; 1579 1580 _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail); 1581 if (!autoload_fail) { 1582 /* bit0~2 */ 1583 rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7); 1584 rtlefuse->eeprom_thermalmeter = 1585 hwinfo[EEPROM_THERMAL_METER] & 0x1f; 1586 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K]; 1587 tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03; 1588 tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2; 1589 rtlefuse->txpwr_fromeprom = true; 1590 if (IS_92D_D_CUT(rtlpriv->rtlhal.version) || 1591 IS_92D_E_CUT(rtlpriv->rtlhal.version)) { 1592 rtlefuse->internal_pa_5g[0] = 1593 !((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6); 1594 rtlefuse->internal_pa_5g[1] = 1595 !((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6); 1596 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1597 "Is D cut,Internal PA0 %d Internal PA1 %d\n", 1598 rtlefuse->internal_pa_5g[0], 1599 rtlefuse->internal_pa_5g[1]); 1600 } 1601 rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6]; 1602 rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7]; 1603 } else { 1604 rtlefuse->eeprom_regulatory = 0; 1605 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; 1606 rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP; 1607 tempval[0] = tempval[1] = 3; 1608 } 1609 1610 /* Use default value to fill parameters if 1611 * efuse is not filled on some place. */ 1612 1613 /* ThermalMeter from EEPROM */ 1614 if (rtlefuse->eeprom_thermalmeter < 0x06 || 1615 rtlefuse->eeprom_thermalmeter > 0x1c) 1616 rtlefuse->eeprom_thermalmeter = 0x12; 1617 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 1618 1619 /* check XTAL_K */ 1620 if (rtlefuse->crystalcap == 0xFF) 1621 rtlefuse->crystalcap = 0; 1622 if (rtlefuse->eeprom_regulatory > 3) 1623 rtlefuse->eeprom_regulatory = 0; 1624 1625 for (i = 0; i < 2; i++) { 1626 switch (tempval[i]) { 1627 case 0: 1628 tempval[i] = 5; 1629 break; 1630 case 1: 1631 tempval[i] = 4; 1632 break; 1633 case 2: 1634 tempval[i] = 3; 1635 break; 1636 case 3: 1637 default: 1638 tempval[i] = 0; 1639 break; 1640 } 1641 } 1642 1643 rtlefuse->delta_iqk = tempval[0]; 1644 if (tempval[1] > 0) 1645 rtlefuse->delta_lck = tempval[1] - 1; 1646 if (rtlefuse->eeprom_c9 == 0xFF) 1647 rtlefuse->eeprom_c9 = 0x00; 1648 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, 1649 "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 1650 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, 1651 "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1652 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, 1653 "CrystalCap = 0x%x\n", rtlefuse->crystalcap); 1654 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, 1655 "Delta_IQK = 0x%x Delta_LCK = 0x%x\n", 1656 rtlefuse->delta_iqk, rtlefuse->delta_lck); 1657 1658 for (rfPath = 0; rfPath < RF6052_MAX_PATH; rfPath++) { 1659 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) { 1660 group = rtl92d_get_chnlgroup_fromarray((u8) ch); 1661 if (ch < CHANNEL_MAX_NUMBER_2G) 1662 rtlefuse->txpwrlevel_cck[rfPath][ch] = 1663 pwrinfo.cck_index[rfPath][group]; 1664 rtlefuse->txpwrlevel_ht40_1s[rfPath][ch] = 1665 pwrinfo.ht40_1sindex[rfPath][group]; 1666 rtlefuse->txpwr_ht20diff[rfPath][ch] = 1667 pwrinfo.ht20indexdiff[rfPath][group]; 1668 rtlefuse->txpwr_legacyhtdiff[rfPath][ch] = 1669 pwrinfo.ofdmindexdiff[rfPath][group]; 1670 rtlefuse->pwrgroup_ht20[rfPath][ch] = 1671 pwrinfo.ht20maxoffset[rfPath][group]; 1672 rtlefuse->pwrgroup_ht40[rfPath][ch] = 1673 pwrinfo.ht40maxoffset[rfPath][group]; 1674 pwr = pwrinfo.ht40_1sindex[rfPath][group]; 1675 diff = pwrinfo.ht40_2sindexdiff[rfPath][group]; 1676 rtlefuse->txpwrlevel_ht40_2s[rfPath][ch] = 1677 (pwr > diff) ? (pwr - diff) : 0; 1678 } 1679 } 1680 } 1681 1682 static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw, 1683 u8 *content) 1684 { 1685 struct rtl_priv *rtlpriv = rtl_priv(hw); 1686 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1687 u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION]; 1688 1689 if (macphy_crvalue & BIT(3)) { 1690 rtlhal->macphymode = SINGLEMAC_SINGLEPHY; 1691 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1692 "MacPhyMode SINGLEMAC_SINGLEPHY\n"); 1693 } else { 1694 rtlhal->macphymode = DUALMAC_DUALPHY; 1695 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1696 "MacPhyMode DUALMAC_DUALPHY\n"); 1697 } 1698 } 1699 1700 static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw, 1701 u8 *content) 1702 { 1703 _rtl92de_read_macphymode_from_prom(hw, content); 1704 rtl92d_phy_config_macphymode(hw); 1705 rtl92d_phy_config_macphymode_info(hw); 1706 } 1707 1708 static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) 1709 { 1710 struct rtl_priv *rtlpriv = rtl_priv(hw); 1711 enum version_8192d chipver = rtlpriv->rtlhal.version; 1712 u8 cutvalue[2]; 1713 u16 chipvalue; 1714 1715 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H, 1716 &cutvalue[1]); 1717 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L, 1718 &cutvalue[0]); 1719 chipvalue = (cutvalue[1] << 8) | cutvalue[0]; 1720 switch (chipvalue) { 1721 case 0xAA55: 1722 chipver |= CHIP_92D_C_CUT; 1723 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n"); 1724 break; 1725 case 0x9966: 1726 chipver |= CHIP_92D_D_CUT; 1727 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n"); 1728 break; 1729 case 0xCC33: 1730 chipver |= CHIP_92D_E_CUT; 1731 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n"); 1732 break; 1733 default: 1734 chipver |= CHIP_92D_D_CUT; 1735 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Unknown CUT!\n"); 1736 break; 1737 } 1738 rtlpriv->rtlhal.version = chipver; 1739 } 1740 1741 static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) 1742 { 1743 struct rtl_priv *rtlpriv = rtl_priv(hw); 1744 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1745 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1746 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, 1747 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D, 1748 EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 1749 COUNTRY_CODE_WORLD_WIDE_13}; 1750 int i; 1751 u16 usvalue; 1752 u8 *hwinfo; 1753 1754 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 1755 if (!hwinfo) 1756 return; 1757 1758 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 1759 goto exit; 1760 1761 _rtl92de_efuse_update_chip_version(hw); 1762 _rtl92de_read_macphymode_and_bandtype(hw, hwinfo); 1763 1764 /* Read Permanent MAC address for 2nd interface */ 1765 if (rtlhal->interfaceindex != 0) { 1766 for (i = 0; i < 6; i += 2) { 1767 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i]; 1768 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; 1769 } 1770 } 1771 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, 1772 rtlefuse->dev_addr); 1773 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); 1774 _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo); 1775 1776 /* Read Channel Plan */ 1777 switch (rtlhal->bandset) { 1778 case BAND_ON_2_4G: 1779 rtlefuse->channel_plan = COUNTRY_CODE_TELEC; 1780 break; 1781 case BAND_ON_5G: 1782 rtlefuse->channel_plan = COUNTRY_CODE_FCC; 1783 break; 1784 case BAND_ON_BOTH: 1785 rtlefuse->channel_plan = COUNTRY_CODE_FCC; 1786 break; 1787 default: 1788 rtlefuse->channel_plan = COUNTRY_CODE_FCC; 1789 break; 1790 } 1791 rtlefuse->txpwr_fromeprom = true; 1792 exit: 1793 kfree(hwinfo); 1794 } 1795 1796 void rtl92de_read_eeprom_info(struct ieee80211_hw *hw) 1797 { 1798 struct rtl_priv *rtlpriv = rtl_priv(hw); 1799 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1800 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1801 u8 tmp_u1b; 1802 1803 rtlhal->version = _rtl92de_read_chip_version(hw); 1804 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 1805 rtlefuse->autoload_status = tmp_u1b; 1806 if (tmp_u1b & BIT(4)) { 1807 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 1808 rtlefuse->epromtype = EEPROM_93C46; 1809 } else { 1810 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 1811 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 1812 } 1813 if (tmp_u1b & BIT(5)) { 1814 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1815 1816 rtlefuse->autoload_failflag = false; 1817 _rtl92de_read_adapter_info(hw); 1818 } else { 1819 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n"); 1820 } 1821 return; 1822 } 1823 1824 static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw, 1825 struct ieee80211_sta *sta) 1826 { 1827 struct rtl_priv *rtlpriv = rtl_priv(hw); 1828 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1829 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1830 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1831 u32 ratr_value; 1832 u8 ratr_index = 0; 1833 u8 nmode = mac->ht_enable; 1834 u8 mimo_ps = IEEE80211_SMPS_OFF; 1835 u16 shortgi_rate; 1836 u32 tmp_ratr_value; 1837 u8 curtxbw_40mhz = mac->bw_40; 1838 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1839 1 : 0; 1840 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1841 1 : 0; 1842 enum wireless_mode wirelessmode = mac->mode; 1843 1844 if (rtlhal->current_bandtype == BAND_ON_5G) 1845 ratr_value = sta->supp_rates[1] << 4; 1846 else 1847 ratr_value = sta->supp_rates[0]; 1848 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1849 sta->ht_cap.mcs.rx_mask[0] << 12); 1850 switch (wirelessmode) { 1851 case WIRELESS_MODE_A: 1852 ratr_value &= 0x00000FF0; 1853 break; 1854 case WIRELESS_MODE_B: 1855 if (ratr_value & 0x0000000c) 1856 ratr_value &= 0x0000000d; 1857 else 1858 ratr_value &= 0x0000000f; 1859 break; 1860 case WIRELESS_MODE_G: 1861 ratr_value &= 0x00000FF5; 1862 break; 1863 case WIRELESS_MODE_N_24G: 1864 case WIRELESS_MODE_N_5G: 1865 nmode = 1; 1866 if (mimo_ps == IEEE80211_SMPS_STATIC) { 1867 ratr_value &= 0x0007F005; 1868 } else { 1869 u32 ratr_mask; 1870 1871 if (get_rf_type(rtlphy) == RF_1T2R || 1872 get_rf_type(rtlphy) == RF_1T1R) { 1873 ratr_mask = 0x000ff005; 1874 } else { 1875 ratr_mask = 0x0f0ff005; 1876 } 1877 1878 ratr_value &= ratr_mask; 1879 } 1880 break; 1881 default: 1882 if (rtlphy->rf_type == RF_1T2R) 1883 ratr_value &= 0x000ff0ff; 1884 else 1885 ratr_value &= 0x0f0ff0ff; 1886 1887 break; 1888 } 1889 ratr_value &= 0x0FFFFFFF; 1890 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) || 1891 (!curtxbw_40mhz && curshortgi_20mhz))) { 1892 ratr_value |= 0x10000000; 1893 tmp_ratr_value = (ratr_value >> 12); 1894 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 1895 if ((1 << shortgi_rate) & tmp_ratr_value) 1896 break; 1897 } 1898 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 1899 (shortgi_rate << 4) | (shortgi_rate); 1900 } 1901 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 1902 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", 1903 rtl_read_dword(rtlpriv, REG_ARFR0)); 1904 } 1905 1906 static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, 1907 struct ieee80211_sta *sta, u8 rssi_level) 1908 { 1909 struct rtl_priv *rtlpriv = rtl_priv(hw); 1910 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1911 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1912 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1913 struct rtl_sta_info *sta_entry = NULL; 1914 u32 ratr_bitmap; 1915 u8 ratr_index; 1916 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; 1917 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1918 1 : 0; 1919 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1920 1 : 0; 1921 enum wireless_mode wirelessmode = 0; 1922 bool shortgi = false; 1923 u32 value[2]; 1924 u8 macid = 0; 1925 u8 mimo_ps = IEEE80211_SMPS_OFF; 1926 1927 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 1928 mimo_ps = sta_entry->mimo_ps; 1929 wirelessmode = sta_entry->wireless_mode; 1930 if (mac->opmode == NL80211_IFTYPE_STATION) 1931 curtxbw_40mhz = mac->bw_40; 1932 else if (mac->opmode == NL80211_IFTYPE_AP || 1933 mac->opmode == NL80211_IFTYPE_ADHOC) 1934 macid = sta->aid + 1; 1935 1936 if (rtlhal->current_bandtype == BAND_ON_5G) 1937 ratr_bitmap = sta->supp_rates[1] << 4; 1938 else 1939 ratr_bitmap = sta->supp_rates[0]; 1940 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1941 sta->ht_cap.mcs.rx_mask[0] << 12); 1942 switch (wirelessmode) { 1943 case WIRELESS_MODE_B: 1944 ratr_index = RATR_INX_WIRELESS_B; 1945 if (ratr_bitmap & 0x0000000c) 1946 ratr_bitmap &= 0x0000000d; 1947 else 1948 ratr_bitmap &= 0x0000000f; 1949 break; 1950 case WIRELESS_MODE_G: 1951 ratr_index = RATR_INX_WIRELESS_GB; 1952 1953 if (rssi_level == 1) 1954 ratr_bitmap &= 0x00000f00; 1955 else if (rssi_level == 2) 1956 ratr_bitmap &= 0x00000ff0; 1957 else 1958 ratr_bitmap &= 0x00000ff5; 1959 break; 1960 case WIRELESS_MODE_A: 1961 ratr_index = RATR_INX_WIRELESS_G; 1962 ratr_bitmap &= 0x00000ff0; 1963 break; 1964 case WIRELESS_MODE_N_24G: 1965 case WIRELESS_MODE_N_5G: 1966 if (wirelessmode == WIRELESS_MODE_N_24G) 1967 ratr_index = RATR_INX_WIRELESS_NGB; 1968 else 1969 ratr_index = RATR_INX_WIRELESS_NG; 1970 if (mimo_ps == IEEE80211_SMPS_STATIC) { 1971 if (rssi_level == 1) 1972 ratr_bitmap &= 0x00070000; 1973 else if (rssi_level == 2) 1974 ratr_bitmap &= 0x0007f000; 1975 else 1976 ratr_bitmap &= 0x0007f005; 1977 } else { 1978 if (rtlphy->rf_type == RF_1T2R || 1979 rtlphy->rf_type == RF_1T1R) { 1980 if (curtxbw_40mhz) { 1981 if (rssi_level == 1) 1982 ratr_bitmap &= 0x000f0000; 1983 else if (rssi_level == 2) 1984 ratr_bitmap &= 0x000ff000; 1985 else 1986 ratr_bitmap &= 0x000ff015; 1987 } else { 1988 if (rssi_level == 1) 1989 ratr_bitmap &= 0x000f0000; 1990 else if (rssi_level == 2) 1991 ratr_bitmap &= 0x000ff000; 1992 else 1993 ratr_bitmap &= 0x000ff005; 1994 } 1995 } else { 1996 if (curtxbw_40mhz) { 1997 if (rssi_level == 1) 1998 ratr_bitmap &= 0x0f0f0000; 1999 else if (rssi_level == 2) 2000 ratr_bitmap &= 0x0f0ff000; 2001 else 2002 ratr_bitmap &= 0x0f0ff015; 2003 } else { 2004 if (rssi_level == 1) 2005 ratr_bitmap &= 0x0f0f0000; 2006 else if (rssi_level == 2) 2007 ratr_bitmap &= 0x0f0ff000; 2008 else 2009 ratr_bitmap &= 0x0f0ff005; 2010 } 2011 } 2012 } 2013 if ((curtxbw_40mhz && curshortgi_40mhz) || 2014 (!curtxbw_40mhz && curshortgi_20mhz)) { 2015 2016 if (macid == 0) 2017 shortgi = true; 2018 else if (macid == 1) 2019 shortgi = false; 2020 } 2021 break; 2022 default: 2023 ratr_index = RATR_INX_WIRELESS_NGB; 2024 2025 if (rtlphy->rf_type == RF_1T2R) 2026 ratr_bitmap &= 0x000ff0ff; 2027 else 2028 ratr_bitmap &= 0x0f0ff0ff; 2029 break; 2030 } 2031 2032 value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28); 2033 value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80; 2034 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2035 "ratr_bitmap :%x value0:%x value1:%x\n", 2036 ratr_bitmap, value[0], value[1]); 2037 rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value); 2038 if (macid != 0) 2039 sta_entry->ratr_index = ratr_index; 2040 } 2041 2042 void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw, 2043 struct ieee80211_sta *sta, u8 rssi_level) 2044 { 2045 struct rtl_priv *rtlpriv = rtl_priv(hw); 2046 2047 if (rtlpriv->dm.useramask) 2048 rtl92de_update_hal_rate_mask(hw, sta, rssi_level); 2049 else 2050 rtl92de_update_hal_rate_table(hw, sta); 2051 } 2052 2053 void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw) 2054 { 2055 struct rtl_priv *rtlpriv = rtl_priv(hw); 2056 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2057 u16 sifs_timer; 2058 2059 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2060 &mac->slot_time); 2061 if (!mac->ht_enable) 2062 sifs_timer = 0x0a0a; 2063 else 2064 sifs_timer = 0x1010; 2065 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2066 } 2067 2068 bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2069 { 2070 struct rtl_priv *rtlpriv = rtl_priv(hw); 2071 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2072 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2073 enum rf_pwrstate e_rfpowerstate_toset; 2074 u8 u1tmp; 2075 bool actuallyset = false; 2076 unsigned long flag; 2077 2078 if (rtlpci->being_init_adapter) 2079 return false; 2080 if (ppsc->swrf_processing) 2081 return false; 2082 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2083 if (ppsc->rfchange_inprogress) { 2084 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2085 return false; 2086 } else { 2087 ppsc->rfchange_inprogress = true; 2088 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2089 } 2090 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv, 2091 REG_MAC_PINMUX_CFG) & ~(BIT(3))); 2092 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); 2093 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; 2094 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) { 2095 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2096 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2097 e_rfpowerstate_toset = ERFON; 2098 ppsc->hwradiooff = false; 2099 actuallyset = true; 2100 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) { 2101 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2102 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 2103 e_rfpowerstate_toset = ERFOFF; 2104 ppsc->hwradiooff = true; 2105 actuallyset = true; 2106 } 2107 if (actuallyset) { 2108 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2109 ppsc->rfchange_inprogress = false; 2110 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2111 } else { 2112 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 2113 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2114 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2115 ppsc->rfchange_inprogress = false; 2116 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2117 } 2118 *valid = 1; 2119 return !ppsc->hwradiooff; 2120 } 2121 2122 void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, 2123 u8 *p_macaddr, bool is_group, u8 enc_algo, 2124 bool is_wepkey, bool clear_all) 2125 { 2126 struct rtl_priv *rtlpriv = rtl_priv(hw); 2127 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2128 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2129 u8 *macaddr = p_macaddr; 2130 u32 entry_id; 2131 bool is_pairwise = false; 2132 static u8 cam_const_addr[4][6] = { 2133 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2134 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2135 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2136 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2137 }; 2138 static u8 cam_const_broad[] = { 2139 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2140 }; 2141 2142 if (clear_all) { 2143 u8 idx; 2144 u8 cam_offset = 0; 2145 u8 clear_number = 5; 2146 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2147 for (idx = 0; idx < clear_number; idx++) { 2148 rtl_cam_mark_invalid(hw, cam_offset + idx); 2149 rtl_cam_empty_entry(hw, cam_offset + idx); 2150 2151 if (idx < 5) { 2152 memset(rtlpriv->sec.key_buf[idx], 0, 2153 MAX_KEY_LEN); 2154 rtlpriv->sec.key_len[idx] = 0; 2155 } 2156 } 2157 } else { 2158 switch (enc_algo) { 2159 case WEP40_ENCRYPTION: 2160 enc_algo = CAM_WEP40; 2161 break; 2162 case WEP104_ENCRYPTION: 2163 enc_algo = CAM_WEP104; 2164 break; 2165 case TKIP_ENCRYPTION: 2166 enc_algo = CAM_TKIP; 2167 break; 2168 case AESCCMP_ENCRYPTION: 2169 enc_algo = CAM_AES; 2170 break; 2171 default: 2172 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2173 "switch case %#x not processed\n", enc_algo); 2174 enc_algo = CAM_TKIP; 2175 break; 2176 } 2177 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2178 macaddr = cam_const_addr[key_index]; 2179 entry_id = key_index; 2180 } else { 2181 if (is_group) { 2182 macaddr = cam_const_broad; 2183 entry_id = key_index; 2184 } else { 2185 if (mac->opmode == NL80211_IFTYPE_AP) { 2186 entry_id = rtl_cam_get_free_entry(hw, 2187 p_macaddr); 2188 if (entry_id >= TOTAL_CAM_ENTRY) { 2189 RT_TRACE(rtlpriv, COMP_SEC, 2190 DBG_EMERG, 2191 "Can not find free hw security cam entry\n"); 2192 return; 2193 } 2194 } else { 2195 entry_id = CAM_PAIRWISE_KEY_POSITION; 2196 } 2197 key_index = PAIRWISE_KEYIDX; 2198 is_pairwise = true; 2199 } 2200 } 2201 if (rtlpriv->sec.key_len[key_index] == 0) { 2202 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2203 "delete one entry, entry_id is %d\n", 2204 entry_id); 2205 if (mac->opmode == NL80211_IFTYPE_AP) 2206 rtl_cam_del_entry(hw, p_macaddr); 2207 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2208 } else { 2209 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 2210 "The insert KEY length is %d\n", 2211 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); 2212 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 2213 "The insert KEY is %x %x\n", 2214 rtlpriv->sec.key_buf[0][0], 2215 rtlpriv->sec.key_buf[0][1]); 2216 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2217 "add one entry\n"); 2218 if (is_pairwise) { 2219 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, 2220 "Pairwise Key content", 2221 rtlpriv->sec.pairwise_key, 2222 rtlpriv-> 2223 sec.key_len[PAIRWISE_KEYIDX]); 2224 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2225 "set Pairwise key\n"); 2226 rtl_cam_add_one_entry(hw, macaddr, key_index, 2227 entry_id, enc_algo, 2228 CAM_CONFIG_NO_USEDK, 2229 rtlpriv-> 2230 sec.key_buf[key_index]); 2231 } else { 2232 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2233 "set group key\n"); 2234 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2235 rtl_cam_add_one_entry(hw, 2236 rtlefuse->dev_addr, 2237 PAIRWISE_KEYIDX, 2238 CAM_PAIRWISE_KEY_POSITION, 2239 enc_algo, CAM_CONFIG_NO_USEDK, 2240 rtlpriv->sec.key_buf[entry_id]); 2241 } 2242 rtl_cam_add_one_entry(hw, macaddr, key_index, 2243 entry_id, enc_algo, 2244 CAM_CONFIG_NO_USEDK, 2245 rtlpriv->sec.key_buf 2246 [entry_id]); 2247 } 2248 } 2249 } 2250 } 2251 2252 void rtl92de_suspend(struct ieee80211_hw *hw) 2253 { 2254 struct rtl_priv *rtlpriv = rtl_priv(hw); 2255 2256 rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv, 2257 REG_MAC_PHY_CTRL_NORMAL); 2258 } 2259 2260 void rtl92de_resume(struct ieee80211_hw *hw) 2261 { 2262 struct rtl_priv *rtlpriv = rtl_priv(hw); 2263 2264 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL, 2265 rtlpriv->rtlhal.macphyctl_reg); 2266 } 2267