1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30 #ifndef __RTL92D_DEF_H__ 31 #define __RTL92D_DEF_H__ 32 33 /* Min Spacing related settings. */ 34 #define MAX_MSS_DENSITY_2T 0x13 35 #define MAX_MSS_DENSITY_1T 0x0A 36 37 #define RF6052_MAX_TX_PWR 0x3F 38 #define RF6052_MAX_PATH 2 39 40 #define PHY_RSSI_SLID_WIN_MAX 100 41 #define PHY_LINKQUALITY_SLID_WIN_MAX 20 42 #define PHY_BEACON_RSSI_SLID_WIN_MAX 10 43 44 #define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK) 45 46 #define RX_SMOOTH_FACTOR 20 47 48 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 49 #define HAL_PRIME_CHNL_OFFSET_LOWER 1 50 #define HAL_PRIME_CHNL_OFFSET_UPPER 2 51 52 #define RX_MPDU_QUEUE 0 53 #define RX_CMD_QUEUE 1 54 55 #define C2H_RX_CMD_HDR_LEN 8 56 #define GET_C2H_CMD_CMD_LEN(__prxhdr) \ 57 LE_BITS_TO_4BYTE((__prxhdr), 0, 16) 58 #define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \ 59 LE_BITS_TO_4BYTE((__prxhdr), 16, 8) 60 #define GET_C2H_CMD_CMD_SEQ(__prxhdr) \ 61 LE_BITS_TO_4BYTE((__prxhdr), 24, 7) 62 #define GET_C2H_CMD_CONTINUE(__prxhdr) \ 63 LE_BITS_TO_4BYTE((__prxhdr), 31, 1) 64 #define GET_C2H_CMD_CONTENT(__prxhdr) \ 65 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN) 66 67 #define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \ 68 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8) 69 #define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \ 70 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8) 71 #define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \ 72 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16) 73 #define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \ 74 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5) 75 #define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \ 76 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1) 77 #define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \ 78 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5) 79 #define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \ 80 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1) 81 #define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \ 82 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4) 83 #define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \ 84 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12) 85 86 enum version_8192d { 87 VERSION_TEST_CHIP_88C = 0x0000, 88 VERSION_TEST_CHIP_92C = 0x0020, 89 VERSION_TEST_UMC_CHIP_8723 = 0x0081, 90 VERSION_NORMAL_TSMC_CHIP_88C = 0x0008, 91 VERSION_NORMAL_TSMC_CHIP_92C = 0x0028, 92 VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x0018, 93 VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x0088, 94 VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x00a8, 95 VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x0098, 96 VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT = 0x0089, 97 VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT = 0x1089, 98 VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x1088, 99 VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x10a8, 100 VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x1090, 101 VERSION_TEST_CHIP_92D_SINGLEPHY = 0x0022, 102 VERSION_TEST_CHIP_92D_DUALPHY = 0x0002, 103 VERSION_NORMAL_CHIP_92D_SINGLEPHY = 0x002a, 104 VERSION_NORMAL_CHIP_92D_DUALPHY = 0x000a, 105 VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x202a, 106 VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x200a, 107 VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0x302a, 108 VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x300a, 109 VERSION_NORMAL_CHIP_92D_E_CUT_SINGLEPHY = 0x402a, 110 VERSION_NORMAL_CHIP_92D_E_CUT_DUALPHY = 0x400a, 111 }; 112 113 /* for 92D */ 114 #define CHIP_92D_SINGLEPHY BIT(9) 115 116 /* Chip specific */ 117 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) 118 #define CHIP_BONDING_92C_1T2R 0x1 119 #define CHIP_BONDING_88C_USB_MCARD 0x2 120 #define CHIP_BONDING_88C_USB_HP 0x1 121 122 /* [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3 */ 123 /* [7] Manufacturer: TSMC=0, UMC=1 */ 124 /* [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2 */ 125 /* [3] Chip type: TEST=0, NORMAL=1 */ 126 /* [2:0] IC type: 81xxC=0, 8723=1, 92D=2 */ 127 #define CHIP_8723 BIT(0) 128 #define CHIP_92D BIT(1) 129 #define NORMAL_CHIP BIT(3) 130 #define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6))) 131 #define RF_TYPE_1T2R BIT(4) 132 #define RF_TYPE_2T2R BIT(5) 133 #define CHIP_VENDOR_UMC BIT(7) 134 #define CHIP_92D_B_CUT BIT(12) 135 #define CHIP_92D_C_CUT BIT(13) 136 #define CHIP_92D_D_CUT (BIT(13)|BIT(12)) 137 #define CHIP_92D_E_CUT BIT(14) 138 139 /* MASK */ 140 #define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2)) 141 #define CHIP_TYPE_MASK BIT(3) 142 #define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6)) 143 #define MANUFACTUER_MASK BIT(7) 144 #define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8)) 145 #define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12)) 146 147 148 /* Get element */ 149 #define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK) 150 #define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK) 151 #define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK) 152 #define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK) 153 #define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK) 154 #define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK) 155 156 #define IS_1T1R(version) ((GET_CVID_RF_TYPE(version)) ? \ 157 false : true) 158 #define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == \ 159 RF_TYPE_1T2R) ? true : false) 160 #define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == \ 161 RF_TYPE_2T2R) ? true : false) 162 163 #define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? \ 164 (IS_2T2R(version) ? true : false) : false) 165 #define IS_92D(version) ((GET_CVID_IC_TYPE(version) == \ 166 CHIP_92D) ? true : false) 167 #define IS_92D_C_CUT(version) ((IS_92D(version)) ? \ 168 ((GET_CVID_CUT_VERSION(version) == \ 169 CHIP_92D_C_CUT) ? true : false) : false) 170 #define IS_92D_D_CUT(version) ((IS_92D(version)) ? \ 171 ((GET_CVID_CUT_VERSION(version) == \ 172 CHIP_92D_D_CUT) ? true : false) : false) 173 #define IS_92D_E_CUT(version) ((IS_92D(version)) ? \ 174 ((GET_CVID_CUT_VERSION(version) == \ 175 CHIP_92D_E_CUT) ? true : false) : false) 176 177 enum rf_optype { 178 RF_OP_BY_SW_3WIRE = 0, 179 RF_OP_BY_FW, 180 RF_OP_MAX 181 }; 182 183 enum rtl_desc_qsel { 184 QSLT_BK = 0x2, 185 QSLT_BE = 0x0, 186 QSLT_VI = 0x5, 187 QSLT_VO = 0x7, 188 QSLT_BEACON = 0x10, 189 QSLT_HIGH = 0x11, 190 QSLT_MGNT = 0x12, 191 QSLT_CMD = 0x13, 192 }; 193 194 enum channel_plan { 195 CHPL_FCC = 0, 196 CHPL_IC = 1, 197 CHPL_ETSI = 2, 198 CHPL_SPAIN = 3, 199 CHPL_FRANCE = 4, 200 CHPL_MKK = 5, 201 CHPL_MKK1 = 6, 202 CHPL_ISRAEL = 7, 203 CHPL_TELEC = 8, 204 CHPL_GLOBAL = 9, 205 CHPL_WORLD = 10, 206 }; 207 208 struct phy_sts_cck_8192d { 209 u8 adc_pwdb_X[4]; 210 u8 sq_rpt; 211 u8 cck_agc_rpt; 212 }; 213 214 struct h2c_cmd_8192c { 215 u8 element_id; 216 u32 cmd_len; 217 u8 *p_cmdbuffer; 218 }; 219 220 struct txpower_info { 221 u8 cck_index[RF6052_MAX_PATH][CHANNEL_GROUP_MAX]; 222 u8 ht40_1sindex[RF6052_MAX_PATH][CHANNEL_GROUP_MAX]; 223 u8 ht40_2sindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX]; 224 u8 ht20indexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX]; 225 u8 ofdmindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX]; 226 u8 ht40maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX]; 227 u8 ht20maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX]; 228 u8 tssi_a[3]; /* 5GL/5GM/5GH */ 229 u8 tssi_b[3]; 230 }; 231 232 #endif 233