1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4 #ifndef __RTL92D_DEF_H__ 5 #define __RTL92D_DEF_H__ 6 7 /* Min Spacing related settings. */ 8 #define MAX_MSS_DENSITY_2T 0x13 9 #define MAX_MSS_DENSITY_1T 0x0A 10 11 #define RF6052_MAX_TX_PWR 0x3F 12 #define RF6052_MAX_PATH 2 13 14 #define PHY_RSSI_SLID_WIN_MAX 100 15 #define PHY_LINKQUALITY_SLID_WIN_MAX 20 16 #define PHY_BEACON_RSSI_SLID_WIN_MAX 10 17 18 #define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK) 19 20 #define RX_SMOOTH_FACTOR 20 21 22 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 23 #define HAL_PRIME_CHNL_OFFSET_LOWER 1 24 #define HAL_PRIME_CHNL_OFFSET_UPPER 2 25 26 #define RX_MPDU_QUEUE 0 27 #define RX_CMD_QUEUE 1 28 29 #define C2H_RX_CMD_HDR_LEN 8 30 #define GET_C2H_CMD_CMD_LEN(__prxhdr) \ 31 LE_BITS_TO_4BYTE((__prxhdr), 0, 16) 32 #define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \ 33 LE_BITS_TO_4BYTE((__prxhdr), 16, 8) 34 #define GET_C2H_CMD_CMD_SEQ(__prxhdr) \ 35 LE_BITS_TO_4BYTE((__prxhdr), 24, 7) 36 #define GET_C2H_CMD_CONTINUE(__prxhdr) \ 37 LE_BITS_TO_4BYTE((__prxhdr), 31, 1) 38 #define GET_C2H_CMD_CONTENT(__prxhdr) \ 39 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN) 40 41 #define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \ 42 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8) 43 #define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \ 44 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8) 45 #define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \ 46 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16) 47 #define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \ 48 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5) 49 #define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \ 50 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1) 51 #define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \ 52 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5) 53 #define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \ 54 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1) 55 #define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \ 56 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4) 57 #define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \ 58 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12) 59 60 enum version_8192d { 61 VERSION_TEST_CHIP_88C = 0x0000, 62 VERSION_TEST_CHIP_92C = 0x0020, 63 VERSION_TEST_UMC_CHIP_8723 = 0x0081, 64 VERSION_NORMAL_TSMC_CHIP_88C = 0x0008, 65 VERSION_NORMAL_TSMC_CHIP_92C = 0x0028, 66 VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x0018, 67 VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x0088, 68 VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x00a8, 69 VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x0098, 70 VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT = 0x0089, 71 VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT = 0x1089, 72 VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x1088, 73 VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x10a8, 74 VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x1090, 75 VERSION_TEST_CHIP_92D_SINGLEPHY = 0x0022, 76 VERSION_TEST_CHIP_92D_DUALPHY = 0x0002, 77 VERSION_NORMAL_CHIP_92D_SINGLEPHY = 0x002a, 78 VERSION_NORMAL_CHIP_92D_DUALPHY = 0x000a, 79 VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x202a, 80 VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x200a, 81 VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0x302a, 82 VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x300a, 83 VERSION_NORMAL_CHIP_92D_E_CUT_SINGLEPHY = 0x402a, 84 VERSION_NORMAL_CHIP_92D_E_CUT_DUALPHY = 0x400a, 85 }; 86 87 /* for 92D */ 88 #define CHIP_92D_SINGLEPHY BIT(9) 89 90 /* Chip specific */ 91 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) 92 #define CHIP_BONDING_92C_1T2R 0x1 93 #define CHIP_BONDING_88C_USB_MCARD 0x2 94 #define CHIP_BONDING_88C_USB_HP 0x1 95 96 /* [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3 */ 97 /* [7] Manufacturer: TSMC=0, UMC=1 */ 98 /* [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2 */ 99 /* [3] Chip type: TEST=0, NORMAL=1 */ 100 /* [2:0] IC type: 81xxC=0, 8723=1, 92D=2 */ 101 #define CHIP_8723 BIT(0) 102 #define CHIP_92D BIT(1) 103 #define NORMAL_CHIP BIT(3) 104 #define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6))) 105 #define RF_TYPE_1T2R BIT(4) 106 #define RF_TYPE_2T2R BIT(5) 107 #define CHIP_VENDOR_UMC BIT(7) 108 #define CHIP_92D_B_CUT BIT(12) 109 #define CHIP_92D_C_CUT BIT(13) 110 #define CHIP_92D_D_CUT (BIT(13)|BIT(12)) 111 #define CHIP_92D_E_CUT BIT(14) 112 113 /* MASK */ 114 #define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2)) 115 #define CHIP_TYPE_MASK BIT(3) 116 #define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6)) 117 #define MANUFACTUER_MASK BIT(7) 118 #define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8)) 119 #define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12)) 120 121 122 /* Get element */ 123 #define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK) 124 #define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK) 125 #define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK) 126 #define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK) 127 #define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK) 128 #define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK) 129 130 #define IS_1T1R(version) ((GET_CVID_RF_TYPE(version)) ? \ 131 false : true) 132 #define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == \ 133 RF_TYPE_1T2R) ? true : false) 134 #define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == \ 135 RF_TYPE_2T2R) ? true : false) 136 137 #define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? \ 138 (IS_2T2R(version) ? true : false) : false) 139 #define IS_92D(version) ((GET_CVID_IC_TYPE(version) == \ 140 CHIP_92D) ? true : false) 141 #define IS_92D_C_CUT(version) ((IS_92D(version)) ? \ 142 ((GET_CVID_CUT_VERSION(version) == \ 143 CHIP_92D_C_CUT) ? true : false) : false) 144 #define IS_92D_D_CUT(version) ((IS_92D(version)) ? \ 145 ((GET_CVID_CUT_VERSION(version) == \ 146 CHIP_92D_D_CUT) ? true : false) : false) 147 #define IS_92D_E_CUT(version) ((IS_92D(version)) ? \ 148 ((GET_CVID_CUT_VERSION(version) == \ 149 CHIP_92D_E_CUT) ? true : false) : false) 150 151 enum rf_optype { 152 RF_OP_BY_SW_3WIRE = 0, 153 RF_OP_BY_FW, 154 RF_OP_MAX 155 }; 156 157 enum rtl_desc_qsel { 158 QSLT_BK = 0x2, 159 QSLT_BE = 0x0, 160 QSLT_VI = 0x5, 161 QSLT_VO = 0x7, 162 QSLT_BEACON = 0x10, 163 QSLT_HIGH = 0x11, 164 QSLT_MGNT = 0x12, 165 QSLT_CMD = 0x13, 166 }; 167 168 enum channel_plan { 169 CHPL_FCC = 0, 170 CHPL_IC = 1, 171 CHPL_ETSI = 2, 172 CHPL_SPAIN = 3, 173 CHPL_FRANCE = 4, 174 CHPL_MKK = 5, 175 CHPL_MKK1 = 6, 176 CHPL_ISRAEL = 7, 177 CHPL_TELEC = 8, 178 CHPL_GLOBAL = 9, 179 CHPL_WORLD = 10, 180 }; 181 182 struct phy_sts_cck_8192d { 183 u8 adc_pwdb_X[4]; 184 u8 sq_rpt; 185 u8 cck_agc_rpt; 186 }; 187 188 struct h2c_cmd_8192c { 189 u8 element_id; 190 u32 cmd_len; 191 u8 *p_cmdbuffer; 192 }; 193 194 struct txpower_info { 195 u8 cck_index[RF6052_MAX_PATH][CHANNEL_GROUP_MAX]; 196 u8 ht40_1sindex[RF6052_MAX_PATH][CHANNEL_GROUP_MAX]; 197 u8 ht40_2sindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX]; 198 u8 ht20indexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX]; 199 u8 ofdmindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX]; 200 u8 ht40maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX]; 201 u8 ht20maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX]; 202 u8 tssi_a[3]; /* 5GL/5GM/5GH */ 203 u8 tssi_b[3]; 204 }; 205 206 #endif 207