1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 ****************************************************************************/ 29 30 #include "../wifi.h" 31 #include "../pci.h" 32 #include "../usb.h" 33 #include "../ps.h" 34 #include "../cam.h" 35 #include "../stats.h" 36 #include "reg.h" 37 #include "def.h" 38 #include "phy.h" 39 #include "rf.h" 40 #include "dm.h" 41 #include "mac.h" 42 #include "trx.h" 43 #include "../rtl8192c/fw_common.h" 44 45 #include <linux/module.h> 46 47 /* macro to shorten lines */ 48 49 #define LINK_Q ui_link_quality 50 #define RX_EVM rx_evm_percentage 51 #define RX_SIGQ rx_mimo_sig_qual 52 53 54 void rtl92c_read_chip_version(struct ieee80211_hw *hw) 55 { 56 struct rtl_priv *rtlpriv = rtl_priv(hw); 57 struct rtl_phy *rtlphy = &(rtlpriv->phy); 58 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 59 enum version_8192c chip_version = VERSION_UNKNOWN; 60 const char *versionid; 61 u32 value32; 62 63 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 64 if (value32 & TRP_VAUX_EN) { 65 chip_version = (value32 & TYPE_ID) ? VERSION_TEST_CHIP_92C : 66 VERSION_TEST_CHIP_88C; 67 } else { 68 /* Normal mass production chip. */ 69 chip_version = NORMAL_CHIP; 70 chip_version |= ((value32 & TYPE_ID) ? CHIP_92C : 0); 71 chip_version |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0); 72 if (IS_VENDOR_UMC(chip_version)) 73 chip_version |= ((value32 & CHIP_VER_RTL_MASK) ? 74 CHIP_VENDOR_UMC_B_CUT : 0); 75 if (IS_92C_SERIAL(chip_version)) { 76 value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM); 77 chip_version |= ((CHIP_BONDING_IDENTIFIER(value32) == 78 CHIP_BONDING_92C_1T2R) ? CHIP_92C_1T2R : 0); 79 } 80 } 81 rtlhal->version = (enum version_8192c)chip_version; 82 pr_info("Chip version 0x%x\n", chip_version); 83 switch (rtlhal->version) { 84 case VERSION_NORMAL_TSMC_CHIP_92C_1T2R: 85 versionid = "NORMAL_B_CHIP_92C"; 86 break; 87 case VERSION_NORMAL_TSMC_CHIP_92C: 88 versionid = "NORMAL_TSMC_CHIP_92C"; 89 break; 90 case VERSION_NORMAL_TSMC_CHIP_88C: 91 versionid = "NORMAL_TSMC_CHIP_88C"; 92 break; 93 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT: 94 versionid = "NORMAL_UMC_CHIP_i92C_1T2R_A_CUT"; 95 break; 96 case VERSION_NORMAL_UMC_CHIP_92C_A_CUT: 97 versionid = "NORMAL_UMC_CHIP_92C_A_CUT"; 98 break; 99 case VERSION_NORMAL_UMC_CHIP_88C_A_CUT: 100 versionid = "NORMAL_UMC_CHIP_88C_A_CUT"; 101 break; 102 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT: 103 versionid = "NORMAL_UMC_CHIP_92C_1T2R_B_CUT"; 104 break; 105 case VERSION_NORMAL_UMC_CHIP_92C_B_CUT: 106 versionid = "NORMAL_UMC_CHIP_92C_B_CUT"; 107 break; 108 case VERSION_NORMAL_UMC_CHIP_88C_B_CUT: 109 versionid = "NORMAL_UMC_CHIP_88C_B_CUT"; 110 break; 111 case VERSION_TEST_CHIP_92C: 112 versionid = "TEST_CHIP_92C"; 113 break; 114 case VERSION_TEST_CHIP_88C: 115 versionid = "TEST_CHIP_88C"; 116 break; 117 default: 118 versionid = "UNKNOWN"; 119 break; 120 } 121 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 122 "Chip Version ID: %s\n", versionid); 123 124 if (IS_92C_SERIAL(rtlhal->version)) 125 rtlphy->rf_type = 126 (IS_92C_1T2R(rtlhal->version)) ? RF_1T2R : RF_2T2R; 127 else 128 rtlphy->rf_type = RF_1T1R; 129 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 130 "Chip RF Type: %s\n", 131 rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R"); 132 if (get_rf_type(rtlphy) == RF_1T1R) 133 rtlpriv->dm.rfpath_rxenable[0] = true; 134 else 135 rtlpriv->dm.rfpath_rxenable[0] = 136 rtlpriv->dm.rfpath_rxenable[1] = true; 137 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 138 rtlhal->version); 139 } 140 141 /** 142 * writeLLT - LLT table write access 143 * @io: io callback 144 * @address: LLT logical address. 145 * @data: LLT data content 146 * 147 * Realtek hardware access function. 148 * 149 */ 150 bool rtl92c_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 151 { 152 struct rtl_priv *rtlpriv = rtl_priv(hw); 153 bool status = true; 154 long count = 0; 155 u32 value = _LLT_INIT_ADDR(address) | 156 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); 157 158 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 159 do { 160 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 161 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 162 break; 163 if (count > POLLING_LLT_THRESHOLD) { 164 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 165 "Failed to polling write LLT done at address %d! _LLT_OP_VALUE(%x)\n", 166 address, _LLT_OP_VALUE(value)); 167 status = false; 168 break; 169 } 170 } while (++count); 171 return status; 172 } 173 /** 174 * rtl92c_init_LLT_table - Init LLT table 175 * @io: io callback 176 * @boundary: 177 * 178 * Realtek hardware access function. 179 * 180 */ 181 bool rtl92c_init_llt_table(struct ieee80211_hw *hw, u32 boundary) 182 { 183 bool rst = true; 184 u32 i; 185 186 for (i = 0; i < (boundary - 1); i++) { 187 rst = rtl92c_llt_write(hw, i , i + 1); 188 if (true != rst) { 189 pr_err("===> %s #1 fail\n", __func__); 190 return rst; 191 } 192 } 193 /* end of list */ 194 rst = rtl92c_llt_write(hw, (boundary - 1), 0xFF); 195 if (true != rst) { 196 pr_err("===> %s #2 fail\n", __func__); 197 return rst; 198 } 199 /* Make the other pages as ring buffer 200 * This ring buffer is used as beacon buffer if we config this MAC 201 * as two MAC transfer. 202 * Otherwise used as local loopback buffer. 203 */ 204 for (i = boundary; i < LLT_LAST_ENTRY_OF_TX_PKT_BUFFER; i++) { 205 rst = rtl92c_llt_write(hw, i, (i + 1)); 206 if (true != rst) { 207 pr_err("===> %s #3 fail\n", __func__); 208 return rst; 209 } 210 } 211 /* Let last entry point to the start entry of ring buffer */ 212 rst = rtl92c_llt_write(hw, LLT_LAST_ENTRY_OF_TX_PKT_BUFFER, boundary); 213 if (true != rst) { 214 pr_err("===> %s #4 fail\n", __func__); 215 return rst; 216 } 217 return rst; 218 } 219 void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index, 220 u8 *p_macaddr, bool is_group, u8 enc_algo, 221 bool is_wepkey, bool clear_all) 222 { 223 struct rtl_priv *rtlpriv = rtl_priv(hw); 224 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 225 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 226 u8 *macaddr = p_macaddr; 227 u32 entry_id = 0; 228 bool is_pairwise = false; 229 static u8 cam_const_addr[4][6] = { 230 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 231 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 232 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 233 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 234 }; 235 static u8 cam_const_broad[] = { 236 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 237 }; 238 239 if (clear_all) { 240 u8 idx = 0; 241 u8 cam_offset = 0; 242 u8 clear_number = 5; 243 244 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 245 for (idx = 0; idx < clear_number; idx++) { 246 rtl_cam_mark_invalid(hw, cam_offset + idx); 247 rtl_cam_empty_entry(hw, cam_offset + idx); 248 if (idx < 5) { 249 memset(rtlpriv->sec.key_buf[idx], 0, 250 MAX_KEY_LEN); 251 rtlpriv->sec.key_len[idx] = 0; 252 } 253 } 254 } else { 255 switch (enc_algo) { 256 case WEP40_ENCRYPTION: 257 enc_algo = CAM_WEP40; 258 break; 259 case WEP104_ENCRYPTION: 260 enc_algo = CAM_WEP104; 261 break; 262 case TKIP_ENCRYPTION: 263 enc_algo = CAM_TKIP; 264 break; 265 case AESCCMP_ENCRYPTION: 266 enc_algo = CAM_AES; 267 break; 268 default: 269 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 270 "illegal switch case\n"); 271 enc_algo = CAM_TKIP; 272 break; 273 } 274 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 275 macaddr = cam_const_addr[key_index]; 276 entry_id = key_index; 277 } else { 278 if (is_group) { 279 macaddr = cam_const_broad; 280 entry_id = key_index; 281 } else { 282 if (mac->opmode == NL80211_IFTYPE_AP || 283 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 284 entry_id = rtl_cam_get_free_entry(hw, 285 p_macaddr); 286 if (entry_id >= TOTAL_CAM_ENTRY) { 287 RT_TRACE(rtlpriv, COMP_SEC, 288 DBG_EMERG, 289 "Can not find free hw security cam entry\n"); 290 return; 291 } 292 } else { 293 entry_id = CAM_PAIRWISE_KEY_POSITION; 294 } 295 296 key_index = PAIRWISE_KEYIDX; 297 is_pairwise = true; 298 } 299 } 300 if (rtlpriv->sec.key_len[key_index] == 0) { 301 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 302 "delete one entry\n"); 303 if (mac->opmode == NL80211_IFTYPE_AP || 304 mac->opmode == NL80211_IFTYPE_MESH_POINT) 305 rtl_cam_del_entry(hw, p_macaddr); 306 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 307 } else { 308 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 309 "The insert KEY length is %d\n", 310 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); 311 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 312 "The insert KEY is %x %x\n", 313 rtlpriv->sec.key_buf[0][0], 314 rtlpriv->sec.key_buf[0][1]); 315 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 316 "add one entry\n"); 317 if (is_pairwise) { 318 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, 319 "Pairwise Key content", 320 rtlpriv->sec.pairwise_key, 321 rtlpriv->sec. 322 key_len[PAIRWISE_KEYIDX]); 323 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 324 "set Pairwise key\n"); 325 326 rtl_cam_add_one_entry(hw, macaddr, key_index, 327 entry_id, enc_algo, 328 CAM_CONFIG_NO_USEDK, 329 rtlpriv->sec. 330 key_buf[key_index]); 331 } else { 332 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 333 "set group key\n"); 334 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 335 rtl_cam_add_one_entry(hw, 336 rtlefuse->dev_addr, 337 PAIRWISE_KEYIDX, 338 CAM_PAIRWISE_KEY_POSITION, 339 enc_algo, 340 CAM_CONFIG_NO_USEDK, 341 rtlpriv->sec.key_buf 342 [entry_id]); 343 } 344 rtl_cam_add_one_entry(hw, macaddr, key_index, 345 entry_id, enc_algo, 346 CAM_CONFIG_NO_USEDK, 347 rtlpriv->sec.key_buf[entry_id]); 348 } 349 } 350 } 351 } 352 353 u32 rtl92c_get_txdma_status(struct ieee80211_hw *hw) 354 { 355 struct rtl_priv *rtlpriv = rtl_priv(hw); 356 357 return rtl_read_dword(rtlpriv, REG_TXDMA_STATUS); 358 } 359 360 void rtl92c_enable_interrupt(struct ieee80211_hw *hw) 361 { 362 struct rtl_priv *rtlpriv = rtl_priv(hw); 363 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 364 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 365 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 366 367 if (IS_HARDWARE_TYPE_8192CE(rtlhal)) { 368 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 369 0xFFFFFFFF); 370 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 371 0xFFFFFFFF); 372 } else { 373 rtl_write_dword(rtlpriv, REG_HIMR, rtlusb->irq_mask[0] & 374 0xFFFFFFFF); 375 rtl_write_dword(rtlpriv, REG_HIMRE, rtlusb->irq_mask[1] & 376 0xFFFFFFFF); 377 } 378 } 379 380 void rtl92c_init_interrupt(struct ieee80211_hw *hw) 381 { 382 rtl92c_enable_interrupt(hw); 383 } 384 385 void rtl92c_disable_interrupt(struct ieee80211_hw *hw) 386 { 387 struct rtl_priv *rtlpriv = rtl_priv(hw); 388 389 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); 390 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); 391 } 392 393 void rtl92c_set_qos(struct ieee80211_hw *hw, int aci) 394 { 395 struct rtl_priv *rtlpriv = rtl_priv(hw); 396 397 rtl92c_dm_init_edca_turbo(hw); 398 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, (u8 *)&aci); 399 } 400 401 void rtl92c_init_driver_info_size(struct ieee80211_hw *hw, u8 size) 402 { 403 struct rtl_priv *rtlpriv = rtl_priv(hw); 404 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, size); 405 } 406 407 int rtl92c_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 408 { 409 u8 value; 410 struct rtl_priv *rtlpriv = rtl_priv(hw); 411 412 switch (type) { 413 case NL80211_IFTYPE_UNSPECIFIED: 414 value = NT_NO_LINK; 415 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 416 "Set Network type to NO LINK!\n"); 417 break; 418 case NL80211_IFTYPE_ADHOC: 419 value = NT_LINK_AD_HOC; 420 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 421 "Set Network type to Ad Hoc!\n"); 422 break; 423 case NL80211_IFTYPE_STATION: 424 value = NT_LINK_AP; 425 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 426 "Set Network type to STA!\n"); 427 break; 428 case NL80211_IFTYPE_AP: 429 value = NT_AS_AP; 430 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 431 "Set Network type to AP!\n"); 432 break; 433 default: 434 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 435 "Network type %d not supported!\n", type); 436 return -EOPNOTSUPP; 437 } 438 rtl_write_byte(rtlpriv, MSR, value); 439 return 0; 440 } 441 442 void rtl92c_init_network_type(struct ieee80211_hw *hw) 443 { 444 rtl92c_set_network_type(hw, NL80211_IFTYPE_UNSPECIFIED); 445 } 446 447 void rtl92c_init_adaptive_ctrl(struct ieee80211_hw *hw) 448 { 449 u16 value16; 450 u32 value32; 451 struct rtl_priv *rtlpriv = rtl_priv(hw); 452 453 /* Response Rate Set */ 454 value32 = rtl_read_dword(rtlpriv, REG_RRSR); 455 value32 &= ~RATE_BITMAP_ALL; 456 value32 |= RATE_RRSR_CCK_ONLY_1M; 457 rtl_write_dword(rtlpriv, REG_RRSR, value32); 458 /* SIFS (used in NAV) */ 459 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10); 460 rtl_write_word(rtlpriv, REG_SPEC_SIFS, value16); 461 /* Retry Limit */ 462 value16 = _LRL(0x30) | _SRL(0x30); 463 rtl_write_dword(rtlpriv, REG_RL, value16); 464 } 465 466 void rtl92c_init_rate_fallback(struct ieee80211_hw *hw) 467 { 468 struct rtl_priv *rtlpriv = rtl_priv(hw); 469 470 /* Set Data Auto Rate Fallback Retry Count register. */ 471 rtl_write_dword(rtlpriv, REG_DARFRC, 0x00000000); 472 rtl_write_dword(rtlpriv, REG_DARFRC+4, 0x10080404); 473 rtl_write_dword(rtlpriv, REG_RARFRC, 0x04030201); 474 rtl_write_dword(rtlpriv, REG_RARFRC+4, 0x08070605); 475 } 476 477 static void rtl92c_set_cck_sifs(struct ieee80211_hw *hw, u8 trx_sifs, 478 u8 ctx_sifs) 479 { 480 struct rtl_priv *rtlpriv = rtl_priv(hw); 481 482 rtl_write_byte(rtlpriv, REG_SIFS_CCK, trx_sifs); 483 rtl_write_byte(rtlpriv, (REG_SIFS_CCK + 1), ctx_sifs); 484 } 485 486 static void rtl92c_set_ofdm_sifs(struct ieee80211_hw *hw, u8 trx_sifs, 487 u8 ctx_sifs) 488 { 489 struct rtl_priv *rtlpriv = rtl_priv(hw); 490 491 rtl_write_byte(rtlpriv, REG_SIFS_OFDM, trx_sifs); 492 rtl_write_byte(rtlpriv, (REG_SIFS_OFDM + 1), ctx_sifs); 493 } 494 495 void rtl92c_init_edca_param(struct ieee80211_hw *hw, 496 u16 queue, u16 txop, u8 cw_min, u8 cw_max, u8 aifs) 497 { 498 /* sequence: VO, VI, BE, BK ==> the same as 92C hardware design. 499 * referenc : enum nl80211_txq_q or ieee80211_set_wmm_default function. 500 */ 501 u32 value; 502 struct rtl_priv *rtlpriv = rtl_priv(hw); 503 504 value = (u32)aifs; 505 value |= ((u32)cw_min & 0xF) << 8; 506 value |= ((u32)cw_max & 0xF) << 12; 507 value |= (u32)txop << 16; 508 /* 92C hardware register sequence is the same as queue number. */ 509 rtl_write_dword(rtlpriv, (REG_EDCA_VO_PARAM + (queue * 4)), value); 510 } 511 512 void rtl92c_init_edca(struct ieee80211_hw *hw) 513 { 514 u16 value16; 515 struct rtl_priv *rtlpriv = rtl_priv(hw); 516 517 /* disable EDCCA count down, to reduce collison and retry */ 518 value16 = rtl_read_word(rtlpriv, REG_RD_CTRL); 519 value16 |= DIS_EDCA_CNT_DWN; 520 rtl_write_word(rtlpriv, REG_RD_CTRL, value16); 521 /* Update SIFS timing. ?????????? 522 * pHalData->SifsTime = 0x0e0e0a0a; */ 523 rtl92c_set_cck_sifs(hw, 0xa, 0xa); 524 rtl92c_set_ofdm_sifs(hw, 0xe, 0xe); 525 /* Set CCK/OFDM SIFS to be 10us. */ 526 rtl_write_word(rtlpriv, REG_SIFS_CCK, 0x0a0a); 527 rtl_write_word(rtlpriv, REG_SIFS_OFDM, 0x1010); 528 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0204); 529 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004); 530 /* TXOP */ 531 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B); 532 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F); 533 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324); 534 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226); 535 /* PIFS */ 536 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); 537 /* AGGR BREAK TIME Register */ 538 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 539 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); 540 rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x02); 541 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x02); 542 } 543 544 void rtl92c_init_ampdu_aggregation(struct ieee80211_hw *hw) 545 { 546 struct rtl_priv *rtlpriv = rtl_priv(hw); 547 548 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x99997631); 549 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 550 /* init AMPDU aggregation number, tuning for Tx's TP, */ 551 rtl_write_word(rtlpriv, 0x4CA, 0x0708); 552 } 553 554 void rtl92c_init_beacon_max_error(struct ieee80211_hw *hw) 555 { 556 struct rtl_priv *rtlpriv = rtl_priv(hw); 557 558 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF); 559 } 560 561 void rtl92c_init_rdg_setting(struct ieee80211_hw *hw) 562 { 563 struct rtl_priv *rtlpriv = rtl_priv(hw); 564 565 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xFF); 566 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200); 567 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05); 568 } 569 570 void rtl92c_init_retry_function(struct ieee80211_hw *hw) 571 { 572 u8 value8; 573 struct rtl_priv *rtlpriv = rtl_priv(hw); 574 575 value8 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL); 576 value8 |= EN_AMPDU_RTY_NEW; 577 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL, value8); 578 /* Set ACK timeout */ 579 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); 580 } 581 582 void rtl92c_disable_fast_edca(struct ieee80211_hw *hw) 583 { 584 struct rtl_priv *rtlpriv = rtl_priv(hw); 585 586 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0); 587 } 588 589 void rtl92c_set_min_space(struct ieee80211_hw *hw, bool is2T) 590 { 591 struct rtl_priv *rtlpriv = rtl_priv(hw); 592 u8 value = is2T ? MAX_MSS_DENSITY_2T : MAX_MSS_DENSITY_1T; 593 594 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, value); 595 } 596 597 /*==============================================================*/ 598 599 static u8 _rtl92c_query_rxpwrpercentage(s8 antpower) 600 { 601 if ((antpower <= -100) || (antpower >= 20)) 602 return 0; 603 else if (antpower >= 0) 604 return 100; 605 else 606 return 100 + antpower; 607 } 608 609 static u8 _rtl92c_evm_db_to_percentage(s8 value) 610 { 611 s8 ret_val; 612 613 ret_val = value; 614 if (ret_val >= 0) 615 ret_val = 0; 616 if (ret_val <= -33) 617 ret_val = -33; 618 ret_val = 0 - ret_val; 619 ret_val *= 3; 620 if (ret_val == 99) 621 ret_val = 100; 622 return ret_val; 623 } 624 625 static long _rtl92c_signal_scale_mapping(struct ieee80211_hw *hw, 626 long currsig) 627 { 628 long retsig; 629 630 if (currsig >= 61 && currsig <= 100) 631 retsig = 90 + ((currsig - 60) / 4); 632 else if (currsig >= 41 && currsig <= 60) 633 retsig = 78 + ((currsig - 40) / 2); 634 else if (currsig >= 31 && currsig <= 40) 635 retsig = 66 + (currsig - 30); 636 else if (currsig >= 21 && currsig <= 30) 637 retsig = 54 + (currsig - 20); 638 else if (currsig >= 5 && currsig <= 20) 639 retsig = 42 + (((currsig - 5) * 2) / 3); 640 else if (currsig == 4) 641 retsig = 36; 642 else if (currsig == 3) 643 retsig = 27; 644 else if (currsig == 2) 645 retsig = 18; 646 else if (currsig == 1) 647 retsig = 9; 648 else 649 retsig = currsig; 650 return retsig; 651 } 652 653 static void _rtl92c_query_rxphystatus(struct ieee80211_hw *hw, 654 struct rtl_stats *pstats, 655 struct rx_desc_92c *p_desc, 656 struct rx_fwinfo_92c *p_drvinfo, 657 bool packet_match_bssid, 658 bool packet_toself, 659 bool packet_beacon) 660 { 661 struct rtl_priv *rtlpriv = rtl_priv(hw); 662 struct rtl_phy *rtlphy = &(rtlpriv->phy); 663 struct phy_sts_cck_8192s_t *cck_buf; 664 s8 rx_pwr_all = 0, rx_pwr[4]; 665 u8 rf_rx_num = 0, evm, pwdb_all; 666 u8 i, max_spatial_stream; 667 u32 rssi, total_rssi = 0; 668 bool in_powersavemode = false; 669 bool is_cck_rate; 670 u8 *pdesc = (u8 *)p_desc; 671 672 is_cck_rate = RX_HAL_IS_CCK_RATE(p_desc->rxmcs); 673 pstats->packet_matchbssid = packet_match_bssid; 674 pstats->packet_toself = packet_toself; 675 pstats->packet_beacon = packet_beacon; 676 pstats->is_cck = is_cck_rate; 677 pstats->RX_SIGQ[0] = -1; 678 pstats->RX_SIGQ[1] = -1; 679 if (is_cck_rate) { 680 u8 report, cck_highpwr; 681 cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo; 682 if (!in_powersavemode) 683 cck_highpwr = rtlphy->cck_high_power; 684 else 685 cck_highpwr = false; 686 if (!cck_highpwr) { 687 u8 cck_agc_rpt = cck_buf->cck_agc_rpt; 688 report = cck_buf->cck_agc_rpt & 0xc0; 689 report = report >> 6; 690 switch (report) { 691 case 0x3: 692 rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); 693 break; 694 case 0x2: 695 rx_pwr_all = -26 - (cck_agc_rpt & 0x3e); 696 break; 697 case 0x1: 698 rx_pwr_all = -12 - (cck_agc_rpt & 0x3e); 699 break; 700 case 0x0: 701 rx_pwr_all = 16 - (cck_agc_rpt & 0x3e); 702 break; 703 } 704 } else { 705 u8 cck_agc_rpt = cck_buf->cck_agc_rpt; 706 report = p_drvinfo->cfosho[0] & 0x60; 707 report = report >> 5; 708 switch (report) { 709 case 0x3: 710 rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1); 711 break; 712 case 0x2: 713 rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1); 714 break; 715 case 0x1: 716 rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1); 717 break; 718 case 0x0: 719 rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1); 720 break; 721 } 722 } 723 pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all); 724 pstats->rx_pwdb_all = pwdb_all; 725 pstats->recvsignalpower = rx_pwr_all; 726 if (packet_match_bssid) { 727 u8 sq; 728 if (pstats->rx_pwdb_all > 40) 729 sq = 100; 730 else { 731 sq = cck_buf->sq_rpt; 732 if (sq > 64) 733 sq = 0; 734 else if (sq < 20) 735 sq = 100; 736 else 737 sq = ((64 - sq) * 100) / 44; 738 } 739 pstats->signalquality = sq; 740 pstats->RX_SIGQ[0] = sq; 741 pstats->RX_SIGQ[1] = -1; 742 } 743 } else { 744 rtlpriv->dm.rfpath_rxenable[0] = 745 rtlpriv->dm.rfpath_rxenable[1] = true; 746 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) { 747 if (rtlpriv->dm.rfpath_rxenable[i]) 748 rf_rx_num++; 749 rx_pwr[i] = 750 ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) - 110; 751 rssi = _rtl92c_query_rxpwrpercentage(rx_pwr[i]); 752 total_rssi += rssi; 753 rtlpriv->stats.rx_snr_db[i] = 754 (long)(p_drvinfo->rxsnr[i] / 2); 755 756 if (packet_match_bssid) 757 pstats->rx_mimo_signalstrength[i] = (u8) rssi; 758 } 759 rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110; 760 pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all); 761 pstats->rx_pwdb_all = pwdb_all; 762 pstats->rxpower = rx_pwr_all; 763 pstats->recvsignalpower = rx_pwr_all; 764 if (GET_RX_DESC_RX_MCS(pdesc) && 765 GET_RX_DESC_RX_MCS(pdesc) >= DESC_RATEMCS8 && 766 GET_RX_DESC_RX_MCS(pdesc) <= DESC_RATEMCS15) 767 max_spatial_stream = 2; 768 else 769 max_spatial_stream = 1; 770 for (i = 0; i < max_spatial_stream; i++) { 771 evm = _rtl92c_evm_db_to_percentage(p_drvinfo->rxevm[i]); 772 if (packet_match_bssid) { 773 if (i == 0) 774 pstats->signalquality = 775 (u8) (evm & 0xff); 776 pstats->RX_SIGQ[i] = 777 (u8) (evm & 0xff); 778 } 779 } 780 } 781 if (is_cck_rate) 782 pstats->signalstrength = 783 (u8) (_rtl92c_signal_scale_mapping(hw, pwdb_all)); 784 else if (rf_rx_num != 0) 785 pstats->signalstrength = 786 (u8) (_rtl92c_signal_scale_mapping 787 (hw, total_rssi /= rf_rx_num)); 788 } 789 790 void rtl92c_translate_rx_signal_stuff(struct ieee80211_hw *hw, 791 struct sk_buff *skb, 792 struct rtl_stats *pstats, 793 struct rx_desc_92c *pdesc, 794 struct rx_fwinfo_92c *p_drvinfo) 795 { 796 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 797 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 798 struct ieee80211_hdr *hdr; 799 u8 *tmp_buf; 800 u8 *praddr; 801 __le16 fc; 802 u16 type, cpu_fc; 803 bool packet_matchbssid, packet_toself, packet_beacon = false; 804 805 tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift; 806 hdr = (struct ieee80211_hdr *)tmp_buf; 807 fc = hdr->frame_control; 808 cpu_fc = le16_to_cpu(fc); 809 type = WLAN_FC_GET_TYPE(fc); 810 praddr = hdr->addr1; 811 packet_matchbssid = 812 ((IEEE80211_FTYPE_CTL != type) && 813 ether_addr_equal(mac->bssid, 814 (cpu_fc & IEEE80211_FCTL_TODS) ? hdr->addr1 : 815 (cpu_fc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 : 816 hdr->addr3) && 817 (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv)); 818 819 packet_toself = packet_matchbssid && 820 ether_addr_equal(praddr, rtlefuse->dev_addr); 821 if (ieee80211_is_beacon(fc)) 822 packet_beacon = true; 823 _rtl92c_query_rxphystatus(hw, pstats, pdesc, p_drvinfo, 824 packet_matchbssid, packet_toself, 825 packet_beacon); 826 rtl_process_phyinfo(hw, tmp_buf, pstats); 827 } 828