1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 ****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../pci.h" 28 #include "../usb.h" 29 #include "../ps.h" 30 #include "../cam.h" 31 #include "../stats.h" 32 #include "reg.h" 33 #include "def.h" 34 #include "phy.h" 35 #include "rf.h" 36 #include "dm.h" 37 #include "mac.h" 38 #include "trx.h" 39 #include "../rtl8192c/fw_common.h" 40 41 #include <linux/module.h> 42 43 /* macro to shorten lines */ 44 45 #define LINK_Q ui_link_quality 46 #define RX_EVM rx_evm_percentage 47 #define RX_SIGQ rx_mimo_sig_qual 48 49 50 void rtl92c_read_chip_version(struct ieee80211_hw *hw) 51 { 52 struct rtl_priv *rtlpriv = rtl_priv(hw); 53 struct rtl_phy *rtlphy = &(rtlpriv->phy); 54 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 55 enum version_8192c chip_version = VERSION_UNKNOWN; 56 const char *versionid; 57 u32 value32; 58 59 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 60 if (value32 & TRP_VAUX_EN) { 61 chip_version = (value32 & TYPE_ID) ? VERSION_TEST_CHIP_92C : 62 VERSION_TEST_CHIP_88C; 63 } else { 64 /* Normal mass production chip. */ 65 chip_version = NORMAL_CHIP; 66 chip_version |= ((value32 & TYPE_ID) ? CHIP_92C : 0); 67 chip_version |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0); 68 if (IS_VENDOR_UMC(chip_version)) 69 chip_version |= ((value32 & CHIP_VER_RTL_MASK) ? 70 CHIP_VENDOR_UMC_B_CUT : 0); 71 if (IS_92C_SERIAL(chip_version)) { 72 value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM); 73 chip_version |= ((CHIP_BONDING_IDENTIFIER(value32) == 74 CHIP_BONDING_92C_1T2R) ? CHIP_92C_1T2R : 0); 75 } 76 } 77 rtlhal->version = (enum version_8192c)chip_version; 78 pr_info("Chip version 0x%x\n", chip_version); 79 switch (rtlhal->version) { 80 case VERSION_NORMAL_TSMC_CHIP_92C_1T2R: 81 versionid = "NORMAL_B_CHIP_92C"; 82 break; 83 case VERSION_NORMAL_TSMC_CHIP_92C: 84 versionid = "NORMAL_TSMC_CHIP_92C"; 85 break; 86 case VERSION_NORMAL_TSMC_CHIP_88C: 87 versionid = "NORMAL_TSMC_CHIP_88C"; 88 break; 89 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT: 90 versionid = "NORMAL_UMC_CHIP_i92C_1T2R_A_CUT"; 91 break; 92 case VERSION_NORMAL_UMC_CHIP_92C_A_CUT: 93 versionid = "NORMAL_UMC_CHIP_92C_A_CUT"; 94 break; 95 case VERSION_NORMAL_UMC_CHIP_88C_A_CUT: 96 versionid = "NORMAL_UMC_CHIP_88C_A_CUT"; 97 break; 98 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT: 99 versionid = "NORMAL_UMC_CHIP_92C_1T2R_B_CUT"; 100 break; 101 case VERSION_NORMAL_UMC_CHIP_92C_B_CUT: 102 versionid = "NORMAL_UMC_CHIP_92C_B_CUT"; 103 break; 104 case VERSION_NORMAL_UMC_CHIP_88C_B_CUT: 105 versionid = "NORMAL_UMC_CHIP_88C_B_CUT"; 106 break; 107 case VERSION_TEST_CHIP_92C: 108 versionid = "TEST_CHIP_92C"; 109 break; 110 case VERSION_TEST_CHIP_88C: 111 versionid = "TEST_CHIP_88C"; 112 break; 113 default: 114 versionid = "UNKNOWN"; 115 break; 116 } 117 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 118 "Chip Version ID: %s\n", versionid); 119 120 if (IS_92C_SERIAL(rtlhal->version)) 121 rtlphy->rf_type = 122 (IS_92C_1T2R(rtlhal->version)) ? RF_1T2R : RF_2T2R; 123 else 124 rtlphy->rf_type = RF_1T1R; 125 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 126 "Chip RF Type: %s\n", 127 rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R"); 128 if (get_rf_type(rtlphy) == RF_1T1R) 129 rtlpriv->dm.rfpath_rxenable[0] = true; 130 else 131 rtlpriv->dm.rfpath_rxenable[0] = 132 rtlpriv->dm.rfpath_rxenable[1] = true; 133 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 134 rtlhal->version); 135 } 136 137 /** 138 * writeLLT - LLT table write access 139 * @io: io callback 140 * @address: LLT logical address. 141 * @data: LLT data content 142 * 143 * Realtek hardware access function. 144 * 145 */ 146 bool rtl92c_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 147 { 148 struct rtl_priv *rtlpriv = rtl_priv(hw); 149 bool status = true; 150 long count = 0; 151 u32 value = _LLT_INIT_ADDR(address) | 152 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); 153 154 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 155 do { 156 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 157 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 158 break; 159 if (count > POLLING_LLT_THRESHOLD) { 160 pr_err("Failed to polling write LLT done at address %d! _LLT_OP_VALUE(%x)\n", 161 address, _LLT_OP_VALUE(value)); 162 status = false; 163 break; 164 } 165 } while (++count); 166 return status; 167 } 168 /** 169 * rtl92c_init_LLT_table - Init LLT table 170 * @io: io callback 171 * @boundary: 172 * 173 * Realtek hardware access function. 174 * 175 */ 176 bool rtl92c_init_llt_table(struct ieee80211_hw *hw, u32 boundary) 177 { 178 bool rst = true; 179 u32 i; 180 181 for (i = 0; i < (boundary - 1); i++) { 182 rst = rtl92c_llt_write(hw, i , i + 1); 183 if (true != rst) { 184 pr_err("===> %s #1 fail\n", __func__); 185 return rst; 186 } 187 } 188 /* end of list */ 189 rst = rtl92c_llt_write(hw, (boundary - 1), 0xFF); 190 if (true != rst) { 191 pr_err("===> %s #2 fail\n", __func__); 192 return rst; 193 } 194 /* Make the other pages as ring buffer 195 * This ring buffer is used as beacon buffer if we config this MAC 196 * as two MAC transfer. 197 * Otherwise used as local loopback buffer. 198 */ 199 for (i = boundary; i < LLT_LAST_ENTRY_OF_TX_PKT_BUFFER; i++) { 200 rst = rtl92c_llt_write(hw, i, (i + 1)); 201 if (true != rst) { 202 pr_err("===> %s #3 fail\n", __func__); 203 return rst; 204 } 205 } 206 /* Let last entry point to the start entry of ring buffer */ 207 rst = rtl92c_llt_write(hw, LLT_LAST_ENTRY_OF_TX_PKT_BUFFER, boundary); 208 if (true != rst) { 209 pr_err("===> %s #4 fail\n", __func__); 210 return rst; 211 } 212 return rst; 213 } 214 void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index, 215 u8 *p_macaddr, bool is_group, u8 enc_algo, 216 bool is_wepkey, bool clear_all) 217 { 218 struct rtl_priv *rtlpriv = rtl_priv(hw); 219 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 220 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 221 u8 *macaddr = p_macaddr; 222 u32 entry_id = 0; 223 bool is_pairwise = false; 224 static u8 cam_const_addr[4][6] = { 225 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 226 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 227 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 228 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 229 }; 230 static u8 cam_const_broad[] = { 231 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 232 }; 233 234 if (clear_all) { 235 u8 idx = 0; 236 u8 cam_offset = 0; 237 u8 clear_number = 5; 238 239 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 240 for (idx = 0; idx < clear_number; idx++) { 241 rtl_cam_mark_invalid(hw, cam_offset + idx); 242 rtl_cam_empty_entry(hw, cam_offset + idx); 243 if (idx < 5) { 244 memset(rtlpriv->sec.key_buf[idx], 0, 245 MAX_KEY_LEN); 246 rtlpriv->sec.key_len[idx] = 0; 247 } 248 } 249 } else { 250 switch (enc_algo) { 251 case WEP40_ENCRYPTION: 252 enc_algo = CAM_WEP40; 253 break; 254 case WEP104_ENCRYPTION: 255 enc_algo = CAM_WEP104; 256 break; 257 case TKIP_ENCRYPTION: 258 enc_algo = CAM_TKIP; 259 break; 260 case AESCCMP_ENCRYPTION: 261 enc_algo = CAM_AES; 262 break; 263 default: 264 pr_err("illegal switch case\n"); 265 enc_algo = CAM_TKIP; 266 break; 267 } 268 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 269 macaddr = cam_const_addr[key_index]; 270 entry_id = key_index; 271 } else { 272 if (is_group) { 273 macaddr = cam_const_broad; 274 entry_id = key_index; 275 } else { 276 if (mac->opmode == NL80211_IFTYPE_AP || 277 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 278 entry_id = rtl_cam_get_free_entry(hw, 279 p_macaddr); 280 if (entry_id >= TOTAL_CAM_ENTRY) { 281 pr_err("Can not find free hw security cam entry\n"); 282 return; 283 } 284 } else { 285 entry_id = CAM_PAIRWISE_KEY_POSITION; 286 } 287 288 key_index = PAIRWISE_KEYIDX; 289 is_pairwise = true; 290 } 291 } 292 if (rtlpriv->sec.key_len[key_index] == 0) { 293 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 294 "delete one entry\n"); 295 if (mac->opmode == NL80211_IFTYPE_AP || 296 mac->opmode == NL80211_IFTYPE_MESH_POINT) 297 rtl_cam_del_entry(hw, p_macaddr); 298 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 299 } else { 300 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 301 "The insert KEY length is %d\n", 302 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); 303 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 304 "The insert KEY is %x %x\n", 305 rtlpriv->sec.key_buf[0][0], 306 rtlpriv->sec.key_buf[0][1]); 307 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 308 "add one entry\n"); 309 if (is_pairwise) { 310 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, 311 "Pairwise Key content", 312 rtlpriv->sec.pairwise_key, 313 rtlpriv->sec. 314 key_len[PAIRWISE_KEYIDX]); 315 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 316 "set Pairwise key\n"); 317 318 rtl_cam_add_one_entry(hw, macaddr, key_index, 319 entry_id, enc_algo, 320 CAM_CONFIG_NO_USEDK, 321 rtlpriv->sec. 322 key_buf[key_index]); 323 } else { 324 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 325 "set group key\n"); 326 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 327 rtl_cam_add_one_entry(hw, 328 rtlefuse->dev_addr, 329 PAIRWISE_KEYIDX, 330 CAM_PAIRWISE_KEY_POSITION, 331 enc_algo, 332 CAM_CONFIG_NO_USEDK, 333 rtlpriv->sec.key_buf 334 [entry_id]); 335 } 336 rtl_cam_add_one_entry(hw, macaddr, key_index, 337 entry_id, enc_algo, 338 CAM_CONFIG_NO_USEDK, 339 rtlpriv->sec.key_buf[entry_id]); 340 } 341 } 342 } 343 } 344 345 u32 rtl92c_get_txdma_status(struct ieee80211_hw *hw) 346 { 347 struct rtl_priv *rtlpriv = rtl_priv(hw); 348 349 return rtl_read_dword(rtlpriv, REG_TXDMA_STATUS); 350 } 351 352 void rtl92c_enable_interrupt(struct ieee80211_hw *hw) 353 { 354 struct rtl_priv *rtlpriv = rtl_priv(hw); 355 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 356 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 357 358 if (IS_HARDWARE_TYPE_8192CE(rtlpriv)) { 359 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 360 0xFFFFFFFF); 361 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 362 0xFFFFFFFF); 363 } else { 364 rtl_write_dword(rtlpriv, REG_HIMR, rtlusb->irq_mask[0] & 365 0xFFFFFFFF); 366 rtl_write_dword(rtlpriv, REG_HIMRE, rtlusb->irq_mask[1] & 367 0xFFFFFFFF); 368 } 369 } 370 371 void rtl92c_init_interrupt(struct ieee80211_hw *hw) 372 { 373 rtl92c_enable_interrupt(hw); 374 } 375 376 void rtl92c_disable_interrupt(struct ieee80211_hw *hw) 377 { 378 struct rtl_priv *rtlpriv = rtl_priv(hw); 379 380 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); 381 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); 382 } 383 384 void rtl92c_set_qos(struct ieee80211_hw *hw, int aci) 385 { 386 struct rtl_priv *rtlpriv = rtl_priv(hw); 387 388 rtl92c_dm_init_edca_turbo(hw); 389 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, (u8 *)&aci); 390 } 391 392 void rtl92c_init_driver_info_size(struct ieee80211_hw *hw, u8 size) 393 { 394 struct rtl_priv *rtlpriv = rtl_priv(hw); 395 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, size); 396 } 397 398 int rtl92c_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 399 { 400 u8 value; 401 struct rtl_priv *rtlpriv = rtl_priv(hw); 402 403 switch (type) { 404 case NL80211_IFTYPE_UNSPECIFIED: 405 value = NT_NO_LINK; 406 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 407 "Set Network type to NO LINK!\n"); 408 break; 409 case NL80211_IFTYPE_ADHOC: 410 value = NT_LINK_AD_HOC; 411 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 412 "Set Network type to Ad Hoc!\n"); 413 break; 414 case NL80211_IFTYPE_STATION: 415 value = NT_LINK_AP; 416 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 417 "Set Network type to STA!\n"); 418 break; 419 case NL80211_IFTYPE_AP: 420 value = NT_AS_AP; 421 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 422 "Set Network type to AP!\n"); 423 break; 424 default: 425 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 426 "Network type %d not supported!\n", type); 427 return -EOPNOTSUPP; 428 } 429 rtl_write_byte(rtlpriv, MSR, value); 430 return 0; 431 } 432 433 void rtl92c_init_network_type(struct ieee80211_hw *hw) 434 { 435 rtl92c_set_network_type(hw, NL80211_IFTYPE_UNSPECIFIED); 436 } 437 438 void rtl92c_init_adaptive_ctrl(struct ieee80211_hw *hw) 439 { 440 u16 value16; 441 u32 value32; 442 struct rtl_priv *rtlpriv = rtl_priv(hw); 443 444 /* Response Rate Set */ 445 value32 = rtl_read_dword(rtlpriv, REG_RRSR); 446 value32 &= ~RATE_BITMAP_ALL; 447 value32 |= RATE_RRSR_CCK_ONLY_1M; 448 rtl_write_dword(rtlpriv, REG_RRSR, value32); 449 /* SIFS (used in NAV) */ 450 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10); 451 rtl_write_word(rtlpriv, REG_SPEC_SIFS, value16); 452 /* Retry Limit */ 453 value16 = _LRL(0x30) | _SRL(0x30); 454 rtl_write_dword(rtlpriv, REG_RL, value16); 455 } 456 457 void rtl92c_init_rate_fallback(struct ieee80211_hw *hw) 458 { 459 struct rtl_priv *rtlpriv = rtl_priv(hw); 460 461 /* Set Data Auto Rate Fallback Retry Count register. */ 462 rtl_write_dword(rtlpriv, REG_DARFRC, 0x00000000); 463 rtl_write_dword(rtlpriv, REG_DARFRC+4, 0x10080404); 464 rtl_write_dword(rtlpriv, REG_RARFRC, 0x04030201); 465 rtl_write_dword(rtlpriv, REG_RARFRC+4, 0x08070605); 466 } 467 468 static void rtl92c_set_cck_sifs(struct ieee80211_hw *hw, u8 trx_sifs, 469 u8 ctx_sifs) 470 { 471 struct rtl_priv *rtlpriv = rtl_priv(hw); 472 473 rtl_write_byte(rtlpriv, REG_SIFS_CCK, trx_sifs); 474 rtl_write_byte(rtlpriv, (REG_SIFS_CCK + 1), ctx_sifs); 475 } 476 477 static void rtl92c_set_ofdm_sifs(struct ieee80211_hw *hw, u8 trx_sifs, 478 u8 ctx_sifs) 479 { 480 struct rtl_priv *rtlpriv = rtl_priv(hw); 481 482 rtl_write_byte(rtlpriv, REG_SIFS_OFDM, trx_sifs); 483 rtl_write_byte(rtlpriv, (REG_SIFS_OFDM + 1), ctx_sifs); 484 } 485 486 void rtl92c_init_edca_param(struct ieee80211_hw *hw, 487 u16 queue, u16 txop, u8 cw_min, u8 cw_max, u8 aifs) 488 { 489 /* sequence: VO, VI, BE, BK ==> the same as 92C hardware design. 490 * referenc : enum nl80211_txq_q or ieee80211_set_wmm_default function. 491 */ 492 u32 value; 493 struct rtl_priv *rtlpriv = rtl_priv(hw); 494 495 value = (u32)aifs; 496 value |= ((u32)cw_min & 0xF) << 8; 497 value |= ((u32)cw_max & 0xF) << 12; 498 value |= (u32)txop << 16; 499 /* 92C hardware register sequence is the same as queue number. */ 500 rtl_write_dword(rtlpriv, (REG_EDCA_VO_PARAM + (queue * 4)), value); 501 } 502 503 void rtl92c_init_edca(struct ieee80211_hw *hw) 504 { 505 u16 value16; 506 struct rtl_priv *rtlpriv = rtl_priv(hw); 507 508 /* disable EDCCA count down, to reduce collison and retry */ 509 value16 = rtl_read_word(rtlpriv, REG_RD_CTRL); 510 value16 |= DIS_EDCA_CNT_DWN; 511 rtl_write_word(rtlpriv, REG_RD_CTRL, value16); 512 /* Update SIFS timing. ?????????? 513 * pHalData->SifsTime = 0x0e0e0a0a; */ 514 rtl92c_set_cck_sifs(hw, 0xa, 0xa); 515 rtl92c_set_ofdm_sifs(hw, 0xe, 0xe); 516 /* Set CCK/OFDM SIFS to be 10us. */ 517 rtl_write_word(rtlpriv, REG_SIFS_CCK, 0x0a0a); 518 rtl_write_word(rtlpriv, REG_SIFS_OFDM, 0x1010); 519 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0204); 520 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004); 521 /* TXOP */ 522 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B); 523 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F); 524 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324); 525 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226); 526 /* PIFS */ 527 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); 528 /* AGGR BREAK TIME Register */ 529 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 530 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); 531 rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x02); 532 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x02); 533 } 534 535 void rtl92c_init_ampdu_aggregation(struct ieee80211_hw *hw) 536 { 537 struct rtl_priv *rtlpriv = rtl_priv(hw); 538 539 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x99997631); 540 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 541 /* init AMPDU aggregation number, tuning for Tx's TP, */ 542 rtl_write_word(rtlpriv, 0x4CA, 0x0708); 543 } 544 545 void rtl92c_init_beacon_max_error(struct ieee80211_hw *hw) 546 { 547 struct rtl_priv *rtlpriv = rtl_priv(hw); 548 549 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF); 550 } 551 552 void rtl92c_init_rdg_setting(struct ieee80211_hw *hw) 553 { 554 struct rtl_priv *rtlpriv = rtl_priv(hw); 555 556 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xFF); 557 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200); 558 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05); 559 } 560 561 void rtl92c_init_retry_function(struct ieee80211_hw *hw) 562 { 563 u8 value8; 564 struct rtl_priv *rtlpriv = rtl_priv(hw); 565 566 value8 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL); 567 value8 |= EN_AMPDU_RTY_NEW; 568 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL, value8); 569 /* Set ACK timeout */ 570 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); 571 } 572 573 void rtl92c_disable_fast_edca(struct ieee80211_hw *hw) 574 { 575 struct rtl_priv *rtlpriv = rtl_priv(hw); 576 577 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0); 578 } 579 580 void rtl92c_set_min_space(struct ieee80211_hw *hw, bool is2T) 581 { 582 struct rtl_priv *rtlpriv = rtl_priv(hw); 583 u8 value = is2T ? MAX_MSS_DENSITY_2T : MAX_MSS_DENSITY_1T; 584 585 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, value); 586 } 587 588 /*==============================================================*/ 589 590 static u8 _rtl92c_query_rxpwrpercentage(s8 antpower) 591 { 592 if ((antpower <= -100) || (antpower >= 20)) 593 return 0; 594 else if (antpower >= 0) 595 return 100; 596 else 597 return 100 + antpower; 598 } 599 600 static u8 _rtl92c_evm_db_to_percentage(s8 value) 601 { 602 s8 ret_val; 603 604 ret_val = value; 605 if (ret_val >= 0) 606 ret_val = 0; 607 if (ret_val <= -33) 608 ret_val = -33; 609 ret_val = 0 - ret_val; 610 ret_val *= 3; 611 if (ret_val == 99) 612 ret_val = 100; 613 return ret_val; 614 } 615 616 static long _rtl92c_signal_scale_mapping(struct ieee80211_hw *hw, 617 long currsig) 618 { 619 long retsig; 620 621 if (currsig >= 61 && currsig <= 100) 622 retsig = 90 + ((currsig - 60) / 4); 623 else if (currsig >= 41 && currsig <= 60) 624 retsig = 78 + ((currsig - 40) / 2); 625 else if (currsig >= 31 && currsig <= 40) 626 retsig = 66 + (currsig - 30); 627 else if (currsig >= 21 && currsig <= 30) 628 retsig = 54 + (currsig - 20); 629 else if (currsig >= 5 && currsig <= 20) 630 retsig = 42 + (((currsig - 5) * 2) / 3); 631 else if (currsig == 4) 632 retsig = 36; 633 else if (currsig == 3) 634 retsig = 27; 635 else if (currsig == 2) 636 retsig = 18; 637 else if (currsig == 1) 638 retsig = 9; 639 else 640 retsig = currsig; 641 return retsig; 642 } 643 644 static void _rtl92c_query_rxphystatus(struct ieee80211_hw *hw, 645 struct rtl_stats *pstats, 646 struct rx_desc_92c *p_desc, 647 struct rx_fwinfo_92c *p_drvinfo, 648 bool packet_match_bssid, 649 bool packet_toself, 650 bool packet_beacon) 651 { 652 struct rtl_priv *rtlpriv = rtl_priv(hw); 653 struct rtl_phy *rtlphy = &(rtlpriv->phy); 654 struct phy_sts_cck_8192s_t *cck_buf; 655 s8 rx_pwr_all = 0, rx_pwr[4]; 656 u8 rf_rx_num = 0, evm, pwdb_all; 657 u8 i, max_spatial_stream; 658 u32 rssi, total_rssi = 0; 659 bool in_powersavemode = false; 660 bool is_cck_rate; 661 u8 *pdesc = (u8 *)p_desc; 662 663 is_cck_rate = RX_HAL_IS_CCK_RATE(p_desc->rxmcs); 664 pstats->packet_matchbssid = packet_match_bssid; 665 pstats->packet_toself = packet_toself; 666 pstats->packet_beacon = packet_beacon; 667 pstats->is_cck = is_cck_rate; 668 pstats->RX_SIGQ[0] = -1; 669 pstats->RX_SIGQ[1] = -1; 670 if (is_cck_rate) { 671 u8 report, cck_highpwr; 672 cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo; 673 if (!in_powersavemode) 674 cck_highpwr = rtlphy->cck_high_power; 675 else 676 cck_highpwr = false; 677 if (!cck_highpwr) { 678 u8 cck_agc_rpt = cck_buf->cck_agc_rpt; 679 report = cck_buf->cck_agc_rpt & 0xc0; 680 report = report >> 6; 681 switch (report) { 682 case 0x3: 683 rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); 684 break; 685 case 0x2: 686 rx_pwr_all = -26 - (cck_agc_rpt & 0x3e); 687 break; 688 case 0x1: 689 rx_pwr_all = -12 - (cck_agc_rpt & 0x3e); 690 break; 691 case 0x0: 692 rx_pwr_all = 16 - (cck_agc_rpt & 0x3e); 693 break; 694 } 695 } else { 696 u8 cck_agc_rpt = cck_buf->cck_agc_rpt; 697 report = p_drvinfo->cfosho[0] & 0x60; 698 report = report >> 5; 699 switch (report) { 700 case 0x3: 701 rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1); 702 break; 703 case 0x2: 704 rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1); 705 break; 706 case 0x1: 707 rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1); 708 break; 709 case 0x0: 710 rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1); 711 break; 712 } 713 } 714 pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all); 715 pstats->rx_pwdb_all = pwdb_all; 716 pstats->recvsignalpower = rx_pwr_all; 717 if (packet_match_bssid) { 718 u8 sq; 719 if (pstats->rx_pwdb_all > 40) 720 sq = 100; 721 else { 722 sq = cck_buf->sq_rpt; 723 if (sq > 64) 724 sq = 0; 725 else if (sq < 20) 726 sq = 100; 727 else 728 sq = ((64 - sq) * 100) / 44; 729 } 730 pstats->signalquality = sq; 731 pstats->RX_SIGQ[0] = sq; 732 pstats->RX_SIGQ[1] = -1; 733 } 734 } else { 735 rtlpriv->dm.rfpath_rxenable[0] = 736 rtlpriv->dm.rfpath_rxenable[1] = true; 737 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) { 738 if (rtlpriv->dm.rfpath_rxenable[i]) 739 rf_rx_num++; 740 rx_pwr[i] = 741 ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) - 110; 742 rssi = _rtl92c_query_rxpwrpercentage(rx_pwr[i]); 743 total_rssi += rssi; 744 rtlpriv->stats.rx_snr_db[i] = 745 (long)(p_drvinfo->rxsnr[i] / 2); 746 747 if (packet_match_bssid) 748 pstats->rx_mimo_signalstrength[i] = (u8) rssi; 749 } 750 rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110; 751 pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all); 752 pstats->rx_pwdb_all = pwdb_all; 753 pstats->rxpower = rx_pwr_all; 754 pstats->recvsignalpower = rx_pwr_all; 755 if (GET_RX_DESC_RX_MCS(pdesc) && 756 GET_RX_DESC_RX_MCS(pdesc) >= DESC_RATEMCS8 && 757 GET_RX_DESC_RX_MCS(pdesc) <= DESC_RATEMCS15) 758 max_spatial_stream = 2; 759 else 760 max_spatial_stream = 1; 761 for (i = 0; i < max_spatial_stream; i++) { 762 evm = _rtl92c_evm_db_to_percentage(p_drvinfo->rxevm[i]); 763 if (packet_match_bssid) { 764 if (i == 0) 765 pstats->signalquality = 766 (u8) (evm & 0xff); 767 pstats->RX_SIGQ[i] = 768 (u8) (evm & 0xff); 769 } 770 } 771 } 772 if (is_cck_rate) 773 pstats->signalstrength = 774 (u8) (_rtl92c_signal_scale_mapping(hw, pwdb_all)); 775 else if (rf_rx_num != 0) 776 pstats->signalstrength = 777 (u8) (_rtl92c_signal_scale_mapping 778 (hw, total_rssi /= rf_rx_num)); 779 } 780 781 void rtl92c_translate_rx_signal_stuff(struct ieee80211_hw *hw, 782 struct sk_buff *skb, 783 struct rtl_stats *pstats, 784 struct rx_desc_92c *pdesc, 785 struct rx_fwinfo_92c *p_drvinfo) 786 { 787 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 788 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 789 struct ieee80211_hdr *hdr; 790 u8 *tmp_buf; 791 u8 *praddr; 792 __le16 fc; 793 u16 type, cpu_fc; 794 bool packet_matchbssid, packet_toself, packet_beacon = false; 795 796 tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift; 797 hdr = (struct ieee80211_hdr *)tmp_buf; 798 fc = hdr->frame_control; 799 cpu_fc = le16_to_cpu(fc); 800 type = WLAN_FC_GET_TYPE(fc); 801 praddr = hdr->addr1; 802 packet_matchbssid = 803 ((IEEE80211_FTYPE_CTL != type) && 804 ether_addr_equal(mac->bssid, 805 (cpu_fc & IEEE80211_FCTL_TODS) ? hdr->addr1 : 806 (cpu_fc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 : 807 hdr->addr3) && 808 (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv)); 809 810 packet_toself = packet_matchbssid && 811 ether_addr_equal(praddr, rtlefuse->dev_addr); 812 if (ieee80211_is_beacon(fc)) 813 packet_beacon = true; 814 _rtl92c_query_rxphystatus(hw, pstats, pdesc, p_drvinfo, 815 packet_matchbssid, packet_toself, 816 packet_beacon); 817 rtl_process_phyinfo(hw, tmp_buf, pstats); 818 } 819