1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 ****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../pci.h" 28 #include "../usb.h" 29 #include "../ps.h" 30 #include "../cam.h" 31 #include "../stats.h" 32 #include "reg.h" 33 #include "def.h" 34 #include "phy.h" 35 #include "rf.h" 36 #include "dm.h" 37 #include "mac.h" 38 #include "trx.h" 39 #include "../rtl8192c/fw_common.h" 40 41 #include <linux/module.h> 42 43 /* macro to shorten lines */ 44 45 #define LINK_Q ui_link_quality 46 #define RX_EVM rx_evm_percentage 47 #define RX_SIGQ rx_mimo_sig_qual 48 49 50 void rtl92c_read_chip_version(struct ieee80211_hw *hw) 51 { 52 struct rtl_priv *rtlpriv = rtl_priv(hw); 53 struct rtl_phy *rtlphy = &(rtlpriv->phy); 54 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 55 enum version_8192c chip_version = VERSION_UNKNOWN; 56 const char *versionid; 57 u32 value32; 58 59 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 60 if (value32 & TRP_VAUX_EN) { 61 chip_version = (value32 & TYPE_ID) ? VERSION_TEST_CHIP_92C : 62 VERSION_TEST_CHIP_88C; 63 } else { 64 /* Normal mass production chip. */ 65 chip_version = NORMAL_CHIP; 66 chip_version |= ((value32 & TYPE_ID) ? CHIP_92C : 0); 67 chip_version |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0); 68 if (IS_VENDOR_UMC(chip_version)) 69 chip_version |= ((value32 & CHIP_VER_RTL_MASK) ? 70 CHIP_VENDOR_UMC_B_CUT : 0); 71 if (IS_92C_SERIAL(chip_version)) { 72 value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM); 73 chip_version |= ((CHIP_BONDING_IDENTIFIER(value32) == 74 CHIP_BONDING_92C_1T2R) ? CHIP_92C_1T2R : 0); 75 } 76 } 77 rtlhal->version = (enum version_8192c)chip_version; 78 pr_info("Chip version 0x%x\n", chip_version); 79 switch (rtlhal->version) { 80 case VERSION_NORMAL_TSMC_CHIP_92C_1T2R: 81 versionid = "NORMAL_B_CHIP_92C"; 82 break; 83 case VERSION_NORMAL_TSMC_CHIP_92C: 84 versionid = "NORMAL_TSMC_CHIP_92C"; 85 break; 86 case VERSION_NORMAL_TSMC_CHIP_88C: 87 versionid = "NORMAL_TSMC_CHIP_88C"; 88 break; 89 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT: 90 versionid = "NORMAL_UMC_CHIP_i92C_1T2R_A_CUT"; 91 break; 92 case VERSION_NORMAL_UMC_CHIP_92C_A_CUT: 93 versionid = "NORMAL_UMC_CHIP_92C_A_CUT"; 94 break; 95 case VERSION_NORMAL_UMC_CHIP_88C_A_CUT: 96 versionid = "NORMAL_UMC_CHIP_88C_A_CUT"; 97 break; 98 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT: 99 versionid = "NORMAL_UMC_CHIP_92C_1T2R_B_CUT"; 100 break; 101 case VERSION_NORMAL_UMC_CHIP_92C_B_CUT: 102 versionid = "NORMAL_UMC_CHIP_92C_B_CUT"; 103 break; 104 case VERSION_NORMAL_UMC_CHIP_88C_B_CUT: 105 versionid = "NORMAL_UMC_CHIP_88C_B_CUT"; 106 break; 107 case VERSION_TEST_CHIP_92C: 108 versionid = "TEST_CHIP_92C"; 109 break; 110 case VERSION_TEST_CHIP_88C: 111 versionid = "TEST_CHIP_88C"; 112 break; 113 default: 114 versionid = "UNKNOWN"; 115 break; 116 } 117 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 118 "Chip Version ID: %s\n", versionid); 119 120 if (IS_92C_SERIAL(rtlhal->version)) 121 rtlphy->rf_type = 122 (IS_92C_1T2R(rtlhal->version)) ? RF_1T2R : RF_2T2R; 123 else 124 rtlphy->rf_type = RF_1T1R; 125 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 126 "Chip RF Type: %s\n", 127 rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R"); 128 if (get_rf_type(rtlphy) == RF_1T1R) 129 rtlpriv->dm.rfpath_rxenable[0] = true; 130 else 131 rtlpriv->dm.rfpath_rxenable[0] = 132 rtlpriv->dm.rfpath_rxenable[1] = true; 133 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 134 rtlhal->version); 135 } 136 137 /** 138 * writeLLT - LLT table write access 139 * @io: io callback 140 * @address: LLT logical address. 141 * @data: LLT data content 142 * 143 * Realtek hardware access function. 144 * 145 */ 146 bool rtl92c_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 147 { 148 struct rtl_priv *rtlpriv = rtl_priv(hw); 149 bool status = true; 150 long count = 0; 151 u32 value = _LLT_INIT_ADDR(address) | 152 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); 153 154 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 155 do { 156 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 157 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 158 break; 159 if (count > POLLING_LLT_THRESHOLD) { 160 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 161 "Failed to polling write LLT done at address %d! _LLT_OP_VALUE(%x)\n", 162 address, _LLT_OP_VALUE(value)); 163 status = false; 164 break; 165 } 166 } while (++count); 167 return status; 168 } 169 /** 170 * rtl92c_init_LLT_table - Init LLT table 171 * @io: io callback 172 * @boundary: 173 * 174 * Realtek hardware access function. 175 * 176 */ 177 bool rtl92c_init_llt_table(struct ieee80211_hw *hw, u32 boundary) 178 { 179 bool rst = true; 180 u32 i; 181 182 for (i = 0; i < (boundary - 1); i++) { 183 rst = rtl92c_llt_write(hw, i , i + 1); 184 if (true != rst) { 185 pr_err("===> %s #1 fail\n", __func__); 186 return rst; 187 } 188 } 189 /* end of list */ 190 rst = rtl92c_llt_write(hw, (boundary - 1), 0xFF); 191 if (true != rst) { 192 pr_err("===> %s #2 fail\n", __func__); 193 return rst; 194 } 195 /* Make the other pages as ring buffer 196 * This ring buffer is used as beacon buffer if we config this MAC 197 * as two MAC transfer. 198 * Otherwise used as local loopback buffer. 199 */ 200 for (i = boundary; i < LLT_LAST_ENTRY_OF_TX_PKT_BUFFER; i++) { 201 rst = rtl92c_llt_write(hw, i, (i + 1)); 202 if (true != rst) { 203 pr_err("===> %s #3 fail\n", __func__); 204 return rst; 205 } 206 } 207 /* Let last entry point to the start entry of ring buffer */ 208 rst = rtl92c_llt_write(hw, LLT_LAST_ENTRY_OF_TX_PKT_BUFFER, boundary); 209 if (true != rst) { 210 pr_err("===> %s #4 fail\n", __func__); 211 return rst; 212 } 213 return rst; 214 } 215 void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index, 216 u8 *p_macaddr, bool is_group, u8 enc_algo, 217 bool is_wepkey, bool clear_all) 218 { 219 struct rtl_priv *rtlpriv = rtl_priv(hw); 220 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 221 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 222 u8 *macaddr = p_macaddr; 223 u32 entry_id = 0; 224 bool is_pairwise = false; 225 static u8 cam_const_addr[4][6] = { 226 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 227 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 228 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 229 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 230 }; 231 static u8 cam_const_broad[] = { 232 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 233 }; 234 235 if (clear_all) { 236 u8 idx = 0; 237 u8 cam_offset = 0; 238 u8 clear_number = 5; 239 240 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 241 for (idx = 0; idx < clear_number; idx++) { 242 rtl_cam_mark_invalid(hw, cam_offset + idx); 243 rtl_cam_empty_entry(hw, cam_offset + idx); 244 if (idx < 5) { 245 memset(rtlpriv->sec.key_buf[idx], 0, 246 MAX_KEY_LEN); 247 rtlpriv->sec.key_len[idx] = 0; 248 } 249 } 250 } else { 251 switch (enc_algo) { 252 case WEP40_ENCRYPTION: 253 enc_algo = CAM_WEP40; 254 break; 255 case WEP104_ENCRYPTION: 256 enc_algo = CAM_WEP104; 257 break; 258 case TKIP_ENCRYPTION: 259 enc_algo = CAM_TKIP; 260 break; 261 case AESCCMP_ENCRYPTION: 262 enc_algo = CAM_AES; 263 break; 264 default: 265 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 266 "illegal switch case\n"); 267 enc_algo = CAM_TKIP; 268 break; 269 } 270 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 271 macaddr = cam_const_addr[key_index]; 272 entry_id = key_index; 273 } else { 274 if (is_group) { 275 macaddr = cam_const_broad; 276 entry_id = key_index; 277 } else { 278 if (mac->opmode == NL80211_IFTYPE_AP || 279 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 280 entry_id = rtl_cam_get_free_entry(hw, 281 p_macaddr); 282 if (entry_id >= TOTAL_CAM_ENTRY) { 283 RT_TRACE(rtlpriv, COMP_SEC, 284 DBG_EMERG, 285 "Can not find free hw security cam entry\n"); 286 return; 287 } 288 } else { 289 entry_id = CAM_PAIRWISE_KEY_POSITION; 290 } 291 292 key_index = PAIRWISE_KEYIDX; 293 is_pairwise = true; 294 } 295 } 296 if (rtlpriv->sec.key_len[key_index] == 0) { 297 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 298 "delete one entry\n"); 299 if (mac->opmode == NL80211_IFTYPE_AP || 300 mac->opmode == NL80211_IFTYPE_MESH_POINT) 301 rtl_cam_del_entry(hw, p_macaddr); 302 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 303 } else { 304 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 305 "The insert KEY length is %d\n", 306 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); 307 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 308 "The insert KEY is %x %x\n", 309 rtlpriv->sec.key_buf[0][0], 310 rtlpriv->sec.key_buf[0][1]); 311 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 312 "add one entry\n"); 313 if (is_pairwise) { 314 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, 315 "Pairwise Key content", 316 rtlpriv->sec.pairwise_key, 317 rtlpriv->sec. 318 key_len[PAIRWISE_KEYIDX]); 319 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 320 "set Pairwise key\n"); 321 322 rtl_cam_add_one_entry(hw, macaddr, key_index, 323 entry_id, enc_algo, 324 CAM_CONFIG_NO_USEDK, 325 rtlpriv->sec. 326 key_buf[key_index]); 327 } else { 328 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 329 "set group key\n"); 330 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 331 rtl_cam_add_one_entry(hw, 332 rtlefuse->dev_addr, 333 PAIRWISE_KEYIDX, 334 CAM_PAIRWISE_KEY_POSITION, 335 enc_algo, 336 CAM_CONFIG_NO_USEDK, 337 rtlpriv->sec.key_buf 338 [entry_id]); 339 } 340 rtl_cam_add_one_entry(hw, macaddr, key_index, 341 entry_id, enc_algo, 342 CAM_CONFIG_NO_USEDK, 343 rtlpriv->sec.key_buf[entry_id]); 344 } 345 } 346 } 347 } 348 349 u32 rtl92c_get_txdma_status(struct ieee80211_hw *hw) 350 { 351 struct rtl_priv *rtlpriv = rtl_priv(hw); 352 353 return rtl_read_dword(rtlpriv, REG_TXDMA_STATUS); 354 } 355 356 void rtl92c_enable_interrupt(struct ieee80211_hw *hw) 357 { 358 struct rtl_priv *rtlpriv = rtl_priv(hw); 359 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 360 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 361 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 362 363 if (IS_HARDWARE_TYPE_8192CE(rtlhal)) { 364 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 365 0xFFFFFFFF); 366 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 367 0xFFFFFFFF); 368 } else { 369 rtl_write_dword(rtlpriv, REG_HIMR, rtlusb->irq_mask[0] & 370 0xFFFFFFFF); 371 rtl_write_dword(rtlpriv, REG_HIMRE, rtlusb->irq_mask[1] & 372 0xFFFFFFFF); 373 } 374 } 375 376 void rtl92c_init_interrupt(struct ieee80211_hw *hw) 377 { 378 rtl92c_enable_interrupt(hw); 379 } 380 381 void rtl92c_disable_interrupt(struct ieee80211_hw *hw) 382 { 383 struct rtl_priv *rtlpriv = rtl_priv(hw); 384 385 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); 386 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); 387 } 388 389 void rtl92c_set_qos(struct ieee80211_hw *hw, int aci) 390 { 391 struct rtl_priv *rtlpriv = rtl_priv(hw); 392 393 rtl92c_dm_init_edca_turbo(hw); 394 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, (u8 *)&aci); 395 } 396 397 void rtl92c_init_driver_info_size(struct ieee80211_hw *hw, u8 size) 398 { 399 struct rtl_priv *rtlpriv = rtl_priv(hw); 400 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, size); 401 } 402 403 int rtl92c_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 404 { 405 u8 value; 406 struct rtl_priv *rtlpriv = rtl_priv(hw); 407 408 switch (type) { 409 case NL80211_IFTYPE_UNSPECIFIED: 410 value = NT_NO_LINK; 411 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 412 "Set Network type to NO LINK!\n"); 413 break; 414 case NL80211_IFTYPE_ADHOC: 415 value = NT_LINK_AD_HOC; 416 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 417 "Set Network type to Ad Hoc!\n"); 418 break; 419 case NL80211_IFTYPE_STATION: 420 value = NT_LINK_AP; 421 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 422 "Set Network type to STA!\n"); 423 break; 424 case NL80211_IFTYPE_AP: 425 value = NT_AS_AP; 426 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 427 "Set Network type to AP!\n"); 428 break; 429 default: 430 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 431 "Network type %d not supported!\n", type); 432 return -EOPNOTSUPP; 433 } 434 rtl_write_byte(rtlpriv, MSR, value); 435 return 0; 436 } 437 438 void rtl92c_init_network_type(struct ieee80211_hw *hw) 439 { 440 rtl92c_set_network_type(hw, NL80211_IFTYPE_UNSPECIFIED); 441 } 442 443 void rtl92c_init_adaptive_ctrl(struct ieee80211_hw *hw) 444 { 445 u16 value16; 446 u32 value32; 447 struct rtl_priv *rtlpriv = rtl_priv(hw); 448 449 /* Response Rate Set */ 450 value32 = rtl_read_dword(rtlpriv, REG_RRSR); 451 value32 &= ~RATE_BITMAP_ALL; 452 value32 |= RATE_RRSR_CCK_ONLY_1M; 453 rtl_write_dword(rtlpriv, REG_RRSR, value32); 454 /* SIFS (used in NAV) */ 455 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10); 456 rtl_write_word(rtlpriv, REG_SPEC_SIFS, value16); 457 /* Retry Limit */ 458 value16 = _LRL(0x30) | _SRL(0x30); 459 rtl_write_dword(rtlpriv, REG_RL, value16); 460 } 461 462 void rtl92c_init_rate_fallback(struct ieee80211_hw *hw) 463 { 464 struct rtl_priv *rtlpriv = rtl_priv(hw); 465 466 /* Set Data Auto Rate Fallback Retry Count register. */ 467 rtl_write_dword(rtlpriv, REG_DARFRC, 0x00000000); 468 rtl_write_dword(rtlpriv, REG_DARFRC+4, 0x10080404); 469 rtl_write_dword(rtlpriv, REG_RARFRC, 0x04030201); 470 rtl_write_dword(rtlpriv, REG_RARFRC+4, 0x08070605); 471 } 472 473 static void rtl92c_set_cck_sifs(struct ieee80211_hw *hw, u8 trx_sifs, 474 u8 ctx_sifs) 475 { 476 struct rtl_priv *rtlpriv = rtl_priv(hw); 477 478 rtl_write_byte(rtlpriv, REG_SIFS_CCK, trx_sifs); 479 rtl_write_byte(rtlpriv, (REG_SIFS_CCK + 1), ctx_sifs); 480 } 481 482 static void rtl92c_set_ofdm_sifs(struct ieee80211_hw *hw, u8 trx_sifs, 483 u8 ctx_sifs) 484 { 485 struct rtl_priv *rtlpriv = rtl_priv(hw); 486 487 rtl_write_byte(rtlpriv, REG_SIFS_OFDM, trx_sifs); 488 rtl_write_byte(rtlpriv, (REG_SIFS_OFDM + 1), ctx_sifs); 489 } 490 491 void rtl92c_init_edca_param(struct ieee80211_hw *hw, 492 u16 queue, u16 txop, u8 cw_min, u8 cw_max, u8 aifs) 493 { 494 /* sequence: VO, VI, BE, BK ==> the same as 92C hardware design. 495 * referenc : enum nl80211_txq_q or ieee80211_set_wmm_default function. 496 */ 497 u32 value; 498 struct rtl_priv *rtlpriv = rtl_priv(hw); 499 500 value = (u32)aifs; 501 value |= ((u32)cw_min & 0xF) << 8; 502 value |= ((u32)cw_max & 0xF) << 12; 503 value |= (u32)txop << 16; 504 /* 92C hardware register sequence is the same as queue number. */ 505 rtl_write_dword(rtlpriv, (REG_EDCA_VO_PARAM + (queue * 4)), value); 506 } 507 508 void rtl92c_init_edca(struct ieee80211_hw *hw) 509 { 510 u16 value16; 511 struct rtl_priv *rtlpriv = rtl_priv(hw); 512 513 /* disable EDCCA count down, to reduce collison and retry */ 514 value16 = rtl_read_word(rtlpriv, REG_RD_CTRL); 515 value16 |= DIS_EDCA_CNT_DWN; 516 rtl_write_word(rtlpriv, REG_RD_CTRL, value16); 517 /* Update SIFS timing. ?????????? 518 * pHalData->SifsTime = 0x0e0e0a0a; */ 519 rtl92c_set_cck_sifs(hw, 0xa, 0xa); 520 rtl92c_set_ofdm_sifs(hw, 0xe, 0xe); 521 /* Set CCK/OFDM SIFS to be 10us. */ 522 rtl_write_word(rtlpriv, REG_SIFS_CCK, 0x0a0a); 523 rtl_write_word(rtlpriv, REG_SIFS_OFDM, 0x1010); 524 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0204); 525 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004); 526 /* TXOP */ 527 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B); 528 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F); 529 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324); 530 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226); 531 /* PIFS */ 532 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); 533 /* AGGR BREAK TIME Register */ 534 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 535 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); 536 rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x02); 537 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x02); 538 } 539 540 void rtl92c_init_ampdu_aggregation(struct ieee80211_hw *hw) 541 { 542 struct rtl_priv *rtlpriv = rtl_priv(hw); 543 544 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x99997631); 545 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 546 /* init AMPDU aggregation number, tuning for Tx's TP, */ 547 rtl_write_word(rtlpriv, 0x4CA, 0x0708); 548 } 549 550 void rtl92c_init_beacon_max_error(struct ieee80211_hw *hw) 551 { 552 struct rtl_priv *rtlpriv = rtl_priv(hw); 553 554 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF); 555 } 556 557 void rtl92c_init_rdg_setting(struct ieee80211_hw *hw) 558 { 559 struct rtl_priv *rtlpriv = rtl_priv(hw); 560 561 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xFF); 562 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200); 563 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05); 564 } 565 566 void rtl92c_init_retry_function(struct ieee80211_hw *hw) 567 { 568 u8 value8; 569 struct rtl_priv *rtlpriv = rtl_priv(hw); 570 571 value8 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL); 572 value8 |= EN_AMPDU_RTY_NEW; 573 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL, value8); 574 /* Set ACK timeout */ 575 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); 576 } 577 578 void rtl92c_disable_fast_edca(struct ieee80211_hw *hw) 579 { 580 struct rtl_priv *rtlpriv = rtl_priv(hw); 581 582 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0); 583 } 584 585 void rtl92c_set_min_space(struct ieee80211_hw *hw, bool is2T) 586 { 587 struct rtl_priv *rtlpriv = rtl_priv(hw); 588 u8 value = is2T ? MAX_MSS_DENSITY_2T : MAX_MSS_DENSITY_1T; 589 590 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, value); 591 } 592 593 /*==============================================================*/ 594 595 static u8 _rtl92c_query_rxpwrpercentage(s8 antpower) 596 { 597 if ((antpower <= -100) || (antpower >= 20)) 598 return 0; 599 else if (antpower >= 0) 600 return 100; 601 else 602 return 100 + antpower; 603 } 604 605 static u8 _rtl92c_evm_db_to_percentage(s8 value) 606 { 607 s8 ret_val; 608 609 ret_val = value; 610 if (ret_val >= 0) 611 ret_val = 0; 612 if (ret_val <= -33) 613 ret_val = -33; 614 ret_val = 0 - ret_val; 615 ret_val *= 3; 616 if (ret_val == 99) 617 ret_val = 100; 618 return ret_val; 619 } 620 621 static long _rtl92c_signal_scale_mapping(struct ieee80211_hw *hw, 622 long currsig) 623 { 624 long retsig; 625 626 if (currsig >= 61 && currsig <= 100) 627 retsig = 90 + ((currsig - 60) / 4); 628 else if (currsig >= 41 && currsig <= 60) 629 retsig = 78 + ((currsig - 40) / 2); 630 else if (currsig >= 31 && currsig <= 40) 631 retsig = 66 + (currsig - 30); 632 else if (currsig >= 21 && currsig <= 30) 633 retsig = 54 + (currsig - 20); 634 else if (currsig >= 5 && currsig <= 20) 635 retsig = 42 + (((currsig - 5) * 2) / 3); 636 else if (currsig == 4) 637 retsig = 36; 638 else if (currsig == 3) 639 retsig = 27; 640 else if (currsig == 2) 641 retsig = 18; 642 else if (currsig == 1) 643 retsig = 9; 644 else 645 retsig = currsig; 646 return retsig; 647 } 648 649 static void _rtl92c_query_rxphystatus(struct ieee80211_hw *hw, 650 struct rtl_stats *pstats, 651 struct rx_desc_92c *p_desc, 652 struct rx_fwinfo_92c *p_drvinfo, 653 bool packet_match_bssid, 654 bool packet_toself, 655 bool packet_beacon) 656 { 657 struct rtl_priv *rtlpriv = rtl_priv(hw); 658 struct rtl_phy *rtlphy = &(rtlpriv->phy); 659 struct phy_sts_cck_8192s_t *cck_buf; 660 s8 rx_pwr_all = 0, rx_pwr[4]; 661 u8 rf_rx_num = 0, evm, pwdb_all; 662 u8 i, max_spatial_stream; 663 u32 rssi, total_rssi = 0; 664 bool in_powersavemode = false; 665 bool is_cck_rate; 666 u8 *pdesc = (u8 *)p_desc; 667 668 is_cck_rate = RX_HAL_IS_CCK_RATE(p_desc->rxmcs); 669 pstats->packet_matchbssid = packet_match_bssid; 670 pstats->packet_toself = packet_toself; 671 pstats->packet_beacon = packet_beacon; 672 pstats->is_cck = is_cck_rate; 673 pstats->RX_SIGQ[0] = -1; 674 pstats->RX_SIGQ[1] = -1; 675 if (is_cck_rate) { 676 u8 report, cck_highpwr; 677 cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo; 678 if (!in_powersavemode) 679 cck_highpwr = rtlphy->cck_high_power; 680 else 681 cck_highpwr = false; 682 if (!cck_highpwr) { 683 u8 cck_agc_rpt = cck_buf->cck_agc_rpt; 684 report = cck_buf->cck_agc_rpt & 0xc0; 685 report = report >> 6; 686 switch (report) { 687 case 0x3: 688 rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); 689 break; 690 case 0x2: 691 rx_pwr_all = -26 - (cck_agc_rpt & 0x3e); 692 break; 693 case 0x1: 694 rx_pwr_all = -12 - (cck_agc_rpt & 0x3e); 695 break; 696 case 0x0: 697 rx_pwr_all = 16 - (cck_agc_rpt & 0x3e); 698 break; 699 } 700 } else { 701 u8 cck_agc_rpt = cck_buf->cck_agc_rpt; 702 report = p_drvinfo->cfosho[0] & 0x60; 703 report = report >> 5; 704 switch (report) { 705 case 0x3: 706 rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1); 707 break; 708 case 0x2: 709 rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1); 710 break; 711 case 0x1: 712 rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1); 713 break; 714 case 0x0: 715 rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1); 716 break; 717 } 718 } 719 pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all); 720 pstats->rx_pwdb_all = pwdb_all; 721 pstats->recvsignalpower = rx_pwr_all; 722 if (packet_match_bssid) { 723 u8 sq; 724 if (pstats->rx_pwdb_all > 40) 725 sq = 100; 726 else { 727 sq = cck_buf->sq_rpt; 728 if (sq > 64) 729 sq = 0; 730 else if (sq < 20) 731 sq = 100; 732 else 733 sq = ((64 - sq) * 100) / 44; 734 } 735 pstats->signalquality = sq; 736 pstats->RX_SIGQ[0] = sq; 737 pstats->RX_SIGQ[1] = -1; 738 } 739 } else { 740 rtlpriv->dm.rfpath_rxenable[0] = 741 rtlpriv->dm.rfpath_rxenable[1] = true; 742 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) { 743 if (rtlpriv->dm.rfpath_rxenable[i]) 744 rf_rx_num++; 745 rx_pwr[i] = 746 ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) - 110; 747 rssi = _rtl92c_query_rxpwrpercentage(rx_pwr[i]); 748 total_rssi += rssi; 749 rtlpriv->stats.rx_snr_db[i] = 750 (long)(p_drvinfo->rxsnr[i] / 2); 751 752 if (packet_match_bssid) 753 pstats->rx_mimo_signalstrength[i] = (u8) rssi; 754 } 755 rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110; 756 pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all); 757 pstats->rx_pwdb_all = pwdb_all; 758 pstats->rxpower = rx_pwr_all; 759 pstats->recvsignalpower = rx_pwr_all; 760 if (GET_RX_DESC_RX_MCS(pdesc) && 761 GET_RX_DESC_RX_MCS(pdesc) >= DESC_RATEMCS8 && 762 GET_RX_DESC_RX_MCS(pdesc) <= DESC_RATEMCS15) 763 max_spatial_stream = 2; 764 else 765 max_spatial_stream = 1; 766 for (i = 0; i < max_spatial_stream; i++) { 767 evm = _rtl92c_evm_db_to_percentage(p_drvinfo->rxevm[i]); 768 if (packet_match_bssid) { 769 if (i == 0) 770 pstats->signalquality = 771 (u8) (evm & 0xff); 772 pstats->RX_SIGQ[i] = 773 (u8) (evm & 0xff); 774 } 775 } 776 } 777 if (is_cck_rate) 778 pstats->signalstrength = 779 (u8) (_rtl92c_signal_scale_mapping(hw, pwdb_all)); 780 else if (rf_rx_num != 0) 781 pstats->signalstrength = 782 (u8) (_rtl92c_signal_scale_mapping 783 (hw, total_rssi /= rf_rx_num)); 784 } 785 786 void rtl92c_translate_rx_signal_stuff(struct ieee80211_hw *hw, 787 struct sk_buff *skb, 788 struct rtl_stats *pstats, 789 struct rx_desc_92c *pdesc, 790 struct rx_fwinfo_92c *p_drvinfo) 791 { 792 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 793 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 794 struct ieee80211_hdr *hdr; 795 u8 *tmp_buf; 796 u8 *praddr; 797 __le16 fc; 798 u16 type, cpu_fc; 799 bool packet_matchbssid, packet_toself, packet_beacon = false; 800 801 tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift; 802 hdr = (struct ieee80211_hdr *)tmp_buf; 803 fc = hdr->frame_control; 804 cpu_fc = le16_to_cpu(fc); 805 type = WLAN_FC_GET_TYPE(fc); 806 praddr = hdr->addr1; 807 packet_matchbssid = 808 ((IEEE80211_FTYPE_CTL != type) && 809 ether_addr_equal(mac->bssid, 810 (cpu_fc & IEEE80211_FCTL_TODS) ? hdr->addr1 : 811 (cpu_fc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 : 812 hdr->addr3) && 813 (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv)); 814 815 packet_toself = packet_matchbssid && 816 ether_addr_equal(praddr, rtlefuse->dev_addr); 817 if (ieee80211_is_beacon(fc)) 818 packet_beacon = true; 819 _rtl92c_query_rxphystatus(hw, pstats, pdesc, p_drvinfo, 820 packet_matchbssid, packet_toself, 821 packet_beacon); 822 rtl_process_phyinfo(hw, tmp_buf, pstats); 823 } 824