1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../cam.h" 30 #include "../ps.h" 31 #include "../usb.h" 32 #include "reg.h" 33 #include "def.h" 34 #include "phy.h" 35 #include "../rtl8192c/phy_common.h" 36 #include "mac.h" 37 #include "dm.h" 38 #include "../rtl8192c/dm_common.h" 39 #include "../rtl8192c/fw_common.h" 40 #include "hw.h" 41 #include "../rtl8192ce/hw.h" 42 #include "trx.h" 43 #include "led.h" 44 #include "table.h" 45 46 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw) 47 { 48 struct rtl_priv *rtlpriv = rtl_priv(hw); 49 struct rtl_phy *rtlphy = &(rtlpriv->phy); 50 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); 51 52 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH; 53 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY; 54 if (IS_HIGHT_PA(rtlefuse->board_type)) { 55 rtlphy->hwparam_tables[PHY_REG_PG].length = 56 RTL8192CUPHY_REG_Array_PG_HPLength; 57 rtlphy->hwparam_tables[PHY_REG_PG].pdata = 58 RTL8192CUPHY_REG_Array_PG_HP; 59 } else { 60 rtlphy->hwparam_tables[PHY_REG_PG].length = 61 RTL8192CUPHY_REG_ARRAY_PGLENGTH; 62 rtlphy->hwparam_tables[PHY_REG_PG].pdata = 63 RTL8192CUPHY_REG_ARRAY_PG; 64 } 65 /* 2T */ 66 rtlphy->hwparam_tables[PHY_REG_2T].length = 67 RTL8192CUPHY_REG_2TARRAY_LENGTH; 68 rtlphy->hwparam_tables[PHY_REG_2T].pdata = 69 RTL8192CUPHY_REG_2TARRAY; 70 rtlphy->hwparam_tables[RADIOA_2T].length = 71 RTL8192CURADIOA_2TARRAYLENGTH; 72 rtlphy->hwparam_tables[RADIOA_2T].pdata = 73 RTL8192CURADIOA_2TARRAY; 74 rtlphy->hwparam_tables[RADIOB_2T].length = 75 RTL8192CURADIOB_2TARRAYLENGTH; 76 rtlphy->hwparam_tables[RADIOB_2T].pdata = 77 RTL8192CU_RADIOB_2TARRAY; 78 rtlphy->hwparam_tables[AGCTAB_2T].length = 79 RTL8192CUAGCTAB_2TARRAYLENGTH; 80 rtlphy->hwparam_tables[AGCTAB_2T].pdata = 81 RTL8192CUAGCTAB_2TARRAY; 82 /* 1T */ 83 if (IS_HIGHT_PA(rtlefuse->board_type)) { 84 rtlphy->hwparam_tables[PHY_REG_1T].length = 85 RTL8192CUPHY_REG_1T_HPArrayLength; 86 rtlphy->hwparam_tables[PHY_REG_1T].pdata = 87 RTL8192CUPHY_REG_1T_HPArray; 88 rtlphy->hwparam_tables[RADIOA_1T].length = 89 RTL8192CURadioA_1T_HPArrayLength; 90 rtlphy->hwparam_tables[RADIOA_1T].pdata = 91 RTL8192CURadioA_1T_HPArray; 92 rtlphy->hwparam_tables[RADIOB_1T].length = 93 RTL8192CURADIOB_1TARRAYLENGTH; 94 rtlphy->hwparam_tables[RADIOB_1T].pdata = 95 RTL8192CU_RADIOB_1TARRAY; 96 rtlphy->hwparam_tables[AGCTAB_1T].length = 97 RTL8192CUAGCTAB_1T_HPArrayLength; 98 rtlphy->hwparam_tables[AGCTAB_1T].pdata = 99 Rtl8192CUAGCTAB_1T_HPArray; 100 } else { 101 rtlphy->hwparam_tables[PHY_REG_1T].length = 102 RTL8192CUPHY_REG_1TARRAY_LENGTH; 103 rtlphy->hwparam_tables[PHY_REG_1T].pdata = 104 RTL8192CUPHY_REG_1TARRAY; 105 rtlphy->hwparam_tables[RADIOA_1T].length = 106 RTL8192CURADIOA_1TARRAYLENGTH; 107 rtlphy->hwparam_tables[RADIOA_1T].pdata = 108 RTL8192CU_RADIOA_1TARRAY; 109 rtlphy->hwparam_tables[RADIOB_1T].length = 110 RTL8192CURADIOB_1TARRAYLENGTH; 111 rtlphy->hwparam_tables[RADIOB_1T].pdata = 112 RTL8192CU_RADIOB_1TARRAY; 113 rtlphy->hwparam_tables[AGCTAB_1T].length = 114 RTL8192CUAGCTAB_1TARRAYLENGTH; 115 rtlphy->hwparam_tables[AGCTAB_1T].pdata = 116 RTL8192CUAGCTAB_1TARRAY; 117 } 118 } 119 120 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 121 bool autoload_fail, 122 u8 *hwinfo) 123 { 124 struct rtl_priv *rtlpriv = rtl_priv(hw); 125 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 126 u8 rf_path, index, tempval; 127 u16 i; 128 129 for (rf_path = 0; rf_path < 2; rf_path++) { 130 for (i = 0; i < 3; i++) { 131 if (!autoload_fail) { 132 rtlefuse-> 133 eeprom_chnlarea_txpwr_cck[rf_path][i] = 134 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; 135 rtlefuse-> 136 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 137 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + 138 i]; 139 } else { 140 rtlefuse-> 141 eeprom_chnlarea_txpwr_cck[rf_path][i] = 142 EEPROM_DEFAULT_TXPOWERLEVEL; 143 rtlefuse-> 144 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 145 EEPROM_DEFAULT_TXPOWERLEVEL; 146 } 147 } 148 } 149 for (i = 0; i < 3; i++) { 150 if (!autoload_fail) 151 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i]; 152 else 153 tempval = EEPROM_DEFAULT_HT40_2SDIFF; 154 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] = 155 (tempval & 0xf); 156 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] = 157 ((tempval & 0xf0) >> 4); 158 } 159 for (rf_path = 0; rf_path < 2; rf_path++) 160 for (i = 0; i < 3; i++) 161 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 162 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", 163 rf_path, i, 164 rtlefuse-> 165 eeprom_chnlarea_txpwr_cck[rf_path][i]); 166 for (rf_path = 0; rf_path < 2; rf_path++) 167 for (i = 0; i < 3; i++) 168 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 169 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 170 rf_path, i, 171 rtlefuse-> 172 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]); 173 for (rf_path = 0; rf_path < 2; rf_path++) 174 for (i = 0; i < 3; i++) 175 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 176 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 177 rf_path, i, 178 rtlefuse-> 179 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]); 180 for (rf_path = 0; rf_path < 2; rf_path++) { 181 for (i = 0; i < 14; i++) { 182 index = rtl92c_get_chnl_group((u8)i); 183 rtlefuse->txpwrlevel_cck[rf_path][i] = 184 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index]; 185 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 186 rtlefuse-> 187 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index]; 188 if ((rtlefuse-> 189 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] - 190 rtlefuse-> 191 eprom_chnl_txpwr_ht40_2sdf[rf_path][index]) 192 > 0) { 193 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 194 rtlefuse-> 195 eeprom_chnlarea_txpwr_ht40_1s[rf_path] 196 [index] - rtlefuse-> 197 eprom_chnl_txpwr_ht40_2sdf[rf_path] 198 [index]; 199 } else { 200 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; 201 } 202 } 203 for (i = 0; i < 14; i++) { 204 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 205 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i, 206 rtlefuse->txpwrlevel_cck[rf_path][i], 207 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 208 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 209 } 210 } 211 for (i = 0; i < 3; i++) { 212 if (!autoload_fail) { 213 rtlefuse->eeprom_pwrlimit_ht40[i] = 214 hwinfo[EEPROM_TXPWR_GROUP + i]; 215 rtlefuse->eeprom_pwrlimit_ht20[i] = 216 hwinfo[EEPROM_TXPWR_GROUP + 3 + i]; 217 } else { 218 rtlefuse->eeprom_pwrlimit_ht40[i] = 0; 219 rtlefuse->eeprom_pwrlimit_ht20[i] = 0; 220 } 221 } 222 for (rf_path = 0; rf_path < 2; rf_path++) { 223 for (i = 0; i < 14; i++) { 224 index = rtl92c_get_chnl_group((u8)i); 225 if (rf_path == RF90_PATH_A) { 226 rtlefuse->pwrgroup_ht20[rf_path][i] = 227 (rtlefuse->eeprom_pwrlimit_ht20[index] 228 & 0xf); 229 rtlefuse->pwrgroup_ht40[rf_path][i] = 230 (rtlefuse->eeprom_pwrlimit_ht40[index] 231 & 0xf); 232 } else if (rf_path == RF90_PATH_B) { 233 rtlefuse->pwrgroup_ht20[rf_path][i] = 234 ((rtlefuse->eeprom_pwrlimit_ht20[index] 235 & 0xf0) >> 4); 236 rtlefuse->pwrgroup_ht40[rf_path][i] = 237 ((rtlefuse->eeprom_pwrlimit_ht40[index] 238 & 0xf0) >> 4); 239 } 240 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 241 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", 242 rf_path, i, 243 rtlefuse->pwrgroup_ht20[rf_path][i]); 244 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 245 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", 246 rf_path, i, 247 rtlefuse->pwrgroup_ht40[rf_path][i]); 248 } 249 } 250 for (i = 0; i < 14; i++) { 251 index = rtl92c_get_chnl_group((u8)i); 252 if (!autoload_fail) 253 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; 254 else 255 tempval = EEPROM_DEFAULT_HT20_DIFF; 256 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 257 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 258 ((tempval >> 4) & 0xF); 259 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) 260 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; 261 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) 262 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; 263 index = rtl92c_get_chnl_group((u8)i); 264 if (!autoload_fail) 265 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; 266 else 267 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 268 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); 269 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 270 ((tempval >> 4) & 0xF); 271 } 272 rtlefuse->legacy_ht_txpowerdiff = 273 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; 274 for (i = 0; i < 14; i++) 275 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 276 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", 277 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 278 for (i = 0; i < 14; i++) 279 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 280 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", 281 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 282 for (i = 0; i < 14; i++) 283 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 284 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", 285 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 286 for (i = 0; i < 14; i++) 287 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 288 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", 289 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 290 if (!autoload_fail) 291 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); 292 else 293 rtlefuse->eeprom_regulatory = 0; 294 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 295 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 296 if (!autoload_fail) { 297 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; 298 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B]; 299 } else { 300 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; 301 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI; 302 } 303 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 304 "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 305 rtlefuse->eeprom_tssi[RF90_PATH_A], 306 rtlefuse->eeprom_tssi[RF90_PATH_B]); 307 if (!autoload_fail) 308 tempval = hwinfo[EEPROM_THERMAL_METER]; 309 else 310 tempval = EEPROM_DEFAULT_THERMALMETER; 311 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); 312 if (rtlefuse->eeprom_thermalmeter < 0x06 || 313 rtlefuse->eeprom_thermalmeter > 0x1c) 314 rtlefuse->eeprom_thermalmeter = 0x12; 315 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) 316 rtlefuse->apk_thermalmeterignore = true; 317 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 318 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 319 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 320 } 321 322 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents) 323 { 324 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 325 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 326 u8 boardType; 327 328 if (IS_NORMAL_CHIP(rtlhal->version)) { 329 boardType = ((contents[EEPROM_RF_OPT1]) & 330 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/ 331 } else { 332 boardType = contents[EEPROM_RF_OPT4]; 333 boardType &= BOARD_TYPE_TEST_MASK; 334 } 335 rtlefuse->board_type = boardType; 336 if (IS_HIGHT_PA(rtlefuse->board_type)) 337 rtlefuse->external_pa = 1; 338 pr_info("Board Type %x\n", rtlefuse->board_type); 339 } 340 341 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw) 342 { 343 struct rtl_priv *rtlpriv = rtl_priv(hw); 344 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 345 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 346 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, 347 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 348 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 349 0}; 350 u8 *hwinfo; 351 352 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 353 if (!hwinfo) 354 return; 355 356 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 357 goto exit; 358 359 _rtl92cu_read_txpower_info_from_hwpg(hw, 360 rtlefuse->autoload_failflag, hwinfo); 361 _rtl92cu_read_board_type(hw, hwinfo); 362 363 rtlefuse->txpwr_fromeprom = true; 364 if (rtlhal->oem_id == RT_CID_DEFAULT) { 365 switch (rtlefuse->eeprom_oemid) { 366 case EEPROM_CID_DEFAULT: 367 if (rtlefuse->eeprom_did == 0x8176) { 368 if ((rtlefuse->eeprom_svid == 0x103C && 369 rtlefuse->eeprom_smid == 0x1629)) 370 rtlhal->oem_id = RT_CID_819X_HP; 371 else 372 rtlhal->oem_id = RT_CID_DEFAULT; 373 } else { 374 rtlhal->oem_id = RT_CID_DEFAULT; 375 } 376 break; 377 case EEPROM_CID_TOSHIBA: 378 rtlhal->oem_id = RT_CID_TOSHIBA; 379 break; 380 case EEPROM_CID_QMI: 381 rtlhal->oem_id = RT_CID_819X_QMI; 382 break; 383 case EEPROM_CID_WHQL: 384 default: 385 rtlhal->oem_id = RT_CID_DEFAULT; 386 break; 387 } 388 } 389 exit: 390 kfree(hwinfo); 391 } 392 393 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw) 394 { 395 struct rtl_priv *rtlpriv = rtl_priv(hw); 396 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw); 397 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 398 399 switch (rtlhal->oem_id) { 400 case RT_CID_819X_HP: 401 usb_priv->ledctl.led_opendrain = true; 402 break; 403 case RT_CID_819X_LENOVO: 404 case RT_CID_DEFAULT: 405 case RT_CID_TOSHIBA: 406 case RT_CID_CCX: 407 case RT_CID_819X_ACER: 408 case RT_CID_WHQL: 409 default: 410 break; 411 } 412 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n", 413 rtlhal->oem_id); 414 } 415 416 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw) 417 { 418 419 struct rtl_priv *rtlpriv = rtl_priv(hw); 420 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 421 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 422 u8 tmp_u1b; 423 424 if (!IS_NORMAL_CHIP(rtlhal->version)) 425 return; 426 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 427 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ? 428 EEPROM_93C46 : EEPROM_BOOT_EFUSE; 429 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n", 430 tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE"); 431 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true; 432 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n", 433 tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!"); 434 _rtl92cu_read_adapter_info(hw); 435 _rtl92cu_hal_customized_behavior(hw); 436 return; 437 } 438 439 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw) 440 { 441 struct rtl_priv *rtlpriv = rtl_priv(hw); 442 int status = 0; 443 u16 value16; 444 u8 value8; 445 /* polling autoload done. */ 446 u32 pollingCount = 0; 447 448 do { 449 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) { 450 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 451 "Autoload Done!\n"); 452 break; 453 } 454 if (pollingCount++ > 100) { 455 pr_err("Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n"); 456 return -ENODEV; 457 } 458 } while (true); 459 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */ 460 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); 461 /* Power on when re-enter from IPS/Radio off/card disable */ 462 /* enable SPS into PWM mode */ 463 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 464 udelay(100); 465 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL); 466 if (0 == (value8 & LDV12_EN)) { 467 value8 |= LDV12_EN; 468 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8); 469 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 470 " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n", 471 value8); 472 udelay(100); 473 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL); 474 value8 &= ~ISO_MD2PP; 475 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8); 476 } 477 /* auto enable WLAN */ 478 pollingCount = 0; 479 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO); 480 value16 |= APFM_ONMAC; 481 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16); 482 do { 483 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) { 484 pr_info("MAC auto ON okay!\n"); 485 break; 486 } 487 if (pollingCount++ > 1000) { 488 pr_err("Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n"); 489 return -ENODEV; 490 } 491 } while (true); 492 /* Enable Radio ,GPIO ,and LED function */ 493 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812); 494 /* release RF digital isolation */ 495 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); 496 value16 &= ~ISO_DIOR; 497 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16); 498 /* Reconsider when to do this operation after asking HWSD. */ 499 pollingCount = 0; 500 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv, 501 REG_APSD_CTRL) & ~BIT(6))); 502 do { 503 pollingCount++; 504 } while ((pollingCount < 200) && 505 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7))); 506 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ 507 value16 = rtl_read_word(rtlpriv, REG_CR); 508 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN | 509 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC); 510 rtl_write_word(rtlpriv, REG_CR, value16); 511 return status; 512 } 513 514 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw, 515 bool wmm_enable, 516 u8 out_ep_num, 517 u8 queue_sel) 518 { 519 struct rtl_priv *rtlpriv = rtl_priv(hw); 520 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 521 bool isChipN = IS_NORMAL_CHIP(rtlhal->version); 522 u32 outEPNum = (u32)out_ep_num; 523 u32 numHQ = 0; 524 u32 numLQ = 0; 525 u32 numNQ = 0; 526 u32 numPubQ; 527 u32 value32; 528 u8 value8; 529 u32 txQPageNum, txQPageUnit, txQRemainPage; 530 531 if (!wmm_enable) { 532 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ : 533 CHIP_A_PAGE_NUM_PUBQ; 534 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ; 535 536 txQPageUnit = txQPageNum/outEPNum; 537 txQRemainPage = txQPageNum % outEPNum; 538 if (queue_sel & TX_SELE_HQ) 539 numHQ = txQPageUnit; 540 if (queue_sel & TX_SELE_LQ) 541 numLQ = txQPageUnit; 542 /* HIGH priority queue always present in the configuration of 543 * 2 out-ep. Remainder pages have assigned to High queue */ 544 if ((outEPNum > 1) && (txQRemainPage)) 545 numHQ += txQRemainPage; 546 /* NOTE: This step done before writting REG_RQPN. */ 547 if (isChipN) { 548 if (queue_sel & TX_SELE_NQ) 549 numNQ = txQPageUnit; 550 value8 = (u8)_NPQ(numNQ); 551 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); 552 } 553 } else { 554 /* for WMM ,number of out-ep must more than or equal to 2! */ 555 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ : 556 WMM_CHIP_A_PAGE_NUM_PUBQ; 557 if (queue_sel & TX_SELE_HQ) { 558 numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ : 559 WMM_CHIP_A_PAGE_NUM_HPQ; 560 } 561 if (queue_sel & TX_SELE_LQ) { 562 numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ : 563 WMM_CHIP_A_PAGE_NUM_LPQ; 564 } 565 /* NOTE: This step done before writting REG_RQPN. */ 566 if (isChipN) { 567 if (queue_sel & TX_SELE_NQ) 568 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ; 569 value8 = (u8)_NPQ(numNQ); 570 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); 571 } 572 } 573 /* TX DMA */ 574 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN; 575 rtl_write_dword(rtlpriv, REG_RQPN, value32); 576 } 577 578 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable) 579 { 580 struct rtl_priv *rtlpriv = rtl_priv(hw); 581 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 582 u8 txpktbuf_bndy; 583 u8 value8; 584 585 if (!wmm_enable) 586 txpktbuf_bndy = TX_PAGE_BOUNDARY; 587 else /* for WMM */ 588 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version)) 589 ? WMM_CHIP_B_TX_PAGE_BOUNDARY 590 : WMM_CHIP_A_TX_PAGE_BOUNDARY; 591 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 592 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 593 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy); 594 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy); 595 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy); 596 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); 597 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128); 598 rtl_write_byte(rtlpriv, REG_PBP, value8); 599 } 600 601 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ, 602 u16 bkQ, u16 viQ, u16 voQ, 603 u16 mgtQ, u16 hiQ) 604 { 605 struct rtl_priv *rtlpriv = rtl_priv(hw); 606 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7); 607 608 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) | 609 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) | 610 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ); 611 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16); 612 } 613 614 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw, 615 bool wmm_enable, 616 u8 queue_sel) 617 { 618 u16 uninitialized_var(value); 619 620 switch (queue_sel) { 621 case TX_SELE_HQ: 622 value = QUEUE_HIGH; 623 break; 624 case TX_SELE_LQ: 625 value = QUEUE_LOW; 626 break; 627 case TX_SELE_NQ: 628 value = QUEUE_NORMAL; 629 break; 630 default: 631 WARN_ON(1); /* Shall not reach here! */ 632 break; 633 } 634 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value, 635 value, value); 636 pr_info("Tx queue select: 0x%02x\n", queue_sel); 637 } 638 639 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw, 640 bool wmm_enable, 641 u8 queue_sel) 642 { 643 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; 644 u16 uninitialized_var(valueHi); 645 u16 uninitialized_var(valueLow); 646 647 switch (queue_sel) { 648 case (TX_SELE_HQ | TX_SELE_LQ): 649 valueHi = QUEUE_HIGH; 650 valueLow = QUEUE_LOW; 651 break; 652 case (TX_SELE_NQ | TX_SELE_LQ): 653 valueHi = QUEUE_NORMAL; 654 valueLow = QUEUE_LOW; 655 break; 656 case (TX_SELE_HQ | TX_SELE_NQ): 657 valueHi = QUEUE_HIGH; 658 valueLow = QUEUE_NORMAL; 659 break; 660 default: 661 WARN_ON(1); 662 break; 663 } 664 if (!wmm_enable) { 665 beQ = valueLow; 666 bkQ = valueLow; 667 viQ = valueHi; 668 voQ = valueHi; 669 mgtQ = valueHi; 670 hiQ = valueHi; 671 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */ 672 beQ = valueHi; 673 bkQ = valueLow; 674 viQ = valueLow; 675 voQ = valueHi; 676 mgtQ = valueHi; 677 hiQ = valueHi; 678 } 679 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ); 680 pr_info("Tx queue select: 0x%02x\n", queue_sel); 681 } 682 683 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw, 684 bool wmm_enable, 685 u8 queue_sel) 686 { 687 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; 688 689 if (!wmm_enable) { /* typical setting */ 690 beQ = QUEUE_LOW; 691 bkQ = QUEUE_LOW; 692 viQ = QUEUE_NORMAL; 693 voQ = QUEUE_HIGH; 694 mgtQ = QUEUE_HIGH; 695 hiQ = QUEUE_HIGH; 696 } else { /* for WMM */ 697 beQ = QUEUE_LOW; 698 bkQ = QUEUE_NORMAL; 699 viQ = QUEUE_NORMAL; 700 voQ = QUEUE_HIGH; 701 mgtQ = QUEUE_HIGH; 702 hiQ = QUEUE_HIGH; 703 } 704 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ); 705 pr_info("Tx queue select :0x%02x..\n", queue_sel); 706 } 707 708 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw, 709 bool wmm_enable, 710 u8 out_ep_num, 711 u8 queue_sel) 712 { 713 switch (out_ep_num) { 714 case 1: 715 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable, 716 queue_sel); 717 break; 718 case 2: 719 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable, 720 queue_sel); 721 break; 722 case 3: 723 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable, 724 queue_sel); 725 break; 726 default: 727 WARN_ON(1); /* Shall not reach here! */ 728 break; 729 } 730 } 731 732 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw, 733 bool wmm_enable, 734 u8 out_ep_num, 735 u8 queue_sel) 736 { 737 u8 hq_sele = 0; 738 struct rtl_priv *rtlpriv = rtl_priv(hw); 739 740 switch (out_ep_num) { 741 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */ 742 if (!wmm_enable) /* typical setting */ 743 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ | 744 HQSEL_HIQ; 745 else /* for WMM */ 746 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ | 747 HQSEL_HIQ; 748 break; 749 case 1: 750 if (TX_SELE_LQ == queue_sel) { 751 /* map all endpoint to Low queue */ 752 hq_sele = 0; 753 } else if (TX_SELE_HQ == queue_sel) { 754 /* map all endpoint to High queue */ 755 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ | 756 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ; 757 } 758 break; 759 default: 760 WARN_ON(1); /* Shall not reach here! */ 761 break; 762 } 763 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele); 764 pr_info("Tx queue select :0x%02x..\n", hq_sele); 765 } 766 767 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw, 768 bool wmm_enable, 769 u8 out_ep_num, 770 u8 queue_sel) 771 { 772 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 773 if (IS_NORMAL_CHIP(rtlhal->version)) 774 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num, 775 queue_sel); 776 else 777 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num, 778 queue_sel); 779 } 780 781 static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw) 782 { 783 } 784 785 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw) 786 { 787 u16 value16; 788 u32 value32; 789 struct rtl_priv *rtlpriv = rtl_priv(hw); 790 791 value32 = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS | 792 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | 793 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32); 794 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&value32)); 795 /* Accept all multicast address */ 796 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF); 797 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF); 798 /* Accept all management frames */ 799 value16 = 0xFFFF; 800 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MGT_FILTER, 801 (u8 *)(&value16)); 802 /* Reject all control frame - default value is 0 */ 803 value16 = 0x0; 804 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_CTRL_FILTER, 805 (u8 *)(&value16)); 806 /* Accept all data frames */ 807 value16 = 0xFFFF; 808 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_DATA_FILTER, 809 (u8 *)(&value16)); 810 } 811 812 static void _rtl92cu_init_beacon_parameters(struct ieee80211_hw *hw) 813 { 814 struct rtl_priv *rtlpriv = rtl_priv(hw); 815 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 816 817 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010); 818 819 /* TODO: Remove these magic number */ 820 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404); 821 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME); 822 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); 823 /* Change beacon AIFS to the largest number 824 * beacause test chip does not contension before sending beacon. 825 */ 826 if (IS_NORMAL_CHIP(rtlhal->version)) 827 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F); 828 else 829 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF); 830 } 831 832 static int _rtl92cu_init_mac(struct ieee80211_hw *hw) 833 { 834 struct rtl_priv *rtlpriv = rtl_priv(hw); 835 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 836 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw); 837 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv); 838 int err = 0; 839 u32 boundary = 0; 840 u8 wmm_enable = false; /* TODO */ 841 u8 out_ep_nums = rtlusb->out_ep_nums; 842 u8 queue_sel = rtlusb->out_queue_sel; 843 err = _rtl92cu_init_power_on(hw); 844 845 if (err) { 846 pr_err("Failed to init power on!\n"); 847 return err; 848 } 849 if (!wmm_enable) { 850 boundary = TX_PAGE_BOUNDARY; 851 } else { /* for WMM */ 852 boundary = (IS_NORMAL_CHIP(rtlhal->version)) 853 ? WMM_CHIP_B_TX_PAGE_BOUNDARY 854 : WMM_CHIP_A_TX_PAGE_BOUNDARY; 855 } 856 if (false == rtl92c_init_llt_table(hw, boundary)) { 857 pr_err("Failed to init LLT Table!\n"); 858 return -EINVAL; 859 } 860 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums, 861 queue_sel); 862 _rtl92c_init_trx_buffer(hw, wmm_enable); 863 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums, 864 queue_sel); 865 /* Get Rx PHY status in order to report RSSI and others. */ 866 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE); 867 rtl92c_init_interrupt(hw); 868 rtl92c_init_network_type(hw); 869 _rtl92cu_init_wmac_setting(hw); 870 rtl92c_init_adaptive_ctrl(hw); 871 rtl92c_init_edca(hw); 872 rtl92c_init_rate_fallback(hw); 873 rtl92c_init_retry_function(hw); 874 _rtl92cu_init_usb_aggregation(hw); 875 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20); 876 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version)); 877 _rtl92cu_init_beacon_parameters(hw); 878 rtl92c_init_ampdu_aggregation(hw); 879 rtl92c_init_beacon_max_error(hw); 880 return err; 881 } 882 883 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw) 884 { 885 struct rtl_priv *rtlpriv = rtl_priv(hw); 886 u8 sec_reg_value = 0x0; 887 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 888 889 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 890 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 891 rtlpriv->sec.pairwise_enc_algorithm, 892 rtlpriv->sec.group_enc_algorithm); 893 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 894 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 895 "not open sw encryption\n"); 896 return; 897 } 898 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable; 899 if (rtlpriv->sec.use_defaultkey) { 900 sec_reg_value |= SCR_TxUseDK; 901 sec_reg_value |= SCR_RxUseDK; 902 } 903 if (IS_NORMAL_CHIP(rtlhal->version)) 904 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 905 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 906 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n", 907 sec_reg_value); 908 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 909 } 910 911 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw) 912 { 913 struct rtl_priv *rtlpriv = rtl_priv(hw); 914 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 915 916 /* To Fix MAC loopback mode fail. */ 917 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f); 918 rtl_write_byte(rtlpriv, 0x15, 0xe9); 919 /* HW SEQ CTRL */ 920 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */ 921 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 922 /* fixed USB interface interference issue */ 923 rtl_write_byte(rtlpriv, 0xfe40, 0xe0); 924 rtl_write_byte(rtlpriv, 0xfe41, 0x8d); 925 rtl_write_byte(rtlpriv, 0xfe42, 0x80); 926 rtlusb->reg_bcn_ctrl_val = 0x18; 927 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val); 928 } 929 930 static void _InitPABias(struct ieee80211_hw *hw) 931 { 932 struct rtl_priv *rtlpriv = rtl_priv(hw); 933 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 934 u8 pa_setting; 935 936 /* FIXED PA current issue */ 937 pa_setting = efuse_read_1byte(hw, 0x1FA); 938 if (!(pa_setting & BIT(0))) { 939 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406); 940 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406); 941 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406); 942 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406); 943 } 944 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) && 945 IS_92C_SERIAL(rtlhal->version)) { 946 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406); 947 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406); 948 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406); 949 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406); 950 } 951 if (!(pa_setting & BIT(4))) { 952 pa_setting = rtl_read_byte(rtlpriv, 0x16); 953 pa_setting &= 0x0F; 954 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90); 955 } 956 } 957 958 int rtl92cu_hw_init(struct ieee80211_hw *hw) 959 { 960 struct rtl_priv *rtlpriv = rtl_priv(hw); 961 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 962 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 963 struct rtl_phy *rtlphy = &(rtlpriv->phy); 964 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 965 int err = 0; 966 unsigned long flags; 967 968 /* As this function can take a very long time (up to 350 ms) 969 * and can be called with irqs disabled, reenable the irqs 970 * to let the other devices continue being serviced. 971 * 972 * It is safe doing so since our own interrupts will only be enabled 973 * in a subsequent step. 974 */ 975 local_save_flags(flags); 976 local_irq_enable(); 977 978 rtlhal->fw_ready = false; 979 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU; 980 err = _rtl92cu_init_mac(hw); 981 if (err) { 982 pr_err("init mac failed!\n"); 983 goto exit; 984 } 985 err = rtl92c_download_fw(hw); 986 if (err) { 987 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 988 "Failed to download FW. Init HW without FW now..\n"); 989 err = 1; 990 goto exit; 991 } 992 993 rtlhal->fw_ready = true; 994 rtlhal->last_hmeboxnum = 0; /* h2c */ 995 _rtl92cu_phy_param_tab_init(hw); 996 rtl92cu_phy_mac_config(hw); 997 rtl92cu_phy_bb_config(hw); 998 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 999 rtl92c_phy_rf_config(hw); 1000 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) && 1001 !IS_92C_SERIAL(rtlhal->version)) { 1002 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); 1003 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); 1004 } 1005 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 1006 RF_CHNLBW, RFREG_OFFSET_MASK); 1007 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 1008 RF_CHNLBW, RFREG_OFFSET_MASK); 1009 rtl92cu_bb_block_on(hw); 1010 rtl_cam_reset_all_entry(hw); 1011 rtl92cu_enable_hw_security_config(hw); 1012 ppsc->rfpwr_state = ERFON; 1013 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1014 if (ppsc->rfpwr_state == ERFON) { 1015 rtl92c_phy_set_rfpath_switch(hw, 1); 1016 if (rtlphy->iqk_initialized) { 1017 rtl92c_phy_iq_calibrate(hw, true); 1018 } else { 1019 rtl92c_phy_iq_calibrate(hw, false); 1020 rtlphy->iqk_initialized = true; 1021 } 1022 rtl92c_dm_check_txpower_tracking(hw); 1023 rtl92c_phy_lc_calibrate(hw); 1024 } 1025 _rtl92cu_hw_configure(hw); 1026 _InitPABias(hw); 1027 rtl92c_dm_init(hw); 1028 exit: 1029 local_irq_restore(flags); 1030 return err; 1031 } 1032 1033 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw) 1034 { 1035 struct rtl_priv *rtlpriv = rtl_priv(hw); 1036 /************************************** 1037 a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue 1038 b. RF path 0 offset 0x00 = 0x00 disable RF 1039 c. APSD_CTRL 0x600[7:0] = 0x40 1040 d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine 1041 e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine 1042 ***************************************/ 1043 u8 eRFPath = 0, value8 = 0; 1044 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1045 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0); 1046 1047 value8 |= APSDOFF; 1048 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/ 1049 value8 = 0; 1050 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn); 1051 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/ 1052 value8 &= (~FEN_BB_GLB_RSTn); 1053 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/ 1054 } 1055 1056 static void _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM) 1057 { 1058 struct rtl_priv *rtlpriv = rtl_priv(hw); 1059 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1060 1061 if (rtlhal->fw_version <= 0x20) { 1062 /***************************** 1063 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status 1064 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset) 1065 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE 1066 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable) 1067 ******************************/ 1068 u16 valu16 = 0; 1069 1070 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1071 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1072 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 & 1073 (~FEN_CPUEN))); /* reset MCU ,8051 */ 1074 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF; 1075 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 | 1076 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */ 1077 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1078 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 | 1079 FEN_CPUEN)); /* enable MCU ,8051 */ 1080 } else { 1081 u8 retry_cnts = 0; 1082 1083 /* IF fw in RAM code, do reset */ 1084 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) { 1085 /* reset MCU ready status */ 1086 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1087 /* 8051 reset by self */ 1088 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20); 1089 while ((retry_cnts++ < 100) && 1090 (FEN_CPUEN & rtl_read_word(rtlpriv, 1091 REG_SYS_FUNC_EN))) { 1092 udelay(50); 1093 } 1094 if (retry_cnts >= 100) { 1095 pr_err("8051 reset failed!.........................\n"); 1096 /* if 8051 reset fail, reset MAC. */ 1097 rtl_write_byte(rtlpriv, 1098 REG_SYS_FUNC_EN + 1, 1099 0x50); 1100 udelay(100); 1101 } 1102 } 1103 /* Reset MAC and Enable 8051 */ 1104 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54); 1105 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1106 } 1107 if (bWithoutHWSM) { 1108 /***************************** 1109 Without HW auto state machine 1110 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock 1111 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL 1112 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK 1113 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON 1114 ******************************/ 1115 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3); 1116 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); 1117 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F); 1118 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9); 1119 } 1120 } 1121 1122 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw) 1123 { 1124 struct rtl_priv *rtlpriv = rtl_priv(hw); 1125 /***************************** 1126 k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction 1127 l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock 1128 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON 1129 ******************************/ 1130 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3); 1131 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82); 1132 } 1133 1134 static void _DisableGPIO(struct ieee80211_hw *hw) 1135 { 1136 struct rtl_priv *rtlpriv = rtl_priv(hw); 1137 /*************************************** 1138 j. GPIO_PIN_CTRL 0x44[31:0]=0x000 1139 k. Value = GPIO_PIN_CTRL[7:0] 1140 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level 1141 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780 1142 n. LEDCFG 0x4C[15:0] = 0x8080 1143 ***************************************/ 1144 u8 value8; 1145 u16 value16; 1146 u32 value32; 1147 1148 /* 1. Disable GPIO[7:0] */ 1149 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000); 1150 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF; 1151 value8 = (u8)(value32&0x000000FF); 1152 value32 |= ((value8<<8) | 0x00FF0000); 1153 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32); 1154 /* 2. Disable GPIO[10:8] */ 1155 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00); 1156 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F; 1157 value8 = (u8)(value16&0x000F); 1158 value16 |= ((value8<<4) | 0x0780); 1159 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16); 1160 /* 3. Disable LED0 & 1 */ 1161 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); 1162 } 1163 1164 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM) 1165 { 1166 struct rtl_priv *rtlpriv = rtl_priv(hw); 1167 u16 value16 = 0; 1168 u8 value8 = 0; 1169 1170 if (bWithoutHWSM) { 1171 /***************************** 1172 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power 1173 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power 1174 r. When driver call disable, the ASIC will turn off remaining 1175 clock automatically 1176 ******************************/ 1177 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04); 1178 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL); 1179 value8 &= (~LDV12_EN); 1180 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8); 1181 } 1182 1183 /***************************** 1184 h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode 1185 i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend 1186 ******************************/ 1187 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); 1188 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN); 1189 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16); 1190 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E); 1191 } 1192 1193 static void _CardDisableHWSM(struct ieee80211_hw *hw) 1194 { 1195 /* ==== RF Off Sequence ==== */ 1196 _DisableRFAFEAndResetBB(hw); 1197 /* ==== Reset digital sequence ====== */ 1198 _ResetDigitalProcedure1(hw, false); 1199 /* ==== Pull GPIO PIN to balance level and LED control ====== */ 1200 _DisableGPIO(hw); 1201 /* ==== Disable analog sequence === */ 1202 _DisableAnalog(hw, false); 1203 } 1204 1205 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw) 1206 { 1207 /*==== RF Off Sequence ==== */ 1208 _DisableRFAFEAndResetBB(hw); 1209 /* ==== Reset digital sequence ====== */ 1210 _ResetDigitalProcedure1(hw, true); 1211 /* ==== Pull GPIO PIN to balance level and LED control ====== */ 1212 _DisableGPIO(hw); 1213 /* ==== Reset digital sequence ====== */ 1214 _ResetDigitalProcedure2(hw); 1215 /* ==== Disable analog sequence === */ 1216 _DisableAnalog(hw, true); 1217 } 1218 1219 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 1220 u8 set_bits, u8 clear_bits) 1221 { 1222 struct rtl_priv *rtlpriv = rtl_priv(hw); 1223 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 1224 1225 rtlusb->reg_bcn_ctrl_val |= set_bits; 1226 rtlusb->reg_bcn_ctrl_val &= ~clear_bits; 1227 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val); 1228 } 1229 1230 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw) 1231 { 1232 struct rtl_priv *rtlpriv = rtl_priv(hw); 1233 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1234 u8 tmp1byte = 0; 1235 if (IS_NORMAL_CHIP(rtlhal->version)) { 1236 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 1237 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1238 tmp1byte & (~BIT(6))); 1239 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 1240 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 1241 tmp1byte &= ~(BIT(0)); 1242 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 1243 } else { 1244 rtl_write_byte(rtlpriv, REG_TXPAUSE, 1245 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6)); 1246 } 1247 } 1248 1249 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw) 1250 { 1251 struct rtl_priv *rtlpriv = rtl_priv(hw); 1252 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1253 u8 tmp1byte = 0; 1254 1255 if (IS_NORMAL_CHIP(rtlhal->version)) { 1256 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 1257 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1258 tmp1byte | BIT(6)); 1259 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 1260 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 1261 tmp1byte |= BIT(0); 1262 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 1263 } else { 1264 rtl_write_byte(rtlpriv, REG_TXPAUSE, 1265 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6))); 1266 } 1267 } 1268 1269 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw) 1270 { 1271 struct rtl_priv *rtlpriv = rtl_priv(hw); 1272 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1273 1274 if (IS_NORMAL_CHIP(rtlhal->version)) 1275 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1)); 1276 else 1277 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1278 } 1279 1280 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw) 1281 { 1282 struct rtl_priv *rtlpriv = rtl_priv(hw); 1283 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1284 1285 if (IS_NORMAL_CHIP(rtlhal->version)) 1286 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0); 1287 else 1288 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0); 1289 } 1290 1291 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw, 1292 enum nl80211_iftype type) 1293 { 1294 struct rtl_priv *rtlpriv = rtl_priv(hw); 1295 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1296 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1297 1298 bt_msr &= 0xfc; 1299 if (type == NL80211_IFTYPE_UNSPECIFIED || type == 1300 NL80211_IFTYPE_STATION) { 1301 _rtl92cu_stop_tx_beacon(hw); 1302 _rtl92cu_enable_bcn_sub_func(hw); 1303 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) { 1304 _rtl92cu_resume_tx_beacon(hw); 1305 _rtl92cu_disable_bcn_sub_func(hw); 1306 } else { 1307 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1308 "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n", 1309 type); 1310 } 1311 switch (type) { 1312 case NL80211_IFTYPE_UNSPECIFIED: 1313 bt_msr |= MSR_NOLINK; 1314 ledaction = LED_CTL_LINK; 1315 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1316 "Set Network type to NO LINK!\n"); 1317 break; 1318 case NL80211_IFTYPE_ADHOC: 1319 bt_msr |= MSR_ADHOC; 1320 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1321 "Set Network type to Ad Hoc!\n"); 1322 break; 1323 case NL80211_IFTYPE_STATION: 1324 bt_msr |= MSR_INFRA; 1325 ledaction = LED_CTL_LINK; 1326 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1327 "Set Network type to STA!\n"); 1328 break; 1329 case NL80211_IFTYPE_AP: 1330 bt_msr |= MSR_AP; 1331 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1332 "Set Network type to AP!\n"); 1333 break; 1334 default: 1335 pr_err("Network type %d not supported!\n", type); 1336 goto error_out; 1337 } 1338 rtl_write_byte(rtlpriv, MSR, bt_msr); 1339 rtlpriv->cfg->ops->led_control(hw, ledaction); 1340 if ((bt_msr & MSR_MASK) == MSR_AP) 1341 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1342 else 1343 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1344 return 0; 1345 error_out: 1346 return 1; 1347 } 1348 1349 void rtl92cu_card_disable(struct ieee80211_hw *hw) 1350 { 1351 struct rtl_priv *rtlpriv = rtl_priv(hw); 1352 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1353 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 1354 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1355 enum nl80211_iftype opmode; 1356 1357 mac->link_state = MAC80211_NOLINK; 1358 opmode = NL80211_IFTYPE_UNSPECIFIED; 1359 _rtl92cu_set_media_status(hw, opmode); 1360 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1361 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1362 if (rtlusb->disableHWSM) 1363 _CardDisableHWSM(hw); 1364 else 1365 _CardDisableWithoutHWSM(hw); 1366 1367 /* after power off we should do iqk again */ 1368 rtlpriv->phy.iqk_initialized = false; 1369 } 1370 1371 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1372 { 1373 struct rtl_priv *rtlpriv = rtl_priv(hw); 1374 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1375 u32 reg_rcr; 1376 1377 if (rtlpriv->psc.rfpwr_state != ERFON) 1378 return; 1379 1380 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1381 1382 if (check_bssid) { 1383 u8 tmp; 1384 if (IS_NORMAL_CHIP(rtlhal->version)) { 1385 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1386 tmp = BIT(4); 1387 } else { 1388 reg_rcr |= RCR_CBSSID; 1389 tmp = BIT(4) | BIT(5); 1390 } 1391 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1392 (u8 *) (®_rcr)); 1393 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp); 1394 } else { 1395 u8 tmp; 1396 if (IS_NORMAL_CHIP(rtlhal->version)) { 1397 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1398 tmp = BIT(4); 1399 } else { 1400 reg_rcr &= ~RCR_CBSSID; 1401 tmp = BIT(4) | BIT(5); 1402 } 1403 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1404 rtlpriv->cfg->ops->set_hw_reg(hw, 1405 HW_VAR_RCR, (u8 *) (®_rcr)); 1406 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0); 1407 } 1408 } 1409 1410 /*========================================================================== */ 1411 1412 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1413 { 1414 struct rtl_priv *rtlpriv = rtl_priv(hw); 1415 1416 if (_rtl92cu_set_media_status(hw, type)) 1417 return -EOPNOTSUPP; 1418 1419 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1420 if (type != NL80211_IFTYPE_AP) 1421 rtl92cu_set_check_bssid(hw, true); 1422 } else { 1423 rtl92cu_set_check_bssid(hw, false); 1424 } 1425 1426 return 0; 1427 } 1428 1429 static void _beacon_function_enable(struct ieee80211_hw *hw) 1430 { 1431 struct rtl_priv *rtlpriv = rtl_priv(hw); 1432 1433 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00); 1434 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F); 1435 } 1436 1437 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw) 1438 { 1439 1440 struct rtl_priv *rtlpriv = rtl_priv(hw); 1441 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1442 u16 bcn_interval, atim_window; 1443 u32 value32; 1444 1445 bcn_interval = mac->beacon_interval; 1446 atim_window = 2; /*FIX MERGE */ 1447 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1448 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1449 _rtl92cu_init_beacon_parameters(hw); 1450 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 1451 /* 1452 * Force beacon frame transmission even after receiving beacon frame 1453 * from other ad hoc STA 1454 * 1455 * 1456 * Reset TSF Timer to zero, added by Roger. 2008.06.24 1457 */ 1458 value32 = rtl_read_dword(rtlpriv, REG_TCR); 1459 value32 &= ~TSFRST; 1460 rtl_write_dword(rtlpriv, REG_TCR, value32); 1461 value32 |= TSFRST; 1462 rtl_write_dword(rtlpriv, REG_TCR, value32); 1463 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD, 1464 "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n", 1465 value32); 1466 /* TODO: Modify later (Find the right parameters) 1467 * NOTE: Fix test chip's bug (about contention windows's randomness) */ 1468 if ((mac->opmode == NL80211_IFTYPE_ADHOC) || 1469 (mac->opmode == NL80211_IFTYPE_MESH_POINT) || 1470 (mac->opmode == NL80211_IFTYPE_AP)) { 1471 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50); 1472 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50); 1473 } 1474 _beacon_function_enable(hw); 1475 } 1476 1477 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw) 1478 { 1479 struct rtl_priv *rtlpriv = rtl_priv(hw); 1480 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1481 u16 bcn_interval = mac->beacon_interval; 1482 1483 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n", 1484 bcn_interval); 1485 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1486 } 1487 1488 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw, 1489 u32 add_msr, u32 rm_msr) 1490 { 1491 } 1492 1493 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 1494 { 1495 struct rtl_priv *rtlpriv = rtl_priv(hw); 1496 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1497 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1498 1499 switch (variable) { 1500 case HW_VAR_RCR: 1501 *((u32 *)(val)) = mac->rx_conf; 1502 break; 1503 case HW_VAR_RF_STATE: 1504 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 1505 break; 1506 case HW_VAR_FWLPS_RF_ON:{ 1507 enum rf_pwrstate rfState; 1508 u32 val_rcr; 1509 1510 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, 1511 (u8 *)(&rfState)); 1512 if (rfState == ERFOFF) { 1513 *((bool *) (val)) = true; 1514 } else { 1515 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 1516 val_rcr &= 0x00070000; 1517 if (val_rcr) 1518 *((bool *) (val)) = false; 1519 else 1520 *((bool *) (val)) = true; 1521 } 1522 break; 1523 } 1524 case HW_VAR_FW_PSMODE_STATUS: 1525 *((bool *) (val)) = ppsc->fw_current_inpsmode; 1526 break; 1527 case HW_VAR_CORRECT_TSF:{ 1528 u64 tsf; 1529 u32 *ptsf_low = (u32 *)&tsf; 1530 u32 *ptsf_high = ((u32 *)&tsf) + 1; 1531 1532 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 1533 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 1534 *((u64 *)(val)) = tsf; 1535 break; 1536 } 1537 case HW_VAR_MGT_FILTER: 1538 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0); 1539 break; 1540 case HW_VAR_CTRL_FILTER: 1541 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1); 1542 break; 1543 case HW_VAR_DATA_FILTER: 1544 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2); 1545 break; 1546 case HAL_DEF_WOWLAN: 1547 break; 1548 default: 1549 pr_err("switch case %#x not processed\n", variable); 1550 break; 1551 } 1552 } 1553 1554 static bool usb_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb) 1555 { 1556 /* Currently nothing happens here. 1557 * Traffic stops after some seconds in WPA2 802.11n mode. 1558 * Maybe because rtl8192cu chip should be set from here? 1559 * If I understand correctly, the realtek vendor driver sends some urbs 1560 * if its "here". 1561 * 1562 * This is maybe necessary: 1563 * rtlpriv->cfg->ops->fill_tx_cmddesc(hw, buffer, 1, 1, skb); 1564 */ 1565 return true; 1566 } 1567 1568 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 1569 { 1570 struct rtl_priv *rtlpriv = rtl_priv(hw); 1571 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1572 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1573 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1574 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1575 enum wireless_mode wirelessmode = mac->mode; 1576 u8 idx = 0; 1577 1578 switch (variable) { 1579 case HW_VAR_ETHER_ADDR:{ 1580 for (idx = 0; idx < ETH_ALEN; idx++) { 1581 rtl_write_byte(rtlpriv, (REG_MACID + idx), 1582 val[idx]); 1583 } 1584 break; 1585 } 1586 case HW_VAR_BASIC_RATE:{ 1587 u16 rate_cfg = ((u16 *) val)[0]; 1588 u8 rate_index = 0; 1589 1590 rate_cfg &= 0x15f; 1591 /* TODO */ 1592 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO 1593 * && ((rate_cfg & 0x150) == 0)) { 1594 * rate_cfg |= 0x010; 1595 * } */ 1596 rate_cfg |= 0x01; 1597 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); 1598 rtl_write_byte(rtlpriv, REG_RRSR + 1, 1599 (rate_cfg >> 8) & 0xff); 1600 while (rate_cfg > 0x1) { 1601 rate_cfg >>= 1; 1602 rate_index++; 1603 } 1604 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 1605 rate_index); 1606 break; 1607 } 1608 case HW_VAR_BSSID:{ 1609 for (idx = 0; idx < ETH_ALEN; idx++) { 1610 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 1611 val[idx]); 1612 } 1613 break; 1614 } 1615 case HW_VAR_SIFS:{ 1616 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]); 1617 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]); 1618 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 1619 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 1620 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]); 1621 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]); 1622 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n"); 1623 break; 1624 } 1625 case HW_VAR_SLOT_TIME:{ 1626 u8 e_aci; 1627 u8 QOS_MODE = 1; 1628 1629 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 1630 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1631 "HW_VAR_SLOT_TIME %x\n", val[0]); 1632 if (QOS_MODE) { 1633 for (e_aci = 0; e_aci < AC_MAX; e_aci++) 1634 rtlpriv->cfg->ops->set_hw_reg(hw, 1635 HW_VAR_AC_PARAM, 1636 &e_aci); 1637 } else { 1638 u8 sifstime = 0; 1639 u8 u1bAIFS; 1640 1641 if (IS_WIRELESS_MODE_A(wirelessmode) || 1642 IS_WIRELESS_MODE_N_24G(wirelessmode) || 1643 IS_WIRELESS_MODE_N_5G(wirelessmode)) 1644 sifstime = 16; 1645 else 1646 sifstime = 10; 1647 u1bAIFS = sifstime + (2 * val[0]); 1648 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM, 1649 u1bAIFS); 1650 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM, 1651 u1bAIFS); 1652 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM, 1653 u1bAIFS); 1654 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM, 1655 u1bAIFS); 1656 } 1657 break; 1658 } 1659 case HW_VAR_ACK_PREAMBLE:{ 1660 u8 reg_tmp; 1661 u8 short_preamble = (bool)*val; 1662 reg_tmp = 0; 1663 if (short_preamble) 1664 reg_tmp |= 0x80; 1665 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 1666 break; 1667 } 1668 case HW_VAR_AMPDU_MIN_SPACE:{ 1669 u8 min_spacing_to_set; 1670 u8 sec_min_space; 1671 1672 min_spacing_to_set = *val; 1673 if (min_spacing_to_set <= 7) { 1674 switch (rtlpriv->sec.pairwise_enc_algorithm) { 1675 case NO_ENCRYPTION: 1676 case AESCCMP_ENCRYPTION: 1677 sec_min_space = 0; 1678 break; 1679 case WEP40_ENCRYPTION: 1680 case WEP104_ENCRYPTION: 1681 case TKIP_ENCRYPTION: 1682 sec_min_space = 6; 1683 break; 1684 default: 1685 sec_min_space = 7; 1686 break; 1687 } 1688 if (min_spacing_to_set < sec_min_space) 1689 min_spacing_to_set = sec_min_space; 1690 mac->min_space_cfg = ((mac->min_space_cfg & 1691 0xf8) | 1692 min_spacing_to_set); 1693 *val = min_spacing_to_set; 1694 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1695 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 1696 mac->min_space_cfg); 1697 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 1698 mac->min_space_cfg); 1699 } 1700 break; 1701 } 1702 case HW_VAR_SHORTGI_DENSITY:{ 1703 u8 density_to_set; 1704 1705 density_to_set = *val; 1706 density_to_set &= 0x1f; 1707 mac->min_space_cfg &= 0x07; 1708 mac->min_space_cfg |= (density_to_set << 3); 1709 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1710 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 1711 mac->min_space_cfg); 1712 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 1713 mac->min_space_cfg); 1714 break; 1715 } 1716 case HW_VAR_AMPDU_FACTOR:{ 1717 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; 1718 u8 factor_toset; 1719 u8 *p_regtoset = NULL; 1720 u8 index = 0; 1721 1722 p_regtoset = regtoset_normal; 1723 factor_toset = *val; 1724 if (factor_toset <= 3) { 1725 factor_toset = (1 << (factor_toset + 2)); 1726 if (factor_toset > 0xf) 1727 factor_toset = 0xf; 1728 for (index = 0; index < 4; index++) { 1729 if ((p_regtoset[index] & 0xf0) > 1730 (factor_toset << 4)) 1731 p_regtoset[index] = 1732 (p_regtoset[index] & 0x0f) 1733 | (factor_toset << 4); 1734 if ((p_regtoset[index] & 0x0f) > 1735 factor_toset) 1736 p_regtoset[index] = 1737 (p_regtoset[index] & 0xf0) 1738 | (factor_toset); 1739 rtl_write_byte(rtlpriv, 1740 (REG_AGGLEN_LMT + index), 1741 p_regtoset[index]); 1742 } 1743 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1744 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 1745 factor_toset); 1746 } 1747 break; 1748 } 1749 case HW_VAR_AC_PARAM:{ 1750 u8 e_aci = *val; 1751 u32 u4b_ac_param; 1752 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min); 1753 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max); 1754 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op); 1755 1756 u4b_ac_param = (u32) mac->ac[e_aci].aifs; 1757 u4b_ac_param |= (u32) ((cw_min & 0xF) << 1758 AC_PARAM_ECW_MIN_OFFSET); 1759 u4b_ac_param |= (u32) ((cw_max & 0xF) << 1760 AC_PARAM_ECW_MAX_OFFSET); 1761 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET; 1762 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1763 "queue:%x, ac_param:%x\n", 1764 e_aci, u4b_ac_param); 1765 switch (e_aci) { 1766 case AC1_BK: 1767 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 1768 u4b_ac_param); 1769 break; 1770 case AC0_BE: 1771 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 1772 u4b_ac_param); 1773 break; 1774 case AC2_VI: 1775 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 1776 u4b_ac_param); 1777 break; 1778 case AC3_VO: 1779 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 1780 u4b_ac_param); 1781 break; 1782 default: 1783 WARN_ONCE(true, "rtl8192cu: invalid aci: %d !\n", 1784 e_aci); 1785 break; 1786 } 1787 break; 1788 } 1789 case HW_VAR_RCR:{ 1790 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); 1791 mac->rx_conf = ((u32 *) (val))[0]; 1792 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG, 1793 "### Set RCR(0x%08x) ###\n", mac->rx_conf); 1794 break; 1795 } 1796 case HW_VAR_RETRY_LIMIT:{ 1797 u8 retry_limit = val[0]; 1798 1799 rtl_write_word(rtlpriv, REG_RL, 1800 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 1801 retry_limit << RETRY_LIMIT_LONG_SHIFT); 1802 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG, 1803 "Set HW_VAR_RETRY_LIMIT(0x%08x)\n", 1804 retry_limit); 1805 break; 1806 } 1807 case HW_VAR_DUAL_TSF_RST: 1808 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 1809 break; 1810 case HW_VAR_EFUSE_BYTES: 1811 rtlefuse->efuse_usedbytes = *((u16 *) val); 1812 break; 1813 case HW_VAR_EFUSE_USAGE: 1814 rtlefuse->efuse_usedpercentage = *val; 1815 break; 1816 case HW_VAR_IO_CMD: 1817 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val)); 1818 break; 1819 case HW_VAR_WPA_CONFIG: 1820 rtl_write_byte(rtlpriv, REG_SECCFG, *val); 1821 break; 1822 case HW_VAR_SET_RPWM:{ 1823 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM); 1824 1825 if (rpwm_val & BIT(7)) 1826 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val); 1827 else 1828 rtl_write_byte(rtlpriv, REG_USB_HRPWM, 1829 *val | BIT(7)); 1830 break; 1831 } 1832 case HW_VAR_H2C_FW_PWRMODE:{ 1833 u8 psmode = *val; 1834 1835 if ((psmode != FW_PS_ACTIVE_MODE) && 1836 (!IS_92C_SERIAL(rtlhal->version))) 1837 rtl92c_dm_rf_saving(hw, true); 1838 rtl92c_set_fw_pwrmode_cmd(hw, (*val)); 1839 break; 1840 } 1841 case HW_VAR_FW_PSMODE_STATUS: 1842 ppsc->fw_current_inpsmode = *((bool *) val); 1843 break; 1844 case HW_VAR_H2C_FW_JOINBSSRPT:{ 1845 u8 mstatus = *val; 1846 u8 tmp_reg422; 1847 bool recover = false; 1848 1849 if (mstatus == RT_MEDIA_CONNECT) { 1850 rtlpriv->cfg->ops->set_hw_reg(hw, 1851 HW_VAR_AID, NULL); 1852 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03); 1853 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); 1854 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0); 1855 tmp_reg422 = rtl_read_byte(rtlpriv, 1856 REG_FWHW_TXQ_CTRL + 2); 1857 if (tmp_reg422 & BIT(6)) 1858 recover = true; 1859 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1860 tmp_reg422 & (~BIT(6))); 1861 rtl92c_set_fw_rsvdpagepkt(hw, 1862 &usb_cmd_send_packet); 1863 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); 1864 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1865 if (recover) 1866 rtl_write_byte(rtlpriv, 1867 REG_FWHW_TXQ_CTRL + 2, 1868 tmp_reg422 | BIT(6)); 1869 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 1870 } 1871 rtl92c_set_fw_joinbss_report_cmd(hw, (*val)); 1872 break; 1873 } 1874 case HW_VAR_AID:{ 1875 u16 u2btmp; 1876 1877 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 1878 u2btmp &= 0xC000; 1879 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, 1880 (u2btmp | mac->assoc_id)); 1881 break; 1882 } 1883 case HW_VAR_CORRECT_TSF:{ 1884 u8 btype_ibss = val[0]; 1885 1886 if (btype_ibss) 1887 _rtl92cu_stop_tx_beacon(hw); 1888 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); 1889 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf & 1890 0xffffffff)); 1891 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 1892 (u32)((mac->tsf >> 32) & 0xffffffff)); 1893 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); 1894 if (btype_ibss) 1895 _rtl92cu_resume_tx_beacon(hw); 1896 break; 1897 } 1898 case HW_VAR_MGT_FILTER: 1899 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val); 1900 mac->rx_mgt_filter = *(u16 *)val; 1901 break; 1902 case HW_VAR_CTRL_FILTER: 1903 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val); 1904 mac->rx_ctrl_filter = *(u16 *)val; 1905 break; 1906 case HW_VAR_DATA_FILTER: 1907 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val); 1908 mac->rx_data_filter = *(u16 *)val; 1909 break; 1910 case HW_VAR_KEEP_ALIVE:{ 1911 u8 array[2]; 1912 array[0] = 0xff; 1913 array[1] = *((u8 *)val); 1914 rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2, 1915 array); 1916 break; 1917 } 1918 default: 1919 pr_err("switch case %#x not processed\n", variable); 1920 break; 1921 } 1922 } 1923 1924 static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw, 1925 struct ieee80211_sta *sta) 1926 { 1927 struct rtl_priv *rtlpriv = rtl_priv(hw); 1928 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1929 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1930 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1931 u32 ratr_value; 1932 u8 ratr_index = 0; 1933 u8 nmode = mac->ht_enable; 1934 u8 mimo_ps = IEEE80211_SMPS_OFF; 1935 u16 shortgi_rate; 1936 u32 tmp_ratr_value; 1937 u8 curtxbw_40mhz = mac->bw_40; 1938 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1939 1 : 0; 1940 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1941 1 : 0; 1942 enum wireless_mode wirelessmode = mac->mode; 1943 1944 if (rtlhal->current_bandtype == BAND_ON_5G) 1945 ratr_value = sta->supp_rates[1] << 4; 1946 else 1947 ratr_value = sta->supp_rates[0]; 1948 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1949 ratr_value = 0xfff; 1950 1951 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1952 sta->ht_cap.mcs.rx_mask[0] << 12); 1953 switch (wirelessmode) { 1954 case WIRELESS_MODE_B: 1955 if (ratr_value & 0x0000000c) 1956 ratr_value &= 0x0000000d; 1957 else 1958 ratr_value &= 0x0000000f; 1959 break; 1960 case WIRELESS_MODE_G: 1961 ratr_value &= 0x00000FF5; 1962 break; 1963 case WIRELESS_MODE_N_24G: 1964 case WIRELESS_MODE_N_5G: 1965 nmode = 1; 1966 if (mimo_ps == IEEE80211_SMPS_STATIC) { 1967 ratr_value &= 0x0007F005; 1968 } else { 1969 u32 ratr_mask; 1970 1971 if (get_rf_type(rtlphy) == RF_1T2R || 1972 get_rf_type(rtlphy) == RF_1T1R) 1973 ratr_mask = 0x000ff005; 1974 else 1975 ratr_mask = 0x0f0ff005; 1976 1977 ratr_value &= ratr_mask; 1978 } 1979 break; 1980 default: 1981 if (rtlphy->rf_type == RF_1T2R) 1982 ratr_value &= 0x000ff0ff; 1983 else 1984 ratr_value &= 0x0f0ff0ff; 1985 1986 break; 1987 } 1988 1989 ratr_value &= 0x0FFFFFFF; 1990 1991 if (nmode && ((curtxbw_40mhz && 1992 curshortgi_40mhz) || (!curtxbw_40mhz && 1993 curshortgi_20mhz))) { 1994 1995 ratr_value |= 0x10000000; 1996 tmp_ratr_value = (ratr_value >> 12); 1997 1998 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 1999 if ((1 << shortgi_rate) & tmp_ratr_value) 2000 break; 2001 } 2002 2003 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 2004 (shortgi_rate << 4) | (shortgi_rate); 2005 } 2006 2007 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 2008 2009 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", 2010 rtl_read_dword(rtlpriv, REG_ARFR0)); 2011 } 2012 2013 static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, 2014 struct ieee80211_sta *sta, 2015 u8 rssi_level) 2016 { 2017 struct rtl_priv *rtlpriv = rtl_priv(hw); 2018 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2019 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2020 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2021 struct rtl_sta_info *sta_entry = NULL; 2022 u32 ratr_bitmap; 2023 u8 ratr_index; 2024 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; 2025 u8 curshortgi_40mhz = curtxbw_40mhz && 2026 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2027 1 : 0; 2028 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2029 1 : 0; 2030 enum wireless_mode wirelessmode = 0; 2031 bool shortgi = false; 2032 u8 rate_mask[5]; 2033 u8 macid = 0; 2034 u8 mimo_ps = IEEE80211_SMPS_OFF; 2035 2036 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 2037 wirelessmode = sta_entry->wireless_mode; 2038 if (mac->opmode == NL80211_IFTYPE_STATION || 2039 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2040 curtxbw_40mhz = mac->bw_40; 2041 else if (mac->opmode == NL80211_IFTYPE_AP || 2042 mac->opmode == NL80211_IFTYPE_ADHOC) 2043 macid = sta->aid + 1; 2044 2045 if (rtlhal->current_bandtype == BAND_ON_5G) 2046 ratr_bitmap = sta->supp_rates[1] << 4; 2047 else 2048 ratr_bitmap = sta->supp_rates[0]; 2049 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2050 ratr_bitmap = 0xfff; 2051 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 2052 sta->ht_cap.mcs.rx_mask[0] << 12); 2053 switch (wirelessmode) { 2054 case WIRELESS_MODE_B: 2055 ratr_index = RATR_INX_WIRELESS_B; 2056 if (ratr_bitmap & 0x0000000c) 2057 ratr_bitmap &= 0x0000000d; 2058 else 2059 ratr_bitmap &= 0x0000000f; 2060 break; 2061 case WIRELESS_MODE_G: 2062 ratr_index = RATR_INX_WIRELESS_GB; 2063 2064 if (rssi_level == 1) 2065 ratr_bitmap &= 0x00000f00; 2066 else if (rssi_level == 2) 2067 ratr_bitmap &= 0x00000ff0; 2068 else 2069 ratr_bitmap &= 0x00000ff5; 2070 break; 2071 case WIRELESS_MODE_A: 2072 ratr_index = RATR_INX_WIRELESS_A; 2073 ratr_bitmap &= 0x00000ff0; 2074 break; 2075 case WIRELESS_MODE_N_24G: 2076 case WIRELESS_MODE_N_5G: 2077 ratr_index = RATR_INX_WIRELESS_NGB; 2078 2079 if (mimo_ps == IEEE80211_SMPS_STATIC) { 2080 if (rssi_level == 1) 2081 ratr_bitmap &= 0x00070000; 2082 else if (rssi_level == 2) 2083 ratr_bitmap &= 0x0007f000; 2084 else 2085 ratr_bitmap &= 0x0007f005; 2086 } else { 2087 if (rtlphy->rf_type == RF_1T2R || 2088 rtlphy->rf_type == RF_1T1R) { 2089 if (curtxbw_40mhz) { 2090 if (rssi_level == 1) 2091 ratr_bitmap &= 0x000f0000; 2092 else if (rssi_level == 2) 2093 ratr_bitmap &= 0x000ff000; 2094 else 2095 ratr_bitmap &= 0x000ff015; 2096 } else { 2097 if (rssi_level == 1) 2098 ratr_bitmap &= 0x000f0000; 2099 else if (rssi_level == 2) 2100 ratr_bitmap &= 0x000ff000; 2101 else 2102 ratr_bitmap &= 0x000ff005; 2103 } 2104 } else { 2105 if (curtxbw_40mhz) { 2106 if (rssi_level == 1) 2107 ratr_bitmap &= 0x0f0f0000; 2108 else if (rssi_level == 2) 2109 ratr_bitmap &= 0x0f0ff000; 2110 else 2111 ratr_bitmap &= 0x0f0ff015; 2112 } else { 2113 if (rssi_level == 1) 2114 ratr_bitmap &= 0x0f0f0000; 2115 else if (rssi_level == 2) 2116 ratr_bitmap &= 0x0f0ff000; 2117 else 2118 ratr_bitmap &= 0x0f0ff005; 2119 } 2120 } 2121 } 2122 2123 if ((curtxbw_40mhz && curshortgi_40mhz) || 2124 (!curtxbw_40mhz && curshortgi_20mhz)) { 2125 2126 if (macid == 0) 2127 shortgi = true; 2128 else if (macid == 1) 2129 shortgi = false; 2130 } 2131 break; 2132 default: 2133 ratr_index = RATR_INX_WIRELESS_NGB; 2134 2135 if (rtlphy->rf_type == RF_1T2R) 2136 ratr_bitmap &= 0x000ff0ff; 2137 else 2138 ratr_bitmap &= 0x0f0ff0ff; 2139 break; 2140 } 2141 sta_entry->ratr_index = ratr_index; 2142 2143 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2144 "ratr_bitmap :%x\n", ratr_bitmap); 2145 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 2146 (ratr_index << 28); 2147 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; 2148 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2149 "Rate_index:%x, ratr_val:%x, %5phC\n", 2150 ratr_index, ratr_bitmap, rate_mask); 2151 memcpy(rtlpriv->rate_mask, rate_mask, 5); 2152 /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a 2153 * "scheduled while atomic" if called directly */ 2154 schedule_work(&rtlpriv->works.fill_h2c_cmd); 2155 2156 if (macid != 0) 2157 sta_entry->ratr_index = ratr_index; 2158 } 2159 2160 void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw, 2161 struct ieee80211_sta *sta, 2162 u8 rssi_level) 2163 { 2164 struct rtl_priv *rtlpriv = rtl_priv(hw); 2165 2166 if (rtlpriv->dm.useramask) 2167 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level); 2168 else 2169 rtl92cu_update_hal_rate_table(hw, sta); 2170 } 2171 2172 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw) 2173 { 2174 struct rtl_priv *rtlpriv = rtl_priv(hw); 2175 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2176 u16 sifs_timer; 2177 2178 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2179 &mac->slot_time); 2180 if (!mac->ht_enable) 2181 sifs_timer = 0x0a0a; 2182 else 2183 sifs_timer = 0x0e0e; 2184 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2185 } 2186 2187 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid) 2188 { 2189 struct rtl_priv *rtlpriv = rtl_priv(hw); 2190 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2191 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate; 2192 u8 u1tmp = 0; 2193 bool actuallyset = false; 2194 unsigned long flag = 0; 2195 /* to do - usb autosuspend */ 2196 u8 usb_autosuspend = 0; 2197 2198 if (ppsc->swrf_processing) 2199 return false; 2200 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2201 if (ppsc->rfchange_inprogress) { 2202 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2203 return false; 2204 } else { 2205 ppsc->rfchange_inprogress = true; 2206 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2207 } 2208 cur_rfstate = ppsc->rfpwr_state; 2209 if (usb_autosuspend) { 2210 /* to do................... */ 2211 } else { 2212 if (ppsc->pwrdown_mode) { 2213 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR); 2214 e_rfpowerstate_toset = (u1tmp & BIT(7)) ? 2215 ERFOFF : ERFON; 2216 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 2217 "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp); 2218 } else { 2219 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, 2220 rtl_read_byte(rtlpriv, 2221 REG_MAC_PINMUX_CFG) & ~(BIT(3))); 2222 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); 2223 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? 2224 ERFON : ERFOFF; 2225 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 2226 "GPIO_IN=%02x\n", u1tmp); 2227 } 2228 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n", 2229 e_rfpowerstate_toset); 2230 } 2231 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { 2232 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2233 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2234 ppsc->hwradiooff = false; 2235 actuallyset = true; 2236 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset == 2237 ERFOFF)) { 2238 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2239 "GPIOChangeRF - HW Radio OFF\n"); 2240 ppsc->hwradiooff = true; 2241 actuallyset = true; 2242 } else { 2243 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2244 "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n", 2245 ppsc->hwradiooff, e_rfpowerstate_toset); 2246 } 2247 if (actuallyset) { 2248 ppsc->hwradiooff = true; 2249 if (e_rfpowerstate_toset == ERFON) { 2250 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) && 2251 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM)) 2252 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2253 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2254 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3)) 2255 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2256 } 2257 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2258 ppsc->rfchange_inprogress = false; 2259 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2260 /* For power down module, we need to enable register block 2261 * contrl reg at 0x1c. Then enable power down control bit 2262 * of register 0x04 BIT4 and BIT15 as 1. 2263 */ 2264 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) { 2265 /* Enable register area 0x0-0xc. */ 2266 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); 2267 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812); 2268 } 2269 if (e_rfpowerstate_toset == ERFOFF) { 2270 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) 2271 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2272 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2273 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2274 } 2275 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) { 2276 /* Enter D3 or ASPM after GPIO had been done. */ 2277 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) 2278 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2279 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2280 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2281 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2282 ppsc->rfchange_inprogress = false; 2283 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2284 } else { 2285 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2286 ppsc->rfchange_inprogress = false; 2287 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2288 } 2289 *valid = 1; 2290 return !ppsc->hwradiooff; 2291 } 2292