1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../cam.h" 30 #include "../ps.h" 31 #include "../usb.h" 32 #include "reg.h" 33 #include "def.h" 34 #include "phy.h" 35 #include "../rtl8192c/phy_common.h" 36 #include "mac.h" 37 #include "dm.h" 38 #include "../rtl8192c/dm_common.h" 39 #include "../rtl8192c/fw_common.h" 40 #include "hw.h" 41 #include "../rtl8192ce/hw.h" 42 #include "trx.h" 43 #include "led.h" 44 #include "table.h" 45 46 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw) 47 { 48 struct rtl_priv *rtlpriv = rtl_priv(hw); 49 struct rtl_phy *rtlphy = &(rtlpriv->phy); 50 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); 51 52 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH; 53 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY; 54 if (IS_HIGHT_PA(rtlefuse->board_type)) { 55 rtlphy->hwparam_tables[PHY_REG_PG].length = 56 RTL8192CUPHY_REG_Array_PG_HPLength; 57 rtlphy->hwparam_tables[PHY_REG_PG].pdata = 58 RTL8192CUPHY_REG_Array_PG_HP; 59 } else { 60 rtlphy->hwparam_tables[PHY_REG_PG].length = 61 RTL8192CUPHY_REG_ARRAY_PGLENGTH; 62 rtlphy->hwparam_tables[PHY_REG_PG].pdata = 63 RTL8192CUPHY_REG_ARRAY_PG; 64 } 65 /* 2T */ 66 rtlphy->hwparam_tables[PHY_REG_2T].length = 67 RTL8192CUPHY_REG_2TARRAY_LENGTH; 68 rtlphy->hwparam_tables[PHY_REG_2T].pdata = 69 RTL8192CUPHY_REG_2TARRAY; 70 rtlphy->hwparam_tables[RADIOA_2T].length = 71 RTL8192CURADIOA_2TARRAYLENGTH; 72 rtlphy->hwparam_tables[RADIOA_2T].pdata = 73 RTL8192CURADIOA_2TARRAY; 74 rtlphy->hwparam_tables[RADIOB_2T].length = 75 RTL8192CURADIOB_2TARRAYLENGTH; 76 rtlphy->hwparam_tables[RADIOB_2T].pdata = 77 RTL8192CU_RADIOB_2TARRAY; 78 rtlphy->hwparam_tables[AGCTAB_2T].length = 79 RTL8192CUAGCTAB_2TARRAYLENGTH; 80 rtlphy->hwparam_tables[AGCTAB_2T].pdata = 81 RTL8192CUAGCTAB_2TARRAY; 82 /* 1T */ 83 if (IS_HIGHT_PA(rtlefuse->board_type)) { 84 rtlphy->hwparam_tables[PHY_REG_1T].length = 85 RTL8192CUPHY_REG_1T_HPArrayLength; 86 rtlphy->hwparam_tables[PHY_REG_1T].pdata = 87 RTL8192CUPHY_REG_1T_HPArray; 88 rtlphy->hwparam_tables[RADIOA_1T].length = 89 RTL8192CURadioA_1T_HPArrayLength; 90 rtlphy->hwparam_tables[RADIOA_1T].pdata = 91 RTL8192CURadioA_1T_HPArray; 92 rtlphy->hwparam_tables[RADIOB_1T].length = 93 RTL8192CURADIOB_1TARRAYLENGTH; 94 rtlphy->hwparam_tables[RADIOB_1T].pdata = 95 RTL8192CU_RADIOB_1TARRAY; 96 rtlphy->hwparam_tables[AGCTAB_1T].length = 97 RTL8192CUAGCTAB_1T_HPArrayLength; 98 rtlphy->hwparam_tables[AGCTAB_1T].pdata = 99 Rtl8192CUAGCTAB_1T_HPArray; 100 } else { 101 rtlphy->hwparam_tables[PHY_REG_1T].length = 102 RTL8192CUPHY_REG_1TARRAY_LENGTH; 103 rtlphy->hwparam_tables[PHY_REG_1T].pdata = 104 RTL8192CUPHY_REG_1TARRAY; 105 rtlphy->hwparam_tables[RADIOA_1T].length = 106 RTL8192CURADIOA_1TARRAYLENGTH; 107 rtlphy->hwparam_tables[RADIOA_1T].pdata = 108 RTL8192CU_RADIOA_1TARRAY; 109 rtlphy->hwparam_tables[RADIOB_1T].length = 110 RTL8192CURADIOB_1TARRAYLENGTH; 111 rtlphy->hwparam_tables[RADIOB_1T].pdata = 112 RTL8192CU_RADIOB_1TARRAY; 113 rtlphy->hwparam_tables[AGCTAB_1T].length = 114 RTL8192CUAGCTAB_1TARRAYLENGTH; 115 rtlphy->hwparam_tables[AGCTAB_1T].pdata = 116 RTL8192CUAGCTAB_1TARRAY; 117 } 118 } 119 120 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 121 bool autoload_fail, 122 u8 *hwinfo) 123 { 124 struct rtl_priv *rtlpriv = rtl_priv(hw); 125 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 126 u8 rf_path, index, tempval; 127 u16 i; 128 129 for (rf_path = 0; rf_path < 2; rf_path++) { 130 for (i = 0; i < 3; i++) { 131 if (!autoload_fail) { 132 rtlefuse-> 133 eeprom_chnlarea_txpwr_cck[rf_path][i] = 134 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; 135 rtlefuse-> 136 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 137 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + 138 i]; 139 } else { 140 rtlefuse-> 141 eeprom_chnlarea_txpwr_cck[rf_path][i] = 142 EEPROM_DEFAULT_TXPOWERLEVEL; 143 rtlefuse-> 144 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 145 EEPROM_DEFAULT_TXPOWERLEVEL; 146 } 147 } 148 } 149 for (i = 0; i < 3; i++) { 150 if (!autoload_fail) 151 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i]; 152 else 153 tempval = EEPROM_DEFAULT_HT40_2SDIFF; 154 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] = 155 (tempval & 0xf); 156 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] = 157 ((tempval & 0xf0) >> 4); 158 } 159 for (rf_path = 0; rf_path < 2; rf_path++) 160 for (i = 0; i < 3; i++) 161 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 162 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", 163 rf_path, i, 164 rtlefuse-> 165 eeprom_chnlarea_txpwr_cck[rf_path][i]); 166 for (rf_path = 0; rf_path < 2; rf_path++) 167 for (i = 0; i < 3; i++) 168 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 169 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 170 rf_path, i, 171 rtlefuse-> 172 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]); 173 for (rf_path = 0; rf_path < 2; rf_path++) 174 for (i = 0; i < 3; i++) 175 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 176 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 177 rf_path, i, 178 rtlefuse-> 179 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]); 180 for (rf_path = 0; rf_path < 2; rf_path++) { 181 for (i = 0; i < 14; i++) { 182 index = rtl92c_get_chnl_group((u8)i); 183 rtlefuse->txpwrlevel_cck[rf_path][i] = 184 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index]; 185 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 186 rtlefuse-> 187 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index]; 188 if ((rtlefuse-> 189 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] - 190 rtlefuse-> 191 eprom_chnl_txpwr_ht40_2sdf[rf_path][index]) 192 > 0) { 193 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 194 rtlefuse-> 195 eeprom_chnlarea_txpwr_ht40_1s[rf_path] 196 [index] - rtlefuse-> 197 eprom_chnl_txpwr_ht40_2sdf[rf_path] 198 [index]; 199 } else { 200 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; 201 } 202 } 203 for (i = 0; i < 14; i++) { 204 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 205 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i, 206 rtlefuse->txpwrlevel_cck[rf_path][i], 207 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 208 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 209 } 210 } 211 for (i = 0; i < 3; i++) { 212 if (!autoload_fail) { 213 rtlefuse->eeprom_pwrlimit_ht40[i] = 214 hwinfo[EEPROM_TXPWR_GROUP + i]; 215 rtlefuse->eeprom_pwrlimit_ht20[i] = 216 hwinfo[EEPROM_TXPWR_GROUP + 3 + i]; 217 } else { 218 rtlefuse->eeprom_pwrlimit_ht40[i] = 0; 219 rtlefuse->eeprom_pwrlimit_ht20[i] = 0; 220 } 221 } 222 for (rf_path = 0; rf_path < 2; rf_path++) { 223 for (i = 0; i < 14; i++) { 224 index = rtl92c_get_chnl_group((u8)i); 225 if (rf_path == RF90_PATH_A) { 226 rtlefuse->pwrgroup_ht20[rf_path][i] = 227 (rtlefuse->eeprom_pwrlimit_ht20[index] 228 & 0xf); 229 rtlefuse->pwrgroup_ht40[rf_path][i] = 230 (rtlefuse->eeprom_pwrlimit_ht40[index] 231 & 0xf); 232 } else if (rf_path == RF90_PATH_B) { 233 rtlefuse->pwrgroup_ht20[rf_path][i] = 234 ((rtlefuse->eeprom_pwrlimit_ht20[index] 235 & 0xf0) >> 4); 236 rtlefuse->pwrgroup_ht40[rf_path][i] = 237 ((rtlefuse->eeprom_pwrlimit_ht40[index] 238 & 0xf0) >> 4); 239 } 240 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 241 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", 242 rf_path, i, 243 rtlefuse->pwrgroup_ht20[rf_path][i]); 244 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 245 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", 246 rf_path, i, 247 rtlefuse->pwrgroup_ht40[rf_path][i]); 248 } 249 } 250 for (i = 0; i < 14; i++) { 251 index = rtl92c_get_chnl_group((u8)i); 252 if (!autoload_fail) 253 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; 254 else 255 tempval = EEPROM_DEFAULT_HT20_DIFF; 256 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 257 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 258 ((tempval >> 4) & 0xF); 259 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) 260 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; 261 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) 262 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; 263 index = rtl92c_get_chnl_group((u8)i); 264 if (!autoload_fail) 265 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; 266 else 267 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 268 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); 269 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 270 ((tempval >> 4) & 0xF); 271 } 272 rtlefuse->legacy_ht_txpowerdiff = 273 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; 274 for (i = 0; i < 14; i++) 275 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 276 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", 277 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 278 for (i = 0; i < 14; i++) 279 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 280 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", 281 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 282 for (i = 0; i < 14; i++) 283 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 284 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", 285 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 286 for (i = 0; i < 14; i++) 287 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 288 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", 289 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 290 if (!autoload_fail) 291 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); 292 else 293 rtlefuse->eeprom_regulatory = 0; 294 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 295 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 296 if (!autoload_fail) { 297 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; 298 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B]; 299 } else { 300 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; 301 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI; 302 } 303 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 304 "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 305 rtlefuse->eeprom_tssi[RF90_PATH_A], 306 rtlefuse->eeprom_tssi[RF90_PATH_B]); 307 if (!autoload_fail) 308 tempval = hwinfo[EEPROM_THERMAL_METER]; 309 else 310 tempval = EEPROM_DEFAULT_THERMALMETER; 311 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); 312 if (rtlefuse->eeprom_thermalmeter < 0x06 || 313 rtlefuse->eeprom_thermalmeter > 0x1c) 314 rtlefuse->eeprom_thermalmeter = 0x12; 315 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) 316 rtlefuse->apk_thermalmeterignore = true; 317 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 318 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 319 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 320 } 321 322 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents) 323 { 324 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 325 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 326 u8 boardType; 327 328 if (IS_NORMAL_CHIP(rtlhal->version)) { 329 boardType = ((contents[EEPROM_RF_OPT1]) & 330 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/ 331 } else { 332 boardType = contents[EEPROM_RF_OPT4]; 333 boardType &= BOARD_TYPE_TEST_MASK; 334 } 335 rtlefuse->board_type = boardType; 336 if (IS_HIGHT_PA(rtlefuse->board_type)) 337 rtlefuse->external_pa = 1; 338 pr_info("Board Type %x\n", rtlefuse->board_type); 339 } 340 341 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw) 342 { 343 struct rtl_priv *rtlpriv = rtl_priv(hw); 344 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 345 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 346 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, 347 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 348 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 349 0}; 350 u8 *hwinfo; 351 352 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 353 if (!hwinfo) 354 return; 355 356 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 357 goto exit; 358 359 _rtl92cu_read_txpower_info_from_hwpg(hw, 360 rtlefuse->autoload_failflag, hwinfo); 361 _rtl92cu_read_board_type(hw, hwinfo); 362 363 rtlefuse->txpwr_fromeprom = true; 364 if (rtlhal->oem_id == RT_CID_DEFAULT) { 365 switch (rtlefuse->eeprom_oemid) { 366 case EEPROM_CID_DEFAULT: 367 if (rtlefuse->eeprom_did == 0x8176) { 368 if ((rtlefuse->eeprom_svid == 0x103C && 369 rtlefuse->eeprom_smid == 0x1629)) 370 rtlhal->oem_id = RT_CID_819X_HP; 371 else 372 rtlhal->oem_id = RT_CID_DEFAULT; 373 } else { 374 rtlhal->oem_id = RT_CID_DEFAULT; 375 } 376 break; 377 case EEPROM_CID_TOSHIBA: 378 rtlhal->oem_id = RT_CID_TOSHIBA; 379 break; 380 case EEPROM_CID_QMI: 381 rtlhal->oem_id = RT_CID_819X_QMI; 382 break; 383 case EEPROM_CID_WHQL: 384 default: 385 rtlhal->oem_id = RT_CID_DEFAULT; 386 break; 387 } 388 } 389 exit: 390 kfree(hwinfo); 391 } 392 393 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw) 394 { 395 struct rtl_priv *rtlpriv = rtl_priv(hw); 396 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw); 397 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 398 399 switch (rtlhal->oem_id) { 400 case RT_CID_819X_HP: 401 usb_priv->ledctl.led_opendrain = true; 402 break; 403 case RT_CID_819X_LENOVO: 404 case RT_CID_DEFAULT: 405 case RT_CID_TOSHIBA: 406 case RT_CID_CCX: 407 case RT_CID_819X_ACER: 408 case RT_CID_WHQL: 409 default: 410 break; 411 } 412 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n", 413 rtlhal->oem_id); 414 } 415 416 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw) 417 { 418 419 struct rtl_priv *rtlpriv = rtl_priv(hw); 420 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 421 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 422 u8 tmp_u1b; 423 424 if (!IS_NORMAL_CHIP(rtlhal->version)) 425 return; 426 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 427 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ? 428 EEPROM_93C46 : EEPROM_BOOT_EFUSE; 429 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n", 430 tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE"); 431 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true; 432 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n", 433 tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!"); 434 _rtl92cu_read_adapter_info(hw); 435 _rtl92cu_hal_customized_behavior(hw); 436 return; 437 } 438 439 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw) 440 { 441 struct rtl_priv *rtlpriv = rtl_priv(hw); 442 int status = 0; 443 u16 value16; 444 u8 value8; 445 /* polling autoload done. */ 446 u32 pollingCount = 0; 447 448 do { 449 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) { 450 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 451 "Autoload Done!\n"); 452 break; 453 } 454 if (pollingCount++ > 100) { 455 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, 456 "Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n"); 457 return -ENODEV; 458 } 459 } while (true); 460 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */ 461 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); 462 /* Power on when re-enter from IPS/Radio off/card disable */ 463 /* enable SPS into PWM mode */ 464 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 465 udelay(100); 466 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL); 467 if (0 == (value8 & LDV12_EN)) { 468 value8 |= LDV12_EN; 469 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8); 470 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 471 " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n", 472 value8); 473 udelay(100); 474 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL); 475 value8 &= ~ISO_MD2PP; 476 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8); 477 } 478 /* auto enable WLAN */ 479 pollingCount = 0; 480 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO); 481 value16 |= APFM_ONMAC; 482 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16); 483 do { 484 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) { 485 pr_info("MAC auto ON okay!\n"); 486 break; 487 } 488 if (pollingCount++ > 1000) { 489 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, 490 "Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n"); 491 return -ENODEV; 492 } 493 } while (true); 494 /* Enable Radio ,GPIO ,and LED function */ 495 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812); 496 /* release RF digital isolation */ 497 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); 498 value16 &= ~ISO_DIOR; 499 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16); 500 /* Reconsider when to do this operation after asking HWSD. */ 501 pollingCount = 0; 502 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv, 503 REG_APSD_CTRL) & ~BIT(6))); 504 do { 505 pollingCount++; 506 } while ((pollingCount < 200) && 507 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7))); 508 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ 509 value16 = rtl_read_word(rtlpriv, REG_CR); 510 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN | 511 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC); 512 rtl_write_word(rtlpriv, REG_CR, value16); 513 return status; 514 } 515 516 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw, 517 bool wmm_enable, 518 u8 out_ep_num, 519 u8 queue_sel) 520 { 521 struct rtl_priv *rtlpriv = rtl_priv(hw); 522 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 523 bool isChipN = IS_NORMAL_CHIP(rtlhal->version); 524 u32 outEPNum = (u32)out_ep_num; 525 u32 numHQ = 0; 526 u32 numLQ = 0; 527 u32 numNQ = 0; 528 u32 numPubQ; 529 u32 value32; 530 u8 value8; 531 u32 txQPageNum, txQPageUnit, txQRemainPage; 532 533 if (!wmm_enable) { 534 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ : 535 CHIP_A_PAGE_NUM_PUBQ; 536 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ; 537 538 txQPageUnit = txQPageNum/outEPNum; 539 txQRemainPage = txQPageNum % outEPNum; 540 if (queue_sel & TX_SELE_HQ) 541 numHQ = txQPageUnit; 542 if (queue_sel & TX_SELE_LQ) 543 numLQ = txQPageUnit; 544 /* HIGH priority queue always present in the configuration of 545 * 2 out-ep. Remainder pages have assigned to High queue */ 546 if ((outEPNum > 1) && (txQRemainPage)) 547 numHQ += txQRemainPage; 548 /* NOTE: This step done before writting REG_RQPN. */ 549 if (isChipN) { 550 if (queue_sel & TX_SELE_NQ) 551 numNQ = txQPageUnit; 552 value8 = (u8)_NPQ(numNQ); 553 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); 554 } 555 } else { 556 /* for WMM ,number of out-ep must more than or equal to 2! */ 557 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ : 558 WMM_CHIP_A_PAGE_NUM_PUBQ; 559 if (queue_sel & TX_SELE_HQ) { 560 numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ : 561 WMM_CHIP_A_PAGE_NUM_HPQ; 562 } 563 if (queue_sel & TX_SELE_LQ) { 564 numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ : 565 WMM_CHIP_A_PAGE_NUM_LPQ; 566 } 567 /* NOTE: This step done before writting REG_RQPN. */ 568 if (isChipN) { 569 if (queue_sel & TX_SELE_NQ) 570 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ; 571 value8 = (u8)_NPQ(numNQ); 572 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); 573 } 574 } 575 /* TX DMA */ 576 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN; 577 rtl_write_dword(rtlpriv, REG_RQPN, value32); 578 } 579 580 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable) 581 { 582 struct rtl_priv *rtlpriv = rtl_priv(hw); 583 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 584 u8 txpktbuf_bndy; 585 u8 value8; 586 587 if (!wmm_enable) 588 txpktbuf_bndy = TX_PAGE_BOUNDARY; 589 else /* for WMM */ 590 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version)) 591 ? WMM_CHIP_B_TX_PAGE_BOUNDARY 592 : WMM_CHIP_A_TX_PAGE_BOUNDARY; 593 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 594 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 595 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy); 596 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy); 597 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy); 598 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); 599 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128); 600 rtl_write_byte(rtlpriv, REG_PBP, value8); 601 } 602 603 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ, 604 u16 bkQ, u16 viQ, u16 voQ, 605 u16 mgtQ, u16 hiQ) 606 { 607 struct rtl_priv *rtlpriv = rtl_priv(hw); 608 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7); 609 610 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) | 611 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) | 612 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ); 613 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16); 614 } 615 616 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw, 617 bool wmm_enable, 618 u8 queue_sel) 619 { 620 u16 uninitialized_var(value); 621 622 switch (queue_sel) { 623 case TX_SELE_HQ: 624 value = QUEUE_HIGH; 625 break; 626 case TX_SELE_LQ: 627 value = QUEUE_LOW; 628 break; 629 case TX_SELE_NQ: 630 value = QUEUE_NORMAL; 631 break; 632 default: 633 WARN_ON(1); /* Shall not reach here! */ 634 break; 635 } 636 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value, 637 value, value); 638 pr_info("Tx queue select: 0x%02x\n", queue_sel); 639 } 640 641 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw, 642 bool wmm_enable, 643 u8 queue_sel) 644 { 645 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; 646 u16 uninitialized_var(valueHi); 647 u16 uninitialized_var(valueLow); 648 649 switch (queue_sel) { 650 case (TX_SELE_HQ | TX_SELE_LQ): 651 valueHi = QUEUE_HIGH; 652 valueLow = QUEUE_LOW; 653 break; 654 case (TX_SELE_NQ | TX_SELE_LQ): 655 valueHi = QUEUE_NORMAL; 656 valueLow = QUEUE_LOW; 657 break; 658 case (TX_SELE_HQ | TX_SELE_NQ): 659 valueHi = QUEUE_HIGH; 660 valueLow = QUEUE_NORMAL; 661 break; 662 default: 663 WARN_ON(1); 664 break; 665 } 666 if (!wmm_enable) { 667 beQ = valueLow; 668 bkQ = valueLow; 669 viQ = valueHi; 670 voQ = valueHi; 671 mgtQ = valueHi; 672 hiQ = valueHi; 673 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */ 674 beQ = valueHi; 675 bkQ = valueLow; 676 viQ = valueLow; 677 voQ = valueHi; 678 mgtQ = valueHi; 679 hiQ = valueHi; 680 } 681 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ); 682 pr_info("Tx queue select: 0x%02x\n", queue_sel); 683 } 684 685 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw, 686 bool wmm_enable, 687 u8 queue_sel) 688 { 689 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; 690 struct rtl_priv *rtlpriv = rtl_priv(hw); 691 692 if (!wmm_enable) { /* typical setting */ 693 beQ = QUEUE_LOW; 694 bkQ = QUEUE_LOW; 695 viQ = QUEUE_NORMAL; 696 voQ = QUEUE_HIGH; 697 mgtQ = QUEUE_HIGH; 698 hiQ = QUEUE_HIGH; 699 } else { /* for WMM */ 700 beQ = QUEUE_LOW; 701 bkQ = QUEUE_NORMAL; 702 viQ = QUEUE_NORMAL; 703 voQ = QUEUE_HIGH; 704 mgtQ = QUEUE_HIGH; 705 hiQ = QUEUE_HIGH; 706 } 707 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ); 708 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n", 709 queue_sel); 710 } 711 712 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw, 713 bool wmm_enable, 714 u8 out_ep_num, 715 u8 queue_sel) 716 { 717 switch (out_ep_num) { 718 case 1: 719 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable, 720 queue_sel); 721 break; 722 case 2: 723 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable, 724 queue_sel); 725 break; 726 case 3: 727 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable, 728 queue_sel); 729 break; 730 default: 731 WARN_ON(1); /* Shall not reach here! */ 732 break; 733 } 734 } 735 736 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw, 737 bool wmm_enable, 738 u8 out_ep_num, 739 u8 queue_sel) 740 { 741 u8 hq_sele = 0; 742 struct rtl_priv *rtlpriv = rtl_priv(hw); 743 744 switch (out_ep_num) { 745 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */ 746 if (!wmm_enable) /* typical setting */ 747 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ | 748 HQSEL_HIQ; 749 else /* for WMM */ 750 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ | 751 HQSEL_HIQ; 752 break; 753 case 1: 754 if (TX_SELE_LQ == queue_sel) { 755 /* map all endpoint to Low queue */ 756 hq_sele = 0; 757 } else if (TX_SELE_HQ == queue_sel) { 758 /* map all endpoint to High queue */ 759 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ | 760 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ; 761 } 762 break; 763 default: 764 WARN_ON(1); /* Shall not reach here! */ 765 break; 766 } 767 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele); 768 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n", 769 hq_sele); 770 } 771 772 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw, 773 bool wmm_enable, 774 u8 out_ep_num, 775 u8 queue_sel) 776 { 777 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 778 if (IS_NORMAL_CHIP(rtlhal->version)) 779 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num, 780 queue_sel); 781 else 782 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num, 783 queue_sel); 784 } 785 786 static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw) 787 { 788 } 789 790 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw) 791 { 792 u16 value16; 793 u32 value32; 794 struct rtl_priv *rtlpriv = rtl_priv(hw); 795 796 value32 = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS | 797 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | 798 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32); 799 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&value32)); 800 /* Accept all multicast address */ 801 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF); 802 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF); 803 /* Accept all management frames */ 804 value16 = 0xFFFF; 805 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MGT_FILTER, 806 (u8 *)(&value16)); 807 /* Reject all control frame - default value is 0 */ 808 value16 = 0x0; 809 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_CTRL_FILTER, 810 (u8 *)(&value16)); 811 /* Accept all data frames */ 812 value16 = 0xFFFF; 813 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_DATA_FILTER, 814 (u8 *)(&value16)); 815 } 816 817 static void _rtl92cu_init_beacon_parameters(struct ieee80211_hw *hw) 818 { 819 struct rtl_priv *rtlpriv = rtl_priv(hw); 820 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 821 822 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010); 823 824 /* TODO: Remove these magic number */ 825 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404); 826 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME); 827 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); 828 /* Change beacon AIFS to the largest number 829 * beacause test chip does not contension before sending beacon. 830 */ 831 if (IS_NORMAL_CHIP(rtlhal->version)) 832 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F); 833 else 834 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF); 835 } 836 837 static int _rtl92cu_init_mac(struct ieee80211_hw *hw) 838 { 839 struct rtl_priv *rtlpriv = rtl_priv(hw); 840 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 841 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw); 842 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv); 843 int err = 0; 844 u32 boundary = 0; 845 u8 wmm_enable = false; /* TODO */ 846 u8 out_ep_nums = rtlusb->out_ep_nums; 847 u8 queue_sel = rtlusb->out_queue_sel; 848 err = _rtl92cu_init_power_on(hw); 849 850 if (err) { 851 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 852 "Failed to init power on!\n"); 853 return err; 854 } 855 if (!wmm_enable) { 856 boundary = TX_PAGE_BOUNDARY; 857 } else { /* for WMM */ 858 boundary = (IS_NORMAL_CHIP(rtlhal->version)) 859 ? WMM_CHIP_B_TX_PAGE_BOUNDARY 860 : WMM_CHIP_A_TX_PAGE_BOUNDARY; 861 } 862 if (false == rtl92c_init_llt_table(hw, boundary)) { 863 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 864 "Failed to init LLT Table!\n"); 865 return -EINVAL; 866 } 867 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums, 868 queue_sel); 869 _rtl92c_init_trx_buffer(hw, wmm_enable); 870 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums, 871 queue_sel); 872 /* Get Rx PHY status in order to report RSSI and others. */ 873 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE); 874 rtl92c_init_interrupt(hw); 875 rtl92c_init_network_type(hw); 876 _rtl92cu_init_wmac_setting(hw); 877 rtl92c_init_adaptive_ctrl(hw); 878 rtl92c_init_edca(hw); 879 rtl92c_init_rate_fallback(hw); 880 rtl92c_init_retry_function(hw); 881 _rtl92cu_init_usb_aggregation(hw); 882 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20); 883 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version)); 884 _rtl92cu_init_beacon_parameters(hw); 885 rtl92c_init_ampdu_aggregation(hw); 886 rtl92c_init_beacon_max_error(hw); 887 return err; 888 } 889 890 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw) 891 { 892 struct rtl_priv *rtlpriv = rtl_priv(hw); 893 u8 sec_reg_value = 0x0; 894 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 895 896 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 897 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 898 rtlpriv->sec.pairwise_enc_algorithm, 899 rtlpriv->sec.group_enc_algorithm); 900 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 901 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 902 "not open sw encryption\n"); 903 return; 904 } 905 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable; 906 if (rtlpriv->sec.use_defaultkey) { 907 sec_reg_value |= SCR_TxUseDK; 908 sec_reg_value |= SCR_RxUseDK; 909 } 910 if (IS_NORMAL_CHIP(rtlhal->version)) 911 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 912 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 913 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n", 914 sec_reg_value); 915 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 916 } 917 918 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw) 919 { 920 struct rtl_priv *rtlpriv = rtl_priv(hw); 921 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 922 923 /* To Fix MAC loopback mode fail. */ 924 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f); 925 rtl_write_byte(rtlpriv, 0x15, 0xe9); 926 /* HW SEQ CTRL */ 927 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */ 928 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 929 /* fixed USB interface interference issue */ 930 rtl_write_byte(rtlpriv, 0xfe40, 0xe0); 931 rtl_write_byte(rtlpriv, 0xfe41, 0x8d); 932 rtl_write_byte(rtlpriv, 0xfe42, 0x80); 933 rtlusb->reg_bcn_ctrl_val = 0x18; 934 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val); 935 } 936 937 static void _InitPABias(struct ieee80211_hw *hw) 938 { 939 struct rtl_priv *rtlpriv = rtl_priv(hw); 940 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 941 u8 pa_setting; 942 943 /* FIXED PA current issue */ 944 pa_setting = efuse_read_1byte(hw, 0x1FA); 945 if (!(pa_setting & BIT(0))) { 946 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406); 947 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406); 948 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406); 949 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406); 950 } 951 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) && 952 IS_92C_SERIAL(rtlhal->version)) { 953 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406); 954 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406); 955 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406); 956 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406); 957 } 958 if (!(pa_setting & BIT(4))) { 959 pa_setting = rtl_read_byte(rtlpriv, 0x16); 960 pa_setting &= 0x0F; 961 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90); 962 } 963 } 964 965 int rtl92cu_hw_init(struct ieee80211_hw *hw) 966 { 967 struct rtl_priv *rtlpriv = rtl_priv(hw); 968 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 969 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 970 struct rtl_phy *rtlphy = &(rtlpriv->phy); 971 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 972 int err = 0; 973 unsigned long flags; 974 975 /* As this function can take a very long time (up to 350 ms) 976 * and can be called with irqs disabled, reenable the irqs 977 * to let the other devices continue being serviced. 978 * 979 * It is safe doing so since our own interrupts will only be enabled 980 * in a subsequent step. 981 */ 982 local_save_flags(flags); 983 local_irq_enable(); 984 985 rtlhal->fw_ready = false; 986 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU; 987 err = _rtl92cu_init_mac(hw); 988 if (err) { 989 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "init mac failed!\n"); 990 goto exit; 991 } 992 err = rtl92c_download_fw(hw); 993 if (err) { 994 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 995 "Failed to download FW. Init HW without FW now..\n"); 996 err = 1; 997 goto exit; 998 } 999 1000 rtlhal->fw_ready = true; 1001 rtlhal->last_hmeboxnum = 0; /* h2c */ 1002 _rtl92cu_phy_param_tab_init(hw); 1003 rtl92cu_phy_mac_config(hw); 1004 rtl92cu_phy_bb_config(hw); 1005 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 1006 rtl92c_phy_rf_config(hw); 1007 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) && 1008 !IS_92C_SERIAL(rtlhal->version)) { 1009 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); 1010 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); 1011 } 1012 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 1013 RF_CHNLBW, RFREG_OFFSET_MASK); 1014 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 1015 RF_CHNLBW, RFREG_OFFSET_MASK); 1016 rtl92cu_bb_block_on(hw); 1017 rtl_cam_reset_all_entry(hw); 1018 rtl92cu_enable_hw_security_config(hw); 1019 ppsc->rfpwr_state = ERFON; 1020 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1021 if (ppsc->rfpwr_state == ERFON) { 1022 rtl92c_phy_set_rfpath_switch(hw, 1); 1023 if (rtlphy->iqk_initialized) { 1024 rtl92c_phy_iq_calibrate(hw, true); 1025 } else { 1026 rtl92c_phy_iq_calibrate(hw, false); 1027 rtlphy->iqk_initialized = true; 1028 } 1029 rtl92c_dm_check_txpower_tracking(hw); 1030 rtl92c_phy_lc_calibrate(hw); 1031 } 1032 _rtl92cu_hw_configure(hw); 1033 _InitPABias(hw); 1034 rtl92c_dm_init(hw); 1035 exit: 1036 local_irq_restore(flags); 1037 return err; 1038 } 1039 1040 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw) 1041 { 1042 struct rtl_priv *rtlpriv = rtl_priv(hw); 1043 /************************************** 1044 a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue 1045 b. RF path 0 offset 0x00 = 0x00 disable RF 1046 c. APSD_CTRL 0x600[7:0] = 0x40 1047 d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine 1048 e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine 1049 ***************************************/ 1050 u8 eRFPath = 0, value8 = 0; 1051 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1052 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0); 1053 1054 value8 |= APSDOFF; 1055 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/ 1056 value8 = 0; 1057 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn); 1058 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/ 1059 value8 &= (~FEN_BB_GLB_RSTn); 1060 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/ 1061 } 1062 1063 static void _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM) 1064 { 1065 struct rtl_priv *rtlpriv = rtl_priv(hw); 1066 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1067 1068 if (rtlhal->fw_version <= 0x20) { 1069 /***************************** 1070 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status 1071 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset) 1072 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE 1073 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable) 1074 ******************************/ 1075 u16 valu16 = 0; 1076 1077 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1078 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1079 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 & 1080 (~FEN_CPUEN))); /* reset MCU ,8051 */ 1081 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF; 1082 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 | 1083 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */ 1084 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1085 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 | 1086 FEN_CPUEN)); /* enable MCU ,8051 */ 1087 } else { 1088 u8 retry_cnts = 0; 1089 1090 /* IF fw in RAM code, do reset */ 1091 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) { 1092 /* reset MCU ready status */ 1093 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1094 /* 8051 reset by self */ 1095 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20); 1096 while ((retry_cnts++ < 100) && 1097 (FEN_CPUEN & rtl_read_word(rtlpriv, 1098 REG_SYS_FUNC_EN))) { 1099 udelay(50); 1100 } 1101 if (retry_cnts >= 100) { 1102 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1103 "#####=> 8051 reset failed!.........................\n"); 1104 /* if 8051 reset fail, reset MAC. */ 1105 rtl_write_byte(rtlpriv, 1106 REG_SYS_FUNC_EN + 1, 1107 0x50); 1108 udelay(100); 1109 } 1110 } 1111 /* Reset MAC and Enable 8051 */ 1112 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54); 1113 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1114 } 1115 if (bWithoutHWSM) { 1116 /***************************** 1117 Without HW auto state machine 1118 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock 1119 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL 1120 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK 1121 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON 1122 ******************************/ 1123 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3); 1124 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); 1125 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F); 1126 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9); 1127 } 1128 } 1129 1130 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw) 1131 { 1132 struct rtl_priv *rtlpriv = rtl_priv(hw); 1133 /***************************** 1134 k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction 1135 l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock 1136 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON 1137 ******************************/ 1138 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3); 1139 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82); 1140 } 1141 1142 static void _DisableGPIO(struct ieee80211_hw *hw) 1143 { 1144 struct rtl_priv *rtlpriv = rtl_priv(hw); 1145 /*************************************** 1146 j. GPIO_PIN_CTRL 0x44[31:0]=0x000 1147 k. Value = GPIO_PIN_CTRL[7:0] 1148 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level 1149 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780 1150 n. LEDCFG 0x4C[15:0] = 0x8080 1151 ***************************************/ 1152 u8 value8; 1153 u16 value16; 1154 u32 value32; 1155 1156 /* 1. Disable GPIO[7:0] */ 1157 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000); 1158 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF; 1159 value8 = (u8)(value32&0x000000FF); 1160 value32 |= ((value8<<8) | 0x00FF0000); 1161 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32); 1162 /* 2. Disable GPIO[10:8] */ 1163 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00); 1164 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F; 1165 value8 = (u8)(value16&0x000F); 1166 value16 |= ((value8<<4) | 0x0780); 1167 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16); 1168 /* 3. Disable LED0 & 1 */ 1169 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); 1170 } 1171 1172 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM) 1173 { 1174 struct rtl_priv *rtlpriv = rtl_priv(hw); 1175 u16 value16 = 0; 1176 u8 value8 = 0; 1177 1178 if (bWithoutHWSM) { 1179 /***************************** 1180 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power 1181 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power 1182 r. When driver call disable, the ASIC will turn off remaining 1183 clock automatically 1184 ******************************/ 1185 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04); 1186 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL); 1187 value8 &= (~LDV12_EN); 1188 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8); 1189 } 1190 1191 /***************************** 1192 h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode 1193 i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend 1194 ******************************/ 1195 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); 1196 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN); 1197 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16); 1198 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E); 1199 } 1200 1201 static void _CardDisableHWSM(struct ieee80211_hw *hw) 1202 { 1203 /* ==== RF Off Sequence ==== */ 1204 _DisableRFAFEAndResetBB(hw); 1205 /* ==== Reset digital sequence ====== */ 1206 _ResetDigitalProcedure1(hw, false); 1207 /* ==== Pull GPIO PIN to balance level and LED control ====== */ 1208 _DisableGPIO(hw); 1209 /* ==== Disable analog sequence === */ 1210 _DisableAnalog(hw, false); 1211 } 1212 1213 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw) 1214 { 1215 /*==== RF Off Sequence ==== */ 1216 _DisableRFAFEAndResetBB(hw); 1217 /* ==== Reset digital sequence ====== */ 1218 _ResetDigitalProcedure1(hw, true); 1219 /* ==== Pull GPIO PIN to balance level and LED control ====== */ 1220 _DisableGPIO(hw); 1221 /* ==== Reset digital sequence ====== */ 1222 _ResetDigitalProcedure2(hw); 1223 /* ==== Disable analog sequence === */ 1224 _DisableAnalog(hw, true); 1225 } 1226 1227 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 1228 u8 set_bits, u8 clear_bits) 1229 { 1230 struct rtl_priv *rtlpriv = rtl_priv(hw); 1231 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 1232 1233 rtlusb->reg_bcn_ctrl_val |= set_bits; 1234 rtlusb->reg_bcn_ctrl_val &= ~clear_bits; 1235 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val); 1236 } 1237 1238 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw) 1239 { 1240 struct rtl_priv *rtlpriv = rtl_priv(hw); 1241 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1242 u8 tmp1byte = 0; 1243 if (IS_NORMAL_CHIP(rtlhal->version)) { 1244 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 1245 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1246 tmp1byte & (~BIT(6))); 1247 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 1248 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 1249 tmp1byte &= ~(BIT(0)); 1250 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 1251 } else { 1252 rtl_write_byte(rtlpriv, REG_TXPAUSE, 1253 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6)); 1254 } 1255 } 1256 1257 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw) 1258 { 1259 struct rtl_priv *rtlpriv = rtl_priv(hw); 1260 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1261 u8 tmp1byte = 0; 1262 1263 if (IS_NORMAL_CHIP(rtlhal->version)) { 1264 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 1265 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1266 tmp1byte | BIT(6)); 1267 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 1268 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 1269 tmp1byte |= BIT(0); 1270 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 1271 } else { 1272 rtl_write_byte(rtlpriv, REG_TXPAUSE, 1273 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6))); 1274 } 1275 } 1276 1277 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw) 1278 { 1279 struct rtl_priv *rtlpriv = rtl_priv(hw); 1280 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1281 1282 if (IS_NORMAL_CHIP(rtlhal->version)) 1283 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1)); 1284 else 1285 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1286 } 1287 1288 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw) 1289 { 1290 struct rtl_priv *rtlpriv = rtl_priv(hw); 1291 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1292 1293 if (IS_NORMAL_CHIP(rtlhal->version)) 1294 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0); 1295 else 1296 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0); 1297 } 1298 1299 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw, 1300 enum nl80211_iftype type) 1301 { 1302 struct rtl_priv *rtlpriv = rtl_priv(hw); 1303 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1304 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1305 1306 bt_msr &= 0xfc; 1307 if (type == NL80211_IFTYPE_UNSPECIFIED || type == 1308 NL80211_IFTYPE_STATION) { 1309 _rtl92cu_stop_tx_beacon(hw); 1310 _rtl92cu_enable_bcn_sub_func(hw); 1311 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) { 1312 _rtl92cu_resume_tx_beacon(hw); 1313 _rtl92cu_disable_bcn_sub_func(hw); 1314 } else { 1315 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1316 "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n", 1317 type); 1318 } 1319 switch (type) { 1320 case NL80211_IFTYPE_UNSPECIFIED: 1321 bt_msr |= MSR_NOLINK; 1322 ledaction = LED_CTL_LINK; 1323 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1324 "Set Network type to NO LINK!\n"); 1325 break; 1326 case NL80211_IFTYPE_ADHOC: 1327 bt_msr |= MSR_ADHOC; 1328 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1329 "Set Network type to Ad Hoc!\n"); 1330 break; 1331 case NL80211_IFTYPE_STATION: 1332 bt_msr |= MSR_INFRA; 1333 ledaction = LED_CTL_LINK; 1334 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1335 "Set Network type to STA!\n"); 1336 break; 1337 case NL80211_IFTYPE_AP: 1338 bt_msr |= MSR_AP; 1339 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1340 "Set Network type to AP!\n"); 1341 break; 1342 default: 1343 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1344 "Network type %d not supported!\n", type); 1345 goto error_out; 1346 } 1347 rtl_write_byte(rtlpriv, MSR, bt_msr); 1348 rtlpriv->cfg->ops->led_control(hw, ledaction); 1349 if ((bt_msr & MSR_MASK) == MSR_AP) 1350 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1351 else 1352 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1353 return 0; 1354 error_out: 1355 return 1; 1356 } 1357 1358 void rtl92cu_card_disable(struct ieee80211_hw *hw) 1359 { 1360 struct rtl_priv *rtlpriv = rtl_priv(hw); 1361 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1362 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 1363 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1364 enum nl80211_iftype opmode; 1365 1366 mac->link_state = MAC80211_NOLINK; 1367 opmode = NL80211_IFTYPE_UNSPECIFIED; 1368 _rtl92cu_set_media_status(hw, opmode); 1369 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1370 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1371 if (rtlusb->disableHWSM) 1372 _CardDisableHWSM(hw); 1373 else 1374 _CardDisableWithoutHWSM(hw); 1375 1376 /* after power off we should do iqk again */ 1377 rtlpriv->phy.iqk_initialized = false; 1378 } 1379 1380 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1381 { 1382 struct rtl_priv *rtlpriv = rtl_priv(hw); 1383 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1384 u32 reg_rcr; 1385 1386 if (rtlpriv->psc.rfpwr_state != ERFON) 1387 return; 1388 1389 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1390 1391 if (check_bssid) { 1392 u8 tmp; 1393 if (IS_NORMAL_CHIP(rtlhal->version)) { 1394 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1395 tmp = BIT(4); 1396 } else { 1397 reg_rcr |= RCR_CBSSID; 1398 tmp = BIT(4) | BIT(5); 1399 } 1400 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1401 (u8 *) (®_rcr)); 1402 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp); 1403 } else { 1404 u8 tmp; 1405 if (IS_NORMAL_CHIP(rtlhal->version)) { 1406 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1407 tmp = BIT(4); 1408 } else { 1409 reg_rcr &= ~RCR_CBSSID; 1410 tmp = BIT(4) | BIT(5); 1411 } 1412 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1413 rtlpriv->cfg->ops->set_hw_reg(hw, 1414 HW_VAR_RCR, (u8 *) (®_rcr)); 1415 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0); 1416 } 1417 } 1418 1419 /*========================================================================== */ 1420 1421 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1422 { 1423 struct rtl_priv *rtlpriv = rtl_priv(hw); 1424 1425 if (_rtl92cu_set_media_status(hw, type)) 1426 return -EOPNOTSUPP; 1427 1428 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1429 if (type != NL80211_IFTYPE_AP) 1430 rtl92cu_set_check_bssid(hw, true); 1431 } else { 1432 rtl92cu_set_check_bssid(hw, false); 1433 } 1434 1435 return 0; 1436 } 1437 1438 static void _beacon_function_enable(struct ieee80211_hw *hw) 1439 { 1440 struct rtl_priv *rtlpriv = rtl_priv(hw); 1441 1442 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00); 1443 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F); 1444 } 1445 1446 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw) 1447 { 1448 1449 struct rtl_priv *rtlpriv = rtl_priv(hw); 1450 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1451 u16 bcn_interval, atim_window; 1452 u32 value32; 1453 1454 bcn_interval = mac->beacon_interval; 1455 atim_window = 2; /*FIX MERGE */ 1456 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1457 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1458 _rtl92cu_init_beacon_parameters(hw); 1459 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 1460 /* 1461 * Force beacon frame transmission even after receiving beacon frame 1462 * from other ad hoc STA 1463 * 1464 * 1465 * Reset TSF Timer to zero, added by Roger. 2008.06.24 1466 */ 1467 value32 = rtl_read_dword(rtlpriv, REG_TCR); 1468 value32 &= ~TSFRST; 1469 rtl_write_dword(rtlpriv, REG_TCR, value32); 1470 value32 |= TSFRST; 1471 rtl_write_dword(rtlpriv, REG_TCR, value32); 1472 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD, 1473 "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n", 1474 value32); 1475 /* TODO: Modify later (Find the right parameters) 1476 * NOTE: Fix test chip's bug (about contention windows's randomness) */ 1477 if ((mac->opmode == NL80211_IFTYPE_ADHOC) || 1478 (mac->opmode == NL80211_IFTYPE_MESH_POINT) || 1479 (mac->opmode == NL80211_IFTYPE_AP)) { 1480 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50); 1481 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50); 1482 } 1483 _beacon_function_enable(hw); 1484 } 1485 1486 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw) 1487 { 1488 struct rtl_priv *rtlpriv = rtl_priv(hw); 1489 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1490 u16 bcn_interval = mac->beacon_interval; 1491 1492 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n", 1493 bcn_interval); 1494 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1495 } 1496 1497 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw, 1498 u32 add_msr, u32 rm_msr) 1499 { 1500 } 1501 1502 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 1503 { 1504 struct rtl_priv *rtlpriv = rtl_priv(hw); 1505 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1506 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1507 1508 switch (variable) { 1509 case HW_VAR_RCR: 1510 *((u32 *)(val)) = mac->rx_conf; 1511 break; 1512 case HW_VAR_RF_STATE: 1513 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 1514 break; 1515 case HW_VAR_FWLPS_RF_ON:{ 1516 enum rf_pwrstate rfState; 1517 u32 val_rcr; 1518 1519 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, 1520 (u8 *)(&rfState)); 1521 if (rfState == ERFOFF) { 1522 *((bool *) (val)) = true; 1523 } else { 1524 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 1525 val_rcr &= 0x00070000; 1526 if (val_rcr) 1527 *((bool *) (val)) = false; 1528 else 1529 *((bool *) (val)) = true; 1530 } 1531 break; 1532 } 1533 case HW_VAR_FW_PSMODE_STATUS: 1534 *((bool *) (val)) = ppsc->fw_current_inpsmode; 1535 break; 1536 case HW_VAR_CORRECT_TSF:{ 1537 u64 tsf; 1538 u32 *ptsf_low = (u32 *)&tsf; 1539 u32 *ptsf_high = ((u32 *)&tsf) + 1; 1540 1541 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 1542 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 1543 *((u64 *)(val)) = tsf; 1544 break; 1545 } 1546 case HW_VAR_MGT_FILTER: 1547 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0); 1548 break; 1549 case HW_VAR_CTRL_FILTER: 1550 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1); 1551 break; 1552 case HW_VAR_DATA_FILTER: 1553 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2); 1554 break; 1555 case HAL_DEF_WOWLAN: 1556 break; 1557 default: 1558 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1559 "switch case %#x not processed\n", variable); 1560 break; 1561 } 1562 } 1563 1564 static bool usb_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb) 1565 { 1566 /* Currently nothing happens here. 1567 * Traffic stops after some seconds in WPA2 802.11n mode. 1568 * Maybe because rtl8192cu chip should be set from here? 1569 * If I understand correctly, the realtek vendor driver sends some urbs 1570 * if its "here". 1571 * 1572 * This is maybe necessary: 1573 * rtlpriv->cfg->ops->fill_tx_cmddesc(hw, buffer, 1, 1, skb); 1574 */ 1575 return true; 1576 } 1577 1578 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 1579 { 1580 struct rtl_priv *rtlpriv = rtl_priv(hw); 1581 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1582 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1583 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1584 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1585 enum wireless_mode wirelessmode = mac->mode; 1586 u8 idx = 0; 1587 1588 switch (variable) { 1589 case HW_VAR_ETHER_ADDR:{ 1590 for (idx = 0; idx < ETH_ALEN; idx++) { 1591 rtl_write_byte(rtlpriv, (REG_MACID + idx), 1592 val[idx]); 1593 } 1594 break; 1595 } 1596 case HW_VAR_BASIC_RATE:{ 1597 u16 rate_cfg = ((u16 *) val)[0]; 1598 u8 rate_index = 0; 1599 1600 rate_cfg &= 0x15f; 1601 /* TODO */ 1602 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO 1603 * && ((rate_cfg & 0x150) == 0)) { 1604 * rate_cfg |= 0x010; 1605 * } */ 1606 rate_cfg |= 0x01; 1607 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); 1608 rtl_write_byte(rtlpriv, REG_RRSR + 1, 1609 (rate_cfg >> 8) & 0xff); 1610 while (rate_cfg > 0x1) { 1611 rate_cfg >>= 1; 1612 rate_index++; 1613 } 1614 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 1615 rate_index); 1616 break; 1617 } 1618 case HW_VAR_BSSID:{ 1619 for (idx = 0; idx < ETH_ALEN; idx++) { 1620 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 1621 val[idx]); 1622 } 1623 break; 1624 } 1625 case HW_VAR_SIFS:{ 1626 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]); 1627 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]); 1628 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 1629 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 1630 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]); 1631 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]); 1632 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n"); 1633 break; 1634 } 1635 case HW_VAR_SLOT_TIME:{ 1636 u8 e_aci; 1637 u8 QOS_MODE = 1; 1638 1639 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 1640 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1641 "HW_VAR_SLOT_TIME %x\n", val[0]); 1642 if (QOS_MODE) { 1643 for (e_aci = 0; e_aci < AC_MAX; e_aci++) 1644 rtlpriv->cfg->ops->set_hw_reg(hw, 1645 HW_VAR_AC_PARAM, 1646 &e_aci); 1647 } else { 1648 u8 sifstime = 0; 1649 u8 u1bAIFS; 1650 1651 if (IS_WIRELESS_MODE_A(wirelessmode) || 1652 IS_WIRELESS_MODE_N_24G(wirelessmode) || 1653 IS_WIRELESS_MODE_N_5G(wirelessmode)) 1654 sifstime = 16; 1655 else 1656 sifstime = 10; 1657 u1bAIFS = sifstime + (2 * val[0]); 1658 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM, 1659 u1bAIFS); 1660 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM, 1661 u1bAIFS); 1662 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM, 1663 u1bAIFS); 1664 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM, 1665 u1bAIFS); 1666 } 1667 break; 1668 } 1669 case HW_VAR_ACK_PREAMBLE:{ 1670 u8 reg_tmp; 1671 u8 short_preamble = (bool)*val; 1672 reg_tmp = 0; 1673 if (short_preamble) 1674 reg_tmp |= 0x80; 1675 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 1676 break; 1677 } 1678 case HW_VAR_AMPDU_MIN_SPACE:{ 1679 u8 min_spacing_to_set; 1680 u8 sec_min_space; 1681 1682 min_spacing_to_set = *val; 1683 if (min_spacing_to_set <= 7) { 1684 switch (rtlpriv->sec.pairwise_enc_algorithm) { 1685 case NO_ENCRYPTION: 1686 case AESCCMP_ENCRYPTION: 1687 sec_min_space = 0; 1688 break; 1689 case WEP40_ENCRYPTION: 1690 case WEP104_ENCRYPTION: 1691 case TKIP_ENCRYPTION: 1692 sec_min_space = 6; 1693 break; 1694 default: 1695 sec_min_space = 7; 1696 break; 1697 } 1698 if (min_spacing_to_set < sec_min_space) 1699 min_spacing_to_set = sec_min_space; 1700 mac->min_space_cfg = ((mac->min_space_cfg & 1701 0xf8) | 1702 min_spacing_to_set); 1703 *val = min_spacing_to_set; 1704 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1705 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 1706 mac->min_space_cfg); 1707 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 1708 mac->min_space_cfg); 1709 } 1710 break; 1711 } 1712 case HW_VAR_SHORTGI_DENSITY:{ 1713 u8 density_to_set; 1714 1715 density_to_set = *val; 1716 density_to_set &= 0x1f; 1717 mac->min_space_cfg &= 0x07; 1718 mac->min_space_cfg |= (density_to_set << 3); 1719 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1720 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 1721 mac->min_space_cfg); 1722 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 1723 mac->min_space_cfg); 1724 break; 1725 } 1726 case HW_VAR_AMPDU_FACTOR:{ 1727 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; 1728 u8 factor_toset; 1729 u8 *p_regtoset = NULL; 1730 u8 index = 0; 1731 1732 p_regtoset = regtoset_normal; 1733 factor_toset = *val; 1734 if (factor_toset <= 3) { 1735 factor_toset = (1 << (factor_toset + 2)); 1736 if (factor_toset > 0xf) 1737 factor_toset = 0xf; 1738 for (index = 0; index < 4; index++) { 1739 if ((p_regtoset[index] & 0xf0) > 1740 (factor_toset << 4)) 1741 p_regtoset[index] = 1742 (p_regtoset[index] & 0x0f) 1743 | (factor_toset << 4); 1744 if ((p_regtoset[index] & 0x0f) > 1745 factor_toset) 1746 p_regtoset[index] = 1747 (p_regtoset[index] & 0xf0) 1748 | (factor_toset); 1749 rtl_write_byte(rtlpriv, 1750 (REG_AGGLEN_LMT + index), 1751 p_regtoset[index]); 1752 } 1753 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1754 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 1755 factor_toset); 1756 } 1757 break; 1758 } 1759 case HW_VAR_AC_PARAM:{ 1760 u8 e_aci = *val; 1761 u32 u4b_ac_param; 1762 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min); 1763 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max); 1764 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op); 1765 1766 u4b_ac_param = (u32) mac->ac[e_aci].aifs; 1767 u4b_ac_param |= (u32) ((cw_min & 0xF) << 1768 AC_PARAM_ECW_MIN_OFFSET); 1769 u4b_ac_param |= (u32) ((cw_max & 0xF) << 1770 AC_PARAM_ECW_MAX_OFFSET); 1771 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET; 1772 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1773 "queue:%x, ac_param:%x\n", 1774 e_aci, u4b_ac_param); 1775 switch (e_aci) { 1776 case AC1_BK: 1777 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 1778 u4b_ac_param); 1779 break; 1780 case AC0_BE: 1781 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 1782 u4b_ac_param); 1783 break; 1784 case AC2_VI: 1785 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 1786 u4b_ac_param); 1787 break; 1788 case AC3_VO: 1789 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 1790 u4b_ac_param); 1791 break; 1792 default: 1793 RT_ASSERT(false, "invalid aci: %d !\n", 1794 e_aci); 1795 break; 1796 } 1797 break; 1798 } 1799 case HW_VAR_RCR:{ 1800 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); 1801 mac->rx_conf = ((u32 *) (val))[0]; 1802 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG, 1803 "### Set RCR(0x%08x) ###\n", mac->rx_conf); 1804 break; 1805 } 1806 case HW_VAR_RETRY_LIMIT:{ 1807 u8 retry_limit = val[0]; 1808 1809 rtl_write_word(rtlpriv, REG_RL, 1810 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 1811 retry_limit << RETRY_LIMIT_LONG_SHIFT); 1812 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG, 1813 "Set HW_VAR_RETRY_LIMIT(0x%08x)\n", 1814 retry_limit); 1815 break; 1816 } 1817 case HW_VAR_DUAL_TSF_RST: 1818 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 1819 break; 1820 case HW_VAR_EFUSE_BYTES: 1821 rtlefuse->efuse_usedbytes = *((u16 *) val); 1822 break; 1823 case HW_VAR_EFUSE_USAGE: 1824 rtlefuse->efuse_usedpercentage = *val; 1825 break; 1826 case HW_VAR_IO_CMD: 1827 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val)); 1828 break; 1829 case HW_VAR_WPA_CONFIG: 1830 rtl_write_byte(rtlpriv, REG_SECCFG, *val); 1831 break; 1832 case HW_VAR_SET_RPWM:{ 1833 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM); 1834 1835 if (rpwm_val & BIT(7)) 1836 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val); 1837 else 1838 rtl_write_byte(rtlpriv, REG_USB_HRPWM, 1839 *val | BIT(7)); 1840 break; 1841 } 1842 case HW_VAR_H2C_FW_PWRMODE:{ 1843 u8 psmode = *val; 1844 1845 if ((psmode != FW_PS_ACTIVE_MODE) && 1846 (!IS_92C_SERIAL(rtlhal->version))) 1847 rtl92c_dm_rf_saving(hw, true); 1848 rtl92c_set_fw_pwrmode_cmd(hw, (*val)); 1849 break; 1850 } 1851 case HW_VAR_FW_PSMODE_STATUS: 1852 ppsc->fw_current_inpsmode = *((bool *) val); 1853 break; 1854 case HW_VAR_H2C_FW_JOINBSSRPT:{ 1855 u8 mstatus = *val; 1856 u8 tmp_reg422; 1857 bool recover = false; 1858 1859 if (mstatus == RT_MEDIA_CONNECT) { 1860 rtlpriv->cfg->ops->set_hw_reg(hw, 1861 HW_VAR_AID, NULL); 1862 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03); 1863 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); 1864 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0); 1865 tmp_reg422 = rtl_read_byte(rtlpriv, 1866 REG_FWHW_TXQ_CTRL + 2); 1867 if (tmp_reg422 & BIT(6)) 1868 recover = true; 1869 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1870 tmp_reg422 & (~BIT(6))); 1871 rtl92c_set_fw_rsvdpagepkt(hw, 1872 &usb_cmd_send_packet); 1873 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); 1874 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1875 if (recover) 1876 rtl_write_byte(rtlpriv, 1877 REG_FWHW_TXQ_CTRL + 2, 1878 tmp_reg422 | BIT(6)); 1879 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 1880 } 1881 rtl92c_set_fw_joinbss_report_cmd(hw, (*val)); 1882 break; 1883 } 1884 case HW_VAR_AID:{ 1885 u16 u2btmp; 1886 1887 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 1888 u2btmp &= 0xC000; 1889 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, 1890 (u2btmp | mac->assoc_id)); 1891 break; 1892 } 1893 case HW_VAR_CORRECT_TSF:{ 1894 u8 btype_ibss = val[0]; 1895 1896 if (btype_ibss) 1897 _rtl92cu_stop_tx_beacon(hw); 1898 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); 1899 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf & 1900 0xffffffff)); 1901 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 1902 (u32)((mac->tsf >> 32) & 0xffffffff)); 1903 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); 1904 if (btype_ibss) 1905 _rtl92cu_resume_tx_beacon(hw); 1906 break; 1907 } 1908 case HW_VAR_MGT_FILTER: 1909 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val); 1910 mac->rx_mgt_filter = *(u16 *)val; 1911 break; 1912 case HW_VAR_CTRL_FILTER: 1913 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val); 1914 mac->rx_ctrl_filter = *(u16 *)val; 1915 break; 1916 case HW_VAR_DATA_FILTER: 1917 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val); 1918 mac->rx_data_filter = *(u16 *)val; 1919 break; 1920 case HW_VAR_KEEP_ALIVE:{ 1921 u8 array[2]; 1922 array[0] = 0xff; 1923 array[1] = *((u8 *)val); 1924 rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2, 1925 array); 1926 break; 1927 } 1928 default: 1929 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1930 "switch case %#x not processed\n", variable); 1931 break; 1932 } 1933 } 1934 1935 static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw, 1936 struct ieee80211_sta *sta) 1937 { 1938 struct rtl_priv *rtlpriv = rtl_priv(hw); 1939 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1940 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1941 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1942 u32 ratr_value; 1943 u8 ratr_index = 0; 1944 u8 nmode = mac->ht_enable; 1945 u8 mimo_ps = IEEE80211_SMPS_OFF; 1946 u16 shortgi_rate; 1947 u32 tmp_ratr_value; 1948 u8 curtxbw_40mhz = mac->bw_40; 1949 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1950 1 : 0; 1951 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1952 1 : 0; 1953 enum wireless_mode wirelessmode = mac->mode; 1954 1955 if (rtlhal->current_bandtype == BAND_ON_5G) 1956 ratr_value = sta->supp_rates[1] << 4; 1957 else 1958 ratr_value = sta->supp_rates[0]; 1959 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1960 ratr_value = 0xfff; 1961 1962 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1963 sta->ht_cap.mcs.rx_mask[0] << 12); 1964 switch (wirelessmode) { 1965 case WIRELESS_MODE_B: 1966 if (ratr_value & 0x0000000c) 1967 ratr_value &= 0x0000000d; 1968 else 1969 ratr_value &= 0x0000000f; 1970 break; 1971 case WIRELESS_MODE_G: 1972 ratr_value &= 0x00000FF5; 1973 break; 1974 case WIRELESS_MODE_N_24G: 1975 case WIRELESS_MODE_N_5G: 1976 nmode = 1; 1977 if (mimo_ps == IEEE80211_SMPS_STATIC) { 1978 ratr_value &= 0x0007F005; 1979 } else { 1980 u32 ratr_mask; 1981 1982 if (get_rf_type(rtlphy) == RF_1T2R || 1983 get_rf_type(rtlphy) == RF_1T1R) 1984 ratr_mask = 0x000ff005; 1985 else 1986 ratr_mask = 0x0f0ff005; 1987 1988 ratr_value &= ratr_mask; 1989 } 1990 break; 1991 default: 1992 if (rtlphy->rf_type == RF_1T2R) 1993 ratr_value &= 0x000ff0ff; 1994 else 1995 ratr_value &= 0x0f0ff0ff; 1996 1997 break; 1998 } 1999 2000 ratr_value &= 0x0FFFFFFF; 2001 2002 if (nmode && ((curtxbw_40mhz && 2003 curshortgi_40mhz) || (!curtxbw_40mhz && 2004 curshortgi_20mhz))) { 2005 2006 ratr_value |= 0x10000000; 2007 tmp_ratr_value = (ratr_value >> 12); 2008 2009 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 2010 if ((1 << shortgi_rate) & tmp_ratr_value) 2011 break; 2012 } 2013 2014 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 2015 (shortgi_rate << 4) | (shortgi_rate); 2016 } 2017 2018 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 2019 2020 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", 2021 rtl_read_dword(rtlpriv, REG_ARFR0)); 2022 } 2023 2024 static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, 2025 struct ieee80211_sta *sta, 2026 u8 rssi_level) 2027 { 2028 struct rtl_priv *rtlpriv = rtl_priv(hw); 2029 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2030 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2031 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2032 struct rtl_sta_info *sta_entry = NULL; 2033 u32 ratr_bitmap; 2034 u8 ratr_index; 2035 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; 2036 u8 curshortgi_40mhz = curtxbw_40mhz && 2037 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2038 1 : 0; 2039 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2040 1 : 0; 2041 enum wireless_mode wirelessmode = 0; 2042 bool shortgi = false; 2043 u8 rate_mask[5]; 2044 u8 macid = 0; 2045 u8 mimo_ps = IEEE80211_SMPS_OFF; 2046 2047 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 2048 wirelessmode = sta_entry->wireless_mode; 2049 if (mac->opmode == NL80211_IFTYPE_STATION || 2050 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2051 curtxbw_40mhz = mac->bw_40; 2052 else if (mac->opmode == NL80211_IFTYPE_AP || 2053 mac->opmode == NL80211_IFTYPE_ADHOC) 2054 macid = sta->aid + 1; 2055 2056 if (rtlhal->current_bandtype == BAND_ON_5G) 2057 ratr_bitmap = sta->supp_rates[1] << 4; 2058 else 2059 ratr_bitmap = sta->supp_rates[0]; 2060 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2061 ratr_bitmap = 0xfff; 2062 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 2063 sta->ht_cap.mcs.rx_mask[0] << 12); 2064 switch (wirelessmode) { 2065 case WIRELESS_MODE_B: 2066 ratr_index = RATR_INX_WIRELESS_B; 2067 if (ratr_bitmap & 0x0000000c) 2068 ratr_bitmap &= 0x0000000d; 2069 else 2070 ratr_bitmap &= 0x0000000f; 2071 break; 2072 case WIRELESS_MODE_G: 2073 ratr_index = RATR_INX_WIRELESS_GB; 2074 2075 if (rssi_level == 1) 2076 ratr_bitmap &= 0x00000f00; 2077 else if (rssi_level == 2) 2078 ratr_bitmap &= 0x00000ff0; 2079 else 2080 ratr_bitmap &= 0x00000ff5; 2081 break; 2082 case WIRELESS_MODE_A: 2083 ratr_index = RATR_INX_WIRELESS_A; 2084 ratr_bitmap &= 0x00000ff0; 2085 break; 2086 case WIRELESS_MODE_N_24G: 2087 case WIRELESS_MODE_N_5G: 2088 ratr_index = RATR_INX_WIRELESS_NGB; 2089 2090 if (mimo_ps == IEEE80211_SMPS_STATIC) { 2091 if (rssi_level == 1) 2092 ratr_bitmap &= 0x00070000; 2093 else if (rssi_level == 2) 2094 ratr_bitmap &= 0x0007f000; 2095 else 2096 ratr_bitmap &= 0x0007f005; 2097 } else { 2098 if (rtlphy->rf_type == RF_1T2R || 2099 rtlphy->rf_type == RF_1T1R) { 2100 if (curtxbw_40mhz) { 2101 if (rssi_level == 1) 2102 ratr_bitmap &= 0x000f0000; 2103 else if (rssi_level == 2) 2104 ratr_bitmap &= 0x000ff000; 2105 else 2106 ratr_bitmap &= 0x000ff015; 2107 } else { 2108 if (rssi_level == 1) 2109 ratr_bitmap &= 0x000f0000; 2110 else if (rssi_level == 2) 2111 ratr_bitmap &= 0x000ff000; 2112 else 2113 ratr_bitmap &= 0x000ff005; 2114 } 2115 } else { 2116 if (curtxbw_40mhz) { 2117 if (rssi_level == 1) 2118 ratr_bitmap &= 0x0f0f0000; 2119 else if (rssi_level == 2) 2120 ratr_bitmap &= 0x0f0ff000; 2121 else 2122 ratr_bitmap &= 0x0f0ff015; 2123 } else { 2124 if (rssi_level == 1) 2125 ratr_bitmap &= 0x0f0f0000; 2126 else if (rssi_level == 2) 2127 ratr_bitmap &= 0x0f0ff000; 2128 else 2129 ratr_bitmap &= 0x0f0ff005; 2130 } 2131 } 2132 } 2133 2134 if ((curtxbw_40mhz && curshortgi_40mhz) || 2135 (!curtxbw_40mhz && curshortgi_20mhz)) { 2136 2137 if (macid == 0) 2138 shortgi = true; 2139 else if (macid == 1) 2140 shortgi = false; 2141 } 2142 break; 2143 default: 2144 ratr_index = RATR_INX_WIRELESS_NGB; 2145 2146 if (rtlphy->rf_type == RF_1T2R) 2147 ratr_bitmap &= 0x000ff0ff; 2148 else 2149 ratr_bitmap &= 0x0f0ff0ff; 2150 break; 2151 } 2152 sta_entry->ratr_index = ratr_index; 2153 2154 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2155 "ratr_bitmap :%x\n", ratr_bitmap); 2156 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 2157 (ratr_index << 28); 2158 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; 2159 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2160 "Rate_index:%x, ratr_val:%x, %5phC\n", 2161 ratr_index, ratr_bitmap, rate_mask); 2162 memcpy(rtlpriv->rate_mask, rate_mask, 5); 2163 /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a 2164 * "scheduled while atomic" if called directly */ 2165 schedule_work(&rtlpriv->works.fill_h2c_cmd); 2166 2167 if (macid != 0) 2168 sta_entry->ratr_index = ratr_index; 2169 } 2170 2171 void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw, 2172 struct ieee80211_sta *sta, 2173 u8 rssi_level) 2174 { 2175 struct rtl_priv *rtlpriv = rtl_priv(hw); 2176 2177 if (rtlpriv->dm.useramask) 2178 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level); 2179 else 2180 rtl92cu_update_hal_rate_table(hw, sta); 2181 } 2182 2183 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw) 2184 { 2185 struct rtl_priv *rtlpriv = rtl_priv(hw); 2186 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2187 u16 sifs_timer; 2188 2189 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2190 &mac->slot_time); 2191 if (!mac->ht_enable) 2192 sifs_timer = 0x0a0a; 2193 else 2194 sifs_timer = 0x0e0e; 2195 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2196 } 2197 2198 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid) 2199 { 2200 struct rtl_priv *rtlpriv = rtl_priv(hw); 2201 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2202 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate; 2203 u8 u1tmp = 0; 2204 bool actuallyset = false; 2205 unsigned long flag = 0; 2206 /* to do - usb autosuspend */ 2207 u8 usb_autosuspend = 0; 2208 2209 if (ppsc->swrf_processing) 2210 return false; 2211 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2212 if (ppsc->rfchange_inprogress) { 2213 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2214 return false; 2215 } else { 2216 ppsc->rfchange_inprogress = true; 2217 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2218 } 2219 cur_rfstate = ppsc->rfpwr_state; 2220 if (usb_autosuspend) { 2221 /* to do................... */ 2222 } else { 2223 if (ppsc->pwrdown_mode) { 2224 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR); 2225 e_rfpowerstate_toset = (u1tmp & BIT(7)) ? 2226 ERFOFF : ERFON; 2227 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 2228 "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp); 2229 } else { 2230 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, 2231 rtl_read_byte(rtlpriv, 2232 REG_MAC_PINMUX_CFG) & ~(BIT(3))); 2233 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); 2234 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? 2235 ERFON : ERFOFF; 2236 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 2237 "GPIO_IN=%02x\n", u1tmp); 2238 } 2239 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n", 2240 e_rfpowerstate_toset); 2241 } 2242 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { 2243 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2244 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2245 ppsc->hwradiooff = false; 2246 actuallyset = true; 2247 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset == 2248 ERFOFF)) { 2249 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2250 "GPIOChangeRF - HW Radio OFF\n"); 2251 ppsc->hwradiooff = true; 2252 actuallyset = true; 2253 } else { 2254 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2255 "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n", 2256 ppsc->hwradiooff, e_rfpowerstate_toset); 2257 } 2258 if (actuallyset) { 2259 ppsc->hwradiooff = true; 2260 if (e_rfpowerstate_toset == ERFON) { 2261 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) && 2262 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM)) 2263 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2264 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2265 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3)) 2266 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2267 } 2268 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2269 ppsc->rfchange_inprogress = false; 2270 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2271 /* For power down module, we need to enable register block 2272 * contrl reg at 0x1c. Then enable power down control bit 2273 * of register 0x04 BIT4 and BIT15 as 1. 2274 */ 2275 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) { 2276 /* Enable register area 0x0-0xc. */ 2277 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); 2278 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812); 2279 } 2280 if (e_rfpowerstate_toset == ERFOFF) { 2281 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) 2282 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2283 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2284 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2285 } 2286 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) { 2287 /* Enter D3 or ASPM after GPIO had been done. */ 2288 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) 2289 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2290 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2291 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2292 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2293 ppsc->rfchange_inprogress = false; 2294 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2295 } else { 2296 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2297 ppsc->rfchange_inprogress = false; 2298 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2299 } 2300 *valid = 1; 2301 return !ppsc->hwradiooff; 2302 } 2303