1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../cam.h" 30 #include "../ps.h" 31 #include "../usb.h" 32 #include "reg.h" 33 #include "def.h" 34 #include "phy.h" 35 #include "../rtl8192c/phy_common.h" 36 #include "mac.h" 37 #include "dm.h" 38 #include "../rtl8192c/dm_common.h" 39 #include "../rtl8192c/fw_common.h" 40 #include "hw.h" 41 #include "../rtl8192ce/hw.h" 42 #include "trx.h" 43 #include "led.h" 44 #include "table.h" 45 46 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw) 47 { 48 struct rtl_priv *rtlpriv = rtl_priv(hw); 49 struct rtl_phy *rtlphy = &(rtlpriv->phy); 50 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); 51 52 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH; 53 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY; 54 if (IS_HIGHT_PA(rtlefuse->board_type)) { 55 rtlphy->hwparam_tables[PHY_REG_PG].length = 56 RTL8192CUPHY_REG_Array_PG_HPLength; 57 rtlphy->hwparam_tables[PHY_REG_PG].pdata = 58 RTL8192CUPHY_REG_Array_PG_HP; 59 } else { 60 rtlphy->hwparam_tables[PHY_REG_PG].length = 61 RTL8192CUPHY_REG_ARRAY_PGLENGTH; 62 rtlphy->hwparam_tables[PHY_REG_PG].pdata = 63 RTL8192CUPHY_REG_ARRAY_PG; 64 } 65 /* 2T */ 66 rtlphy->hwparam_tables[PHY_REG_2T].length = 67 RTL8192CUPHY_REG_2TARRAY_LENGTH; 68 rtlphy->hwparam_tables[PHY_REG_2T].pdata = 69 RTL8192CUPHY_REG_2TARRAY; 70 rtlphy->hwparam_tables[RADIOA_2T].length = 71 RTL8192CURADIOA_2TARRAYLENGTH; 72 rtlphy->hwparam_tables[RADIOA_2T].pdata = 73 RTL8192CURADIOA_2TARRAY; 74 rtlphy->hwparam_tables[RADIOB_2T].length = 75 RTL8192CURADIOB_2TARRAYLENGTH; 76 rtlphy->hwparam_tables[RADIOB_2T].pdata = 77 RTL8192CU_RADIOB_2TARRAY; 78 rtlphy->hwparam_tables[AGCTAB_2T].length = 79 RTL8192CUAGCTAB_2TARRAYLENGTH; 80 rtlphy->hwparam_tables[AGCTAB_2T].pdata = 81 RTL8192CUAGCTAB_2TARRAY; 82 /* 1T */ 83 if (IS_HIGHT_PA(rtlefuse->board_type)) { 84 rtlphy->hwparam_tables[PHY_REG_1T].length = 85 RTL8192CUPHY_REG_1T_HPArrayLength; 86 rtlphy->hwparam_tables[PHY_REG_1T].pdata = 87 RTL8192CUPHY_REG_1T_HPArray; 88 rtlphy->hwparam_tables[RADIOA_1T].length = 89 RTL8192CURadioA_1T_HPArrayLength; 90 rtlphy->hwparam_tables[RADIOA_1T].pdata = 91 RTL8192CURadioA_1T_HPArray; 92 rtlphy->hwparam_tables[RADIOB_1T].length = 93 RTL8192CURADIOB_1TARRAYLENGTH; 94 rtlphy->hwparam_tables[RADIOB_1T].pdata = 95 RTL8192CU_RADIOB_1TARRAY; 96 rtlphy->hwparam_tables[AGCTAB_1T].length = 97 RTL8192CUAGCTAB_1T_HPArrayLength; 98 rtlphy->hwparam_tables[AGCTAB_1T].pdata = 99 Rtl8192CUAGCTAB_1T_HPArray; 100 } else { 101 rtlphy->hwparam_tables[PHY_REG_1T].length = 102 RTL8192CUPHY_REG_1TARRAY_LENGTH; 103 rtlphy->hwparam_tables[PHY_REG_1T].pdata = 104 RTL8192CUPHY_REG_1TARRAY; 105 rtlphy->hwparam_tables[RADIOA_1T].length = 106 RTL8192CURADIOA_1TARRAYLENGTH; 107 rtlphy->hwparam_tables[RADIOA_1T].pdata = 108 RTL8192CU_RADIOA_1TARRAY; 109 rtlphy->hwparam_tables[RADIOB_1T].length = 110 RTL8192CURADIOB_1TARRAYLENGTH; 111 rtlphy->hwparam_tables[RADIOB_1T].pdata = 112 RTL8192CU_RADIOB_1TARRAY; 113 rtlphy->hwparam_tables[AGCTAB_1T].length = 114 RTL8192CUAGCTAB_1TARRAYLENGTH; 115 rtlphy->hwparam_tables[AGCTAB_1T].pdata = 116 RTL8192CUAGCTAB_1TARRAY; 117 } 118 } 119 120 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 121 bool autoload_fail, 122 u8 *hwinfo) 123 { 124 struct rtl_priv *rtlpriv = rtl_priv(hw); 125 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 126 u8 rf_path, index, tempval; 127 u16 i; 128 129 for (rf_path = 0; rf_path < 2; rf_path++) { 130 for (i = 0; i < 3; i++) { 131 if (!autoload_fail) { 132 rtlefuse-> 133 eeprom_chnlarea_txpwr_cck[rf_path][i] = 134 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; 135 rtlefuse-> 136 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 137 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + 138 i]; 139 } else { 140 rtlefuse-> 141 eeprom_chnlarea_txpwr_cck[rf_path][i] = 142 EEPROM_DEFAULT_TXPOWERLEVEL; 143 rtlefuse-> 144 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 145 EEPROM_DEFAULT_TXPOWERLEVEL; 146 } 147 } 148 } 149 for (i = 0; i < 3; i++) { 150 if (!autoload_fail) 151 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i]; 152 else 153 tempval = EEPROM_DEFAULT_HT40_2SDIFF; 154 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] = 155 (tempval & 0xf); 156 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] = 157 ((tempval & 0xf0) >> 4); 158 } 159 for (rf_path = 0; rf_path < 2; rf_path++) 160 for (i = 0; i < 3; i++) 161 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 162 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", 163 rf_path, i, 164 rtlefuse-> 165 eeprom_chnlarea_txpwr_cck[rf_path][i]); 166 for (rf_path = 0; rf_path < 2; rf_path++) 167 for (i = 0; i < 3; i++) 168 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 169 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 170 rf_path, i, 171 rtlefuse-> 172 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]); 173 for (rf_path = 0; rf_path < 2; rf_path++) 174 for (i = 0; i < 3; i++) 175 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 176 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 177 rf_path, i, 178 rtlefuse-> 179 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]); 180 for (rf_path = 0; rf_path < 2; rf_path++) { 181 for (i = 0; i < 14; i++) { 182 index = rtl92c_get_chnl_group((u8)i); 183 rtlefuse->txpwrlevel_cck[rf_path][i] = 184 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index]; 185 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 186 rtlefuse-> 187 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index]; 188 if ((rtlefuse-> 189 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] - 190 rtlefuse-> 191 eprom_chnl_txpwr_ht40_2sdf[rf_path][index]) 192 > 0) { 193 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 194 rtlefuse-> 195 eeprom_chnlarea_txpwr_ht40_1s[rf_path] 196 [index] - rtlefuse-> 197 eprom_chnl_txpwr_ht40_2sdf[rf_path] 198 [index]; 199 } else { 200 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; 201 } 202 } 203 for (i = 0; i < 14; i++) { 204 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 205 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i, 206 rtlefuse->txpwrlevel_cck[rf_path][i], 207 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 208 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 209 } 210 } 211 for (i = 0; i < 3; i++) { 212 if (!autoload_fail) { 213 rtlefuse->eeprom_pwrlimit_ht40[i] = 214 hwinfo[EEPROM_TXPWR_GROUP + i]; 215 rtlefuse->eeprom_pwrlimit_ht20[i] = 216 hwinfo[EEPROM_TXPWR_GROUP + 3 + i]; 217 } else { 218 rtlefuse->eeprom_pwrlimit_ht40[i] = 0; 219 rtlefuse->eeprom_pwrlimit_ht20[i] = 0; 220 } 221 } 222 for (rf_path = 0; rf_path < 2; rf_path++) { 223 for (i = 0; i < 14; i++) { 224 index = rtl92c_get_chnl_group((u8)i); 225 if (rf_path == RF90_PATH_A) { 226 rtlefuse->pwrgroup_ht20[rf_path][i] = 227 (rtlefuse->eeprom_pwrlimit_ht20[index] 228 & 0xf); 229 rtlefuse->pwrgroup_ht40[rf_path][i] = 230 (rtlefuse->eeprom_pwrlimit_ht40[index] 231 & 0xf); 232 } else if (rf_path == RF90_PATH_B) { 233 rtlefuse->pwrgroup_ht20[rf_path][i] = 234 ((rtlefuse->eeprom_pwrlimit_ht20[index] 235 & 0xf0) >> 4); 236 rtlefuse->pwrgroup_ht40[rf_path][i] = 237 ((rtlefuse->eeprom_pwrlimit_ht40[index] 238 & 0xf0) >> 4); 239 } 240 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 241 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", 242 rf_path, i, 243 rtlefuse->pwrgroup_ht20[rf_path][i]); 244 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 245 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", 246 rf_path, i, 247 rtlefuse->pwrgroup_ht40[rf_path][i]); 248 } 249 } 250 for (i = 0; i < 14; i++) { 251 index = rtl92c_get_chnl_group((u8)i); 252 if (!autoload_fail) 253 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; 254 else 255 tempval = EEPROM_DEFAULT_HT20_DIFF; 256 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 257 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 258 ((tempval >> 4) & 0xF); 259 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) 260 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; 261 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) 262 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; 263 index = rtl92c_get_chnl_group((u8)i); 264 if (!autoload_fail) 265 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; 266 else 267 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 268 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); 269 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 270 ((tempval >> 4) & 0xF); 271 } 272 rtlefuse->legacy_ht_txpowerdiff = 273 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; 274 for (i = 0; i < 14; i++) 275 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 276 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", 277 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 278 for (i = 0; i < 14; i++) 279 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 280 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", 281 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 282 for (i = 0; i < 14; i++) 283 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 284 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", 285 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 286 for (i = 0; i < 14; i++) 287 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 288 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", 289 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 290 if (!autoload_fail) 291 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); 292 else 293 rtlefuse->eeprom_regulatory = 0; 294 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 295 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 296 if (!autoload_fail) { 297 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; 298 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B]; 299 } else { 300 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; 301 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI; 302 } 303 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 304 "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 305 rtlefuse->eeprom_tssi[RF90_PATH_A], 306 rtlefuse->eeprom_tssi[RF90_PATH_B]); 307 if (!autoload_fail) 308 tempval = hwinfo[EEPROM_THERMAL_METER]; 309 else 310 tempval = EEPROM_DEFAULT_THERMALMETER; 311 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); 312 if (rtlefuse->eeprom_thermalmeter < 0x06 || 313 rtlefuse->eeprom_thermalmeter > 0x1c) 314 rtlefuse->eeprom_thermalmeter = 0x12; 315 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) 316 rtlefuse->apk_thermalmeterignore = true; 317 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 318 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 319 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 320 } 321 322 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents) 323 { 324 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 325 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 326 u8 boardType; 327 328 if (IS_NORMAL_CHIP(rtlhal->version)) { 329 boardType = ((contents[EEPROM_RF_OPT1]) & 330 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/ 331 } else { 332 boardType = contents[EEPROM_RF_OPT4]; 333 boardType &= BOARD_TYPE_TEST_MASK; 334 } 335 rtlefuse->board_type = boardType; 336 if (IS_HIGHT_PA(rtlefuse->board_type)) 337 rtlefuse->external_pa = 1; 338 pr_info("Board Type %x\n", rtlefuse->board_type); 339 } 340 341 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw) 342 { 343 struct rtl_priv *rtlpriv = rtl_priv(hw); 344 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 345 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 346 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, 347 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 348 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 349 0}; 350 u8 *hwinfo; 351 352 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 353 if (!hwinfo) 354 return; 355 356 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 357 goto exit; 358 359 _rtl92cu_read_txpower_info_from_hwpg(hw, 360 rtlefuse->autoload_failflag, hwinfo); 361 _rtl92cu_read_board_type(hw, hwinfo); 362 363 rtlefuse->txpwr_fromeprom = true; 364 if (rtlhal->oem_id == RT_CID_DEFAULT) { 365 switch (rtlefuse->eeprom_oemid) { 366 case EEPROM_CID_DEFAULT: 367 if (rtlefuse->eeprom_did == 0x8176) { 368 if ((rtlefuse->eeprom_svid == 0x103C && 369 rtlefuse->eeprom_smid == 0x1629)) 370 rtlhal->oem_id = RT_CID_819X_HP; 371 else 372 rtlhal->oem_id = RT_CID_DEFAULT; 373 } else { 374 rtlhal->oem_id = RT_CID_DEFAULT; 375 } 376 break; 377 case EEPROM_CID_TOSHIBA: 378 rtlhal->oem_id = RT_CID_TOSHIBA; 379 break; 380 case EEPROM_CID_QMI: 381 rtlhal->oem_id = RT_CID_819X_QMI; 382 break; 383 case EEPROM_CID_WHQL: 384 default: 385 rtlhal->oem_id = RT_CID_DEFAULT; 386 break; 387 } 388 } 389 exit: 390 kfree(hwinfo); 391 } 392 393 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw) 394 { 395 struct rtl_priv *rtlpriv = rtl_priv(hw); 396 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 397 398 switch (rtlhal->oem_id) { 399 case RT_CID_819X_HP: 400 rtlpriv->ledctl.led_opendrain = true; 401 break; 402 case RT_CID_819X_LENOVO: 403 case RT_CID_DEFAULT: 404 case RT_CID_TOSHIBA: 405 case RT_CID_CCX: 406 case RT_CID_819X_ACER: 407 case RT_CID_WHQL: 408 default: 409 break; 410 } 411 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n", 412 rtlhal->oem_id); 413 } 414 415 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw) 416 { 417 418 struct rtl_priv *rtlpriv = rtl_priv(hw); 419 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 420 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 421 u8 tmp_u1b; 422 423 if (!IS_NORMAL_CHIP(rtlhal->version)) 424 return; 425 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 426 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ? 427 EEPROM_93C46 : EEPROM_BOOT_EFUSE; 428 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n", 429 tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE"); 430 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true; 431 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n", 432 tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!"); 433 _rtl92cu_read_adapter_info(hw); 434 _rtl92cu_hal_customized_behavior(hw); 435 return; 436 } 437 438 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw) 439 { 440 struct rtl_priv *rtlpriv = rtl_priv(hw); 441 int status = 0; 442 u16 value16; 443 u8 value8; 444 /* polling autoload done. */ 445 u32 pollingCount = 0; 446 447 do { 448 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) { 449 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 450 "Autoload Done!\n"); 451 break; 452 } 453 if (pollingCount++ > 100) { 454 pr_err("Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n"); 455 return -ENODEV; 456 } 457 } while (true); 458 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */ 459 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); 460 /* Power on when re-enter from IPS/Radio off/card disable */ 461 /* enable SPS into PWM mode */ 462 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 463 udelay(100); 464 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL); 465 if (0 == (value8 & LDV12_EN)) { 466 value8 |= LDV12_EN; 467 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8); 468 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 469 " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n", 470 value8); 471 udelay(100); 472 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL); 473 value8 &= ~ISO_MD2PP; 474 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8); 475 } 476 /* auto enable WLAN */ 477 pollingCount = 0; 478 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO); 479 value16 |= APFM_ONMAC; 480 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16); 481 do { 482 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) { 483 pr_info("MAC auto ON okay!\n"); 484 break; 485 } 486 if (pollingCount++ > 1000) { 487 pr_err("Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n"); 488 return -ENODEV; 489 } 490 } while (true); 491 /* Enable Radio ,GPIO ,and LED function */ 492 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812); 493 /* release RF digital isolation */ 494 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); 495 value16 &= ~ISO_DIOR; 496 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16); 497 /* Reconsider when to do this operation after asking HWSD. */ 498 pollingCount = 0; 499 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv, 500 REG_APSD_CTRL) & ~BIT(6))); 501 do { 502 pollingCount++; 503 } while ((pollingCount < 200) && 504 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7))); 505 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ 506 value16 = rtl_read_word(rtlpriv, REG_CR); 507 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN | 508 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC); 509 rtl_write_word(rtlpriv, REG_CR, value16); 510 return status; 511 } 512 513 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw, 514 bool wmm_enable, 515 u8 out_ep_num, 516 u8 queue_sel) 517 { 518 struct rtl_priv *rtlpriv = rtl_priv(hw); 519 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 520 bool isChipN = IS_NORMAL_CHIP(rtlhal->version); 521 u32 outEPNum = (u32)out_ep_num; 522 u32 numHQ = 0; 523 u32 numLQ = 0; 524 u32 numNQ = 0; 525 u32 numPubQ; 526 u32 value32; 527 u8 value8; 528 u32 txQPageNum, txQPageUnit, txQRemainPage; 529 530 if (!wmm_enable) { 531 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ : 532 CHIP_A_PAGE_NUM_PUBQ; 533 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ; 534 535 txQPageUnit = txQPageNum/outEPNum; 536 txQRemainPage = txQPageNum % outEPNum; 537 if (queue_sel & TX_SELE_HQ) 538 numHQ = txQPageUnit; 539 if (queue_sel & TX_SELE_LQ) 540 numLQ = txQPageUnit; 541 /* HIGH priority queue always present in the configuration of 542 * 2 out-ep. Remainder pages have assigned to High queue */ 543 if ((outEPNum > 1) && (txQRemainPage)) 544 numHQ += txQRemainPage; 545 /* NOTE: This step done before writting REG_RQPN. */ 546 if (isChipN) { 547 if (queue_sel & TX_SELE_NQ) 548 numNQ = txQPageUnit; 549 value8 = (u8)_NPQ(numNQ); 550 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); 551 } 552 } else { 553 /* for WMM ,number of out-ep must more than or equal to 2! */ 554 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ : 555 WMM_CHIP_A_PAGE_NUM_PUBQ; 556 if (queue_sel & TX_SELE_HQ) { 557 numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ : 558 WMM_CHIP_A_PAGE_NUM_HPQ; 559 } 560 if (queue_sel & TX_SELE_LQ) { 561 numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ : 562 WMM_CHIP_A_PAGE_NUM_LPQ; 563 } 564 /* NOTE: This step done before writting REG_RQPN. */ 565 if (isChipN) { 566 if (queue_sel & TX_SELE_NQ) 567 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ; 568 value8 = (u8)_NPQ(numNQ); 569 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); 570 } 571 } 572 /* TX DMA */ 573 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN; 574 rtl_write_dword(rtlpriv, REG_RQPN, value32); 575 } 576 577 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable) 578 { 579 struct rtl_priv *rtlpriv = rtl_priv(hw); 580 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 581 u8 txpktbuf_bndy; 582 u8 value8; 583 584 if (!wmm_enable) 585 txpktbuf_bndy = TX_PAGE_BOUNDARY; 586 else /* for WMM */ 587 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version)) 588 ? WMM_CHIP_B_TX_PAGE_BOUNDARY 589 : WMM_CHIP_A_TX_PAGE_BOUNDARY; 590 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 591 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 592 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy); 593 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy); 594 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy); 595 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); 596 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128); 597 rtl_write_byte(rtlpriv, REG_PBP, value8); 598 } 599 600 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ, 601 u16 bkQ, u16 viQ, u16 voQ, 602 u16 mgtQ, u16 hiQ) 603 { 604 struct rtl_priv *rtlpriv = rtl_priv(hw); 605 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7); 606 607 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) | 608 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) | 609 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ); 610 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16); 611 } 612 613 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw, 614 bool wmm_enable, 615 u8 queue_sel) 616 { 617 u16 uninitialized_var(value); 618 619 switch (queue_sel) { 620 case TX_SELE_HQ: 621 value = QUEUE_HIGH; 622 break; 623 case TX_SELE_LQ: 624 value = QUEUE_LOW; 625 break; 626 case TX_SELE_NQ: 627 value = QUEUE_NORMAL; 628 break; 629 default: 630 WARN_ON(1); /* Shall not reach here! */ 631 break; 632 } 633 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value, 634 value, value); 635 pr_info("Tx queue select: 0x%02x\n", queue_sel); 636 } 637 638 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw, 639 bool wmm_enable, 640 u8 queue_sel) 641 { 642 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; 643 u16 uninitialized_var(valueHi); 644 u16 uninitialized_var(valueLow); 645 646 switch (queue_sel) { 647 case (TX_SELE_HQ | TX_SELE_LQ): 648 valueHi = QUEUE_HIGH; 649 valueLow = QUEUE_LOW; 650 break; 651 case (TX_SELE_NQ | TX_SELE_LQ): 652 valueHi = QUEUE_NORMAL; 653 valueLow = QUEUE_LOW; 654 break; 655 case (TX_SELE_HQ | TX_SELE_NQ): 656 valueHi = QUEUE_HIGH; 657 valueLow = QUEUE_NORMAL; 658 break; 659 default: 660 WARN_ON(1); 661 break; 662 } 663 if (!wmm_enable) { 664 beQ = valueLow; 665 bkQ = valueLow; 666 viQ = valueHi; 667 voQ = valueHi; 668 mgtQ = valueHi; 669 hiQ = valueHi; 670 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */ 671 beQ = valueHi; 672 bkQ = valueLow; 673 viQ = valueLow; 674 voQ = valueHi; 675 mgtQ = valueHi; 676 hiQ = valueHi; 677 } 678 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ); 679 pr_info("Tx queue select: 0x%02x\n", queue_sel); 680 } 681 682 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw, 683 bool wmm_enable, 684 u8 queue_sel) 685 { 686 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; 687 688 if (!wmm_enable) { /* typical setting */ 689 beQ = QUEUE_LOW; 690 bkQ = QUEUE_LOW; 691 viQ = QUEUE_NORMAL; 692 voQ = QUEUE_HIGH; 693 mgtQ = QUEUE_HIGH; 694 hiQ = QUEUE_HIGH; 695 } else { /* for WMM */ 696 beQ = QUEUE_LOW; 697 bkQ = QUEUE_NORMAL; 698 viQ = QUEUE_NORMAL; 699 voQ = QUEUE_HIGH; 700 mgtQ = QUEUE_HIGH; 701 hiQ = QUEUE_HIGH; 702 } 703 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ); 704 pr_info("Tx queue select :0x%02x..\n", queue_sel); 705 } 706 707 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw, 708 bool wmm_enable, 709 u8 out_ep_num, 710 u8 queue_sel) 711 { 712 switch (out_ep_num) { 713 case 1: 714 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable, 715 queue_sel); 716 break; 717 case 2: 718 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable, 719 queue_sel); 720 break; 721 case 3: 722 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable, 723 queue_sel); 724 break; 725 default: 726 WARN_ON(1); /* Shall not reach here! */ 727 break; 728 } 729 } 730 731 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw, 732 bool wmm_enable, 733 u8 out_ep_num, 734 u8 queue_sel) 735 { 736 u8 hq_sele = 0; 737 struct rtl_priv *rtlpriv = rtl_priv(hw); 738 739 switch (out_ep_num) { 740 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */ 741 if (!wmm_enable) /* typical setting */ 742 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ | 743 HQSEL_HIQ; 744 else /* for WMM */ 745 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ | 746 HQSEL_HIQ; 747 break; 748 case 1: 749 if (TX_SELE_LQ == queue_sel) { 750 /* map all endpoint to Low queue */ 751 hq_sele = 0; 752 } else if (TX_SELE_HQ == queue_sel) { 753 /* map all endpoint to High queue */ 754 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ | 755 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ; 756 } 757 break; 758 default: 759 WARN_ON(1); /* Shall not reach here! */ 760 break; 761 } 762 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele); 763 pr_info("Tx queue select :0x%02x..\n", hq_sele); 764 } 765 766 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw, 767 bool wmm_enable, 768 u8 out_ep_num, 769 u8 queue_sel) 770 { 771 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 772 if (IS_NORMAL_CHIP(rtlhal->version)) 773 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num, 774 queue_sel); 775 else 776 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num, 777 queue_sel); 778 } 779 780 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw) 781 { 782 u16 value16; 783 u32 value32; 784 struct rtl_priv *rtlpriv = rtl_priv(hw); 785 786 value32 = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS | 787 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | 788 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32); 789 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&value32)); 790 /* Accept all multicast address */ 791 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF); 792 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF); 793 /* Accept all management frames */ 794 value16 = 0xFFFF; 795 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MGT_FILTER, 796 (u8 *)(&value16)); 797 /* Reject all control frame - default value is 0 */ 798 value16 = 0x0; 799 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_CTRL_FILTER, 800 (u8 *)(&value16)); 801 /* Accept all data frames */ 802 value16 = 0xFFFF; 803 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_DATA_FILTER, 804 (u8 *)(&value16)); 805 } 806 807 static void _rtl92cu_init_beacon_parameters(struct ieee80211_hw *hw) 808 { 809 struct rtl_priv *rtlpriv = rtl_priv(hw); 810 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 811 812 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010); 813 814 /* TODO: Remove these magic number */ 815 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404); 816 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME); 817 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); 818 /* Change beacon AIFS to the largest number 819 * beacause test chip does not contension before sending beacon. 820 */ 821 if (IS_NORMAL_CHIP(rtlhal->version)) 822 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F); 823 else 824 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF); 825 } 826 827 static int _rtl92cu_init_mac(struct ieee80211_hw *hw) 828 { 829 struct rtl_priv *rtlpriv = rtl_priv(hw); 830 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 831 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw); 832 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv); 833 int err = 0; 834 u32 boundary = 0; 835 u8 wmm_enable = false; /* TODO */ 836 u8 out_ep_nums = rtlusb->out_ep_nums; 837 u8 queue_sel = rtlusb->out_queue_sel; 838 err = _rtl92cu_init_power_on(hw); 839 840 if (err) { 841 pr_err("Failed to init power on!\n"); 842 return err; 843 } 844 if (!wmm_enable) { 845 boundary = TX_PAGE_BOUNDARY; 846 } else { /* for WMM */ 847 boundary = (IS_NORMAL_CHIP(rtlhal->version)) 848 ? WMM_CHIP_B_TX_PAGE_BOUNDARY 849 : WMM_CHIP_A_TX_PAGE_BOUNDARY; 850 } 851 if (false == rtl92c_init_llt_table(hw, boundary)) { 852 pr_err("Failed to init LLT Table!\n"); 853 return -EINVAL; 854 } 855 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums, 856 queue_sel); 857 _rtl92c_init_trx_buffer(hw, wmm_enable); 858 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums, 859 queue_sel); 860 /* Get Rx PHY status in order to report RSSI and others. */ 861 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE); 862 rtl92c_init_interrupt(hw); 863 rtl92c_init_network_type(hw); 864 _rtl92cu_init_wmac_setting(hw); 865 rtl92c_init_adaptive_ctrl(hw); 866 rtl92c_init_edca(hw); 867 rtl92c_init_rate_fallback(hw); 868 rtl92c_init_retry_function(hw); 869 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20); 870 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version)); 871 _rtl92cu_init_beacon_parameters(hw); 872 rtl92c_init_ampdu_aggregation(hw); 873 rtl92c_init_beacon_max_error(hw); 874 return err; 875 } 876 877 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw) 878 { 879 struct rtl_priv *rtlpriv = rtl_priv(hw); 880 u8 sec_reg_value = 0x0; 881 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 882 883 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 884 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 885 rtlpriv->sec.pairwise_enc_algorithm, 886 rtlpriv->sec.group_enc_algorithm); 887 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 888 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 889 "not open sw encryption\n"); 890 return; 891 } 892 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable; 893 if (rtlpriv->sec.use_defaultkey) { 894 sec_reg_value |= SCR_TxUseDK; 895 sec_reg_value |= SCR_RxUseDK; 896 } 897 if (IS_NORMAL_CHIP(rtlhal->version)) 898 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 899 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 900 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n", 901 sec_reg_value); 902 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 903 } 904 905 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw) 906 { 907 struct rtl_priv *rtlpriv = rtl_priv(hw); 908 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 909 910 /* To Fix MAC loopback mode fail. */ 911 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f); 912 rtl_write_byte(rtlpriv, 0x15, 0xe9); 913 /* HW SEQ CTRL */ 914 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */ 915 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 916 /* fixed USB interface interference issue */ 917 rtl_write_byte(rtlpriv, 0xfe40, 0xe0); 918 rtl_write_byte(rtlpriv, 0xfe41, 0x8d); 919 rtl_write_byte(rtlpriv, 0xfe42, 0x80); 920 rtlusb->reg_bcn_ctrl_val = 0x18; 921 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val); 922 } 923 924 static void _InitPABias(struct ieee80211_hw *hw) 925 { 926 struct rtl_priv *rtlpriv = rtl_priv(hw); 927 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 928 u8 pa_setting; 929 930 /* FIXED PA current issue */ 931 pa_setting = efuse_read_1byte(hw, 0x1FA); 932 if (!(pa_setting & BIT(0))) { 933 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406); 934 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406); 935 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406); 936 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406); 937 } 938 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) && 939 IS_92C_SERIAL(rtlhal->version)) { 940 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406); 941 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406); 942 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406); 943 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406); 944 } 945 if (!(pa_setting & BIT(4))) { 946 pa_setting = rtl_read_byte(rtlpriv, 0x16); 947 pa_setting &= 0x0F; 948 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90); 949 } 950 } 951 952 int rtl92cu_hw_init(struct ieee80211_hw *hw) 953 { 954 struct rtl_priv *rtlpriv = rtl_priv(hw); 955 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 956 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 957 struct rtl_phy *rtlphy = &(rtlpriv->phy); 958 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 959 int err = 0; 960 unsigned long flags; 961 962 /* As this function can take a very long time (up to 350 ms) 963 * and can be called with irqs disabled, reenable the irqs 964 * to let the other devices continue being serviced. 965 * 966 * It is safe doing so since our own interrupts will only be enabled 967 * in a subsequent step. 968 */ 969 local_save_flags(flags); 970 local_irq_enable(); 971 972 rtlhal->fw_ready = false; 973 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU; 974 err = _rtl92cu_init_mac(hw); 975 if (err) { 976 pr_err("init mac failed!\n"); 977 goto exit; 978 } 979 err = rtl92c_download_fw(hw); 980 if (err) { 981 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 982 "Failed to download FW. Init HW without FW now..\n"); 983 err = 1; 984 goto exit; 985 } 986 987 rtlhal->fw_ready = true; 988 rtlhal->last_hmeboxnum = 0; /* h2c */ 989 _rtl92cu_phy_param_tab_init(hw); 990 rtl92cu_phy_mac_config(hw); 991 rtl92cu_phy_bb_config(hw); 992 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 993 rtl92c_phy_rf_config(hw); 994 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) && 995 !IS_92C_SERIAL(rtlhal->version)) { 996 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); 997 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); 998 } 999 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 1000 RF_CHNLBW, RFREG_OFFSET_MASK); 1001 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 1002 RF_CHNLBW, RFREG_OFFSET_MASK); 1003 rtl92cu_bb_block_on(hw); 1004 rtl_cam_reset_all_entry(hw); 1005 rtl92cu_enable_hw_security_config(hw); 1006 ppsc->rfpwr_state = ERFON; 1007 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1008 if (ppsc->rfpwr_state == ERFON) { 1009 rtl92c_phy_set_rfpath_switch(hw, 1); 1010 if (rtlphy->iqk_initialized) { 1011 rtl92c_phy_iq_calibrate(hw, true); 1012 } else { 1013 rtl92c_phy_iq_calibrate(hw, false); 1014 rtlphy->iqk_initialized = true; 1015 } 1016 rtl92c_dm_check_txpower_tracking(hw); 1017 rtl92c_phy_lc_calibrate(hw); 1018 } 1019 _rtl92cu_hw_configure(hw); 1020 _InitPABias(hw); 1021 rtl92c_dm_init(hw); 1022 exit: 1023 local_irq_restore(flags); 1024 return err; 1025 } 1026 1027 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw) 1028 { 1029 struct rtl_priv *rtlpriv = rtl_priv(hw); 1030 /************************************** 1031 a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue 1032 b. RF path 0 offset 0x00 = 0x00 disable RF 1033 c. APSD_CTRL 0x600[7:0] = 0x40 1034 d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine 1035 e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine 1036 ***************************************/ 1037 u8 eRFPath = 0, value8 = 0; 1038 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1039 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0); 1040 1041 value8 |= APSDOFF; 1042 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/ 1043 value8 = 0; 1044 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn); 1045 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/ 1046 value8 &= (~FEN_BB_GLB_RSTn); 1047 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/ 1048 } 1049 1050 static void _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM) 1051 { 1052 struct rtl_priv *rtlpriv = rtl_priv(hw); 1053 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1054 1055 if (rtlhal->fw_version <= 0x20) { 1056 /***************************** 1057 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status 1058 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset) 1059 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE 1060 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable) 1061 ******************************/ 1062 u16 valu16 = 0; 1063 1064 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1065 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1066 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 & 1067 (~FEN_CPUEN))); /* reset MCU ,8051 */ 1068 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF; 1069 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 | 1070 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */ 1071 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1072 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 | 1073 FEN_CPUEN)); /* enable MCU ,8051 */ 1074 } else { 1075 u8 retry_cnts = 0; 1076 1077 /* IF fw in RAM code, do reset */ 1078 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) { 1079 /* reset MCU ready status */ 1080 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1081 /* 8051 reset by self */ 1082 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20); 1083 while ((retry_cnts++ < 100) && 1084 (FEN_CPUEN & rtl_read_word(rtlpriv, 1085 REG_SYS_FUNC_EN))) { 1086 udelay(50); 1087 } 1088 if (retry_cnts >= 100) { 1089 pr_err("8051 reset failed!.........................\n"); 1090 /* if 8051 reset fail, reset MAC. */ 1091 rtl_write_byte(rtlpriv, 1092 REG_SYS_FUNC_EN + 1, 1093 0x50); 1094 udelay(100); 1095 } 1096 } 1097 /* Reset MAC and Enable 8051 */ 1098 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54); 1099 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1100 } 1101 if (bWithoutHWSM) { 1102 /***************************** 1103 Without HW auto state machine 1104 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock 1105 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL 1106 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK 1107 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON 1108 ******************************/ 1109 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3); 1110 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); 1111 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F); 1112 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9); 1113 } 1114 } 1115 1116 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw) 1117 { 1118 struct rtl_priv *rtlpriv = rtl_priv(hw); 1119 /***************************** 1120 k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction 1121 l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock 1122 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON 1123 ******************************/ 1124 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3); 1125 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82); 1126 } 1127 1128 static void _DisableGPIO(struct ieee80211_hw *hw) 1129 { 1130 struct rtl_priv *rtlpriv = rtl_priv(hw); 1131 /*************************************** 1132 j. GPIO_PIN_CTRL 0x44[31:0]=0x000 1133 k. Value = GPIO_PIN_CTRL[7:0] 1134 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level 1135 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780 1136 n. LEDCFG 0x4C[15:0] = 0x8080 1137 ***************************************/ 1138 u8 value8; 1139 u16 value16; 1140 u32 value32; 1141 1142 /* 1. Disable GPIO[7:0] */ 1143 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000); 1144 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF; 1145 value8 = (u8)(value32&0x000000FF); 1146 value32 |= ((value8<<8) | 0x00FF0000); 1147 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32); 1148 /* 2. Disable GPIO[10:8] */ 1149 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00); 1150 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F; 1151 value8 = (u8)(value16&0x000F); 1152 value16 |= ((value8<<4) | 0x0780); 1153 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16); 1154 /* 3. Disable LED0 & 1 */ 1155 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); 1156 } 1157 1158 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM) 1159 { 1160 struct rtl_priv *rtlpriv = rtl_priv(hw); 1161 u16 value16 = 0; 1162 u8 value8 = 0; 1163 1164 if (bWithoutHWSM) { 1165 /***************************** 1166 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power 1167 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power 1168 r. When driver call disable, the ASIC will turn off remaining 1169 clock automatically 1170 ******************************/ 1171 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04); 1172 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL); 1173 value8 &= (~LDV12_EN); 1174 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8); 1175 } 1176 1177 /***************************** 1178 h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode 1179 i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend 1180 ******************************/ 1181 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); 1182 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN); 1183 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16); 1184 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E); 1185 } 1186 1187 static void _CardDisableHWSM(struct ieee80211_hw *hw) 1188 { 1189 /* ==== RF Off Sequence ==== */ 1190 _DisableRFAFEAndResetBB(hw); 1191 /* ==== Reset digital sequence ====== */ 1192 _ResetDigitalProcedure1(hw, false); 1193 /* ==== Pull GPIO PIN to balance level and LED control ====== */ 1194 _DisableGPIO(hw); 1195 /* ==== Disable analog sequence === */ 1196 _DisableAnalog(hw, false); 1197 } 1198 1199 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw) 1200 { 1201 /*==== RF Off Sequence ==== */ 1202 _DisableRFAFEAndResetBB(hw); 1203 /* ==== Reset digital sequence ====== */ 1204 _ResetDigitalProcedure1(hw, true); 1205 /* ==== Pull GPIO PIN to balance level and LED control ====== */ 1206 _DisableGPIO(hw); 1207 /* ==== Reset digital sequence ====== */ 1208 _ResetDigitalProcedure2(hw); 1209 /* ==== Disable analog sequence === */ 1210 _DisableAnalog(hw, true); 1211 } 1212 1213 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 1214 u8 set_bits, u8 clear_bits) 1215 { 1216 struct rtl_priv *rtlpriv = rtl_priv(hw); 1217 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 1218 1219 rtlusb->reg_bcn_ctrl_val |= set_bits; 1220 rtlusb->reg_bcn_ctrl_val &= ~clear_bits; 1221 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val); 1222 } 1223 1224 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw) 1225 { 1226 struct rtl_priv *rtlpriv = rtl_priv(hw); 1227 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1228 u8 tmp1byte = 0; 1229 if (IS_NORMAL_CHIP(rtlhal->version)) { 1230 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 1231 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1232 tmp1byte & (~BIT(6))); 1233 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 1234 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 1235 tmp1byte &= ~(BIT(0)); 1236 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 1237 } else { 1238 rtl_write_byte(rtlpriv, REG_TXPAUSE, 1239 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6)); 1240 } 1241 } 1242 1243 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw) 1244 { 1245 struct rtl_priv *rtlpriv = rtl_priv(hw); 1246 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1247 u8 tmp1byte = 0; 1248 1249 if (IS_NORMAL_CHIP(rtlhal->version)) { 1250 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 1251 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1252 tmp1byte | BIT(6)); 1253 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 1254 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 1255 tmp1byte |= BIT(0); 1256 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 1257 } else { 1258 rtl_write_byte(rtlpriv, REG_TXPAUSE, 1259 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6))); 1260 } 1261 } 1262 1263 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw) 1264 { 1265 struct rtl_priv *rtlpriv = rtl_priv(hw); 1266 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1267 1268 if (IS_NORMAL_CHIP(rtlhal->version)) 1269 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1)); 1270 else 1271 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1272 } 1273 1274 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw) 1275 { 1276 struct rtl_priv *rtlpriv = rtl_priv(hw); 1277 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1278 1279 if (IS_NORMAL_CHIP(rtlhal->version)) 1280 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0); 1281 else 1282 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0); 1283 } 1284 1285 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw, 1286 enum nl80211_iftype type) 1287 { 1288 struct rtl_priv *rtlpriv = rtl_priv(hw); 1289 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1290 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1291 1292 bt_msr &= 0xfc; 1293 if (type == NL80211_IFTYPE_UNSPECIFIED || type == 1294 NL80211_IFTYPE_STATION) { 1295 _rtl92cu_stop_tx_beacon(hw); 1296 _rtl92cu_enable_bcn_sub_func(hw); 1297 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) { 1298 _rtl92cu_resume_tx_beacon(hw); 1299 _rtl92cu_disable_bcn_sub_func(hw); 1300 } else { 1301 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1302 "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n", 1303 type); 1304 } 1305 switch (type) { 1306 case NL80211_IFTYPE_UNSPECIFIED: 1307 bt_msr |= MSR_NOLINK; 1308 ledaction = LED_CTL_LINK; 1309 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1310 "Set Network type to NO LINK!\n"); 1311 break; 1312 case NL80211_IFTYPE_ADHOC: 1313 bt_msr |= MSR_ADHOC; 1314 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1315 "Set Network type to Ad Hoc!\n"); 1316 break; 1317 case NL80211_IFTYPE_STATION: 1318 bt_msr |= MSR_INFRA; 1319 ledaction = LED_CTL_LINK; 1320 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1321 "Set Network type to STA!\n"); 1322 break; 1323 case NL80211_IFTYPE_AP: 1324 bt_msr |= MSR_AP; 1325 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1326 "Set Network type to AP!\n"); 1327 break; 1328 default: 1329 pr_err("Network type %d not supported!\n", type); 1330 goto error_out; 1331 } 1332 rtl_write_byte(rtlpriv, MSR, bt_msr); 1333 rtlpriv->cfg->ops->led_control(hw, ledaction); 1334 if ((bt_msr & MSR_MASK) == MSR_AP) 1335 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1336 else 1337 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1338 return 0; 1339 error_out: 1340 return 1; 1341 } 1342 1343 void rtl92cu_card_disable(struct ieee80211_hw *hw) 1344 { 1345 struct rtl_priv *rtlpriv = rtl_priv(hw); 1346 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1347 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 1348 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1349 enum nl80211_iftype opmode; 1350 1351 mac->link_state = MAC80211_NOLINK; 1352 opmode = NL80211_IFTYPE_UNSPECIFIED; 1353 _rtl92cu_set_media_status(hw, opmode); 1354 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1355 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1356 if (rtlusb->disableHWSM) 1357 _CardDisableHWSM(hw); 1358 else 1359 _CardDisableWithoutHWSM(hw); 1360 1361 /* after power off we should do iqk again */ 1362 rtlpriv->phy.iqk_initialized = false; 1363 } 1364 1365 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1366 { 1367 struct rtl_priv *rtlpriv = rtl_priv(hw); 1368 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1369 u32 reg_rcr; 1370 1371 if (rtlpriv->psc.rfpwr_state != ERFON) 1372 return; 1373 1374 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1375 1376 if (check_bssid) { 1377 u8 tmp; 1378 if (IS_NORMAL_CHIP(rtlhal->version)) { 1379 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1380 tmp = BIT(4); 1381 } else { 1382 reg_rcr |= RCR_CBSSID; 1383 tmp = BIT(4) | BIT(5); 1384 } 1385 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1386 (u8 *) (®_rcr)); 1387 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp); 1388 } else { 1389 u8 tmp; 1390 if (IS_NORMAL_CHIP(rtlhal->version)) { 1391 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1392 tmp = BIT(4); 1393 } else { 1394 reg_rcr &= ~RCR_CBSSID; 1395 tmp = BIT(4) | BIT(5); 1396 } 1397 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1398 rtlpriv->cfg->ops->set_hw_reg(hw, 1399 HW_VAR_RCR, (u8 *) (®_rcr)); 1400 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0); 1401 } 1402 } 1403 1404 /*========================================================================== */ 1405 1406 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1407 { 1408 struct rtl_priv *rtlpriv = rtl_priv(hw); 1409 1410 if (_rtl92cu_set_media_status(hw, type)) 1411 return -EOPNOTSUPP; 1412 1413 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1414 if (type != NL80211_IFTYPE_AP) 1415 rtl92cu_set_check_bssid(hw, true); 1416 } else { 1417 rtl92cu_set_check_bssid(hw, false); 1418 } 1419 1420 return 0; 1421 } 1422 1423 static void _beacon_function_enable(struct ieee80211_hw *hw) 1424 { 1425 struct rtl_priv *rtlpriv = rtl_priv(hw); 1426 1427 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00); 1428 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F); 1429 } 1430 1431 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw) 1432 { 1433 1434 struct rtl_priv *rtlpriv = rtl_priv(hw); 1435 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1436 u16 bcn_interval, atim_window; 1437 u32 value32; 1438 1439 bcn_interval = mac->beacon_interval; 1440 atim_window = 2; /*FIX MERGE */ 1441 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1442 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1443 _rtl92cu_init_beacon_parameters(hw); 1444 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 1445 /* 1446 * Force beacon frame transmission even after receiving beacon frame 1447 * from other ad hoc STA 1448 * 1449 * 1450 * Reset TSF Timer to zero, added by Roger. 2008.06.24 1451 */ 1452 value32 = rtl_read_dword(rtlpriv, REG_TCR); 1453 value32 &= ~TSFRST; 1454 rtl_write_dword(rtlpriv, REG_TCR, value32); 1455 value32 |= TSFRST; 1456 rtl_write_dword(rtlpriv, REG_TCR, value32); 1457 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD, 1458 "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n", 1459 value32); 1460 /* TODO: Modify later (Find the right parameters) 1461 * NOTE: Fix test chip's bug (about contention windows's randomness) */ 1462 if ((mac->opmode == NL80211_IFTYPE_ADHOC) || 1463 (mac->opmode == NL80211_IFTYPE_MESH_POINT) || 1464 (mac->opmode == NL80211_IFTYPE_AP)) { 1465 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50); 1466 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50); 1467 } 1468 _beacon_function_enable(hw); 1469 } 1470 1471 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw) 1472 { 1473 struct rtl_priv *rtlpriv = rtl_priv(hw); 1474 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1475 u16 bcn_interval = mac->beacon_interval; 1476 1477 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n", 1478 bcn_interval); 1479 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1480 } 1481 1482 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw, 1483 u32 add_msr, u32 rm_msr) 1484 { 1485 } 1486 1487 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 1488 { 1489 struct rtl_priv *rtlpriv = rtl_priv(hw); 1490 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1491 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1492 1493 switch (variable) { 1494 case HW_VAR_RCR: 1495 *((u32 *)(val)) = mac->rx_conf; 1496 break; 1497 case HW_VAR_RF_STATE: 1498 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 1499 break; 1500 case HW_VAR_FWLPS_RF_ON:{ 1501 enum rf_pwrstate rfState; 1502 u32 val_rcr; 1503 1504 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, 1505 (u8 *)(&rfState)); 1506 if (rfState == ERFOFF) { 1507 *((bool *) (val)) = true; 1508 } else { 1509 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 1510 val_rcr &= 0x00070000; 1511 if (val_rcr) 1512 *((bool *) (val)) = false; 1513 else 1514 *((bool *) (val)) = true; 1515 } 1516 break; 1517 } 1518 case HW_VAR_FW_PSMODE_STATUS: 1519 *((bool *) (val)) = ppsc->fw_current_inpsmode; 1520 break; 1521 case HW_VAR_CORRECT_TSF:{ 1522 u64 tsf; 1523 u32 *ptsf_low = (u32 *)&tsf; 1524 u32 *ptsf_high = ((u32 *)&tsf) + 1; 1525 1526 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 1527 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 1528 *((u64 *)(val)) = tsf; 1529 break; 1530 } 1531 case HW_VAR_MGT_FILTER: 1532 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0); 1533 break; 1534 case HW_VAR_CTRL_FILTER: 1535 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1); 1536 break; 1537 case HW_VAR_DATA_FILTER: 1538 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2); 1539 break; 1540 case HAL_DEF_WOWLAN: 1541 break; 1542 default: 1543 pr_err("switch case %#x not processed\n", variable); 1544 break; 1545 } 1546 } 1547 1548 static bool usb_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb) 1549 { 1550 /* Currently nothing happens here. 1551 * Traffic stops after some seconds in WPA2 802.11n mode. 1552 * Maybe because rtl8192cu chip should be set from here? 1553 * If I understand correctly, the realtek vendor driver sends some urbs 1554 * if its "here". 1555 * 1556 * This is maybe necessary: 1557 * rtlpriv->cfg->ops->fill_tx_cmddesc(hw, buffer, 1, 1, skb); 1558 */ 1559 return true; 1560 } 1561 1562 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 1563 { 1564 struct rtl_priv *rtlpriv = rtl_priv(hw); 1565 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1566 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1567 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1568 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1569 enum wireless_mode wirelessmode = mac->mode; 1570 u8 idx = 0; 1571 1572 switch (variable) { 1573 case HW_VAR_ETHER_ADDR:{ 1574 for (idx = 0; idx < ETH_ALEN; idx++) { 1575 rtl_write_byte(rtlpriv, (REG_MACID + idx), 1576 val[idx]); 1577 } 1578 break; 1579 } 1580 case HW_VAR_BASIC_RATE:{ 1581 u16 rate_cfg = ((u16 *) val)[0]; 1582 u8 rate_index = 0; 1583 1584 rate_cfg &= 0x15f; 1585 /* TODO */ 1586 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO 1587 * && ((rate_cfg & 0x150) == 0)) { 1588 * rate_cfg |= 0x010; 1589 * } */ 1590 rate_cfg |= 0x01; 1591 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); 1592 rtl_write_byte(rtlpriv, REG_RRSR + 1, 1593 (rate_cfg >> 8) & 0xff); 1594 while (rate_cfg > 0x1) { 1595 rate_cfg >>= 1; 1596 rate_index++; 1597 } 1598 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 1599 rate_index); 1600 break; 1601 } 1602 case HW_VAR_BSSID:{ 1603 for (idx = 0; idx < ETH_ALEN; idx++) { 1604 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 1605 val[idx]); 1606 } 1607 break; 1608 } 1609 case HW_VAR_SIFS:{ 1610 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]); 1611 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]); 1612 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 1613 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 1614 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]); 1615 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]); 1616 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n"); 1617 break; 1618 } 1619 case HW_VAR_SLOT_TIME:{ 1620 u8 e_aci; 1621 u8 QOS_MODE = 1; 1622 1623 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 1624 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1625 "HW_VAR_SLOT_TIME %x\n", val[0]); 1626 if (QOS_MODE) { 1627 for (e_aci = 0; e_aci < AC_MAX; e_aci++) 1628 rtlpriv->cfg->ops->set_hw_reg(hw, 1629 HW_VAR_AC_PARAM, 1630 &e_aci); 1631 } else { 1632 u8 sifstime = 0; 1633 u8 u1bAIFS; 1634 1635 if (IS_WIRELESS_MODE_A(wirelessmode) || 1636 IS_WIRELESS_MODE_N_24G(wirelessmode) || 1637 IS_WIRELESS_MODE_N_5G(wirelessmode)) 1638 sifstime = 16; 1639 else 1640 sifstime = 10; 1641 u1bAIFS = sifstime + (2 * val[0]); 1642 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM, 1643 u1bAIFS); 1644 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM, 1645 u1bAIFS); 1646 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM, 1647 u1bAIFS); 1648 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM, 1649 u1bAIFS); 1650 } 1651 break; 1652 } 1653 case HW_VAR_ACK_PREAMBLE:{ 1654 u8 reg_tmp; 1655 u8 short_preamble = (bool)*val; 1656 reg_tmp = 0; 1657 if (short_preamble) 1658 reg_tmp |= 0x80; 1659 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 1660 break; 1661 } 1662 case HW_VAR_AMPDU_MIN_SPACE:{ 1663 u8 min_spacing_to_set; 1664 u8 sec_min_space; 1665 1666 min_spacing_to_set = *val; 1667 if (min_spacing_to_set <= 7) { 1668 switch (rtlpriv->sec.pairwise_enc_algorithm) { 1669 case NO_ENCRYPTION: 1670 case AESCCMP_ENCRYPTION: 1671 sec_min_space = 0; 1672 break; 1673 case WEP40_ENCRYPTION: 1674 case WEP104_ENCRYPTION: 1675 case TKIP_ENCRYPTION: 1676 sec_min_space = 6; 1677 break; 1678 default: 1679 sec_min_space = 7; 1680 break; 1681 } 1682 if (min_spacing_to_set < sec_min_space) 1683 min_spacing_to_set = sec_min_space; 1684 mac->min_space_cfg = ((mac->min_space_cfg & 1685 0xf8) | 1686 min_spacing_to_set); 1687 *val = min_spacing_to_set; 1688 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1689 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 1690 mac->min_space_cfg); 1691 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 1692 mac->min_space_cfg); 1693 } 1694 break; 1695 } 1696 case HW_VAR_SHORTGI_DENSITY:{ 1697 u8 density_to_set; 1698 1699 density_to_set = *val; 1700 density_to_set &= 0x1f; 1701 mac->min_space_cfg &= 0x07; 1702 mac->min_space_cfg |= (density_to_set << 3); 1703 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1704 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 1705 mac->min_space_cfg); 1706 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 1707 mac->min_space_cfg); 1708 break; 1709 } 1710 case HW_VAR_AMPDU_FACTOR:{ 1711 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; 1712 u8 factor_toset; 1713 u8 *p_regtoset = NULL; 1714 u8 index = 0; 1715 1716 p_regtoset = regtoset_normal; 1717 factor_toset = *val; 1718 if (factor_toset <= 3) { 1719 factor_toset = (1 << (factor_toset + 2)); 1720 if (factor_toset > 0xf) 1721 factor_toset = 0xf; 1722 for (index = 0; index < 4; index++) { 1723 if ((p_regtoset[index] & 0xf0) > 1724 (factor_toset << 4)) 1725 p_regtoset[index] = 1726 (p_regtoset[index] & 0x0f) 1727 | (factor_toset << 4); 1728 if ((p_regtoset[index] & 0x0f) > 1729 factor_toset) 1730 p_regtoset[index] = 1731 (p_regtoset[index] & 0xf0) 1732 | (factor_toset); 1733 rtl_write_byte(rtlpriv, 1734 (REG_AGGLEN_LMT + index), 1735 p_regtoset[index]); 1736 } 1737 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1738 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 1739 factor_toset); 1740 } 1741 break; 1742 } 1743 case HW_VAR_AC_PARAM:{ 1744 u8 e_aci = *val; 1745 u32 u4b_ac_param; 1746 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min); 1747 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max); 1748 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op); 1749 1750 u4b_ac_param = (u32) mac->ac[e_aci].aifs; 1751 u4b_ac_param |= (u32) ((cw_min & 0xF) << 1752 AC_PARAM_ECW_MIN_OFFSET); 1753 u4b_ac_param |= (u32) ((cw_max & 0xF) << 1754 AC_PARAM_ECW_MAX_OFFSET); 1755 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET; 1756 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1757 "queue:%x, ac_param:%x\n", 1758 e_aci, u4b_ac_param); 1759 switch (e_aci) { 1760 case AC1_BK: 1761 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 1762 u4b_ac_param); 1763 break; 1764 case AC0_BE: 1765 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 1766 u4b_ac_param); 1767 break; 1768 case AC2_VI: 1769 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 1770 u4b_ac_param); 1771 break; 1772 case AC3_VO: 1773 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 1774 u4b_ac_param); 1775 break; 1776 default: 1777 WARN_ONCE(true, "rtl8192cu: invalid aci: %d !\n", 1778 e_aci); 1779 break; 1780 } 1781 break; 1782 } 1783 case HW_VAR_RCR:{ 1784 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); 1785 mac->rx_conf = ((u32 *) (val))[0]; 1786 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG, 1787 "### Set RCR(0x%08x) ###\n", mac->rx_conf); 1788 break; 1789 } 1790 case HW_VAR_RETRY_LIMIT:{ 1791 u8 retry_limit = val[0]; 1792 1793 rtl_write_word(rtlpriv, REG_RL, 1794 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 1795 retry_limit << RETRY_LIMIT_LONG_SHIFT); 1796 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG, 1797 "Set HW_VAR_RETRY_LIMIT(0x%08x)\n", 1798 retry_limit); 1799 break; 1800 } 1801 case HW_VAR_DUAL_TSF_RST: 1802 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 1803 break; 1804 case HW_VAR_EFUSE_BYTES: 1805 rtlefuse->efuse_usedbytes = *((u16 *) val); 1806 break; 1807 case HW_VAR_EFUSE_USAGE: 1808 rtlefuse->efuse_usedpercentage = *val; 1809 break; 1810 case HW_VAR_IO_CMD: 1811 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val)); 1812 break; 1813 case HW_VAR_WPA_CONFIG: 1814 rtl_write_byte(rtlpriv, REG_SECCFG, *val); 1815 break; 1816 case HW_VAR_SET_RPWM:{ 1817 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM); 1818 1819 if (rpwm_val & BIT(7)) 1820 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val); 1821 else 1822 rtl_write_byte(rtlpriv, REG_USB_HRPWM, 1823 *val | BIT(7)); 1824 break; 1825 } 1826 case HW_VAR_H2C_FW_PWRMODE:{ 1827 u8 psmode = *val; 1828 1829 if ((psmode != FW_PS_ACTIVE_MODE) && 1830 (!IS_92C_SERIAL(rtlhal->version))) 1831 rtl92c_dm_rf_saving(hw, true); 1832 rtl92c_set_fw_pwrmode_cmd(hw, (*val)); 1833 break; 1834 } 1835 case HW_VAR_FW_PSMODE_STATUS: 1836 ppsc->fw_current_inpsmode = *((bool *) val); 1837 break; 1838 case HW_VAR_H2C_FW_JOINBSSRPT:{ 1839 u8 mstatus = *val; 1840 u8 tmp_reg422; 1841 bool recover = false; 1842 1843 if (mstatus == RT_MEDIA_CONNECT) { 1844 rtlpriv->cfg->ops->set_hw_reg(hw, 1845 HW_VAR_AID, NULL); 1846 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03); 1847 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); 1848 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0); 1849 tmp_reg422 = rtl_read_byte(rtlpriv, 1850 REG_FWHW_TXQ_CTRL + 2); 1851 if (tmp_reg422 & BIT(6)) 1852 recover = true; 1853 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1854 tmp_reg422 & (~BIT(6))); 1855 rtl92c_set_fw_rsvdpagepkt(hw, 1856 &usb_cmd_send_packet); 1857 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); 1858 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1859 if (recover) 1860 rtl_write_byte(rtlpriv, 1861 REG_FWHW_TXQ_CTRL + 2, 1862 tmp_reg422 | BIT(6)); 1863 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 1864 } 1865 rtl92c_set_fw_joinbss_report_cmd(hw, (*val)); 1866 break; 1867 } 1868 case HW_VAR_AID:{ 1869 u16 u2btmp; 1870 1871 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 1872 u2btmp &= 0xC000; 1873 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, 1874 (u2btmp | mac->assoc_id)); 1875 break; 1876 } 1877 case HW_VAR_CORRECT_TSF:{ 1878 u8 btype_ibss = val[0]; 1879 1880 if (btype_ibss) 1881 _rtl92cu_stop_tx_beacon(hw); 1882 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); 1883 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf & 1884 0xffffffff)); 1885 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 1886 (u32)((mac->tsf >> 32) & 0xffffffff)); 1887 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); 1888 if (btype_ibss) 1889 _rtl92cu_resume_tx_beacon(hw); 1890 break; 1891 } 1892 case HW_VAR_MGT_FILTER: 1893 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val); 1894 mac->rx_mgt_filter = *(u16 *)val; 1895 break; 1896 case HW_VAR_CTRL_FILTER: 1897 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val); 1898 mac->rx_ctrl_filter = *(u16 *)val; 1899 break; 1900 case HW_VAR_DATA_FILTER: 1901 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val); 1902 mac->rx_data_filter = *(u16 *)val; 1903 break; 1904 case HW_VAR_KEEP_ALIVE:{ 1905 u8 array[2]; 1906 array[0] = 0xff; 1907 array[1] = *((u8 *)val); 1908 rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2, 1909 array); 1910 break; 1911 } 1912 default: 1913 pr_err("switch case %#x not processed\n", variable); 1914 break; 1915 } 1916 } 1917 1918 static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw, 1919 struct ieee80211_sta *sta) 1920 { 1921 struct rtl_priv *rtlpriv = rtl_priv(hw); 1922 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1923 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1924 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1925 u32 ratr_value; 1926 u8 ratr_index = 0; 1927 u8 nmode = mac->ht_enable; 1928 u8 mimo_ps = IEEE80211_SMPS_OFF; 1929 u16 shortgi_rate; 1930 u32 tmp_ratr_value; 1931 u8 curtxbw_40mhz = mac->bw_40; 1932 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1933 1 : 0; 1934 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1935 1 : 0; 1936 enum wireless_mode wirelessmode = mac->mode; 1937 1938 if (rtlhal->current_bandtype == BAND_ON_5G) 1939 ratr_value = sta->supp_rates[1] << 4; 1940 else 1941 ratr_value = sta->supp_rates[0]; 1942 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1943 ratr_value = 0xfff; 1944 1945 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1946 sta->ht_cap.mcs.rx_mask[0] << 12); 1947 switch (wirelessmode) { 1948 case WIRELESS_MODE_B: 1949 if (ratr_value & 0x0000000c) 1950 ratr_value &= 0x0000000d; 1951 else 1952 ratr_value &= 0x0000000f; 1953 break; 1954 case WIRELESS_MODE_G: 1955 ratr_value &= 0x00000FF5; 1956 break; 1957 case WIRELESS_MODE_N_24G: 1958 case WIRELESS_MODE_N_5G: 1959 nmode = 1; 1960 if (mimo_ps == IEEE80211_SMPS_STATIC) { 1961 ratr_value &= 0x0007F005; 1962 } else { 1963 u32 ratr_mask; 1964 1965 if (get_rf_type(rtlphy) == RF_1T2R || 1966 get_rf_type(rtlphy) == RF_1T1R) 1967 ratr_mask = 0x000ff005; 1968 else 1969 ratr_mask = 0x0f0ff005; 1970 1971 ratr_value &= ratr_mask; 1972 } 1973 break; 1974 default: 1975 if (rtlphy->rf_type == RF_1T2R) 1976 ratr_value &= 0x000ff0ff; 1977 else 1978 ratr_value &= 0x0f0ff0ff; 1979 1980 break; 1981 } 1982 1983 ratr_value &= 0x0FFFFFFF; 1984 1985 if (nmode && ((curtxbw_40mhz && 1986 curshortgi_40mhz) || (!curtxbw_40mhz && 1987 curshortgi_20mhz))) { 1988 1989 ratr_value |= 0x10000000; 1990 tmp_ratr_value = (ratr_value >> 12); 1991 1992 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 1993 if ((1 << shortgi_rate) & tmp_ratr_value) 1994 break; 1995 } 1996 1997 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 1998 (shortgi_rate << 4) | (shortgi_rate); 1999 } 2000 2001 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 2002 2003 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", 2004 rtl_read_dword(rtlpriv, REG_ARFR0)); 2005 } 2006 2007 static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, 2008 struct ieee80211_sta *sta, 2009 u8 rssi_level, bool update_bw) 2010 { 2011 struct rtl_priv *rtlpriv = rtl_priv(hw); 2012 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2013 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2014 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2015 struct rtl_sta_info *sta_entry = NULL; 2016 u32 ratr_bitmap; 2017 u8 ratr_index; 2018 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; 2019 u8 curshortgi_40mhz = curtxbw_40mhz && 2020 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2021 1 : 0; 2022 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2023 1 : 0; 2024 enum wireless_mode wirelessmode = 0; 2025 bool shortgi = false; 2026 u8 rate_mask[5]; 2027 u8 macid = 0; 2028 u8 mimo_ps = IEEE80211_SMPS_OFF; 2029 2030 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 2031 wirelessmode = sta_entry->wireless_mode; 2032 if (mac->opmode == NL80211_IFTYPE_STATION || 2033 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2034 curtxbw_40mhz = mac->bw_40; 2035 else if (mac->opmode == NL80211_IFTYPE_AP || 2036 mac->opmode == NL80211_IFTYPE_ADHOC) 2037 macid = sta->aid + 1; 2038 2039 if (rtlhal->current_bandtype == BAND_ON_5G) 2040 ratr_bitmap = sta->supp_rates[1] << 4; 2041 else 2042 ratr_bitmap = sta->supp_rates[0]; 2043 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2044 ratr_bitmap = 0xfff; 2045 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 2046 sta->ht_cap.mcs.rx_mask[0] << 12); 2047 switch (wirelessmode) { 2048 case WIRELESS_MODE_B: 2049 ratr_index = RATR_INX_WIRELESS_B; 2050 if (ratr_bitmap & 0x0000000c) 2051 ratr_bitmap &= 0x0000000d; 2052 else 2053 ratr_bitmap &= 0x0000000f; 2054 break; 2055 case WIRELESS_MODE_G: 2056 ratr_index = RATR_INX_WIRELESS_GB; 2057 2058 if (rssi_level == 1) 2059 ratr_bitmap &= 0x00000f00; 2060 else if (rssi_level == 2) 2061 ratr_bitmap &= 0x00000ff0; 2062 else 2063 ratr_bitmap &= 0x00000ff5; 2064 break; 2065 case WIRELESS_MODE_A: 2066 ratr_index = RATR_INX_WIRELESS_A; 2067 ratr_bitmap &= 0x00000ff0; 2068 break; 2069 case WIRELESS_MODE_N_24G: 2070 case WIRELESS_MODE_N_5G: 2071 ratr_index = RATR_INX_WIRELESS_NGB; 2072 2073 if (mimo_ps == IEEE80211_SMPS_STATIC) { 2074 if (rssi_level == 1) 2075 ratr_bitmap &= 0x00070000; 2076 else if (rssi_level == 2) 2077 ratr_bitmap &= 0x0007f000; 2078 else 2079 ratr_bitmap &= 0x0007f005; 2080 } else { 2081 if (rtlphy->rf_type == RF_1T2R || 2082 rtlphy->rf_type == RF_1T1R) { 2083 if (curtxbw_40mhz) { 2084 if (rssi_level == 1) 2085 ratr_bitmap &= 0x000f0000; 2086 else if (rssi_level == 2) 2087 ratr_bitmap &= 0x000ff000; 2088 else 2089 ratr_bitmap &= 0x000ff015; 2090 } else { 2091 if (rssi_level == 1) 2092 ratr_bitmap &= 0x000f0000; 2093 else if (rssi_level == 2) 2094 ratr_bitmap &= 0x000ff000; 2095 else 2096 ratr_bitmap &= 0x000ff005; 2097 } 2098 } else { 2099 if (curtxbw_40mhz) { 2100 if (rssi_level == 1) 2101 ratr_bitmap &= 0x0f0f0000; 2102 else if (rssi_level == 2) 2103 ratr_bitmap &= 0x0f0ff000; 2104 else 2105 ratr_bitmap &= 0x0f0ff015; 2106 } else { 2107 if (rssi_level == 1) 2108 ratr_bitmap &= 0x0f0f0000; 2109 else if (rssi_level == 2) 2110 ratr_bitmap &= 0x0f0ff000; 2111 else 2112 ratr_bitmap &= 0x0f0ff005; 2113 } 2114 } 2115 } 2116 2117 if ((curtxbw_40mhz && curshortgi_40mhz) || 2118 (!curtxbw_40mhz && curshortgi_20mhz)) { 2119 2120 if (macid == 0) 2121 shortgi = true; 2122 else if (macid == 1) 2123 shortgi = false; 2124 } 2125 break; 2126 default: 2127 ratr_index = RATR_INX_WIRELESS_NGB; 2128 2129 if (rtlphy->rf_type == RF_1T2R) 2130 ratr_bitmap &= 0x000ff0ff; 2131 else 2132 ratr_bitmap &= 0x0f0ff0ff; 2133 break; 2134 } 2135 sta_entry->ratr_index = ratr_index; 2136 2137 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2138 "ratr_bitmap :%x\n", ratr_bitmap); 2139 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 2140 (ratr_index << 28); 2141 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; 2142 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2143 "Rate_index:%x, ratr_val:%x, %5phC\n", 2144 ratr_index, ratr_bitmap, rate_mask); 2145 memcpy(rtlpriv->rate_mask, rate_mask, 5); 2146 /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a 2147 * "scheduled while atomic" if called directly */ 2148 schedule_work(&rtlpriv->works.fill_h2c_cmd); 2149 2150 if (macid != 0) 2151 sta_entry->ratr_index = ratr_index; 2152 } 2153 2154 void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw, 2155 struct ieee80211_sta *sta, 2156 u8 rssi_level, bool update_bw) 2157 { 2158 struct rtl_priv *rtlpriv = rtl_priv(hw); 2159 2160 if (rtlpriv->dm.useramask) 2161 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level, update_bw); 2162 else 2163 rtl92cu_update_hal_rate_table(hw, sta); 2164 } 2165 2166 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw) 2167 { 2168 struct rtl_priv *rtlpriv = rtl_priv(hw); 2169 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2170 u16 sifs_timer; 2171 2172 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2173 &mac->slot_time); 2174 if (!mac->ht_enable) 2175 sifs_timer = 0x0a0a; 2176 else 2177 sifs_timer = 0x0e0e; 2178 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2179 } 2180 2181 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid) 2182 { 2183 struct rtl_priv *rtlpriv = rtl_priv(hw); 2184 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2185 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate; 2186 u8 u1tmp = 0; 2187 bool actuallyset = false; 2188 unsigned long flag = 0; 2189 /* to do - usb autosuspend */ 2190 u8 usb_autosuspend = 0; 2191 2192 if (ppsc->swrf_processing) 2193 return false; 2194 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2195 if (ppsc->rfchange_inprogress) { 2196 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2197 return false; 2198 } else { 2199 ppsc->rfchange_inprogress = true; 2200 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2201 } 2202 cur_rfstate = ppsc->rfpwr_state; 2203 if (usb_autosuspend) { 2204 /* to do................... */ 2205 } else { 2206 if (ppsc->pwrdown_mode) { 2207 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR); 2208 e_rfpowerstate_toset = (u1tmp & BIT(7)) ? 2209 ERFOFF : ERFON; 2210 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 2211 "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp); 2212 } else { 2213 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, 2214 rtl_read_byte(rtlpriv, 2215 REG_MAC_PINMUX_CFG) & ~(BIT(3))); 2216 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); 2217 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? 2218 ERFON : ERFOFF; 2219 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 2220 "GPIO_IN=%02x\n", u1tmp); 2221 } 2222 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n", 2223 e_rfpowerstate_toset); 2224 } 2225 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { 2226 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2227 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2228 ppsc->hwradiooff = false; 2229 actuallyset = true; 2230 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset == 2231 ERFOFF)) { 2232 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2233 "GPIOChangeRF - HW Radio OFF\n"); 2234 ppsc->hwradiooff = true; 2235 actuallyset = true; 2236 } else { 2237 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2238 "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n", 2239 ppsc->hwradiooff, e_rfpowerstate_toset); 2240 } 2241 if (actuallyset) { 2242 ppsc->hwradiooff = true; 2243 if (e_rfpowerstate_toset == ERFON) { 2244 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) && 2245 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM)) 2246 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2247 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2248 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3)) 2249 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2250 } 2251 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2252 ppsc->rfchange_inprogress = false; 2253 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2254 /* For power down module, we need to enable register block 2255 * contrl reg at 0x1c. Then enable power down control bit 2256 * of register 0x04 BIT4 and BIT15 as 1. 2257 */ 2258 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) { 2259 /* Enable register area 0x0-0xc. */ 2260 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); 2261 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812); 2262 } 2263 if (e_rfpowerstate_toset == ERFOFF) { 2264 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) 2265 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2266 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2267 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2268 } 2269 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) { 2270 /* Enter D3 or ASPM after GPIO had been done. */ 2271 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) 2272 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2273 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2274 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2275 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2276 ppsc->rfchange_inprogress = false; 2277 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2278 } else { 2279 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2280 ppsc->rfchange_inprogress = false; 2281 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2282 } 2283 *valid = 1; 2284 return !ppsc->hwradiooff; 2285 } 2286