1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../cam.h" 30 #include "../ps.h" 31 #include "../usb.h" 32 #include "reg.h" 33 #include "def.h" 34 #include "phy.h" 35 #include "../rtl8192c/phy_common.h" 36 #include "mac.h" 37 #include "dm.h" 38 #include "../rtl8192c/dm_common.h" 39 #include "../rtl8192c/fw_common.h" 40 #include "hw.h" 41 #include "../rtl8192ce/hw.h" 42 #include "trx.h" 43 #include "led.h" 44 #include "table.h" 45 46 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw) 47 { 48 struct rtl_priv *rtlpriv = rtl_priv(hw); 49 struct rtl_phy *rtlphy = &(rtlpriv->phy); 50 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); 51 52 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH; 53 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY; 54 if (IS_HIGHT_PA(rtlefuse->board_type)) { 55 rtlphy->hwparam_tables[PHY_REG_PG].length = 56 RTL8192CUPHY_REG_Array_PG_HPLength; 57 rtlphy->hwparam_tables[PHY_REG_PG].pdata = 58 RTL8192CUPHY_REG_Array_PG_HP; 59 } else { 60 rtlphy->hwparam_tables[PHY_REG_PG].length = 61 RTL8192CUPHY_REG_ARRAY_PGLENGTH; 62 rtlphy->hwparam_tables[PHY_REG_PG].pdata = 63 RTL8192CUPHY_REG_ARRAY_PG; 64 } 65 /* 2T */ 66 rtlphy->hwparam_tables[PHY_REG_2T].length = 67 RTL8192CUPHY_REG_2TARRAY_LENGTH; 68 rtlphy->hwparam_tables[PHY_REG_2T].pdata = 69 RTL8192CUPHY_REG_2TARRAY; 70 rtlphy->hwparam_tables[RADIOA_2T].length = 71 RTL8192CURADIOA_2TARRAYLENGTH; 72 rtlphy->hwparam_tables[RADIOA_2T].pdata = 73 RTL8192CURADIOA_2TARRAY; 74 rtlphy->hwparam_tables[RADIOB_2T].length = 75 RTL8192CURADIOB_2TARRAYLENGTH; 76 rtlphy->hwparam_tables[RADIOB_2T].pdata = 77 RTL8192CU_RADIOB_2TARRAY; 78 rtlphy->hwparam_tables[AGCTAB_2T].length = 79 RTL8192CUAGCTAB_2TARRAYLENGTH; 80 rtlphy->hwparam_tables[AGCTAB_2T].pdata = 81 RTL8192CUAGCTAB_2TARRAY; 82 /* 1T */ 83 if (IS_HIGHT_PA(rtlefuse->board_type)) { 84 rtlphy->hwparam_tables[PHY_REG_1T].length = 85 RTL8192CUPHY_REG_1T_HPArrayLength; 86 rtlphy->hwparam_tables[PHY_REG_1T].pdata = 87 RTL8192CUPHY_REG_1T_HPArray; 88 rtlphy->hwparam_tables[RADIOA_1T].length = 89 RTL8192CURadioA_1T_HPArrayLength; 90 rtlphy->hwparam_tables[RADIOA_1T].pdata = 91 RTL8192CURadioA_1T_HPArray; 92 rtlphy->hwparam_tables[RADIOB_1T].length = 93 RTL8192CURADIOB_1TARRAYLENGTH; 94 rtlphy->hwparam_tables[RADIOB_1T].pdata = 95 RTL8192CU_RADIOB_1TARRAY; 96 rtlphy->hwparam_tables[AGCTAB_1T].length = 97 RTL8192CUAGCTAB_1T_HPArrayLength; 98 rtlphy->hwparam_tables[AGCTAB_1T].pdata = 99 Rtl8192CUAGCTAB_1T_HPArray; 100 } else { 101 rtlphy->hwparam_tables[PHY_REG_1T].length = 102 RTL8192CUPHY_REG_1TARRAY_LENGTH; 103 rtlphy->hwparam_tables[PHY_REG_1T].pdata = 104 RTL8192CUPHY_REG_1TARRAY; 105 rtlphy->hwparam_tables[RADIOA_1T].length = 106 RTL8192CURADIOA_1TARRAYLENGTH; 107 rtlphy->hwparam_tables[RADIOA_1T].pdata = 108 RTL8192CU_RADIOA_1TARRAY; 109 rtlphy->hwparam_tables[RADIOB_1T].length = 110 RTL8192CURADIOB_1TARRAYLENGTH; 111 rtlphy->hwparam_tables[RADIOB_1T].pdata = 112 RTL8192CU_RADIOB_1TARRAY; 113 rtlphy->hwparam_tables[AGCTAB_1T].length = 114 RTL8192CUAGCTAB_1TARRAYLENGTH; 115 rtlphy->hwparam_tables[AGCTAB_1T].pdata = 116 RTL8192CUAGCTAB_1TARRAY; 117 } 118 } 119 120 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 121 bool autoload_fail, 122 u8 *hwinfo) 123 { 124 struct rtl_priv *rtlpriv = rtl_priv(hw); 125 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 126 u8 rf_path, index, tempval; 127 u16 i; 128 129 for (rf_path = 0; rf_path < 2; rf_path++) { 130 for (i = 0; i < 3; i++) { 131 if (!autoload_fail) { 132 rtlefuse-> 133 eeprom_chnlarea_txpwr_cck[rf_path][i] = 134 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; 135 rtlefuse-> 136 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 137 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + 138 i]; 139 } else { 140 rtlefuse-> 141 eeprom_chnlarea_txpwr_cck[rf_path][i] = 142 EEPROM_DEFAULT_TXPOWERLEVEL; 143 rtlefuse-> 144 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 145 EEPROM_DEFAULT_TXPOWERLEVEL; 146 } 147 } 148 } 149 for (i = 0; i < 3; i++) { 150 if (!autoload_fail) 151 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i]; 152 else 153 tempval = EEPROM_DEFAULT_HT40_2SDIFF; 154 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] = 155 (tempval & 0xf); 156 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] = 157 ((tempval & 0xf0) >> 4); 158 } 159 for (rf_path = 0; rf_path < 2; rf_path++) 160 for (i = 0; i < 3; i++) 161 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 162 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", 163 rf_path, i, 164 rtlefuse-> 165 eeprom_chnlarea_txpwr_cck[rf_path][i]); 166 for (rf_path = 0; rf_path < 2; rf_path++) 167 for (i = 0; i < 3; i++) 168 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 169 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 170 rf_path, i, 171 rtlefuse-> 172 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]); 173 for (rf_path = 0; rf_path < 2; rf_path++) 174 for (i = 0; i < 3; i++) 175 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 176 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 177 rf_path, i, 178 rtlefuse-> 179 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]); 180 for (rf_path = 0; rf_path < 2; rf_path++) { 181 for (i = 0; i < 14; i++) { 182 index = rtl92c_get_chnl_group((u8)i); 183 rtlefuse->txpwrlevel_cck[rf_path][i] = 184 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index]; 185 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 186 rtlefuse-> 187 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index]; 188 if ((rtlefuse-> 189 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] - 190 rtlefuse-> 191 eprom_chnl_txpwr_ht40_2sdf[rf_path][index]) 192 > 0) { 193 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 194 rtlefuse-> 195 eeprom_chnlarea_txpwr_ht40_1s[rf_path] 196 [index] - rtlefuse-> 197 eprom_chnl_txpwr_ht40_2sdf[rf_path] 198 [index]; 199 } else { 200 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; 201 } 202 } 203 for (i = 0; i < 14; i++) { 204 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 205 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i, 206 rtlefuse->txpwrlevel_cck[rf_path][i], 207 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 208 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 209 } 210 } 211 for (i = 0; i < 3; i++) { 212 if (!autoload_fail) { 213 rtlefuse->eeprom_pwrlimit_ht40[i] = 214 hwinfo[EEPROM_TXPWR_GROUP + i]; 215 rtlefuse->eeprom_pwrlimit_ht20[i] = 216 hwinfo[EEPROM_TXPWR_GROUP + 3 + i]; 217 } else { 218 rtlefuse->eeprom_pwrlimit_ht40[i] = 0; 219 rtlefuse->eeprom_pwrlimit_ht20[i] = 0; 220 } 221 } 222 for (rf_path = 0; rf_path < 2; rf_path++) { 223 for (i = 0; i < 14; i++) { 224 index = rtl92c_get_chnl_group((u8)i); 225 if (rf_path == RF90_PATH_A) { 226 rtlefuse->pwrgroup_ht20[rf_path][i] = 227 (rtlefuse->eeprom_pwrlimit_ht20[index] 228 & 0xf); 229 rtlefuse->pwrgroup_ht40[rf_path][i] = 230 (rtlefuse->eeprom_pwrlimit_ht40[index] 231 & 0xf); 232 } else if (rf_path == RF90_PATH_B) { 233 rtlefuse->pwrgroup_ht20[rf_path][i] = 234 ((rtlefuse->eeprom_pwrlimit_ht20[index] 235 & 0xf0) >> 4); 236 rtlefuse->pwrgroup_ht40[rf_path][i] = 237 ((rtlefuse->eeprom_pwrlimit_ht40[index] 238 & 0xf0) >> 4); 239 } 240 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 241 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", 242 rf_path, i, 243 rtlefuse->pwrgroup_ht20[rf_path][i]); 244 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 245 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", 246 rf_path, i, 247 rtlefuse->pwrgroup_ht40[rf_path][i]); 248 } 249 } 250 for (i = 0; i < 14; i++) { 251 index = rtl92c_get_chnl_group((u8)i); 252 if (!autoload_fail) 253 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; 254 else 255 tempval = EEPROM_DEFAULT_HT20_DIFF; 256 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 257 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 258 ((tempval >> 4) & 0xF); 259 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) 260 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; 261 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) 262 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; 263 index = rtl92c_get_chnl_group((u8)i); 264 if (!autoload_fail) 265 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; 266 else 267 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 268 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); 269 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 270 ((tempval >> 4) & 0xF); 271 } 272 rtlefuse->legacy_ht_txpowerdiff = 273 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; 274 for (i = 0; i < 14; i++) 275 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 276 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", 277 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 278 for (i = 0; i < 14; i++) 279 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 280 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", 281 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 282 for (i = 0; i < 14; i++) 283 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 284 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", 285 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 286 for (i = 0; i < 14; i++) 287 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 288 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", 289 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 290 if (!autoload_fail) 291 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); 292 else 293 rtlefuse->eeprom_regulatory = 0; 294 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 295 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 296 if (!autoload_fail) { 297 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; 298 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B]; 299 } else { 300 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; 301 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI; 302 } 303 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 304 "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 305 rtlefuse->eeprom_tssi[RF90_PATH_A], 306 rtlefuse->eeprom_tssi[RF90_PATH_B]); 307 if (!autoload_fail) 308 tempval = hwinfo[EEPROM_THERMAL_METER]; 309 else 310 tempval = EEPROM_DEFAULT_THERMALMETER; 311 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); 312 if (rtlefuse->eeprom_thermalmeter < 0x06 || 313 rtlefuse->eeprom_thermalmeter > 0x1c) 314 rtlefuse->eeprom_thermalmeter = 0x12; 315 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) 316 rtlefuse->apk_thermalmeterignore = true; 317 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 318 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 319 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 320 } 321 322 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents) 323 { 324 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 325 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 326 u8 boardType; 327 328 if (IS_NORMAL_CHIP(rtlhal->version)) { 329 boardType = ((contents[EEPROM_RF_OPT1]) & 330 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/ 331 } else { 332 boardType = contents[EEPROM_RF_OPT4]; 333 boardType &= BOARD_TYPE_TEST_MASK; 334 } 335 rtlefuse->board_type = boardType; 336 if (IS_HIGHT_PA(rtlefuse->board_type)) 337 rtlefuse->external_pa = 1; 338 pr_info("Board Type %x\n", rtlefuse->board_type); 339 } 340 341 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw) 342 { 343 struct rtl_priv *rtlpriv = rtl_priv(hw); 344 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 345 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 346 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, 347 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 348 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 349 0}; 350 u8 *hwinfo; 351 352 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 353 if (!hwinfo) 354 return; 355 356 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 357 goto exit; 358 359 _rtl92cu_read_txpower_info_from_hwpg(hw, 360 rtlefuse->autoload_failflag, hwinfo); 361 _rtl92cu_read_board_type(hw, hwinfo); 362 363 rtlefuse->txpwr_fromeprom = true; 364 if (rtlhal->oem_id == RT_CID_DEFAULT) { 365 switch (rtlefuse->eeprom_oemid) { 366 case EEPROM_CID_DEFAULT: 367 if (rtlefuse->eeprom_did == 0x8176) { 368 if ((rtlefuse->eeprom_svid == 0x103C && 369 rtlefuse->eeprom_smid == 0x1629)) 370 rtlhal->oem_id = RT_CID_819X_HP; 371 else 372 rtlhal->oem_id = RT_CID_DEFAULT; 373 } else { 374 rtlhal->oem_id = RT_CID_DEFAULT; 375 } 376 break; 377 case EEPROM_CID_TOSHIBA: 378 rtlhal->oem_id = RT_CID_TOSHIBA; 379 break; 380 case EEPROM_CID_QMI: 381 rtlhal->oem_id = RT_CID_819X_QMI; 382 break; 383 case EEPROM_CID_WHQL: 384 default: 385 rtlhal->oem_id = RT_CID_DEFAULT; 386 break; 387 } 388 } 389 exit: 390 kfree(hwinfo); 391 } 392 393 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw) 394 { 395 struct rtl_priv *rtlpriv = rtl_priv(hw); 396 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 397 398 switch (rtlhal->oem_id) { 399 case RT_CID_819X_HP: 400 rtlpriv->ledctl.led_opendrain = true; 401 break; 402 case RT_CID_819X_LENOVO: 403 case RT_CID_DEFAULT: 404 case RT_CID_TOSHIBA: 405 case RT_CID_CCX: 406 case RT_CID_819X_ACER: 407 case RT_CID_WHQL: 408 default: 409 break; 410 } 411 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n", 412 rtlhal->oem_id); 413 } 414 415 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw) 416 { 417 418 struct rtl_priv *rtlpriv = rtl_priv(hw); 419 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 420 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 421 u8 tmp_u1b; 422 423 if (!IS_NORMAL_CHIP(rtlhal->version)) 424 return; 425 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 426 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ? 427 EEPROM_93C46 : EEPROM_BOOT_EFUSE; 428 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n", 429 tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE"); 430 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true; 431 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n", 432 tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!"); 433 _rtl92cu_read_adapter_info(hw); 434 _rtl92cu_hal_customized_behavior(hw); 435 return; 436 } 437 438 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw) 439 { 440 struct rtl_priv *rtlpriv = rtl_priv(hw); 441 int status = 0; 442 u16 value16; 443 u8 value8; 444 /* polling autoload done. */ 445 u32 pollingCount = 0; 446 447 do { 448 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) { 449 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 450 "Autoload Done!\n"); 451 break; 452 } 453 if (pollingCount++ > 100) { 454 pr_err("Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n"); 455 return -ENODEV; 456 } 457 } while (true); 458 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */ 459 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); 460 /* Power on when re-enter from IPS/Radio off/card disable */ 461 /* enable SPS into PWM mode */ 462 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 463 udelay(100); 464 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL); 465 if (0 == (value8 & LDV12_EN)) { 466 value8 |= LDV12_EN; 467 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8); 468 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 469 " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n", 470 value8); 471 udelay(100); 472 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL); 473 value8 &= ~ISO_MD2PP; 474 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8); 475 } 476 /* auto enable WLAN */ 477 pollingCount = 0; 478 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO); 479 value16 |= APFM_ONMAC; 480 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16); 481 do { 482 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) { 483 pr_info("MAC auto ON okay!\n"); 484 break; 485 } 486 if (pollingCount++ > 1000) { 487 pr_err("Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n"); 488 return -ENODEV; 489 } 490 } while (true); 491 /* Enable Radio ,GPIO ,and LED function */ 492 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812); 493 /* release RF digital isolation */ 494 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); 495 value16 &= ~ISO_DIOR; 496 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16); 497 /* Reconsider when to do this operation after asking HWSD. */ 498 pollingCount = 0; 499 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv, 500 REG_APSD_CTRL) & ~BIT(6))); 501 do { 502 pollingCount++; 503 } while ((pollingCount < 200) && 504 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7))); 505 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ 506 value16 = rtl_read_word(rtlpriv, REG_CR); 507 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN | 508 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC); 509 rtl_write_word(rtlpriv, REG_CR, value16); 510 return status; 511 } 512 513 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw, 514 bool wmm_enable, 515 u8 out_ep_num, 516 u8 queue_sel) 517 { 518 struct rtl_priv *rtlpriv = rtl_priv(hw); 519 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 520 bool isChipN = IS_NORMAL_CHIP(rtlhal->version); 521 u32 outEPNum = (u32)out_ep_num; 522 u32 numHQ = 0; 523 u32 numLQ = 0; 524 u32 numNQ = 0; 525 u32 numPubQ; 526 u32 value32; 527 u8 value8; 528 u32 txQPageNum, txQPageUnit, txQRemainPage; 529 530 if (!wmm_enable) { 531 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ : 532 CHIP_A_PAGE_NUM_PUBQ; 533 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ; 534 535 txQPageUnit = txQPageNum/outEPNum; 536 txQRemainPage = txQPageNum % outEPNum; 537 if (queue_sel & TX_SELE_HQ) 538 numHQ = txQPageUnit; 539 if (queue_sel & TX_SELE_LQ) 540 numLQ = txQPageUnit; 541 /* HIGH priority queue always present in the configuration of 542 * 2 out-ep. Remainder pages have assigned to High queue */ 543 if ((outEPNum > 1) && (txQRemainPage)) 544 numHQ += txQRemainPage; 545 /* NOTE: This step done before writting REG_RQPN. */ 546 if (isChipN) { 547 if (queue_sel & TX_SELE_NQ) 548 numNQ = txQPageUnit; 549 value8 = (u8)_NPQ(numNQ); 550 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); 551 } 552 } else { 553 /* for WMM ,number of out-ep must more than or equal to 2! */ 554 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ : 555 WMM_CHIP_A_PAGE_NUM_PUBQ; 556 if (queue_sel & TX_SELE_HQ) { 557 numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ : 558 WMM_CHIP_A_PAGE_NUM_HPQ; 559 } 560 if (queue_sel & TX_SELE_LQ) { 561 numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ : 562 WMM_CHIP_A_PAGE_NUM_LPQ; 563 } 564 /* NOTE: This step done before writting REG_RQPN. */ 565 if (isChipN) { 566 if (queue_sel & TX_SELE_NQ) 567 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ; 568 value8 = (u8)_NPQ(numNQ); 569 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8); 570 } 571 } 572 /* TX DMA */ 573 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN; 574 rtl_write_dword(rtlpriv, REG_RQPN, value32); 575 } 576 577 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable) 578 { 579 struct rtl_priv *rtlpriv = rtl_priv(hw); 580 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 581 u8 txpktbuf_bndy; 582 u8 value8; 583 584 if (!wmm_enable) 585 txpktbuf_bndy = TX_PAGE_BOUNDARY; 586 else /* for WMM */ 587 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version)) 588 ? WMM_CHIP_B_TX_PAGE_BOUNDARY 589 : WMM_CHIP_A_TX_PAGE_BOUNDARY; 590 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 591 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 592 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy); 593 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy); 594 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy); 595 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); 596 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128); 597 rtl_write_byte(rtlpriv, REG_PBP, value8); 598 } 599 600 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ, 601 u16 bkQ, u16 viQ, u16 voQ, 602 u16 mgtQ, u16 hiQ) 603 { 604 struct rtl_priv *rtlpriv = rtl_priv(hw); 605 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7); 606 607 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) | 608 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) | 609 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ); 610 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16); 611 } 612 613 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw, 614 bool wmm_enable, 615 u8 queue_sel) 616 { 617 u16 uninitialized_var(value); 618 619 switch (queue_sel) { 620 case TX_SELE_HQ: 621 value = QUEUE_HIGH; 622 break; 623 case TX_SELE_LQ: 624 value = QUEUE_LOW; 625 break; 626 case TX_SELE_NQ: 627 value = QUEUE_NORMAL; 628 break; 629 default: 630 WARN_ON(1); /* Shall not reach here! */ 631 break; 632 } 633 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value, 634 value, value); 635 pr_info("Tx queue select: 0x%02x\n", queue_sel); 636 } 637 638 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw, 639 bool wmm_enable, 640 u8 queue_sel) 641 { 642 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; 643 u16 uninitialized_var(valueHi); 644 u16 uninitialized_var(valueLow); 645 646 switch (queue_sel) { 647 case (TX_SELE_HQ | TX_SELE_LQ): 648 valueHi = QUEUE_HIGH; 649 valueLow = QUEUE_LOW; 650 break; 651 case (TX_SELE_NQ | TX_SELE_LQ): 652 valueHi = QUEUE_NORMAL; 653 valueLow = QUEUE_LOW; 654 break; 655 case (TX_SELE_HQ | TX_SELE_NQ): 656 valueHi = QUEUE_HIGH; 657 valueLow = QUEUE_NORMAL; 658 break; 659 default: 660 WARN_ON(1); 661 break; 662 } 663 if (!wmm_enable) { 664 beQ = valueLow; 665 bkQ = valueLow; 666 viQ = valueHi; 667 voQ = valueHi; 668 mgtQ = valueHi; 669 hiQ = valueHi; 670 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */ 671 beQ = valueHi; 672 bkQ = valueLow; 673 viQ = valueLow; 674 voQ = valueHi; 675 mgtQ = valueHi; 676 hiQ = valueHi; 677 } 678 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ); 679 pr_info("Tx queue select: 0x%02x\n", queue_sel); 680 } 681 682 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw, 683 bool wmm_enable, 684 u8 queue_sel) 685 { 686 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; 687 688 if (!wmm_enable) { /* typical setting */ 689 beQ = QUEUE_LOW; 690 bkQ = QUEUE_LOW; 691 viQ = QUEUE_NORMAL; 692 voQ = QUEUE_HIGH; 693 mgtQ = QUEUE_HIGH; 694 hiQ = QUEUE_HIGH; 695 } else { /* for WMM */ 696 beQ = QUEUE_LOW; 697 bkQ = QUEUE_NORMAL; 698 viQ = QUEUE_NORMAL; 699 voQ = QUEUE_HIGH; 700 mgtQ = QUEUE_HIGH; 701 hiQ = QUEUE_HIGH; 702 } 703 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ); 704 pr_info("Tx queue select :0x%02x..\n", queue_sel); 705 } 706 707 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw, 708 bool wmm_enable, 709 u8 out_ep_num, 710 u8 queue_sel) 711 { 712 switch (out_ep_num) { 713 case 1: 714 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable, 715 queue_sel); 716 break; 717 case 2: 718 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable, 719 queue_sel); 720 break; 721 case 3: 722 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable, 723 queue_sel); 724 break; 725 default: 726 WARN_ON(1); /* Shall not reach here! */ 727 break; 728 } 729 } 730 731 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw, 732 bool wmm_enable, 733 u8 out_ep_num, 734 u8 queue_sel) 735 { 736 u8 hq_sele = 0; 737 struct rtl_priv *rtlpriv = rtl_priv(hw); 738 739 switch (out_ep_num) { 740 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */ 741 if (!wmm_enable) /* typical setting */ 742 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ | 743 HQSEL_HIQ; 744 else /* for WMM */ 745 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ | 746 HQSEL_HIQ; 747 break; 748 case 1: 749 if (TX_SELE_LQ == queue_sel) { 750 /* map all endpoint to Low queue */ 751 hq_sele = 0; 752 } else if (TX_SELE_HQ == queue_sel) { 753 /* map all endpoint to High queue */ 754 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ | 755 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ; 756 } 757 break; 758 default: 759 WARN_ON(1); /* Shall not reach here! */ 760 break; 761 } 762 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele); 763 pr_info("Tx queue select :0x%02x..\n", hq_sele); 764 } 765 766 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw, 767 bool wmm_enable, 768 u8 out_ep_num, 769 u8 queue_sel) 770 { 771 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 772 if (IS_NORMAL_CHIP(rtlhal->version)) 773 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num, 774 queue_sel); 775 else 776 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num, 777 queue_sel); 778 } 779 780 static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw) 781 { 782 } 783 784 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw) 785 { 786 u16 value16; 787 u32 value32; 788 struct rtl_priv *rtlpriv = rtl_priv(hw); 789 790 value32 = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS | 791 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | 792 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32); 793 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&value32)); 794 /* Accept all multicast address */ 795 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF); 796 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF); 797 /* Accept all management frames */ 798 value16 = 0xFFFF; 799 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MGT_FILTER, 800 (u8 *)(&value16)); 801 /* Reject all control frame - default value is 0 */ 802 value16 = 0x0; 803 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_CTRL_FILTER, 804 (u8 *)(&value16)); 805 /* Accept all data frames */ 806 value16 = 0xFFFF; 807 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_DATA_FILTER, 808 (u8 *)(&value16)); 809 } 810 811 static void _rtl92cu_init_beacon_parameters(struct ieee80211_hw *hw) 812 { 813 struct rtl_priv *rtlpriv = rtl_priv(hw); 814 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 815 816 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010); 817 818 /* TODO: Remove these magic number */ 819 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404); 820 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME); 821 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); 822 /* Change beacon AIFS to the largest number 823 * beacause test chip does not contension before sending beacon. 824 */ 825 if (IS_NORMAL_CHIP(rtlhal->version)) 826 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F); 827 else 828 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF); 829 } 830 831 static int _rtl92cu_init_mac(struct ieee80211_hw *hw) 832 { 833 struct rtl_priv *rtlpriv = rtl_priv(hw); 834 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 835 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw); 836 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv); 837 int err = 0; 838 u32 boundary = 0; 839 u8 wmm_enable = false; /* TODO */ 840 u8 out_ep_nums = rtlusb->out_ep_nums; 841 u8 queue_sel = rtlusb->out_queue_sel; 842 err = _rtl92cu_init_power_on(hw); 843 844 if (err) { 845 pr_err("Failed to init power on!\n"); 846 return err; 847 } 848 if (!wmm_enable) { 849 boundary = TX_PAGE_BOUNDARY; 850 } else { /* for WMM */ 851 boundary = (IS_NORMAL_CHIP(rtlhal->version)) 852 ? WMM_CHIP_B_TX_PAGE_BOUNDARY 853 : WMM_CHIP_A_TX_PAGE_BOUNDARY; 854 } 855 if (false == rtl92c_init_llt_table(hw, boundary)) { 856 pr_err("Failed to init LLT Table!\n"); 857 return -EINVAL; 858 } 859 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums, 860 queue_sel); 861 _rtl92c_init_trx_buffer(hw, wmm_enable); 862 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums, 863 queue_sel); 864 /* Get Rx PHY status in order to report RSSI and others. */ 865 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE); 866 rtl92c_init_interrupt(hw); 867 rtl92c_init_network_type(hw); 868 _rtl92cu_init_wmac_setting(hw); 869 rtl92c_init_adaptive_ctrl(hw); 870 rtl92c_init_edca(hw); 871 rtl92c_init_rate_fallback(hw); 872 rtl92c_init_retry_function(hw); 873 _rtl92cu_init_usb_aggregation(hw); 874 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20); 875 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version)); 876 _rtl92cu_init_beacon_parameters(hw); 877 rtl92c_init_ampdu_aggregation(hw); 878 rtl92c_init_beacon_max_error(hw); 879 return err; 880 } 881 882 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw) 883 { 884 struct rtl_priv *rtlpriv = rtl_priv(hw); 885 u8 sec_reg_value = 0x0; 886 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 887 888 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 889 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 890 rtlpriv->sec.pairwise_enc_algorithm, 891 rtlpriv->sec.group_enc_algorithm); 892 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 893 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 894 "not open sw encryption\n"); 895 return; 896 } 897 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable; 898 if (rtlpriv->sec.use_defaultkey) { 899 sec_reg_value |= SCR_TxUseDK; 900 sec_reg_value |= SCR_RxUseDK; 901 } 902 if (IS_NORMAL_CHIP(rtlhal->version)) 903 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 904 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 905 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n", 906 sec_reg_value); 907 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 908 } 909 910 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw) 911 { 912 struct rtl_priv *rtlpriv = rtl_priv(hw); 913 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 914 915 /* To Fix MAC loopback mode fail. */ 916 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f); 917 rtl_write_byte(rtlpriv, 0x15, 0xe9); 918 /* HW SEQ CTRL */ 919 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */ 920 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 921 /* fixed USB interface interference issue */ 922 rtl_write_byte(rtlpriv, 0xfe40, 0xe0); 923 rtl_write_byte(rtlpriv, 0xfe41, 0x8d); 924 rtl_write_byte(rtlpriv, 0xfe42, 0x80); 925 rtlusb->reg_bcn_ctrl_val = 0x18; 926 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val); 927 } 928 929 static void _InitPABias(struct ieee80211_hw *hw) 930 { 931 struct rtl_priv *rtlpriv = rtl_priv(hw); 932 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 933 u8 pa_setting; 934 935 /* FIXED PA current issue */ 936 pa_setting = efuse_read_1byte(hw, 0x1FA); 937 if (!(pa_setting & BIT(0))) { 938 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406); 939 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406); 940 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406); 941 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406); 942 } 943 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) && 944 IS_92C_SERIAL(rtlhal->version)) { 945 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406); 946 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406); 947 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406); 948 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406); 949 } 950 if (!(pa_setting & BIT(4))) { 951 pa_setting = rtl_read_byte(rtlpriv, 0x16); 952 pa_setting &= 0x0F; 953 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90); 954 } 955 } 956 957 int rtl92cu_hw_init(struct ieee80211_hw *hw) 958 { 959 struct rtl_priv *rtlpriv = rtl_priv(hw); 960 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 961 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 962 struct rtl_phy *rtlphy = &(rtlpriv->phy); 963 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 964 int err = 0; 965 unsigned long flags; 966 967 /* As this function can take a very long time (up to 350 ms) 968 * and can be called with irqs disabled, reenable the irqs 969 * to let the other devices continue being serviced. 970 * 971 * It is safe doing so since our own interrupts will only be enabled 972 * in a subsequent step. 973 */ 974 local_save_flags(flags); 975 local_irq_enable(); 976 977 rtlhal->fw_ready = false; 978 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU; 979 err = _rtl92cu_init_mac(hw); 980 if (err) { 981 pr_err("init mac failed!\n"); 982 goto exit; 983 } 984 err = rtl92c_download_fw(hw); 985 if (err) { 986 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 987 "Failed to download FW. Init HW without FW now..\n"); 988 err = 1; 989 goto exit; 990 } 991 992 rtlhal->fw_ready = true; 993 rtlhal->last_hmeboxnum = 0; /* h2c */ 994 _rtl92cu_phy_param_tab_init(hw); 995 rtl92cu_phy_mac_config(hw); 996 rtl92cu_phy_bb_config(hw); 997 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 998 rtl92c_phy_rf_config(hw); 999 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) && 1000 !IS_92C_SERIAL(rtlhal->version)) { 1001 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); 1002 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); 1003 } 1004 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 1005 RF_CHNLBW, RFREG_OFFSET_MASK); 1006 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 1007 RF_CHNLBW, RFREG_OFFSET_MASK); 1008 rtl92cu_bb_block_on(hw); 1009 rtl_cam_reset_all_entry(hw); 1010 rtl92cu_enable_hw_security_config(hw); 1011 ppsc->rfpwr_state = ERFON; 1012 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1013 if (ppsc->rfpwr_state == ERFON) { 1014 rtl92c_phy_set_rfpath_switch(hw, 1); 1015 if (rtlphy->iqk_initialized) { 1016 rtl92c_phy_iq_calibrate(hw, true); 1017 } else { 1018 rtl92c_phy_iq_calibrate(hw, false); 1019 rtlphy->iqk_initialized = true; 1020 } 1021 rtl92c_dm_check_txpower_tracking(hw); 1022 rtl92c_phy_lc_calibrate(hw); 1023 } 1024 _rtl92cu_hw_configure(hw); 1025 _InitPABias(hw); 1026 rtl92c_dm_init(hw); 1027 exit: 1028 local_irq_restore(flags); 1029 return err; 1030 } 1031 1032 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw) 1033 { 1034 struct rtl_priv *rtlpriv = rtl_priv(hw); 1035 /************************************** 1036 a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue 1037 b. RF path 0 offset 0x00 = 0x00 disable RF 1038 c. APSD_CTRL 0x600[7:0] = 0x40 1039 d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine 1040 e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine 1041 ***************************************/ 1042 u8 eRFPath = 0, value8 = 0; 1043 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1044 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0); 1045 1046 value8 |= APSDOFF; 1047 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/ 1048 value8 = 0; 1049 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn); 1050 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/ 1051 value8 &= (~FEN_BB_GLB_RSTn); 1052 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/ 1053 } 1054 1055 static void _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM) 1056 { 1057 struct rtl_priv *rtlpriv = rtl_priv(hw); 1058 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1059 1060 if (rtlhal->fw_version <= 0x20) { 1061 /***************************** 1062 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status 1063 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset) 1064 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE 1065 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable) 1066 ******************************/ 1067 u16 valu16 = 0; 1068 1069 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1070 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1071 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 & 1072 (~FEN_CPUEN))); /* reset MCU ,8051 */ 1073 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF; 1074 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 | 1075 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */ 1076 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 1077 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 | 1078 FEN_CPUEN)); /* enable MCU ,8051 */ 1079 } else { 1080 u8 retry_cnts = 0; 1081 1082 /* IF fw in RAM code, do reset */ 1083 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) { 1084 /* reset MCU ready status */ 1085 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1086 /* 8051 reset by self */ 1087 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20); 1088 while ((retry_cnts++ < 100) && 1089 (FEN_CPUEN & rtl_read_word(rtlpriv, 1090 REG_SYS_FUNC_EN))) { 1091 udelay(50); 1092 } 1093 if (retry_cnts >= 100) { 1094 pr_err("8051 reset failed!.........................\n"); 1095 /* if 8051 reset fail, reset MAC. */ 1096 rtl_write_byte(rtlpriv, 1097 REG_SYS_FUNC_EN + 1, 1098 0x50); 1099 udelay(100); 1100 } 1101 } 1102 /* Reset MAC and Enable 8051 */ 1103 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54); 1104 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); 1105 } 1106 if (bWithoutHWSM) { 1107 /***************************** 1108 Without HW auto state machine 1109 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock 1110 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL 1111 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK 1112 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON 1113 ******************************/ 1114 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3); 1115 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); 1116 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F); 1117 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9); 1118 } 1119 } 1120 1121 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw) 1122 { 1123 struct rtl_priv *rtlpriv = rtl_priv(hw); 1124 /***************************** 1125 k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction 1126 l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock 1127 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON 1128 ******************************/ 1129 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3); 1130 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82); 1131 } 1132 1133 static void _DisableGPIO(struct ieee80211_hw *hw) 1134 { 1135 struct rtl_priv *rtlpriv = rtl_priv(hw); 1136 /*************************************** 1137 j. GPIO_PIN_CTRL 0x44[31:0]=0x000 1138 k. Value = GPIO_PIN_CTRL[7:0] 1139 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level 1140 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780 1141 n. LEDCFG 0x4C[15:0] = 0x8080 1142 ***************************************/ 1143 u8 value8; 1144 u16 value16; 1145 u32 value32; 1146 1147 /* 1. Disable GPIO[7:0] */ 1148 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000); 1149 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF; 1150 value8 = (u8)(value32&0x000000FF); 1151 value32 |= ((value8<<8) | 0x00FF0000); 1152 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32); 1153 /* 2. Disable GPIO[10:8] */ 1154 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00); 1155 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F; 1156 value8 = (u8)(value16&0x000F); 1157 value16 |= ((value8<<4) | 0x0780); 1158 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16); 1159 /* 3. Disable LED0 & 1 */ 1160 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); 1161 } 1162 1163 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM) 1164 { 1165 struct rtl_priv *rtlpriv = rtl_priv(hw); 1166 u16 value16 = 0; 1167 u8 value8 = 0; 1168 1169 if (bWithoutHWSM) { 1170 /***************************** 1171 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power 1172 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power 1173 r. When driver call disable, the ASIC will turn off remaining 1174 clock automatically 1175 ******************************/ 1176 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04); 1177 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL); 1178 value8 &= (~LDV12_EN); 1179 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8); 1180 } 1181 1182 /***************************** 1183 h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode 1184 i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend 1185 ******************************/ 1186 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); 1187 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN); 1188 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16); 1189 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E); 1190 } 1191 1192 static void _CardDisableHWSM(struct ieee80211_hw *hw) 1193 { 1194 /* ==== RF Off Sequence ==== */ 1195 _DisableRFAFEAndResetBB(hw); 1196 /* ==== Reset digital sequence ====== */ 1197 _ResetDigitalProcedure1(hw, false); 1198 /* ==== Pull GPIO PIN to balance level and LED control ====== */ 1199 _DisableGPIO(hw); 1200 /* ==== Disable analog sequence === */ 1201 _DisableAnalog(hw, false); 1202 } 1203 1204 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw) 1205 { 1206 /*==== RF Off Sequence ==== */ 1207 _DisableRFAFEAndResetBB(hw); 1208 /* ==== Reset digital sequence ====== */ 1209 _ResetDigitalProcedure1(hw, true); 1210 /* ==== Pull GPIO PIN to balance level and LED control ====== */ 1211 _DisableGPIO(hw); 1212 /* ==== Reset digital sequence ====== */ 1213 _ResetDigitalProcedure2(hw); 1214 /* ==== Disable analog sequence === */ 1215 _DisableAnalog(hw, true); 1216 } 1217 1218 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 1219 u8 set_bits, u8 clear_bits) 1220 { 1221 struct rtl_priv *rtlpriv = rtl_priv(hw); 1222 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 1223 1224 rtlusb->reg_bcn_ctrl_val |= set_bits; 1225 rtlusb->reg_bcn_ctrl_val &= ~clear_bits; 1226 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val); 1227 } 1228 1229 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw) 1230 { 1231 struct rtl_priv *rtlpriv = rtl_priv(hw); 1232 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1233 u8 tmp1byte = 0; 1234 if (IS_NORMAL_CHIP(rtlhal->version)) { 1235 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 1236 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1237 tmp1byte & (~BIT(6))); 1238 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 1239 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 1240 tmp1byte &= ~(BIT(0)); 1241 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 1242 } else { 1243 rtl_write_byte(rtlpriv, REG_TXPAUSE, 1244 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6)); 1245 } 1246 } 1247 1248 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw) 1249 { 1250 struct rtl_priv *rtlpriv = rtl_priv(hw); 1251 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1252 u8 tmp1byte = 0; 1253 1254 if (IS_NORMAL_CHIP(rtlhal->version)) { 1255 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 1256 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1257 tmp1byte | BIT(6)); 1258 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 1259 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 1260 tmp1byte |= BIT(0); 1261 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 1262 } else { 1263 rtl_write_byte(rtlpriv, REG_TXPAUSE, 1264 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6))); 1265 } 1266 } 1267 1268 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw) 1269 { 1270 struct rtl_priv *rtlpriv = rtl_priv(hw); 1271 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1272 1273 if (IS_NORMAL_CHIP(rtlhal->version)) 1274 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1)); 1275 else 1276 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1277 } 1278 1279 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw) 1280 { 1281 struct rtl_priv *rtlpriv = rtl_priv(hw); 1282 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1283 1284 if (IS_NORMAL_CHIP(rtlhal->version)) 1285 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0); 1286 else 1287 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0); 1288 } 1289 1290 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw, 1291 enum nl80211_iftype type) 1292 { 1293 struct rtl_priv *rtlpriv = rtl_priv(hw); 1294 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1295 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1296 1297 bt_msr &= 0xfc; 1298 if (type == NL80211_IFTYPE_UNSPECIFIED || type == 1299 NL80211_IFTYPE_STATION) { 1300 _rtl92cu_stop_tx_beacon(hw); 1301 _rtl92cu_enable_bcn_sub_func(hw); 1302 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) { 1303 _rtl92cu_resume_tx_beacon(hw); 1304 _rtl92cu_disable_bcn_sub_func(hw); 1305 } else { 1306 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1307 "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n", 1308 type); 1309 } 1310 switch (type) { 1311 case NL80211_IFTYPE_UNSPECIFIED: 1312 bt_msr |= MSR_NOLINK; 1313 ledaction = LED_CTL_LINK; 1314 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1315 "Set Network type to NO LINK!\n"); 1316 break; 1317 case NL80211_IFTYPE_ADHOC: 1318 bt_msr |= MSR_ADHOC; 1319 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1320 "Set Network type to Ad Hoc!\n"); 1321 break; 1322 case NL80211_IFTYPE_STATION: 1323 bt_msr |= MSR_INFRA; 1324 ledaction = LED_CTL_LINK; 1325 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1326 "Set Network type to STA!\n"); 1327 break; 1328 case NL80211_IFTYPE_AP: 1329 bt_msr |= MSR_AP; 1330 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1331 "Set Network type to AP!\n"); 1332 break; 1333 default: 1334 pr_err("Network type %d not supported!\n", type); 1335 goto error_out; 1336 } 1337 rtl_write_byte(rtlpriv, MSR, bt_msr); 1338 rtlpriv->cfg->ops->led_control(hw, ledaction); 1339 if ((bt_msr & MSR_MASK) == MSR_AP) 1340 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1341 else 1342 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1343 return 0; 1344 error_out: 1345 return 1; 1346 } 1347 1348 void rtl92cu_card_disable(struct ieee80211_hw *hw) 1349 { 1350 struct rtl_priv *rtlpriv = rtl_priv(hw); 1351 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1352 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); 1353 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1354 enum nl80211_iftype opmode; 1355 1356 mac->link_state = MAC80211_NOLINK; 1357 opmode = NL80211_IFTYPE_UNSPECIFIED; 1358 _rtl92cu_set_media_status(hw, opmode); 1359 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1360 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1361 if (rtlusb->disableHWSM) 1362 _CardDisableHWSM(hw); 1363 else 1364 _CardDisableWithoutHWSM(hw); 1365 1366 /* after power off we should do iqk again */ 1367 rtlpriv->phy.iqk_initialized = false; 1368 } 1369 1370 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1371 { 1372 struct rtl_priv *rtlpriv = rtl_priv(hw); 1373 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1374 u32 reg_rcr; 1375 1376 if (rtlpriv->psc.rfpwr_state != ERFON) 1377 return; 1378 1379 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1380 1381 if (check_bssid) { 1382 u8 tmp; 1383 if (IS_NORMAL_CHIP(rtlhal->version)) { 1384 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1385 tmp = BIT(4); 1386 } else { 1387 reg_rcr |= RCR_CBSSID; 1388 tmp = BIT(4) | BIT(5); 1389 } 1390 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1391 (u8 *) (®_rcr)); 1392 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp); 1393 } else { 1394 u8 tmp; 1395 if (IS_NORMAL_CHIP(rtlhal->version)) { 1396 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1397 tmp = BIT(4); 1398 } else { 1399 reg_rcr &= ~RCR_CBSSID; 1400 tmp = BIT(4) | BIT(5); 1401 } 1402 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1403 rtlpriv->cfg->ops->set_hw_reg(hw, 1404 HW_VAR_RCR, (u8 *) (®_rcr)); 1405 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0); 1406 } 1407 } 1408 1409 /*========================================================================== */ 1410 1411 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1412 { 1413 struct rtl_priv *rtlpriv = rtl_priv(hw); 1414 1415 if (_rtl92cu_set_media_status(hw, type)) 1416 return -EOPNOTSUPP; 1417 1418 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1419 if (type != NL80211_IFTYPE_AP) 1420 rtl92cu_set_check_bssid(hw, true); 1421 } else { 1422 rtl92cu_set_check_bssid(hw, false); 1423 } 1424 1425 return 0; 1426 } 1427 1428 static void _beacon_function_enable(struct ieee80211_hw *hw) 1429 { 1430 struct rtl_priv *rtlpriv = rtl_priv(hw); 1431 1432 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00); 1433 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F); 1434 } 1435 1436 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw) 1437 { 1438 1439 struct rtl_priv *rtlpriv = rtl_priv(hw); 1440 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1441 u16 bcn_interval, atim_window; 1442 u32 value32; 1443 1444 bcn_interval = mac->beacon_interval; 1445 atim_window = 2; /*FIX MERGE */ 1446 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1447 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1448 _rtl92cu_init_beacon_parameters(hw); 1449 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 1450 /* 1451 * Force beacon frame transmission even after receiving beacon frame 1452 * from other ad hoc STA 1453 * 1454 * 1455 * Reset TSF Timer to zero, added by Roger. 2008.06.24 1456 */ 1457 value32 = rtl_read_dword(rtlpriv, REG_TCR); 1458 value32 &= ~TSFRST; 1459 rtl_write_dword(rtlpriv, REG_TCR, value32); 1460 value32 |= TSFRST; 1461 rtl_write_dword(rtlpriv, REG_TCR, value32); 1462 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD, 1463 "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n", 1464 value32); 1465 /* TODO: Modify later (Find the right parameters) 1466 * NOTE: Fix test chip's bug (about contention windows's randomness) */ 1467 if ((mac->opmode == NL80211_IFTYPE_ADHOC) || 1468 (mac->opmode == NL80211_IFTYPE_MESH_POINT) || 1469 (mac->opmode == NL80211_IFTYPE_AP)) { 1470 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50); 1471 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50); 1472 } 1473 _beacon_function_enable(hw); 1474 } 1475 1476 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw) 1477 { 1478 struct rtl_priv *rtlpriv = rtl_priv(hw); 1479 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1480 u16 bcn_interval = mac->beacon_interval; 1481 1482 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n", 1483 bcn_interval); 1484 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1485 } 1486 1487 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw, 1488 u32 add_msr, u32 rm_msr) 1489 { 1490 } 1491 1492 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 1493 { 1494 struct rtl_priv *rtlpriv = rtl_priv(hw); 1495 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1496 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1497 1498 switch (variable) { 1499 case HW_VAR_RCR: 1500 *((u32 *)(val)) = mac->rx_conf; 1501 break; 1502 case HW_VAR_RF_STATE: 1503 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 1504 break; 1505 case HW_VAR_FWLPS_RF_ON:{ 1506 enum rf_pwrstate rfState; 1507 u32 val_rcr; 1508 1509 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, 1510 (u8 *)(&rfState)); 1511 if (rfState == ERFOFF) { 1512 *((bool *) (val)) = true; 1513 } else { 1514 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 1515 val_rcr &= 0x00070000; 1516 if (val_rcr) 1517 *((bool *) (val)) = false; 1518 else 1519 *((bool *) (val)) = true; 1520 } 1521 break; 1522 } 1523 case HW_VAR_FW_PSMODE_STATUS: 1524 *((bool *) (val)) = ppsc->fw_current_inpsmode; 1525 break; 1526 case HW_VAR_CORRECT_TSF:{ 1527 u64 tsf; 1528 u32 *ptsf_low = (u32 *)&tsf; 1529 u32 *ptsf_high = ((u32 *)&tsf) + 1; 1530 1531 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 1532 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 1533 *((u64 *)(val)) = tsf; 1534 break; 1535 } 1536 case HW_VAR_MGT_FILTER: 1537 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0); 1538 break; 1539 case HW_VAR_CTRL_FILTER: 1540 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1); 1541 break; 1542 case HW_VAR_DATA_FILTER: 1543 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2); 1544 break; 1545 case HAL_DEF_WOWLAN: 1546 break; 1547 default: 1548 pr_err("switch case %#x not processed\n", variable); 1549 break; 1550 } 1551 } 1552 1553 static bool usb_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb) 1554 { 1555 /* Currently nothing happens here. 1556 * Traffic stops after some seconds in WPA2 802.11n mode. 1557 * Maybe because rtl8192cu chip should be set from here? 1558 * If I understand correctly, the realtek vendor driver sends some urbs 1559 * if its "here". 1560 * 1561 * This is maybe necessary: 1562 * rtlpriv->cfg->ops->fill_tx_cmddesc(hw, buffer, 1, 1, skb); 1563 */ 1564 return true; 1565 } 1566 1567 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 1568 { 1569 struct rtl_priv *rtlpriv = rtl_priv(hw); 1570 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1571 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1572 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1573 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1574 enum wireless_mode wirelessmode = mac->mode; 1575 u8 idx = 0; 1576 1577 switch (variable) { 1578 case HW_VAR_ETHER_ADDR:{ 1579 for (idx = 0; idx < ETH_ALEN; idx++) { 1580 rtl_write_byte(rtlpriv, (REG_MACID + idx), 1581 val[idx]); 1582 } 1583 break; 1584 } 1585 case HW_VAR_BASIC_RATE:{ 1586 u16 rate_cfg = ((u16 *) val)[0]; 1587 u8 rate_index = 0; 1588 1589 rate_cfg &= 0x15f; 1590 /* TODO */ 1591 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO 1592 * && ((rate_cfg & 0x150) == 0)) { 1593 * rate_cfg |= 0x010; 1594 * } */ 1595 rate_cfg |= 0x01; 1596 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); 1597 rtl_write_byte(rtlpriv, REG_RRSR + 1, 1598 (rate_cfg >> 8) & 0xff); 1599 while (rate_cfg > 0x1) { 1600 rate_cfg >>= 1; 1601 rate_index++; 1602 } 1603 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 1604 rate_index); 1605 break; 1606 } 1607 case HW_VAR_BSSID:{ 1608 for (idx = 0; idx < ETH_ALEN; idx++) { 1609 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 1610 val[idx]); 1611 } 1612 break; 1613 } 1614 case HW_VAR_SIFS:{ 1615 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]); 1616 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]); 1617 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 1618 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 1619 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]); 1620 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]); 1621 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n"); 1622 break; 1623 } 1624 case HW_VAR_SLOT_TIME:{ 1625 u8 e_aci; 1626 u8 QOS_MODE = 1; 1627 1628 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 1629 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1630 "HW_VAR_SLOT_TIME %x\n", val[0]); 1631 if (QOS_MODE) { 1632 for (e_aci = 0; e_aci < AC_MAX; e_aci++) 1633 rtlpriv->cfg->ops->set_hw_reg(hw, 1634 HW_VAR_AC_PARAM, 1635 &e_aci); 1636 } else { 1637 u8 sifstime = 0; 1638 u8 u1bAIFS; 1639 1640 if (IS_WIRELESS_MODE_A(wirelessmode) || 1641 IS_WIRELESS_MODE_N_24G(wirelessmode) || 1642 IS_WIRELESS_MODE_N_5G(wirelessmode)) 1643 sifstime = 16; 1644 else 1645 sifstime = 10; 1646 u1bAIFS = sifstime + (2 * val[0]); 1647 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM, 1648 u1bAIFS); 1649 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM, 1650 u1bAIFS); 1651 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM, 1652 u1bAIFS); 1653 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM, 1654 u1bAIFS); 1655 } 1656 break; 1657 } 1658 case HW_VAR_ACK_PREAMBLE:{ 1659 u8 reg_tmp; 1660 u8 short_preamble = (bool)*val; 1661 reg_tmp = 0; 1662 if (short_preamble) 1663 reg_tmp |= 0x80; 1664 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 1665 break; 1666 } 1667 case HW_VAR_AMPDU_MIN_SPACE:{ 1668 u8 min_spacing_to_set; 1669 u8 sec_min_space; 1670 1671 min_spacing_to_set = *val; 1672 if (min_spacing_to_set <= 7) { 1673 switch (rtlpriv->sec.pairwise_enc_algorithm) { 1674 case NO_ENCRYPTION: 1675 case AESCCMP_ENCRYPTION: 1676 sec_min_space = 0; 1677 break; 1678 case WEP40_ENCRYPTION: 1679 case WEP104_ENCRYPTION: 1680 case TKIP_ENCRYPTION: 1681 sec_min_space = 6; 1682 break; 1683 default: 1684 sec_min_space = 7; 1685 break; 1686 } 1687 if (min_spacing_to_set < sec_min_space) 1688 min_spacing_to_set = sec_min_space; 1689 mac->min_space_cfg = ((mac->min_space_cfg & 1690 0xf8) | 1691 min_spacing_to_set); 1692 *val = min_spacing_to_set; 1693 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1694 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 1695 mac->min_space_cfg); 1696 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 1697 mac->min_space_cfg); 1698 } 1699 break; 1700 } 1701 case HW_VAR_SHORTGI_DENSITY:{ 1702 u8 density_to_set; 1703 1704 density_to_set = *val; 1705 density_to_set &= 0x1f; 1706 mac->min_space_cfg &= 0x07; 1707 mac->min_space_cfg |= (density_to_set << 3); 1708 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1709 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 1710 mac->min_space_cfg); 1711 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 1712 mac->min_space_cfg); 1713 break; 1714 } 1715 case HW_VAR_AMPDU_FACTOR:{ 1716 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; 1717 u8 factor_toset; 1718 u8 *p_regtoset = NULL; 1719 u8 index = 0; 1720 1721 p_regtoset = regtoset_normal; 1722 factor_toset = *val; 1723 if (factor_toset <= 3) { 1724 factor_toset = (1 << (factor_toset + 2)); 1725 if (factor_toset > 0xf) 1726 factor_toset = 0xf; 1727 for (index = 0; index < 4; index++) { 1728 if ((p_regtoset[index] & 0xf0) > 1729 (factor_toset << 4)) 1730 p_regtoset[index] = 1731 (p_regtoset[index] & 0x0f) 1732 | (factor_toset << 4); 1733 if ((p_regtoset[index] & 0x0f) > 1734 factor_toset) 1735 p_regtoset[index] = 1736 (p_regtoset[index] & 0xf0) 1737 | (factor_toset); 1738 rtl_write_byte(rtlpriv, 1739 (REG_AGGLEN_LMT + index), 1740 p_regtoset[index]); 1741 } 1742 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1743 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 1744 factor_toset); 1745 } 1746 break; 1747 } 1748 case HW_VAR_AC_PARAM:{ 1749 u8 e_aci = *val; 1750 u32 u4b_ac_param; 1751 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min); 1752 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max); 1753 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op); 1754 1755 u4b_ac_param = (u32) mac->ac[e_aci].aifs; 1756 u4b_ac_param |= (u32) ((cw_min & 0xF) << 1757 AC_PARAM_ECW_MIN_OFFSET); 1758 u4b_ac_param |= (u32) ((cw_max & 0xF) << 1759 AC_PARAM_ECW_MAX_OFFSET); 1760 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET; 1761 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 1762 "queue:%x, ac_param:%x\n", 1763 e_aci, u4b_ac_param); 1764 switch (e_aci) { 1765 case AC1_BK: 1766 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 1767 u4b_ac_param); 1768 break; 1769 case AC0_BE: 1770 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 1771 u4b_ac_param); 1772 break; 1773 case AC2_VI: 1774 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 1775 u4b_ac_param); 1776 break; 1777 case AC3_VO: 1778 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 1779 u4b_ac_param); 1780 break; 1781 default: 1782 WARN_ONCE(true, "rtl8192cu: invalid aci: %d !\n", 1783 e_aci); 1784 break; 1785 } 1786 break; 1787 } 1788 case HW_VAR_RCR:{ 1789 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); 1790 mac->rx_conf = ((u32 *) (val))[0]; 1791 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG, 1792 "### Set RCR(0x%08x) ###\n", mac->rx_conf); 1793 break; 1794 } 1795 case HW_VAR_RETRY_LIMIT:{ 1796 u8 retry_limit = val[0]; 1797 1798 rtl_write_word(rtlpriv, REG_RL, 1799 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 1800 retry_limit << RETRY_LIMIT_LONG_SHIFT); 1801 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG, 1802 "Set HW_VAR_RETRY_LIMIT(0x%08x)\n", 1803 retry_limit); 1804 break; 1805 } 1806 case HW_VAR_DUAL_TSF_RST: 1807 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 1808 break; 1809 case HW_VAR_EFUSE_BYTES: 1810 rtlefuse->efuse_usedbytes = *((u16 *) val); 1811 break; 1812 case HW_VAR_EFUSE_USAGE: 1813 rtlefuse->efuse_usedpercentage = *val; 1814 break; 1815 case HW_VAR_IO_CMD: 1816 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val)); 1817 break; 1818 case HW_VAR_WPA_CONFIG: 1819 rtl_write_byte(rtlpriv, REG_SECCFG, *val); 1820 break; 1821 case HW_VAR_SET_RPWM:{ 1822 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM); 1823 1824 if (rpwm_val & BIT(7)) 1825 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val); 1826 else 1827 rtl_write_byte(rtlpriv, REG_USB_HRPWM, 1828 *val | BIT(7)); 1829 break; 1830 } 1831 case HW_VAR_H2C_FW_PWRMODE:{ 1832 u8 psmode = *val; 1833 1834 if ((psmode != FW_PS_ACTIVE_MODE) && 1835 (!IS_92C_SERIAL(rtlhal->version))) 1836 rtl92c_dm_rf_saving(hw, true); 1837 rtl92c_set_fw_pwrmode_cmd(hw, (*val)); 1838 break; 1839 } 1840 case HW_VAR_FW_PSMODE_STATUS: 1841 ppsc->fw_current_inpsmode = *((bool *) val); 1842 break; 1843 case HW_VAR_H2C_FW_JOINBSSRPT:{ 1844 u8 mstatus = *val; 1845 u8 tmp_reg422; 1846 bool recover = false; 1847 1848 if (mstatus == RT_MEDIA_CONNECT) { 1849 rtlpriv->cfg->ops->set_hw_reg(hw, 1850 HW_VAR_AID, NULL); 1851 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03); 1852 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); 1853 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0); 1854 tmp_reg422 = rtl_read_byte(rtlpriv, 1855 REG_FWHW_TXQ_CTRL + 2); 1856 if (tmp_reg422 & BIT(6)) 1857 recover = true; 1858 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 1859 tmp_reg422 & (~BIT(6))); 1860 rtl92c_set_fw_rsvdpagepkt(hw, 1861 &usb_cmd_send_packet); 1862 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); 1863 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1864 if (recover) 1865 rtl_write_byte(rtlpriv, 1866 REG_FWHW_TXQ_CTRL + 2, 1867 tmp_reg422 | BIT(6)); 1868 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 1869 } 1870 rtl92c_set_fw_joinbss_report_cmd(hw, (*val)); 1871 break; 1872 } 1873 case HW_VAR_AID:{ 1874 u16 u2btmp; 1875 1876 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 1877 u2btmp &= 0xC000; 1878 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, 1879 (u2btmp | mac->assoc_id)); 1880 break; 1881 } 1882 case HW_VAR_CORRECT_TSF:{ 1883 u8 btype_ibss = val[0]; 1884 1885 if (btype_ibss) 1886 _rtl92cu_stop_tx_beacon(hw); 1887 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); 1888 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf & 1889 0xffffffff)); 1890 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 1891 (u32)((mac->tsf >> 32) & 0xffffffff)); 1892 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); 1893 if (btype_ibss) 1894 _rtl92cu_resume_tx_beacon(hw); 1895 break; 1896 } 1897 case HW_VAR_MGT_FILTER: 1898 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val); 1899 mac->rx_mgt_filter = *(u16 *)val; 1900 break; 1901 case HW_VAR_CTRL_FILTER: 1902 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val); 1903 mac->rx_ctrl_filter = *(u16 *)val; 1904 break; 1905 case HW_VAR_DATA_FILTER: 1906 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val); 1907 mac->rx_data_filter = *(u16 *)val; 1908 break; 1909 case HW_VAR_KEEP_ALIVE:{ 1910 u8 array[2]; 1911 array[0] = 0xff; 1912 array[1] = *((u8 *)val); 1913 rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2, 1914 array); 1915 break; 1916 } 1917 default: 1918 pr_err("switch case %#x not processed\n", variable); 1919 break; 1920 } 1921 } 1922 1923 static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw, 1924 struct ieee80211_sta *sta) 1925 { 1926 struct rtl_priv *rtlpriv = rtl_priv(hw); 1927 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1928 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1929 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1930 u32 ratr_value; 1931 u8 ratr_index = 0; 1932 u8 nmode = mac->ht_enable; 1933 u8 mimo_ps = IEEE80211_SMPS_OFF; 1934 u16 shortgi_rate; 1935 u32 tmp_ratr_value; 1936 u8 curtxbw_40mhz = mac->bw_40; 1937 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1938 1 : 0; 1939 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1940 1 : 0; 1941 enum wireless_mode wirelessmode = mac->mode; 1942 1943 if (rtlhal->current_bandtype == BAND_ON_5G) 1944 ratr_value = sta->supp_rates[1] << 4; 1945 else 1946 ratr_value = sta->supp_rates[0]; 1947 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1948 ratr_value = 0xfff; 1949 1950 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1951 sta->ht_cap.mcs.rx_mask[0] << 12); 1952 switch (wirelessmode) { 1953 case WIRELESS_MODE_B: 1954 if (ratr_value & 0x0000000c) 1955 ratr_value &= 0x0000000d; 1956 else 1957 ratr_value &= 0x0000000f; 1958 break; 1959 case WIRELESS_MODE_G: 1960 ratr_value &= 0x00000FF5; 1961 break; 1962 case WIRELESS_MODE_N_24G: 1963 case WIRELESS_MODE_N_5G: 1964 nmode = 1; 1965 if (mimo_ps == IEEE80211_SMPS_STATIC) { 1966 ratr_value &= 0x0007F005; 1967 } else { 1968 u32 ratr_mask; 1969 1970 if (get_rf_type(rtlphy) == RF_1T2R || 1971 get_rf_type(rtlphy) == RF_1T1R) 1972 ratr_mask = 0x000ff005; 1973 else 1974 ratr_mask = 0x0f0ff005; 1975 1976 ratr_value &= ratr_mask; 1977 } 1978 break; 1979 default: 1980 if (rtlphy->rf_type == RF_1T2R) 1981 ratr_value &= 0x000ff0ff; 1982 else 1983 ratr_value &= 0x0f0ff0ff; 1984 1985 break; 1986 } 1987 1988 ratr_value &= 0x0FFFFFFF; 1989 1990 if (nmode && ((curtxbw_40mhz && 1991 curshortgi_40mhz) || (!curtxbw_40mhz && 1992 curshortgi_20mhz))) { 1993 1994 ratr_value |= 0x10000000; 1995 tmp_ratr_value = (ratr_value >> 12); 1996 1997 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 1998 if ((1 << shortgi_rate) & tmp_ratr_value) 1999 break; 2000 } 2001 2002 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 2003 (shortgi_rate << 4) | (shortgi_rate); 2004 } 2005 2006 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 2007 2008 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", 2009 rtl_read_dword(rtlpriv, REG_ARFR0)); 2010 } 2011 2012 static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, 2013 struct ieee80211_sta *sta, 2014 u8 rssi_level) 2015 { 2016 struct rtl_priv *rtlpriv = rtl_priv(hw); 2017 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2018 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2019 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 2020 struct rtl_sta_info *sta_entry = NULL; 2021 u32 ratr_bitmap; 2022 u8 ratr_index; 2023 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; 2024 u8 curshortgi_40mhz = curtxbw_40mhz && 2025 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 2026 1 : 0; 2027 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 2028 1 : 0; 2029 enum wireless_mode wirelessmode = 0; 2030 bool shortgi = false; 2031 u8 rate_mask[5]; 2032 u8 macid = 0; 2033 u8 mimo_ps = IEEE80211_SMPS_OFF; 2034 2035 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 2036 wirelessmode = sta_entry->wireless_mode; 2037 if (mac->opmode == NL80211_IFTYPE_STATION || 2038 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2039 curtxbw_40mhz = mac->bw_40; 2040 else if (mac->opmode == NL80211_IFTYPE_AP || 2041 mac->opmode == NL80211_IFTYPE_ADHOC) 2042 macid = sta->aid + 1; 2043 2044 if (rtlhal->current_bandtype == BAND_ON_5G) 2045 ratr_bitmap = sta->supp_rates[1] << 4; 2046 else 2047 ratr_bitmap = sta->supp_rates[0]; 2048 if (mac->opmode == NL80211_IFTYPE_ADHOC) 2049 ratr_bitmap = 0xfff; 2050 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 2051 sta->ht_cap.mcs.rx_mask[0] << 12); 2052 switch (wirelessmode) { 2053 case WIRELESS_MODE_B: 2054 ratr_index = RATR_INX_WIRELESS_B; 2055 if (ratr_bitmap & 0x0000000c) 2056 ratr_bitmap &= 0x0000000d; 2057 else 2058 ratr_bitmap &= 0x0000000f; 2059 break; 2060 case WIRELESS_MODE_G: 2061 ratr_index = RATR_INX_WIRELESS_GB; 2062 2063 if (rssi_level == 1) 2064 ratr_bitmap &= 0x00000f00; 2065 else if (rssi_level == 2) 2066 ratr_bitmap &= 0x00000ff0; 2067 else 2068 ratr_bitmap &= 0x00000ff5; 2069 break; 2070 case WIRELESS_MODE_A: 2071 ratr_index = RATR_INX_WIRELESS_A; 2072 ratr_bitmap &= 0x00000ff0; 2073 break; 2074 case WIRELESS_MODE_N_24G: 2075 case WIRELESS_MODE_N_5G: 2076 ratr_index = RATR_INX_WIRELESS_NGB; 2077 2078 if (mimo_ps == IEEE80211_SMPS_STATIC) { 2079 if (rssi_level == 1) 2080 ratr_bitmap &= 0x00070000; 2081 else if (rssi_level == 2) 2082 ratr_bitmap &= 0x0007f000; 2083 else 2084 ratr_bitmap &= 0x0007f005; 2085 } else { 2086 if (rtlphy->rf_type == RF_1T2R || 2087 rtlphy->rf_type == RF_1T1R) { 2088 if (curtxbw_40mhz) { 2089 if (rssi_level == 1) 2090 ratr_bitmap &= 0x000f0000; 2091 else if (rssi_level == 2) 2092 ratr_bitmap &= 0x000ff000; 2093 else 2094 ratr_bitmap &= 0x000ff015; 2095 } else { 2096 if (rssi_level == 1) 2097 ratr_bitmap &= 0x000f0000; 2098 else if (rssi_level == 2) 2099 ratr_bitmap &= 0x000ff000; 2100 else 2101 ratr_bitmap &= 0x000ff005; 2102 } 2103 } else { 2104 if (curtxbw_40mhz) { 2105 if (rssi_level == 1) 2106 ratr_bitmap &= 0x0f0f0000; 2107 else if (rssi_level == 2) 2108 ratr_bitmap &= 0x0f0ff000; 2109 else 2110 ratr_bitmap &= 0x0f0ff015; 2111 } else { 2112 if (rssi_level == 1) 2113 ratr_bitmap &= 0x0f0f0000; 2114 else if (rssi_level == 2) 2115 ratr_bitmap &= 0x0f0ff000; 2116 else 2117 ratr_bitmap &= 0x0f0ff005; 2118 } 2119 } 2120 } 2121 2122 if ((curtxbw_40mhz && curshortgi_40mhz) || 2123 (!curtxbw_40mhz && curshortgi_20mhz)) { 2124 2125 if (macid == 0) 2126 shortgi = true; 2127 else if (macid == 1) 2128 shortgi = false; 2129 } 2130 break; 2131 default: 2132 ratr_index = RATR_INX_WIRELESS_NGB; 2133 2134 if (rtlphy->rf_type == RF_1T2R) 2135 ratr_bitmap &= 0x000ff0ff; 2136 else 2137 ratr_bitmap &= 0x0f0ff0ff; 2138 break; 2139 } 2140 sta_entry->ratr_index = ratr_index; 2141 2142 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2143 "ratr_bitmap :%x\n", ratr_bitmap); 2144 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 2145 (ratr_index << 28); 2146 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; 2147 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2148 "Rate_index:%x, ratr_val:%x, %5phC\n", 2149 ratr_index, ratr_bitmap, rate_mask); 2150 memcpy(rtlpriv->rate_mask, rate_mask, 5); 2151 /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a 2152 * "scheduled while atomic" if called directly */ 2153 schedule_work(&rtlpriv->works.fill_h2c_cmd); 2154 2155 if (macid != 0) 2156 sta_entry->ratr_index = ratr_index; 2157 } 2158 2159 void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw, 2160 struct ieee80211_sta *sta, 2161 u8 rssi_level) 2162 { 2163 struct rtl_priv *rtlpriv = rtl_priv(hw); 2164 2165 if (rtlpriv->dm.useramask) 2166 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level); 2167 else 2168 rtl92cu_update_hal_rate_table(hw, sta); 2169 } 2170 2171 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw) 2172 { 2173 struct rtl_priv *rtlpriv = rtl_priv(hw); 2174 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2175 u16 sifs_timer; 2176 2177 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2178 &mac->slot_time); 2179 if (!mac->ht_enable) 2180 sifs_timer = 0x0a0a; 2181 else 2182 sifs_timer = 0x0e0e; 2183 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2184 } 2185 2186 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid) 2187 { 2188 struct rtl_priv *rtlpriv = rtl_priv(hw); 2189 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2190 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate; 2191 u8 u1tmp = 0; 2192 bool actuallyset = false; 2193 unsigned long flag = 0; 2194 /* to do - usb autosuspend */ 2195 u8 usb_autosuspend = 0; 2196 2197 if (ppsc->swrf_processing) 2198 return false; 2199 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2200 if (ppsc->rfchange_inprogress) { 2201 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2202 return false; 2203 } else { 2204 ppsc->rfchange_inprogress = true; 2205 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2206 } 2207 cur_rfstate = ppsc->rfpwr_state; 2208 if (usb_autosuspend) { 2209 /* to do................... */ 2210 } else { 2211 if (ppsc->pwrdown_mode) { 2212 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR); 2213 e_rfpowerstate_toset = (u1tmp & BIT(7)) ? 2214 ERFOFF : ERFON; 2215 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 2216 "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp); 2217 } else { 2218 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, 2219 rtl_read_byte(rtlpriv, 2220 REG_MAC_PINMUX_CFG) & ~(BIT(3))); 2221 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); 2222 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? 2223 ERFON : ERFOFF; 2224 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, 2225 "GPIO_IN=%02x\n", u1tmp); 2226 } 2227 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n", 2228 e_rfpowerstate_toset); 2229 } 2230 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { 2231 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2232 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2233 ppsc->hwradiooff = false; 2234 actuallyset = true; 2235 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset == 2236 ERFOFF)) { 2237 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2238 "GPIOChangeRF - HW Radio OFF\n"); 2239 ppsc->hwradiooff = true; 2240 actuallyset = true; 2241 } else { 2242 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, 2243 "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n", 2244 ppsc->hwradiooff, e_rfpowerstate_toset); 2245 } 2246 if (actuallyset) { 2247 ppsc->hwradiooff = true; 2248 if (e_rfpowerstate_toset == ERFON) { 2249 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) && 2250 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM)) 2251 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2252 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2253 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3)) 2254 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2255 } 2256 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2257 ppsc->rfchange_inprogress = false; 2258 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2259 /* For power down module, we need to enable register block 2260 * contrl reg at 0x1c. Then enable power down control bit 2261 * of register 0x04 BIT4 and BIT15 as 1. 2262 */ 2263 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) { 2264 /* Enable register area 0x0-0xc. */ 2265 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); 2266 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812); 2267 } 2268 if (e_rfpowerstate_toset == ERFOFF) { 2269 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) 2270 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2271 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2272 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2273 } 2274 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) { 2275 /* Enter D3 or ASPM after GPIO had been done. */ 2276 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) 2277 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM); 2278 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3) 2279 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3); 2280 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2281 ppsc->rfchange_inprogress = false; 2282 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2283 } else { 2284 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2285 ppsc->rfchange_inprogress = false; 2286 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2287 } 2288 *valid = 1; 2289 return !ppsc->hwradiooff; 2290 } 2291