1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../pci.h"
6 #include "../base.h"
7 #include "../stats.h"
8 #include "reg.h"
9 #include "def.h"
10 #include "phy.h"
11 #include "trx.h"
12 #include "led.h"
13 
14 static u8 _rtl92ce_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
15 {
16 	__le16 fc = rtl_get_fc(skb);
17 
18 	if (unlikely(ieee80211_is_beacon(fc)))
19 		return QSLT_BEACON;
20 	if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
21 		return QSLT_MGNT;
22 
23 	return skb->priority;
24 }
25 
26 static u8 _rtl92c_query_rxpwrpercentage(s8 antpower)
27 {
28 	if ((antpower <= -100) || (antpower >= 20))
29 		return 0;
30 	else if (antpower >= 0)
31 		return 100;
32 	else
33 		return 100 + antpower;
34 }
35 
36 static u8 _rtl92c_evm_db_to_percentage(s8 value)
37 {
38 	s8 ret_val;
39 
40 	ret_val = value;
41 
42 	if (ret_val >= 0)
43 		ret_val = 0;
44 
45 	if (ret_val <= -33)
46 		ret_val = -33;
47 
48 	ret_val = 0 - ret_val;
49 	ret_val *= 3;
50 
51 	if (ret_val == 99)
52 		ret_val = 100;
53 
54 	return ret_val;
55 }
56 
57 static long _rtl92ce_signal_scale_mapping(struct ieee80211_hw *hw,
58 		long currsig)
59 {
60 	long retsig;
61 
62 	if (currsig >= 61 && currsig <= 100)
63 		retsig = 90 + ((currsig - 60) / 4);
64 	else if (currsig >= 41 && currsig <= 60)
65 		retsig = 78 + ((currsig - 40) / 2);
66 	else if (currsig >= 31 && currsig <= 40)
67 		retsig = 66 + (currsig - 30);
68 	else if (currsig >= 21 && currsig <= 30)
69 		retsig = 54 + (currsig - 20);
70 	else if (currsig >= 5 && currsig <= 20)
71 		retsig = 42 + (((currsig - 5) * 2) / 3);
72 	else if (currsig == 4)
73 		retsig = 36;
74 	else if (currsig == 3)
75 		retsig = 27;
76 	else if (currsig == 2)
77 		retsig = 18;
78 	else if (currsig == 1)
79 		retsig = 9;
80 	else
81 		retsig = currsig;
82 
83 	return retsig;
84 }
85 
86 static void _rtl92ce_query_rxphystatus(struct ieee80211_hw *hw,
87 				       struct rtl_stats *pstats,
88 				       struct rx_desc_92c *pdesc,
89 				       struct rx_fwinfo_92c *p_drvinfo,
90 				       bool packet_match_bssid,
91 				       bool packet_toself,
92 				       bool packet_beacon)
93 {
94 	struct rtl_priv *rtlpriv = rtl_priv(hw);
95 	struct phy_sts_cck_8192s_t *cck_buf;
96 	struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
97 	s8 rx_pwr_all = 0, rx_pwr[4];
98 	u8 evm, pwdb_all, rf_rx_num = 0;
99 	u8 i, max_spatial_stream;
100 	u32 rssi, total_rssi = 0;
101 	bool is_cck_rate;
102 
103 	is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc->rxmcs);
104 	pstats->packet_matchbssid = packet_match_bssid;
105 	pstats->packet_toself = packet_toself;
106 	pstats->is_cck = is_cck_rate;
107 	pstats->packet_beacon = packet_beacon;
108 	pstats->rx_mimo_sig_qual[0] = -1;
109 	pstats->rx_mimo_sig_qual[1] = -1;
110 
111 	if (is_cck_rate) {
112 		u8 report, cck_highpwr;
113 
114 		cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo;
115 
116 		if (ppsc->rfpwr_state == ERFON)
117 			cck_highpwr = (u8) rtl_get_bbreg(hw,
118 						 RFPGA0_XA_HSSIPARAMETER2,
119 						 BIT(9));
120 		else
121 			cck_highpwr = false;
122 
123 		if (!cck_highpwr) {
124 			u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
125 
126 			report = cck_buf->cck_agc_rpt & 0xc0;
127 			report = report >> 6;
128 			switch (report) {
129 			case 0x3:
130 				rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
131 				break;
132 			case 0x2:
133 				rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
134 				break;
135 			case 0x1:
136 				rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
137 				break;
138 			case 0x0:
139 				rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
140 				break;
141 			}
142 		} else {
143 			u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
144 
145 			report = p_drvinfo->cfosho[0] & 0x60;
146 			report = report >> 5;
147 			switch (report) {
148 			case 0x3:
149 				rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1);
150 				break;
151 			case 0x2:
152 				rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1);
153 				break;
154 			case 0x1:
155 				rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1);
156 				break;
157 			case 0x0:
158 				rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1);
159 				break;
160 			}
161 		}
162 
163 		pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
164 		/* CCK gain is smaller than OFDM/MCS gain,
165 		 * so we add gain diff by experiences,
166 		 * the val is 6
167 		 */
168 		pwdb_all += 6;
169 		if (pwdb_all > 100)
170 			pwdb_all = 100;
171 		/* modify the offset to make the same
172 		 * gain index with OFDM.
173 		 */
174 		if (pwdb_all > 34 && pwdb_all <= 42)
175 			pwdb_all -= 2;
176 		else if (pwdb_all > 26 && pwdb_all <= 34)
177 			pwdb_all -= 6;
178 		else if (pwdb_all > 14 && pwdb_all <= 26)
179 			pwdb_all -= 8;
180 		else if (pwdb_all > 4 && pwdb_all <= 14)
181 			pwdb_all -= 4;
182 
183 		pstats->rx_pwdb_all = pwdb_all;
184 		pstats->recvsignalpower = rx_pwr_all;
185 
186 		/* (3) Get Signal Quality (EVM) */
187 		if (packet_match_bssid) {
188 			u8 sq;
189 
190 			if (pstats->rx_pwdb_all > 40)
191 				sq = 100;
192 			else {
193 				sq = cck_buf->sq_rpt;
194 				if (sq > 64)
195 					sq = 0;
196 				else if (sq < 20)
197 					sq = 100;
198 				else
199 					sq = ((64 - sq) * 100) / 44;
200 			}
201 
202 			pstats->signalquality = sq;
203 			pstats->rx_mimo_sig_qual[0] = sq;
204 			pstats->rx_mimo_sig_qual[1] = -1;
205 		}
206 	} else {
207 		rtlpriv->dm.rfpath_rxenable[0] =
208 		    rtlpriv->dm.rfpath_rxenable[1] = true;
209 		/* (1)Get RSSI for HT rate */
210 		for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
211 			/* we will judge RF RX path now. */
212 			if (rtlpriv->dm.rfpath_rxenable[i])
213 				rf_rx_num++;
214 
215 			rx_pwr[i] =
216 			    ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) - 110;
217 			/* Translate DBM to percentage. */
218 			rssi = _rtl92c_query_rxpwrpercentage(rx_pwr[i]);
219 			total_rssi += rssi;
220 			/* Get Rx snr value in DB */
221 			rtlpriv->stats.rx_snr_db[i] =
222 			    (long)(p_drvinfo->rxsnr[i] / 2);
223 
224 			/* Record Signal Strength for next packet */
225 			if (packet_match_bssid)
226 				pstats->rx_mimo_signalstrength[i] = (u8) rssi;
227 		}
228 
229 		/* (2)PWDB, Average PWDB cacluated by
230 		 * hardware (for rate adaptive)
231 		 */
232 		rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110;
233 		pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
234 		pstats->rx_pwdb_all = pwdb_all;
235 		pstats->rxpower = rx_pwr_all;
236 		pstats->recvsignalpower = rx_pwr_all;
237 
238 		/* (3)EVM of HT rate */
239 		if (pstats->is_ht && pstats->rate >= DESC_RATEMCS8 &&
240 		    pstats->rate <= DESC_RATEMCS15)
241 			max_spatial_stream = 2;
242 		else
243 			max_spatial_stream = 1;
244 
245 		for (i = 0; i < max_spatial_stream; i++) {
246 			evm = _rtl92c_evm_db_to_percentage(p_drvinfo->rxevm[i]);
247 
248 			if (packet_match_bssid) {
249 				/* Fill value in RFD, Get the first
250 				 * spatial stream only
251 				 */
252 				if (i == 0)
253 					pstats->signalquality =
254 					    (u8)(evm & 0xff);
255 				pstats->rx_mimo_sig_qual[i] = (u8)(evm & 0xff);
256 			}
257 		}
258 	}
259 
260 	/* UI BSS List signal strength(in percentage),
261 	 * make it good looking, from 0~100.
262 	 */
263 	if (is_cck_rate)
264 		pstats->signalstrength =
265 		    (u8)(_rtl92ce_signal_scale_mapping(hw, pwdb_all));
266 	else if (rf_rx_num != 0)
267 		pstats->signalstrength =
268 		    (u8)(_rtl92ce_signal_scale_mapping
269 			  (hw, total_rssi /= rf_rx_num));
270 }
271 
272 static void _rtl92ce_translate_rx_signal_stuff(struct ieee80211_hw *hw,
273 					       struct sk_buff *skb,
274 					       struct rtl_stats *pstats,
275 					       struct rx_desc_92c *pdesc,
276 					       struct rx_fwinfo_92c *p_drvinfo)
277 {
278 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
279 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
280 
281 	struct ieee80211_hdr *hdr;
282 	u8 *tmp_buf;
283 	u8 *praddr;
284 	__le16 fc;
285 	u16 type, c_fc;
286 	bool packet_matchbssid, packet_toself, packet_beacon = false;
287 
288 	tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift;
289 
290 	hdr = (struct ieee80211_hdr *)tmp_buf;
291 	fc = hdr->frame_control;
292 	c_fc = le16_to_cpu(fc);
293 	type = WLAN_FC_GET_TYPE(fc);
294 	praddr = hdr->addr1;
295 
296 	packet_matchbssid =
297 	    ((IEEE80211_FTYPE_CTL != type) &&
298 	     ether_addr_equal(mac->bssid,
299 			      (c_fc & IEEE80211_FCTL_TODS) ? hdr->addr1 :
300 			      (c_fc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 :
301 			      hdr->addr3) &&
302 	     (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv));
303 
304 	packet_toself = packet_matchbssid &&
305 	     ether_addr_equal(praddr, rtlefuse->dev_addr);
306 
307 	if (ieee80211_is_beacon(fc))
308 		packet_beacon = true;
309 
310 	_rtl92ce_query_rxphystatus(hw, pstats, pdesc, p_drvinfo,
311 				   packet_matchbssid, packet_toself,
312 				   packet_beacon);
313 
314 	rtl_process_phyinfo(hw, tmp_buf, pstats);
315 }
316 
317 bool rtl92ce_rx_query_desc(struct ieee80211_hw *hw,
318 			   struct rtl_stats *stats,
319 			   struct ieee80211_rx_status *rx_status,
320 			   u8 *p_desc8, struct sk_buff *skb)
321 {
322 	struct rx_fwinfo_92c *p_drvinfo;
323 	struct rx_desc_92c *pdesc = (struct rx_desc_92c *)p_desc8;
324 	struct ieee80211_hdr *hdr;
325 	__le32 *p_desc = (__le32 *)p_desc8;
326 	u32 phystatus = get_rx_desc_physt(p_desc);
327 
328 	stats->length = (u16)get_rx_desc_pkt_len(p_desc);
329 	stats->rx_drvinfo_size = (u8)get_rx_desc_drv_info_size(p_desc) *
330 	    RX_DRV_INFO_SIZE_UNIT;
331 	stats->rx_bufshift = (u8)(get_rx_desc_shift(p_desc) & 0x03);
332 	stats->icv = (u16)get_rx_desc_icv(p_desc);
333 	stats->crc = (u16)get_rx_desc_crc32(p_desc);
334 	stats->hwerror = (stats->crc | stats->icv);
335 	stats->decrypted = !get_rx_desc_swdec(p_desc);
336 	stats->rate = (u8)get_rx_desc_rxmcs(p_desc);
337 	stats->shortpreamble = (u16)get_rx_desc_splcp(p_desc);
338 	stats->isampdu = (bool)(get_rx_desc_paggr(p_desc) == 1);
339 	stats->isfirst_ampdu = (bool)((get_rx_desc_paggr(p_desc) == 1) &&
340 				      (get_rx_desc_faggr(p_desc) == 1));
341 	stats->timestamp_low = get_rx_desc_tsfl(p_desc);
342 	stats->rx_is40mhzpacket = (bool)get_rx_desc_bw(p_desc);
343 	stats->is_ht = (bool)get_rx_desc_rxht(p_desc);
344 
345 	stats->is_cck = RX_HAL_IS_CCK_RATE(pdesc->rxmcs);
346 
347 	rx_status->freq = hw->conf.chandef.chan->center_freq;
348 	rx_status->band = hw->conf.chandef.chan->band;
349 
350 	hdr = (struct ieee80211_hdr *)(skb->data + stats->rx_drvinfo_size
351 			+ stats->rx_bufshift);
352 
353 	if (stats->crc)
354 		rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
355 
356 	if (stats->rx_is40mhzpacket)
357 		rx_status->bw = RATE_INFO_BW_40;
358 
359 	if (stats->is_ht)
360 		rx_status->encoding = RX_ENC_HT;
361 
362 	rx_status->flag |= RX_FLAG_MACTIME_START;
363 
364 	/* hw will set stats->decrypted true, if it finds the
365 	 * frame is open data frame or mgmt frame.
366 	 * So hw will not decryption robust managment frame
367 	 * for IEEE80211w but still set status->decrypted
368 	 * true, so here we should set it back to undecrypted
369 	 * for IEEE80211w frame, and mac80211 sw will help
370 	 * to decrypt it
371 	 */
372 	if (stats->decrypted) {
373 		if ((_ieee80211_is_robust_mgmt_frame(hdr)) &&
374 		    (ieee80211_has_protected(hdr->frame_control)))
375 			rx_status->flag &= ~RX_FLAG_DECRYPTED;
376 		else
377 			rx_status->flag |= RX_FLAG_DECRYPTED;
378 	}
379 	/* rate_idx: index of data rate into band's
380 	 * supported rates or MCS index if HT rates
381 	 * are use (RX_FLAG_HT)
382 	 * Notice: this is diff with windows define
383 	 */
384 	rx_status->rate_idx = rtlwifi_rate_mapping(hw, stats->is_ht,
385 						   false, stats->rate);
386 
387 	rx_status->mactime = stats->timestamp_low;
388 	if (phystatus) {
389 		p_drvinfo = (struct rx_fwinfo_92c *)(skb->data +
390 						     stats->rx_bufshift);
391 
392 		_rtl92ce_translate_rx_signal_stuff(hw,
393 						   skb, stats, pdesc,
394 						   p_drvinfo);
395 	}
396 
397 	/*rx_status->qual = stats->signal; */
398 	rx_status->signal = stats->recvsignalpower + 10;
399 
400 	return true;
401 }
402 
403 void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw,
404 			  struct ieee80211_hdr *hdr, u8 *pdesc8,
405 			  u8 *pbd_desc_tx, struct ieee80211_tx_info *info,
406 			  struct ieee80211_sta *sta,
407 			  struct sk_buff *skb,
408 			  u8 hw_queue, struct rtl_tcb_desc *tcb_desc)
409 {
410 	struct rtl_priv *rtlpriv = rtl_priv(hw);
411 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
412 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
413 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
414 	bool defaultadapter = true;
415 	__le32 *pdesc = (__le32 *)pdesc8;
416 	u16 seq_number;
417 	__le16 fc = hdr->frame_control;
418 	u8 fw_qsel = _rtl92ce_map_hwqueue_to_fwqueue(skb, hw_queue);
419 	bool firstseg = ((hdr->seq_ctrl &
420 			  cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
421 
422 	bool lastseg = ((hdr->frame_control &
423 			 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
424 
425 	dma_addr_t mapping = pci_map_single(rtlpci->pdev,
426 					    skb->data, skb->len,
427 					    PCI_DMA_TODEVICE);
428 
429 	u8 bw_40 = 0;
430 
431 	if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
432 		RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
433 			 "DMA mapping error\n");
434 		return;
435 	}
436 	rcu_read_lock();
437 	sta = get_sta(hw, mac->vif, mac->bssid);
438 	if (mac->opmode == NL80211_IFTYPE_STATION) {
439 		bw_40 = mac->bw_40;
440 	} else if (mac->opmode == NL80211_IFTYPE_AP ||
441 		   mac->opmode == NL80211_IFTYPE_ADHOC ||
442 		   mac->opmode == NL80211_IFTYPE_MESH_POINT) {
443 		if (sta)
444 			bw_40 = sta->bandwidth >= IEEE80211_STA_RX_BW_40;
445 	}
446 
447 	seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
448 
449 	rtl_get_tcb_desc(hw, info, sta, skb, tcb_desc);
450 
451 	clear_pci_tx_desc_content(pdesc, sizeof(struct tx_desc_92c));
452 
453 	if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
454 		firstseg = true;
455 		lastseg = true;
456 	}
457 	if (firstseg) {
458 		set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN);
459 
460 		set_tx_desc_tx_rate(pdesc, tcb_desc->hw_rate);
461 
462 		if (tcb_desc->use_shortgi || tcb_desc->use_shortpreamble)
463 			set_tx_desc_data_shortgi(pdesc, 1);
464 
465 		if (info->flags & IEEE80211_TX_CTL_AMPDU) {
466 			set_tx_desc_agg_break(pdesc, 1);
467 			set_tx_desc_max_agg_num(pdesc, 0x14);
468 		}
469 		set_tx_desc_seq(pdesc, seq_number);
470 
471 		set_tx_desc_rts_enable(pdesc, ((tcb_desc->rts_enable &&
472 						!tcb_desc->
473 						cts_enable) ? 1 : 0));
474 		set_tx_desc_hw_rts_enable(pdesc,
475 					  ((tcb_desc->rts_enable
476 					    || tcb_desc->cts_enable) ? 1 : 0));
477 		set_tx_desc_cts2self(pdesc, ((tcb_desc->cts_enable) ? 1 : 0));
478 		set_tx_desc_rts_stbc(pdesc, ((tcb_desc->rts_stbc) ? 1 : 0));
479 
480 		set_tx_desc_rts_rate(pdesc, tcb_desc->rts_rate);
481 		set_tx_desc_rts_bw(pdesc, 0);
482 		set_tx_desc_rts_sc(pdesc, tcb_desc->rts_sc);
483 		set_tx_desc_rts_short(pdesc,
484 				      ((tcb_desc->rts_rate <= DESC_RATE54M) ?
485 				       (tcb_desc->rts_use_shortpreamble ? 1 : 0)
486 				       : (tcb_desc->rts_use_shortgi ? 1 : 0)));
487 
488 		if (bw_40) {
489 			if (tcb_desc->packet_bw) {
490 				set_tx_desc_data_bw(pdesc, 1);
491 				set_tx_desc_tx_sub_carrier(pdesc, 3);
492 			} else {
493 				set_tx_desc_data_bw(pdesc, 0);
494 				set_tx_desc_tx_sub_carrier(pdesc,
495 						 mac->cur_40_prime_sc);
496 			}
497 		} else {
498 			set_tx_desc_data_bw(pdesc, 0);
499 			set_tx_desc_tx_sub_carrier(pdesc, 0);
500 		}
501 
502 		set_tx_desc_linip(pdesc, 0);
503 		set_tx_desc_pkt_size(pdesc, (u16)skb->len);
504 
505 		if (sta) {
506 			u8 ampdu_density = sta->ht_cap.ampdu_density;
507 
508 			set_tx_desc_ampdu_density(pdesc, ampdu_density);
509 		}
510 
511 		if (info->control.hw_key) {
512 			struct ieee80211_key_conf *keyconf =
513 			    info->control.hw_key;
514 
515 			switch (keyconf->cipher) {
516 			case WLAN_CIPHER_SUITE_WEP40:
517 			case WLAN_CIPHER_SUITE_WEP104:
518 			case WLAN_CIPHER_SUITE_TKIP:
519 				set_tx_desc_sec_type(pdesc, 0x1);
520 				break;
521 			case WLAN_CIPHER_SUITE_CCMP:
522 				set_tx_desc_sec_type(pdesc, 0x3);
523 				break;
524 			default:
525 				set_tx_desc_sec_type(pdesc, 0x0);
526 				break;
527 
528 			}
529 		}
530 
531 		set_tx_desc_pkt_id(pdesc, 0);
532 		set_tx_desc_queue_sel(pdesc, fw_qsel);
533 
534 		set_tx_desc_data_rate_fb_limit(pdesc, 0x1F);
535 		set_tx_desc_rts_rate_fb_limit(pdesc, 0xF);
536 		set_tx_desc_disable_fb(pdesc, 0);
537 		set_tx_desc_use_rate(pdesc, tcb_desc->use_driver_rate ? 1 : 0);
538 
539 		if (ieee80211_is_data_qos(fc)) {
540 			if (mac->rdg_en) {
541 				RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
542 					 "Enable RDG function\n");
543 				set_tx_desc_rdg_enable(pdesc, 1);
544 				set_tx_desc_htc(pdesc, 1);
545 			}
546 		}
547 	}
548 	rcu_read_unlock();
549 
550 	set_tx_desc_first_seg(pdesc, (firstseg ? 1 : 0));
551 	set_tx_desc_last_seg(pdesc, (lastseg ? 1 : 0));
552 
553 	set_tx_desc_tx_buffer_size(pdesc, (u16)skb->len);
554 
555 	set_tx_desc_tx_buffer_address(pdesc, mapping);
556 
557 	if (rtlpriv->dm.useramask) {
558 		set_tx_desc_rate_id(pdesc, tcb_desc->ratr_index);
559 		set_tx_desc_macid(pdesc, tcb_desc->mac_id);
560 	} else {
561 		set_tx_desc_rate_id(pdesc, 0xC + tcb_desc->ratr_index);
562 		set_tx_desc_macid(pdesc, tcb_desc->ratr_index);
563 	}
564 
565 	if ((!ieee80211_is_data_qos(fc)) && ppsc->fwctrl_lps) {
566 		set_tx_desc_hwseq_en(pdesc, 1);
567 		set_tx_desc_pkt_id(pdesc, 8);
568 
569 		if (!defaultadapter)
570 			set_tx_desc_qos(pdesc, 1);
571 	}
572 
573 	set_tx_desc_more_frag(pdesc, (lastseg ? 0 : 1));
574 
575 	if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
576 	    is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
577 		set_tx_desc_bmc(pdesc, 1);
578 	}
579 
580 	RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
581 }
582 
583 void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw,
584 			     u8 *pdesc8, bool firstseg,
585 			     bool lastseg, struct sk_buff *skb)
586 {
587 	struct rtl_priv *rtlpriv = rtl_priv(hw);
588 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
589 	u8 fw_queue = QSLT_BEACON;
590 	__le32 *pdesc = (__le32 *)pdesc8;
591 
592 	dma_addr_t mapping = pci_map_single(rtlpci->pdev,
593 					    skb->data, skb->len,
594 					    PCI_DMA_TODEVICE);
595 
596 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
597 	__le16 fc = hdr->frame_control;
598 
599 	if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
600 		RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
601 			 "DMA mapping error\n");
602 		return;
603 	}
604 	clear_pci_tx_desc_content(pdesc, TX_DESC_SIZE);
605 
606 	if (firstseg)
607 		set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN);
608 
609 	set_tx_desc_tx_rate(pdesc, DESC_RATE1M);
610 
611 	set_tx_desc_seq(pdesc, 0);
612 
613 	set_tx_desc_linip(pdesc, 0);
614 
615 	set_tx_desc_queue_sel(pdesc, fw_queue);
616 
617 	set_tx_desc_first_seg(pdesc, 1);
618 	set_tx_desc_last_seg(pdesc, 1);
619 
620 	set_tx_desc_tx_buffer_size(pdesc, (u16)(skb->len));
621 
622 	set_tx_desc_tx_buffer_address(pdesc, mapping);
623 
624 	set_tx_desc_rate_id(pdesc, 7);
625 	set_tx_desc_macid(pdesc, 0);
626 
627 	set_tx_desc_own(pdesc, 1);
628 
629 	set_tx_desc_pkt_size(pdesc, (u16)(skb->len));
630 
631 	set_tx_desc_first_seg(pdesc, 1);
632 	set_tx_desc_last_seg(pdesc, 1);
633 
634 	set_tx_desc_offset(pdesc, 0x20);
635 
636 	set_tx_desc_use_rate(pdesc, 1);
637 
638 	if (!ieee80211_is_data_qos(fc)) {
639 		set_tx_desc_hwseq_en(pdesc, 1);
640 		set_tx_desc_pkt_id(pdesc, 8);
641 	}
642 
643 	RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
644 		      "H2C Tx Cmd Content", pdesc, TX_DESC_SIZE);
645 }
646 
647 void rtl92ce_set_desc(struct ieee80211_hw *hw, u8 *pdesc8, bool istx,
648 		      u8 desc_name, u8 *val)
649 {
650 	__le32 *pdesc = (__le32 *)pdesc8;
651 
652 	if (istx) {
653 		switch (desc_name) {
654 		case HW_DESC_OWN:
655 			wmb();
656 			set_tx_desc_own(pdesc, 1);
657 			break;
658 		case HW_DESC_TX_NEXTDESC_ADDR:
659 			set_tx_desc_next_desc_address(pdesc, *(u32 *)val);
660 			break;
661 		default:
662 			WARN_ONCE(true, "rtl8192ce: ERR txdesc :%d not processed\n",
663 				  desc_name);
664 			break;
665 		}
666 	} else {
667 		switch (desc_name) {
668 		case HW_DESC_RXOWN:
669 			wmb();
670 			set_rx_desc_own(pdesc, 1);
671 			break;
672 		case HW_DESC_RXBUFF_ADDR:
673 			set_rx_desc_buff_addr(pdesc, *(u32 *)val);
674 			break;
675 		case HW_DESC_RXPKT_LEN:
676 			set_rx_desc_pkt_len(pdesc, *(u32 *)val);
677 			break;
678 		case HW_DESC_RXERO:
679 			set_rx_desc_eor(pdesc, 1);
680 			break;
681 		default:
682 			WARN_ONCE(true, "rtl8192ce: ERR rxdesc :%d not processed\n",
683 				  desc_name);
684 			break;
685 		}
686 	}
687 }
688 
689 u64 rtl92ce_get_desc(struct ieee80211_hw *hw, u8 *p_desc8,
690 		     bool istx, u8 desc_name)
691 {
692 	u32 ret = 0;
693 	__le32 *p_desc = (__le32 *)p_desc8;
694 
695 	if (istx) {
696 		switch (desc_name) {
697 		case HW_DESC_OWN:
698 			ret = get_tx_desc_own(p_desc);
699 			break;
700 		case HW_DESC_TXBUFF_ADDR:
701 			ret = get_tx_desc_tx_buffer_address(p_desc);
702 			break;
703 		default:
704 			WARN_ONCE(true, "rtl8192ce: ERR txdesc :%d not processed\n",
705 				  desc_name);
706 			break;
707 		}
708 	} else {
709 		switch (desc_name) {
710 		case HW_DESC_OWN:
711 			ret = get_rx_desc_own(p_desc);
712 			break;
713 		case HW_DESC_RXPKT_LEN:
714 			ret = get_rx_desc_pkt_len(p_desc);
715 			break;
716 		case HW_DESC_RXBUFF_ADDR:
717 			ret = get_rx_desc_buff_addr(p_desc);
718 			break;
719 		default:
720 			WARN_ONCE(true, "rtl8192ce: ERR rxdesc :%d not processed\n",
721 				  desc_name);
722 			break;
723 		}
724 	}
725 	return ret;
726 }
727 
728 bool rtl92ce_is_tx_desc_closed(struct ieee80211_hw *hw,
729 			       u8 hw_queue, u16 index)
730 {
731 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
732 	struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
733 	u8 *entry = (u8 *)(&ring->desc[ring->idx]);
734 	u8 own = (u8)rtl92ce_get_desc(hw, entry, true, HW_DESC_OWN);
735 
736 	/*beacon packet will only use the first
737 	 *descriptor defautly,and the own may not
738 	 *be cleared by the hardware
739 	 */
740 	if (own)
741 		return false;
742 	return true;
743 }
744 
745 void rtl92ce_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
746 {
747 	struct rtl_priv *rtlpriv = rtl_priv(hw);
748 
749 	if (hw_queue == BEACON_QUEUE) {
750 		rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, BIT(4));
751 	} else {
752 		rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG,
753 			       BIT(0) << (hw_queue));
754 	}
755 }
756 
757