1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30 #include "../wifi.h" 31 #include "../core.h" 32 #include "../pci.h" 33 #include "../base.h" 34 #include "reg.h" 35 #include "def.h" 36 #include "phy.h" 37 #include "dm.h" 38 #include "../rtl8192c/dm_common.h" 39 #include "../rtl8192c/fw_common.h" 40 #include "../rtl8192c/phy_common.h" 41 #include "hw.h" 42 #include "rf.h" 43 #include "sw.h" 44 #include "trx.h" 45 #include "led.h" 46 47 #include <linux/module.h> 48 49 static void rtl92c_init_aspm_vars(struct ieee80211_hw *hw) 50 { 51 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 52 53 /*close ASPM for AMD defaultly */ 54 rtlpci->const_amdpci_aspm = 0; 55 56 /* 57 * ASPM PS mode. 58 * 0 - Disable ASPM, 59 * 1 - Enable ASPM without Clock Req, 60 * 2 - Enable ASPM with Clock Req, 61 * 3 - Alwyas Enable ASPM with Clock Req, 62 * 4 - Always Enable ASPM without Clock Req. 63 * set defult to RTL8192CE:3 RTL8192E:2 64 * */ 65 rtlpci->const_pci_aspm = 3; 66 67 /*Setting for PCI-E device */ 68 rtlpci->const_devicepci_aspm_setting = 0x03; 69 70 /*Setting for PCI-E bridge */ 71 rtlpci->const_hostpci_aspm_setting = 0x02; 72 73 /* 74 * In Hw/Sw Radio Off situation. 75 * 0 - Default, 76 * 1 - From ASPM setting without low Mac Pwr, 77 * 2 - From ASPM setting with low Mac Pwr, 78 * 3 - Bus D3 79 * set default to RTL8192CE:0 RTL8192SE:2 80 */ 81 rtlpci->const_hwsw_rfoff_d3 = 0; 82 83 /* 84 * This setting works for those device with 85 * backdoor ASPM setting such as EPHY setting. 86 * 0 - Not support ASPM, 87 * 1 - Support ASPM, 88 * 2 - According to chipset. 89 */ 90 rtlpci->const_support_pciaspm = 1; 91 } 92 93 int rtl92c_init_sw_vars(struct ieee80211_hw *hw) 94 { 95 int err; 96 struct rtl_priv *rtlpriv = rtl_priv(hw); 97 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 98 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 99 100 rtl8192ce_bt_reg_init(hw); 101 102 rtlpriv->dm.dm_initialgain_enable = true; 103 rtlpriv->dm.dm_flag = 0; 104 rtlpriv->dm.disable_framebursting = false; 105 rtlpriv->dm.thermalvalue = 0; 106 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13); 107 108 /* compatible 5G band 88ce just 2.4G band & smsp */ 109 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G; 110 rtlpriv->rtlhal.bandset = BAND_ON_2_4G; 111 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY; 112 113 rtlpci->receive_config = (RCR_APPFCS | 114 RCR_AMF | 115 RCR_ADF | 116 RCR_APP_MIC | 117 RCR_APP_ICV | 118 RCR_AICV | 119 RCR_ACRC32 | 120 RCR_AB | 121 RCR_AM | 122 RCR_APM | 123 RCR_APP_PHYST_RXFF | RCR_HTC_LOC_CTRL | 0); 124 125 rtlpci->irq_mask[0] = 126 (u32) (IMR_ROK | 127 IMR_VODOK | 128 IMR_VIDOK | 129 IMR_BEDOK | 130 IMR_BKDOK | 131 IMR_MGNTDOK | 132 IMR_HIGHDOK | IMR_BDOK | IMR_RDU | IMR_RXFOVW | 0); 133 134 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD | 0); 135 136 /* for debug level */ 137 rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug; 138 /* for LPS & IPS */ 139 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; 140 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; 141 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; 142 rtlpriv->cfg->mod_params->sw_crypto = 143 rtlpriv->cfg->mod_params->sw_crypto; 144 if (!rtlpriv->psc.inactiveps) 145 pr_info("rtl8192ce: Power Save off (module option)\n"); 146 if (!rtlpriv->psc.fwctrl_lps) 147 pr_info("rtl8192ce: FW Power Save off (module option)\n"); 148 rtlpriv->psc.reg_fwctrl_lps = 3; 149 rtlpriv->psc.reg_max_lps_awakeintvl = 5; 150 /* for ASPM, you can close aspm through 151 * set const_support_pciaspm = 0 */ 152 rtl92c_init_aspm_vars(hw); 153 154 if (rtlpriv->psc.reg_fwctrl_lps == 1) 155 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE; 156 else if (rtlpriv->psc.reg_fwctrl_lps == 2) 157 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE; 158 else if (rtlpriv->psc.reg_fwctrl_lps == 3) 159 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE; 160 161 /* for firmware buf */ 162 rtlpriv->rtlhal.pfirmware = vzalloc(0x4000); 163 if (!rtlpriv->rtlhal.pfirmware) { 164 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 165 "Can't alloc buffer for fw\n"); 166 return 1; 167 } 168 169 /* request fw */ 170 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) && 171 !IS_92C_SERIAL(rtlhal->version)) 172 rtlpriv->cfg->fw_name = "rtlwifi/rtl8192cfwU.bin"; 173 else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) 174 rtlpriv->cfg->fw_name = "rtlwifi/rtl8192cfwU_B.bin"; 175 176 rtlpriv->max_fw_size = 0x4000; 177 pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name); 178 err = request_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name, 179 rtlpriv->io.dev, GFP_KERNEL, hw, 180 rtl_fw_cb); 181 if (err) { 182 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 183 "Failed to request firmware!\n"); 184 return 1; 185 } 186 187 return 0; 188 } 189 190 void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw) 191 { 192 struct rtl_priv *rtlpriv = rtl_priv(hw); 193 194 if (rtlpriv->rtlhal.pfirmware) { 195 vfree(rtlpriv->rtlhal.pfirmware); 196 rtlpriv->rtlhal.pfirmware = NULL; 197 } 198 } 199 200 static struct rtl_hal_ops rtl8192ce_hal_ops = { 201 .init_sw_vars = rtl92c_init_sw_vars, 202 .deinit_sw_vars = rtl92c_deinit_sw_vars, 203 .read_eeprom_info = rtl92ce_read_eeprom_info, 204 .interrupt_recognized = rtl92ce_interrupt_recognized, 205 .hw_init = rtl92ce_hw_init, 206 .hw_disable = rtl92ce_card_disable, 207 .hw_suspend = rtl92ce_suspend, 208 .hw_resume = rtl92ce_resume, 209 .enable_interrupt = rtl92ce_enable_interrupt, 210 .disable_interrupt = rtl92ce_disable_interrupt, 211 .set_network_type = rtl92ce_set_network_type, 212 .set_chk_bssid = rtl92ce_set_check_bssid, 213 .set_qos = rtl92ce_set_qos, 214 .set_bcn_reg = rtl92ce_set_beacon_related_registers, 215 .set_bcn_intv = rtl92ce_set_beacon_interval, 216 .update_interrupt_mask = rtl92ce_update_interrupt_mask, 217 .get_hw_reg = rtl92ce_get_hw_reg, 218 .set_hw_reg = rtl92ce_set_hw_reg, 219 .update_rate_tbl = rtl92ce_update_hal_rate_tbl, 220 .fill_tx_desc = rtl92ce_tx_fill_desc, 221 .fill_tx_cmddesc = rtl92ce_tx_fill_cmddesc, 222 .query_rx_desc = rtl92ce_rx_query_desc, 223 .set_channel_access = rtl92ce_update_channel_access_setting, 224 .radio_onoff_checking = rtl92ce_gpio_radio_on_off_checking, 225 .set_bw_mode = rtl92c_phy_set_bw_mode, 226 .switch_channel = rtl92c_phy_sw_chnl, 227 .dm_watchdog = rtl92c_dm_watchdog, 228 .scan_operation_backup = rtl_phy_scan_operation_backup, 229 .set_rf_power_state = rtl92c_phy_set_rf_power_state, 230 .led_control = rtl92ce_led_control, 231 .set_desc = rtl92ce_set_desc, 232 .get_desc = rtl92ce_get_desc, 233 .is_tx_desc_closed = rtl92ce_is_tx_desc_closed, 234 .tx_polling = rtl92ce_tx_polling, 235 .enable_hw_sec = rtl92ce_enable_hw_security_config, 236 .set_key = rtl92ce_set_key, 237 .init_sw_leds = rtl92ce_init_sw_leds, 238 .get_bbreg = rtl92c_phy_query_bb_reg, 239 .set_bbreg = rtl92c_phy_set_bb_reg, 240 .set_rfreg = rtl92ce_phy_set_rf_reg, 241 .get_rfreg = rtl92c_phy_query_rf_reg, 242 .phy_rf6052_config = rtl92ce_phy_rf6052_config, 243 .phy_rf6052_set_cck_txpower = rtl92ce_phy_rf6052_set_cck_txpower, 244 .phy_rf6052_set_ofdm_txpower = rtl92ce_phy_rf6052_set_ofdm_txpower, 245 .config_bb_with_headerfile = _rtl92ce_phy_config_bb_with_headerfile, 246 .config_bb_with_pgheaderfile = _rtl92ce_phy_config_bb_with_pgheaderfile, 247 .phy_lc_calibrate = _rtl92ce_phy_lc_calibrate, 248 .phy_set_bw_mode_callback = rtl92ce_phy_set_bw_mode_callback, 249 .dm_dynamic_txpower = rtl92ce_dm_dynamic_txpower, 250 .get_btc_status = rtl_btc_status_false, 251 }; 252 253 static struct rtl_mod_params rtl92ce_mod_params = { 254 .sw_crypto = false, 255 .inactiveps = true, 256 .swctrl_lps = false, 257 .fwctrl_lps = true, 258 .debug = DBG_EMERG, 259 }; 260 261 static struct rtl_hal_cfg rtl92ce_hal_cfg = { 262 .bar_id = 2, 263 .write_readback = true, 264 .name = "rtl92c_pci", 265 .fw_name = "rtlwifi/rtl8192cfw.bin", 266 .ops = &rtl8192ce_hal_ops, 267 .mod_params = &rtl92ce_mod_params, 268 269 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, 270 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, 271 .maps[SYS_CLK] = REG_SYS_CLKR, 272 .maps[MAC_RCR_AM] = AM, 273 .maps[MAC_RCR_AB] = AB, 274 .maps[MAC_RCR_ACRC32] = ACRC32, 275 .maps[MAC_RCR_ACF] = ACF, 276 .maps[MAC_RCR_AAP] = AAP, 277 .maps[MAC_HIMR] = REG_HIMR, 278 .maps[MAC_HIMRE] = REG_HIMRE, 279 280 .maps[EFUSE_TEST] = REG_EFUSE_TEST, 281 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, 282 .maps[EFUSE_CLK] = 0, 283 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, 284 .maps[EFUSE_PWC_EV12V] = PWC_EV12V, 285 .maps[EFUSE_FEN_ELDR] = FEN_ELDR, 286 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN, 287 .maps[EFUSE_ANA8M] = EFUSE_ANA8M, 288 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE, 289 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, 290 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, 291 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES, 292 293 .maps[RWCAM] = REG_CAMCMD, 294 .maps[WCAMI] = REG_CAMWRITE, 295 .maps[RCAMO] = REG_CAMREAD, 296 .maps[CAMDBG] = REG_CAMDBG, 297 .maps[SECR] = REG_SECCFG, 298 .maps[SEC_CAM_NONE] = CAM_NONE, 299 .maps[SEC_CAM_WEP40] = CAM_WEP40, 300 .maps[SEC_CAM_TKIP] = CAM_TKIP, 301 .maps[SEC_CAM_AES] = CAM_AES, 302 .maps[SEC_CAM_WEP104] = CAM_WEP104, 303 304 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, 305 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, 306 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, 307 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, 308 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, 309 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, 310 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, 311 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, 312 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, 313 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, 314 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, 315 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, 316 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, 317 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, 318 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2, 319 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1, 320 321 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, 322 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, 323 .maps[RTL_IMR_BCNINT] = IMR_BCNINT, 324 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, 325 .maps[RTL_IMR_RDU] = IMR_RDU, 326 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, 327 .maps[RTL_IMR_BDOK] = IMR_BDOK, 328 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, 329 .maps[RTL_IMR_TBDER] = IMR_TBDER, 330 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, 331 .maps[RTL_IMR_TBDOK] = IMR_TBDOK, 332 .maps[RTL_IMR_BKDOK] = IMR_BKDOK, 333 .maps[RTL_IMR_BEDOK] = IMR_BEDOK, 334 .maps[RTL_IMR_VIDOK] = IMR_VIDOK, 335 .maps[RTL_IMR_VODOK] = IMR_VODOK, 336 .maps[RTL_IMR_ROK] = IMR_ROK, 337 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER), 338 339 .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M, 340 .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M, 341 .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M, 342 .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M, 343 .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M, 344 .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M, 345 .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M, 346 .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M, 347 .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M, 348 .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M, 349 .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M, 350 .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M, 351 352 .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7, 353 .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15, 354 }; 355 356 static const struct pci_device_id rtl92ce_pci_ids[] = { 357 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8191, rtl92ce_hal_cfg)}, 358 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8178, rtl92ce_hal_cfg)}, 359 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8177, rtl92ce_hal_cfg)}, 360 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8176, rtl92ce_hal_cfg)}, 361 {}, 362 }; 363 364 MODULE_DEVICE_TABLE(pci, rtl92ce_pci_ids); 365 366 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); 367 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); 368 MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>"); 369 MODULE_LICENSE("GPL"); 370 MODULE_DESCRIPTION("Realtek 8192C/8188C 802.11n PCI wireless"); 371 MODULE_FIRMWARE("rtlwifi/rtl8192cfw.bin"); 372 MODULE_FIRMWARE("rtlwifi/rtl8192cfwU.bin"); 373 MODULE_FIRMWARE("rtlwifi/rtl8192cfwU_B.bin"); 374 375 module_param_named(swenc, rtl92ce_mod_params.sw_crypto, bool, 0444); 376 module_param_named(debug, rtl92ce_mod_params.debug, int, 0444); 377 module_param_named(ips, rtl92ce_mod_params.inactiveps, bool, 0444); 378 module_param_named(swlps, rtl92ce_mod_params.swctrl_lps, bool, 0444); 379 module_param_named(fwlps, rtl92ce_mod_params.fwctrl_lps, bool, 0444); 380 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); 381 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n"); 382 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n"); 383 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n"); 384 MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)"); 385 386 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume); 387 388 static struct pci_driver rtl92ce_driver = { 389 .name = KBUILD_MODNAME, 390 .id_table = rtl92ce_pci_ids, 391 .probe = rtl_pci_probe, 392 .remove = rtl_pci_disconnect, 393 .driver.pm = &rtlwifi_pm_ops, 394 }; 395 396 module_pci_driver(rtl92ce_driver); 397