1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../pci.h" 28 #include "../ps.h" 29 #include "../core.h" 30 #include "reg.h" 31 #include "def.h" 32 #include "hw.h" 33 #include "phy.h" 34 #include "../rtl8192c/phy_common.h" 35 #include "rf.h" 36 #include "dm.h" 37 #include "../rtl8192c/dm_common.h" 38 #include "../rtl8192c/fw_common.h" 39 #include "table.h" 40 41 static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw); 42 43 u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw, 44 enum radio_path rfpath, u32 regaddr, u32 bitmask) 45 { 46 struct rtl_priv *rtlpriv = rtl_priv(hw); 47 u32 original_value, readback_value, bitshift; 48 struct rtl_phy *rtlphy = &(rtlpriv->phy); 49 50 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 51 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", 52 regaddr, rfpath, bitmask); 53 54 spin_lock(&rtlpriv->locks.rf_lock); 55 56 if (rtlphy->rf_mode != RF_OP_BY_FW) { 57 original_value = _rtl92c_phy_rf_serial_read(hw, 58 rfpath, regaddr); 59 } else { 60 original_value = _rtl92c_phy_fw_rf_serial_read(hw, 61 rfpath, regaddr); 62 } 63 64 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask); 65 readback_value = (original_value & bitmask) >> bitshift; 66 67 spin_unlock(&rtlpriv->locks.rf_lock); 68 69 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 70 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", 71 regaddr, rfpath, bitmask, original_value); 72 73 return readback_value; 74 } 75 76 bool rtl92c_phy_mac_config(struct ieee80211_hw *hw) 77 { 78 struct rtl_priv *rtlpriv = rtl_priv(hw); 79 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 80 bool is92c = IS_92C_SERIAL(rtlhal->version); 81 bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw); 82 83 if (is92c) 84 rtl_write_byte(rtlpriv, 0x14, 0x71); 85 else 86 rtl_write_byte(rtlpriv, 0x04CA, 0x0A); 87 return rtstatus; 88 } 89 90 bool rtl92c_phy_bb_config(struct ieee80211_hw *hw) 91 { 92 bool rtstatus = true; 93 struct rtl_priv *rtlpriv = rtl_priv(hw); 94 u16 regval; 95 u32 regvaldw; 96 u8 reg_hwparafile = 1; 97 98 _rtl92c_phy_init_bb_rf_register_definition(hw); 99 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 100 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, 101 regval | BIT(13) | BIT(0) | BIT(1)); 102 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83); 103 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb); 104 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB); 105 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 106 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE | 107 FEN_BB_GLB_RSTn | FEN_BBRSTB); 108 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); 109 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0); 110 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23)); 111 if (reg_hwparafile == 1) 112 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw); 113 return rtstatus; 114 } 115 116 void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw, 117 enum radio_path rfpath, 118 u32 regaddr, u32 bitmask, u32 data) 119 { 120 struct rtl_priv *rtlpriv = rtl_priv(hw); 121 struct rtl_phy *rtlphy = &(rtlpriv->phy); 122 u32 original_value, bitshift; 123 124 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 125 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 126 regaddr, bitmask, data, rfpath); 127 128 spin_lock(&rtlpriv->locks.rf_lock); 129 130 if (rtlphy->rf_mode != RF_OP_BY_FW) { 131 if (bitmask != RFREG_OFFSET_MASK) { 132 original_value = _rtl92c_phy_rf_serial_read(hw, 133 rfpath, 134 regaddr); 135 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask); 136 data = 137 ((original_value & (~bitmask)) | 138 (data << bitshift)); 139 } 140 141 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data); 142 } else { 143 if (bitmask != RFREG_OFFSET_MASK) { 144 original_value = _rtl92c_phy_fw_rf_serial_read(hw, 145 rfpath, 146 regaddr); 147 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask); 148 data = 149 ((original_value & (~bitmask)) | 150 (data << bitshift)); 151 } 152 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data); 153 } 154 155 spin_unlock(&rtlpriv->locks.rf_lock); 156 157 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 158 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 159 regaddr, bitmask, data, rfpath); 160 } 161 162 static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw) 163 { 164 struct rtl_priv *rtlpriv = rtl_priv(hw); 165 u32 i; 166 u32 arraylength; 167 u32 *ptrarray; 168 169 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n"); 170 arraylength = MAC_2T_ARRAYLENGTH; 171 ptrarray = RTL8192CEMAC_2T_ARRAY; 172 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CEMAC_2T_ARRAY\n"); 173 for (i = 0; i < arraylength; i = i + 2) 174 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]); 175 return true; 176 } 177 178 bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 179 u8 configtype) 180 { 181 int i; 182 u32 *phy_regarray_table; 183 u32 *agctab_array_table; 184 u16 phy_reg_arraylen, agctab_arraylen; 185 struct rtl_priv *rtlpriv = rtl_priv(hw); 186 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 187 188 if (IS_92C_SERIAL(rtlhal->version)) { 189 agctab_arraylen = AGCTAB_2TARRAYLENGTH; 190 agctab_array_table = RTL8192CEAGCTAB_2TARRAY; 191 phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH; 192 phy_regarray_table = RTL8192CEPHY_REG_2TARRAY; 193 } else { 194 agctab_arraylen = AGCTAB_1TARRAYLENGTH; 195 agctab_array_table = RTL8192CEAGCTAB_1TARRAY; 196 phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH; 197 phy_regarray_table = RTL8192CEPHY_REG_1TARRAY; 198 } 199 if (configtype == BASEBAND_CONFIG_PHY_REG) { 200 for (i = 0; i < phy_reg_arraylen; i = i + 2) { 201 rtl_addr_delay(phy_regarray_table[i]); 202 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, 203 phy_regarray_table[i + 1]); 204 udelay(1); 205 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 206 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", 207 phy_regarray_table[i], 208 phy_regarray_table[i + 1]); 209 } 210 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 211 for (i = 0; i < agctab_arraylen; i = i + 2) { 212 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD, 213 agctab_array_table[i + 1]); 214 udelay(1); 215 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 216 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", 217 agctab_array_table[i], 218 agctab_array_table[i + 1]); 219 } 220 } 221 return true; 222 } 223 224 bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, 225 u8 configtype) 226 { 227 struct rtl_priv *rtlpriv = rtl_priv(hw); 228 int i; 229 u32 *phy_regarray_table_pg; 230 u16 phy_regarray_pg_len; 231 232 phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH; 233 phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG; 234 235 if (configtype == BASEBAND_CONFIG_PHY_REG) { 236 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { 237 rtl_addr_delay(phy_regarray_table_pg[i]); 238 239 _rtl92c_store_pwrIndex_diffrate_offset(hw, 240 phy_regarray_table_pg[i], 241 phy_regarray_table_pg[i + 1], 242 phy_regarray_table_pg[i + 2]); 243 } 244 } else { 245 246 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, 247 "configtype != BaseBand_Config_PHY_REG\n"); 248 } 249 return true; 250 } 251 252 bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, 253 enum radio_path rfpath) 254 { 255 256 int i; 257 u32 *radioa_array_table; 258 u32 *radiob_array_table; 259 u16 radioa_arraylen, radiob_arraylen; 260 struct rtl_priv *rtlpriv = rtl_priv(hw); 261 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 262 263 if (IS_92C_SERIAL(rtlhal->version)) { 264 radioa_arraylen = RADIOA_2TARRAYLENGTH; 265 radioa_array_table = RTL8192CERADIOA_2TARRAY; 266 radiob_arraylen = RADIOB_2TARRAYLENGTH; 267 radiob_array_table = RTL8192CE_RADIOB_2TARRAY; 268 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 269 "Radio_A:RTL8192CERADIOA_2TARRAY\n"); 270 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 271 "Radio_B:RTL8192CE_RADIOB_2TARRAY\n"); 272 } else { 273 radioa_arraylen = RADIOA_1TARRAYLENGTH; 274 radioa_array_table = RTL8192CE_RADIOA_1TARRAY; 275 radiob_arraylen = RADIOB_1TARRAYLENGTH; 276 radiob_array_table = RTL8192CE_RADIOB_1TARRAY; 277 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 278 "Radio_A:RTL8192CE_RADIOA_1TARRAY\n"); 279 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 280 "Radio_B:RTL8192CE_RADIOB_1TARRAY\n"); 281 } 282 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath); 283 switch (rfpath) { 284 case RF90_PATH_A: 285 for (i = 0; i < radioa_arraylen; i = i + 2) { 286 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i], 287 RFREG_OFFSET_MASK, 288 radioa_array_table[i + 1]); 289 } 290 break; 291 case RF90_PATH_B: 292 for (i = 0; i < radiob_arraylen; i = i + 2) { 293 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i], 294 RFREG_OFFSET_MASK, 295 radiob_array_table[i + 1]); 296 } 297 break; 298 case RF90_PATH_C: 299 case RF90_PATH_D: 300 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 301 "switch case %#x not processed\n", rfpath); 302 break; 303 default: 304 break; 305 } 306 return true; 307 } 308 309 void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw) 310 { 311 struct rtl_priv *rtlpriv = rtl_priv(hw); 312 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 313 struct rtl_phy *rtlphy = &(rtlpriv->phy); 314 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 315 u8 reg_bw_opmode; 316 u8 reg_prsr_rsc; 317 318 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n", 319 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 320 "20MHz" : "40MHz"); 321 322 if (is_hal_stop(rtlhal)) { 323 rtlphy->set_bwmode_inprogress = false; 324 return; 325 } 326 327 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE); 328 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2); 329 330 switch (rtlphy->current_chan_bw) { 331 case HT_CHANNEL_WIDTH_20: 332 reg_bw_opmode |= BW_OPMODE_20MHZ; 333 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 334 break; 335 case HT_CHANNEL_WIDTH_20_40: 336 reg_bw_opmode &= ~BW_OPMODE_20MHZ; 337 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 338 reg_prsr_rsc = 339 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5); 340 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc); 341 break; 342 default: 343 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 344 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); 345 break; 346 } 347 348 switch (rtlphy->current_chan_bw) { 349 case HT_CHANNEL_WIDTH_20: 350 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); 351 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); 352 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); 353 break; 354 case HT_CHANNEL_WIDTH_20_40: 355 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); 356 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); 357 358 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, 359 (mac->cur_40_prime_sc >> 1)); 360 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); 361 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0); 362 363 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), 364 (mac->cur_40_prime_sc == 365 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); 366 break; 367 default: 368 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 369 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); 370 break; 371 } 372 rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); 373 rtlphy->set_bwmode_inprogress = false; 374 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); 375 } 376 377 void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) 378 { 379 u8 tmpreg; 380 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal; 381 struct rtl_priv *rtlpriv = rtl_priv(hw); 382 383 tmpreg = rtl_read_byte(rtlpriv, 0xd03); 384 385 if ((tmpreg & 0x70) != 0) 386 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); 387 else 388 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 389 390 if ((tmpreg & 0x70) != 0) { 391 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); 392 393 if (is2t) 394 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, 395 MASK12BITS); 396 397 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, 398 (rf_a_mode & 0x8FFFF) | 0x10000); 399 400 if (is2t) 401 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, 402 (rf_b_mode & 0x8FFFF) | 0x10000); 403 } 404 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); 405 406 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); 407 408 mdelay(100); 409 410 if ((tmpreg & 0x70) != 0) { 411 rtl_write_byte(rtlpriv, 0xd03, tmpreg); 412 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); 413 414 if (is2t) 415 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, 416 rf_b_mode); 417 } else { 418 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 419 } 420 } 421 422 static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw) 423 { 424 u32 u4b_tmp; 425 u8 delay = 5; 426 struct rtl_priv *rtlpriv = rtl_priv(hw); 427 428 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 429 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 430 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 431 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); 432 while (u4b_tmp != 0 && delay > 0) { 433 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); 434 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 435 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 436 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); 437 delay--; 438 } 439 if (delay == 0) { 440 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); 441 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 442 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); 443 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); 444 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, 445 "Switch RF timeout !!!\n"); 446 return; 447 } 448 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 449 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); 450 } 451 452 static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw, 453 enum rf_pwrstate rfpwr_state) 454 { 455 struct rtl_priv *rtlpriv = rtl_priv(hw); 456 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 457 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 458 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 459 bool bresult = true; 460 u8 i, queue_id; 461 struct rtl8192_tx_ring *ring = NULL; 462 463 switch (rfpwr_state) { 464 case ERFON:{ 465 if ((ppsc->rfpwr_state == ERFOFF) && 466 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { 467 bool rtstatus; 468 u32 InitializeCount = 0; 469 do { 470 InitializeCount++; 471 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 472 "IPS Set eRf nic enable\n"); 473 rtstatus = rtl_ps_enable_nic(hw); 474 } while (!rtstatus && (InitializeCount < 10)); 475 RT_CLEAR_PS_LEVEL(ppsc, 476 RT_RF_OFF_LEVL_HALT_NIC); 477 } else { 478 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 479 "Set ERFON sleeped:%d ms\n", 480 jiffies_to_msecs(jiffies - 481 ppsc-> 482 last_sleep_jiffies)); 483 ppsc->last_awake_jiffies = jiffies; 484 rtl92ce_phy_set_rf_on(hw); 485 } 486 if (mac->link_state == MAC80211_LINKED) { 487 rtlpriv->cfg->ops->led_control(hw, 488 LED_CTL_LINK); 489 } else { 490 rtlpriv->cfg->ops->led_control(hw, 491 LED_CTL_NO_LINK); 492 } 493 break; 494 } 495 case ERFOFF:{ 496 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { 497 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 498 "IPS Set eRf nic disable\n"); 499 rtl_ps_disable_nic(hw); 500 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 501 } else { 502 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) { 503 rtlpriv->cfg->ops->led_control(hw, 504 LED_CTL_NO_LINK); 505 } else { 506 rtlpriv->cfg->ops->led_control(hw, 507 LED_CTL_POWER_OFF); 508 } 509 } 510 break; 511 } 512 case ERFSLEEP:{ 513 if (ppsc->rfpwr_state == ERFOFF) 514 break; 515 for (queue_id = 0, i = 0; 516 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) { 517 ring = &pcipriv->dev.tx_ring[queue_id]; 518 if (queue_id == BEACON_QUEUE || 519 skb_queue_len(&ring->queue) == 0) { 520 queue_id++; 521 continue; 522 } else { 523 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 524 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n", 525 i + 1, queue_id, 526 skb_queue_len(&ring->queue)); 527 528 udelay(10); 529 i++; 530 } 531 if (i >= MAX_DOZE_WAITING_TIMES_9x) { 532 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 533 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n", 534 MAX_DOZE_WAITING_TIMES_9x, 535 queue_id, 536 skb_queue_len(&ring->queue)); 537 break; 538 } 539 } 540 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 541 "Set ERFSLEEP awaked:%d ms\n", 542 jiffies_to_msecs(jiffies - 543 ppsc->last_awake_jiffies)); 544 ppsc->last_sleep_jiffies = jiffies; 545 _rtl92ce_phy_set_rf_sleep(hw); 546 break; 547 } 548 default: 549 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 550 "switch case %#x not processed\n", rfpwr_state); 551 bresult = false; 552 break; 553 } 554 if (bresult) 555 ppsc->rfpwr_state = rfpwr_state; 556 return bresult; 557 } 558 559 bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw, 560 enum rf_pwrstate rfpwr_state) 561 { 562 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 563 564 bool bresult = false; 565 566 if (rfpwr_state == ppsc->rfpwr_state) 567 return bresult; 568 bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state); 569 return bresult; 570 } 571