1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../regd.h" 30 #include "../cam.h" 31 #include "../ps.h" 32 #include "../pci.h" 33 #include "reg.h" 34 #include "def.h" 35 #include "phy.h" 36 #include "../rtl8192c/dm_common.h" 37 #include "../rtl8192c/fw_common.h" 38 #include "../rtl8192c/phy_common.h" 39 #include "dm.h" 40 #include "led.h" 41 #include "hw.h" 42 43 #define LLT_CONFIG 5 44 45 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 46 u8 set_bits, u8 clear_bits) 47 { 48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 49 struct rtl_priv *rtlpriv = rtl_priv(hw); 50 51 rtlpci->reg_bcn_ctrl_val |= set_bits; 52 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 53 54 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 55 } 56 57 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw) 58 { 59 struct rtl_priv *rtlpriv = rtl_priv(hw); 60 u8 tmp1byte; 61 62 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 63 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 64 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 65 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 66 tmp1byte &= ~(BIT(0)); 67 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 68 } 69 70 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw) 71 { 72 struct rtl_priv *rtlpriv = rtl_priv(hw); 73 u8 tmp1byte; 74 75 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 76 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 77 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 78 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 79 tmp1byte |= BIT(0); 80 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 81 } 82 83 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw) 84 { 85 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1)); 86 } 87 88 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw) 89 { 90 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0); 91 } 92 93 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 94 { 95 struct rtl_priv *rtlpriv = rtl_priv(hw); 96 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 97 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 98 99 switch (variable) { 100 case HW_VAR_RCR: 101 *((u32 *) (val)) = rtlpci->receive_config; 102 break; 103 case HW_VAR_RF_STATE: 104 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 105 break; 106 case HW_VAR_FWLPS_RF_ON:{ 107 enum rf_pwrstate rfState; 108 u32 val_rcr; 109 110 rtlpriv->cfg->ops->get_hw_reg(hw, 111 HW_VAR_RF_STATE, 112 (u8 *) (&rfState)); 113 if (rfState == ERFOFF) { 114 *((bool *) (val)) = true; 115 } else { 116 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 117 val_rcr &= 0x00070000; 118 if (val_rcr) 119 *((bool *) (val)) = false; 120 else 121 *((bool *) (val)) = true; 122 } 123 break; 124 } 125 case HW_VAR_FW_PSMODE_STATUS: 126 *((bool *) (val)) = ppsc->fw_current_inpsmode; 127 break; 128 case HW_VAR_CORRECT_TSF:{ 129 u64 tsf; 130 u32 *ptsf_low = (u32 *)&tsf; 131 u32 *ptsf_high = ((u32 *)&tsf) + 1; 132 133 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 134 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 135 136 *((u64 *) (val)) = tsf; 137 138 break; 139 } 140 case HAL_DEF_WOWLAN: 141 break; 142 default: 143 pr_err("switch case %#x not processed\n", variable); 144 break; 145 } 146 } 147 148 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 149 { 150 struct rtl_priv *rtlpriv = rtl_priv(hw); 151 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 152 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 153 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 154 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 155 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 156 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 157 u8 idx; 158 159 switch (variable) { 160 case HW_VAR_ETHER_ADDR:{ 161 for (idx = 0; idx < ETH_ALEN; idx++) { 162 rtl_write_byte(rtlpriv, (REG_MACID + idx), 163 val[idx]); 164 } 165 break; 166 } 167 case HW_VAR_BASIC_RATE:{ 168 u16 rate_cfg = ((u16 *) val)[0]; 169 u8 rate_index = 0; 170 rate_cfg &= 0x15f; 171 rate_cfg |= 0x01; 172 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); 173 rtl_write_byte(rtlpriv, REG_RRSR + 1, 174 (rate_cfg >> 8) & 0xff); 175 while (rate_cfg > 0x1) { 176 rate_cfg = (rate_cfg >> 1); 177 rate_index++; 178 } 179 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 180 rate_index); 181 break; 182 } 183 case HW_VAR_BSSID:{ 184 for (idx = 0; idx < ETH_ALEN; idx++) { 185 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 186 val[idx]); 187 } 188 break; 189 } 190 case HW_VAR_SIFS:{ 191 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 192 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); 193 194 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 195 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 196 197 if (!mac->ht_enable) 198 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 199 0x0e0e); 200 else 201 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 202 *((u16 *) val)); 203 break; 204 } 205 case HW_VAR_SLOT_TIME:{ 206 u8 e_aci; 207 208 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 209 "HW_VAR_SLOT_TIME %x\n", val[0]); 210 211 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 212 213 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 214 rtlpriv->cfg->ops->set_hw_reg(hw, 215 HW_VAR_AC_PARAM, 216 &e_aci); 217 } 218 break; 219 } 220 case HW_VAR_ACK_PREAMBLE:{ 221 u8 reg_tmp; 222 u8 short_preamble = (bool)*val; 223 reg_tmp = (mac->cur_40_prime_sc) << 5; 224 if (short_preamble) 225 reg_tmp |= 0x80; 226 227 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 228 break; 229 } 230 case HW_VAR_AMPDU_MIN_SPACE:{ 231 u8 min_spacing_to_set; 232 u8 sec_min_space; 233 234 min_spacing_to_set = *val; 235 if (min_spacing_to_set <= 7) { 236 sec_min_space = 0; 237 238 if (min_spacing_to_set < sec_min_space) 239 min_spacing_to_set = sec_min_space; 240 241 mac->min_space_cfg = ((mac->min_space_cfg & 242 0xf8) | 243 min_spacing_to_set); 244 245 *val = min_spacing_to_set; 246 247 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 248 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 249 mac->min_space_cfg); 250 251 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 252 mac->min_space_cfg); 253 } 254 break; 255 } 256 case HW_VAR_SHORTGI_DENSITY:{ 257 u8 density_to_set; 258 259 density_to_set = *val; 260 mac->min_space_cfg |= (density_to_set << 3); 261 262 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 263 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 264 mac->min_space_cfg); 265 266 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 267 mac->min_space_cfg); 268 269 break; 270 } 271 case HW_VAR_AMPDU_FACTOR:{ 272 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; 273 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97}; 274 275 u8 factor_toset; 276 u8 *p_regtoset = NULL; 277 u8 index = 0; 278 279 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 280 (rtlpcipriv->bt_coexist.bt_coexist_type == 281 BT_CSR_BC4)) 282 p_regtoset = regtoset_bt; 283 else 284 p_regtoset = regtoset_normal; 285 286 factor_toset = *(val); 287 if (factor_toset <= 3) { 288 factor_toset = (1 << (factor_toset + 2)); 289 if (factor_toset > 0xf) 290 factor_toset = 0xf; 291 292 for (index = 0; index < 4; index++) { 293 if ((p_regtoset[index] & 0xf0) > 294 (factor_toset << 4)) 295 p_regtoset[index] = 296 (p_regtoset[index] & 0x0f) | 297 (factor_toset << 4); 298 299 if ((p_regtoset[index] & 0x0f) > 300 factor_toset) 301 p_regtoset[index] = 302 (p_regtoset[index] & 0xf0) | 303 (factor_toset); 304 305 rtl_write_byte(rtlpriv, 306 (REG_AGGLEN_LMT + index), 307 p_regtoset[index]); 308 309 } 310 311 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 312 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 313 factor_toset); 314 } 315 break; 316 } 317 case HW_VAR_AC_PARAM:{ 318 u8 e_aci = *(val); 319 rtl92c_dm_init_edca_turbo(hw); 320 321 if (rtlpci->acm_method != EACMWAY2_SW) 322 rtlpriv->cfg->ops->set_hw_reg(hw, 323 HW_VAR_ACM_CTRL, 324 (&e_aci)); 325 break; 326 } 327 case HW_VAR_ACM_CTRL:{ 328 u8 e_aci = *(val); 329 union aci_aifsn *p_aci_aifsn = 330 (union aci_aifsn *)(&(mac->ac[0].aifs)); 331 u8 acm = p_aci_aifsn->f.acm; 332 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 333 334 acm_ctrl = 335 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 336 337 if (acm) { 338 switch (e_aci) { 339 case AC0_BE: 340 acm_ctrl |= AcmHw_BeqEn; 341 break; 342 case AC2_VI: 343 acm_ctrl |= AcmHw_ViqEn; 344 break; 345 case AC3_VO: 346 acm_ctrl |= AcmHw_VoqEn; 347 break; 348 default: 349 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 350 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 351 acm); 352 break; 353 } 354 } else { 355 switch (e_aci) { 356 case AC0_BE: 357 acm_ctrl &= (~AcmHw_BeqEn); 358 break; 359 case AC2_VI: 360 acm_ctrl &= (~AcmHw_ViqEn); 361 break; 362 case AC3_VO: 363 acm_ctrl &= (~AcmHw_VoqEn); 364 break; 365 default: 366 pr_err("switch case %#x not processed\n", 367 e_aci); 368 break; 369 } 370 } 371 372 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 373 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 374 acm_ctrl); 375 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 376 break; 377 } 378 case HW_VAR_RCR:{ 379 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); 380 rtlpci->receive_config = ((u32 *) (val))[0]; 381 break; 382 } 383 case HW_VAR_RETRY_LIMIT:{ 384 u8 retry_limit = val[0]; 385 386 rtl_write_word(rtlpriv, REG_RL, 387 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 388 retry_limit << RETRY_LIMIT_LONG_SHIFT); 389 break; 390 } 391 case HW_VAR_DUAL_TSF_RST: 392 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 393 break; 394 case HW_VAR_EFUSE_BYTES: 395 rtlefuse->efuse_usedbytes = *((u16 *) val); 396 break; 397 case HW_VAR_EFUSE_USAGE: 398 rtlefuse->efuse_usedpercentage = *val; 399 break; 400 case HW_VAR_IO_CMD: 401 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val)); 402 break; 403 case HW_VAR_WPA_CONFIG: 404 rtl_write_byte(rtlpriv, REG_SECCFG, *val); 405 break; 406 case HW_VAR_SET_RPWM:{ 407 u8 rpwm_val; 408 409 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 410 udelay(1); 411 412 if (rpwm_val & BIT(7)) { 413 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val); 414 } else { 415 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 416 *val | BIT(7)); 417 } 418 419 break; 420 } 421 case HW_VAR_H2C_FW_PWRMODE:{ 422 u8 psmode = *val; 423 424 if ((psmode != FW_PS_ACTIVE_MODE) && 425 (!IS_92C_SERIAL(rtlhal->version))) { 426 rtl92c_dm_rf_saving(hw, true); 427 } 428 429 rtl92c_set_fw_pwrmode_cmd(hw, *val); 430 break; 431 } 432 case HW_VAR_FW_PSMODE_STATUS: 433 ppsc->fw_current_inpsmode = *((bool *) val); 434 break; 435 case HW_VAR_H2C_FW_JOINBSSRPT:{ 436 u8 mstatus = *val; 437 u8 tmp_regcr, tmp_reg422; 438 bool recover = false; 439 440 if (mstatus == RT_MEDIA_CONNECT) { 441 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, 442 NULL); 443 444 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 445 rtl_write_byte(rtlpriv, REG_CR + 1, 446 (tmp_regcr | BIT(0))); 447 448 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); 449 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0); 450 451 tmp_reg422 = 452 rtl_read_byte(rtlpriv, 453 REG_FWHW_TXQ_CTRL + 2); 454 if (tmp_reg422 & BIT(6)) 455 recover = true; 456 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 457 tmp_reg422 & (~BIT(6))); 458 459 rtl92c_set_fw_rsvdpagepkt(hw, NULL); 460 461 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); 462 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); 463 464 if (recover) { 465 rtl_write_byte(rtlpriv, 466 REG_FWHW_TXQ_CTRL + 2, 467 tmp_reg422); 468 } 469 470 rtl_write_byte(rtlpriv, REG_CR + 1, 471 (tmp_regcr & ~(BIT(0)))); 472 } 473 rtl92c_set_fw_joinbss_report_cmd(hw, *val); 474 475 break; 476 } 477 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: 478 rtl92c_set_p2p_ps_offload_cmd(hw, *val); 479 break; 480 case HW_VAR_AID:{ 481 u16 u2btmp; 482 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 483 u2btmp &= 0xC000; 484 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | 485 mac->assoc_id)); 486 487 break; 488 } 489 case HW_VAR_CORRECT_TSF:{ 490 u8 btype_ibss = val[0]; 491 492 if (btype_ibss) 493 _rtl92ce_stop_tx_beacon(hw); 494 495 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); 496 497 rtl_write_dword(rtlpriv, REG_TSFTR, 498 (u32) (mac->tsf & 0xffffffff)); 499 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 500 (u32) ((mac->tsf >> 32) & 0xffffffff)); 501 502 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); 503 504 if (btype_ibss) 505 _rtl92ce_resume_tx_beacon(hw); 506 507 break; 508 509 } 510 case HW_VAR_FW_LPS_ACTION: { 511 bool enter_fwlps = *((bool *)val); 512 u8 rpwm_val, fw_pwrmode; 513 bool fw_current_inps; 514 515 if (enter_fwlps) { 516 rpwm_val = 0x02; /* RF off */ 517 fw_current_inps = true; 518 rtlpriv->cfg->ops->set_hw_reg(hw, 519 HW_VAR_FW_PSMODE_STATUS, 520 (u8 *)(&fw_current_inps)); 521 rtlpriv->cfg->ops->set_hw_reg(hw, 522 HW_VAR_H2C_FW_PWRMODE, 523 &ppsc->fwctrl_psmode); 524 525 rtlpriv->cfg->ops->set_hw_reg(hw, 526 HW_VAR_SET_RPWM, 527 &rpwm_val); 528 } else { 529 rpwm_val = 0x0C; /* RF on */ 530 fw_pwrmode = FW_PS_ACTIVE_MODE; 531 fw_current_inps = false; 532 rtlpriv->cfg->ops->set_hw_reg(hw, 533 HW_VAR_SET_RPWM, 534 &rpwm_val); 535 rtlpriv->cfg->ops->set_hw_reg(hw, 536 HW_VAR_H2C_FW_PWRMODE, 537 &fw_pwrmode); 538 539 rtlpriv->cfg->ops->set_hw_reg(hw, 540 HW_VAR_FW_PSMODE_STATUS, 541 (u8 *)(&fw_current_inps)); 542 } 543 break; } 544 case HW_VAR_KEEP_ALIVE: { 545 u8 array[2]; 546 547 array[0] = 0xff; 548 array[1] = *((u8 *)val); 549 rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2, array); 550 break; } 551 default: 552 pr_err("switch case %d not processed\n", variable); 553 break; 554 } 555 } 556 557 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 558 { 559 struct rtl_priv *rtlpriv = rtl_priv(hw); 560 bool status = true; 561 long count = 0; 562 u32 value = _LLT_INIT_ADDR(address) | 563 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); 564 565 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 566 567 do { 568 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 569 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 570 break; 571 572 if (count > POLLING_LLT_THRESHOLD) { 573 pr_err("Failed to polling write LLT done at address %d!\n", 574 address); 575 status = false; 576 break; 577 } 578 } while (++count); 579 580 return status; 581 } 582 583 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw) 584 { 585 struct rtl_priv *rtlpriv = rtl_priv(hw); 586 unsigned short i; 587 u8 txpktbuf_bndy; 588 u8 maxPage; 589 bool status; 590 591 #if LLT_CONFIG == 1 592 maxPage = 255; 593 txpktbuf_bndy = 252; 594 #elif LLT_CONFIG == 2 595 maxPage = 127; 596 txpktbuf_bndy = 124; 597 #elif LLT_CONFIG == 3 598 maxPage = 255; 599 txpktbuf_bndy = 174; 600 #elif LLT_CONFIG == 4 601 maxPage = 255; 602 txpktbuf_bndy = 246; 603 #elif LLT_CONFIG == 5 604 maxPage = 255; 605 txpktbuf_bndy = 246; 606 #endif 607 608 #if LLT_CONFIG == 1 609 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c); 610 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c); 611 #elif LLT_CONFIG == 2 612 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010); 613 #elif LLT_CONFIG == 3 614 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484); 615 #elif LLT_CONFIG == 4 616 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c); 617 #elif LLT_CONFIG == 5 618 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000); 619 620 rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29); 621 #endif 622 623 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy)); 624 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 625 626 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 627 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 628 629 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); 630 rtl_write_byte(rtlpriv, REG_PBP, 0x11); 631 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 632 633 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 634 status = _rtl92ce_llt_write(hw, i, i + 1); 635 if (true != status) 636 return status; 637 } 638 639 status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 640 if (true != status) 641 return status; 642 643 for (i = txpktbuf_bndy; i < maxPage; i++) { 644 status = _rtl92ce_llt_write(hw, i, (i + 1)); 645 if (true != status) 646 return status; 647 } 648 649 status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy); 650 if (true != status) 651 return status; 652 653 return true; 654 } 655 656 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw) 657 { 658 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 659 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 660 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 661 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0); 662 663 if (rtlpci->up_first_time) 664 return; 665 666 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 667 rtl92ce_sw_led_on(hw, pLed0); 668 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 669 rtl92ce_sw_led_on(hw, pLed0); 670 else 671 rtl92ce_sw_led_off(hw, pLed0); 672 } 673 674 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw) 675 { 676 struct rtl_priv *rtlpriv = rtl_priv(hw); 677 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 678 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 679 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 680 681 unsigned char bytetmp; 682 unsigned short wordtmp; 683 u16 retry; 684 685 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 686 if (rtlpcipriv->bt_coexist.bt_coexistence) { 687 u32 value32; 688 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO); 689 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK); 690 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32); 691 } 692 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 693 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F); 694 695 if (rtlpcipriv->bt_coexist.bt_coexistence) { 696 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL); 697 698 u4b_tmp &= (~0x00024800); 699 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp); 700 } 701 702 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0); 703 udelay(2); 704 705 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); 706 udelay(2); 707 708 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); 709 udelay(2); 710 711 retry = 0; 712 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n", 713 rtl_read_dword(rtlpriv, 0xEC), bytetmp); 714 715 while ((bytetmp & BIT(0)) && retry < 1000) { 716 retry++; 717 udelay(50); 718 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); 719 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n", 720 rtl_read_dword(rtlpriv, 0xEC), bytetmp); 721 udelay(50); 722 } 723 724 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012); 725 726 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82); 727 udelay(2); 728 729 if (rtlpcipriv->bt_coexist.bt_coexistence) { 730 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd; 731 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp); 732 } 733 734 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 735 736 if (!_rtl92ce_llt_table_init(hw)) 737 return false; 738 739 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 740 rtl_write_byte(rtlpriv, REG_HISRE, 0xff); 741 742 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff); 743 744 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 745 wordtmp &= 0xf; 746 wordtmp |= 0xF771; 747 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 748 749 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 750 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 751 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); 752 753 rtl_write_byte(rtlpriv, 0x4d0, 0x0); 754 755 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 756 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) & 757 DMA_BIT_MASK(32)); 758 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 759 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma & 760 DMA_BIT_MASK(32)); 761 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 762 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 763 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 764 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 765 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 766 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 767 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 768 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 769 rtl_write_dword(rtlpriv, REG_HQ_DESA, 770 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma & 771 DMA_BIT_MASK(32)); 772 rtl_write_dword(rtlpriv, REG_RX_DESA, 773 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma & 774 DMA_BIT_MASK(32)); 775 776 if (IS_92C_SERIAL(rtlhal->version)) 777 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77); 778 else 779 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22); 780 781 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 782 783 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 784 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); 785 do { 786 retry++; 787 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 788 } while ((retry < 200) && (bytetmp & BIT(7))); 789 790 _rtl92ce_gen_refresh_led_state(hw); 791 792 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); 793 794 return true; 795 } 796 797 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw) 798 { 799 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 800 struct rtl_priv *rtlpriv = rtl_priv(hw); 801 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 802 u8 reg_bw_opmode; 803 u32 reg_prsr; 804 805 reg_bw_opmode = BW_OPMODE_20MHZ; 806 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 807 808 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); 809 810 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 811 812 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr); 813 814 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 815 816 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); 817 818 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); 819 820 rtl_write_word(rtlpriv, REG_RL, 0x0707); 821 822 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); 823 824 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 825 826 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 827 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 828 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 829 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 830 831 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 832 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) 833 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431); 834 else 835 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); 836 837 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); 838 839 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); 840 841 rtlpci->reg_bcn_ctrl_val = 0x1f; 842 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 843 844 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 845 846 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 847 848 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); 849 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 850 851 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 852 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) { 853 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 854 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402); 855 } else { 856 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 857 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 858 } 859 860 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 861 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) 862 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); 863 else 864 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666); 865 866 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); 867 868 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); 869 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); 870 871 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); 872 873 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); 874 875 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); 876 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); 877 878 } 879 880 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw) 881 { 882 struct rtl_priv *rtlpriv = rtl_priv(hw); 883 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 884 885 rtl_write_byte(rtlpriv, 0x34b, 0x93); 886 rtl_write_word(rtlpriv, 0x350, 0x870c); 887 rtl_write_byte(rtlpriv, 0x352, 0x1); 888 889 if (ppsc->support_backdoor) 890 rtl_write_byte(rtlpriv, 0x349, 0x1b); 891 else 892 rtl_write_byte(rtlpriv, 0x349, 0x03); 893 894 rtl_write_word(rtlpriv, 0x350, 0x2718); 895 rtl_write_byte(rtlpriv, 0x352, 0x1); 896 } 897 898 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw) 899 { 900 struct rtl_priv *rtlpriv = rtl_priv(hw); 901 u8 sec_reg_value; 902 903 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 904 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 905 rtlpriv->sec.pairwise_enc_algorithm, 906 rtlpriv->sec.group_enc_algorithm); 907 908 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 909 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 910 "not open hw encryption\n"); 911 return; 912 } 913 914 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable; 915 916 if (rtlpriv->sec.use_defaultkey) { 917 sec_reg_value |= SCR_TxUseDK; 918 sec_reg_value |= SCR_RxUseDK; 919 } 920 921 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 922 923 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 924 925 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 926 "The SECR-value %x\n", sec_reg_value); 927 928 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 929 930 } 931 932 int rtl92ce_hw_init(struct ieee80211_hw *hw) 933 { 934 struct rtl_priv *rtlpriv = rtl_priv(hw); 935 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 936 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 937 struct rtl_phy *rtlphy = &(rtlpriv->phy); 938 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 939 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 940 bool rtstatus = true; 941 bool is92c; 942 int err; 943 u8 tmp_u1b; 944 unsigned long flags; 945 946 rtlpci->being_init_adapter = true; 947 948 /* Since this function can take a very long time (up to 350 ms) 949 * and can be called with irqs disabled, reenable the irqs 950 * to let the other devices continue being serviced. 951 * 952 * It is safe doing so since our own interrupts will only be enabled 953 * in a subsequent step. 954 */ 955 local_save_flags(flags); 956 local_irq_enable(); 957 958 rtlhal->fw_ready = false; 959 rtlpriv->intf_ops->disable_aspm(hw); 960 rtstatus = _rtl92ce_init_mac(hw); 961 if (!rtstatus) { 962 pr_err("Init MAC failed\n"); 963 err = 1; 964 goto exit; 965 } 966 967 err = rtl92c_download_fw(hw); 968 if (err) { 969 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 970 "Failed to download FW. Init HW without FW now..\n"); 971 err = 1; 972 goto exit; 973 } 974 975 rtlhal->fw_ready = true; 976 rtlhal->last_hmeboxnum = 0; 977 rtl92c_phy_mac_config(hw); 978 /* because last function modify RCR, so we update 979 * rcr var here, or TP will unstable for receive_config 980 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 981 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/ 982 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); 983 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 984 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 985 rtl92c_phy_bb_config(hw); 986 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 987 rtl92c_phy_rf_config(hw); 988 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) && 989 !IS_92C_SERIAL(rtlhal->version)) { 990 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); 991 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); 992 } else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) { 993 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE); 994 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31); 995 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425); 996 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200); 997 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053); 998 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201); 999 } 1000 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 1001 RF_CHNLBW, RFREG_OFFSET_MASK); 1002 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 1003 RF_CHNLBW, RFREG_OFFSET_MASK); 1004 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1005 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1006 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); 1007 _rtl92ce_hw_configure(hw); 1008 rtl_cam_reset_all_entry(hw); 1009 rtl92ce_enable_hw_security_config(hw); 1010 1011 ppsc->rfpwr_state = ERFON; 1012 1013 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1014 _rtl92ce_enable_aspm_back_door(hw); 1015 rtlpriv->intf_ops->enable_aspm(hw); 1016 1017 rtl8192ce_bt_hw_init(hw); 1018 1019 if (ppsc->rfpwr_state == ERFON) { 1020 rtl92c_phy_set_rfpath_switch(hw, 1); 1021 if (rtlphy->iqk_initialized) { 1022 rtl92c_phy_iq_calibrate(hw, true); 1023 } else { 1024 rtl92c_phy_iq_calibrate(hw, false); 1025 rtlphy->iqk_initialized = true; 1026 } 1027 1028 rtl92c_dm_check_txpower_tracking(hw); 1029 rtl92c_phy_lc_calibrate(hw); 1030 } 1031 1032 is92c = IS_92C_SERIAL(rtlhal->version); 1033 tmp_u1b = efuse_read_1byte(hw, 0x1FA); 1034 if (!(tmp_u1b & BIT(0))) { 1035 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); 1036 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n"); 1037 } 1038 1039 if (!(tmp_u1b & BIT(1)) && is92c) { 1040 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05); 1041 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n"); 1042 } 1043 1044 if (!(tmp_u1b & BIT(4))) { 1045 tmp_u1b = rtl_read_byte(rtlpriv, 0x16); 1046 tmp_u1b &= 0x0F; 1047 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80); 1048 udelay(10); 1049 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90); 1050 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n"); 1051 } 1052 rtl92c_dm_init(hw); 1053 exit: 1054 local_irq_restore(flags); 1055 rtlpci->being_init_adapter = false; 1056 return err; 1057 } 1058 1059 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw) 1060 { 1061 struct rtl_priv *rtlpriv = rtl_priv(hw); 1062 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1063 enum version_8192c version = VERSION_UNKNOWN; 1064 u32 value32; 1065 const char *versionid; 1066 1067 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 1068 if (value32 & TRP_VAUX_EN) { 1069 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C : 1070 VERSION_A_CHIP_88C; 1071 } else { 1072 version = (enum version_8192c) (CHIP_VER_B | 1073 ((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) | 1074 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); 1075 if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 & 1076 CHIP_VER_RTL_MASK)) { 1077 version = (enum version_8192c)(version | 1078 ((((value32 & CHIP_VER_RTL_MASK) == BIT(12)) 1079 ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) | 1080 CHIP_VENDOR_UMC)); 1081 } 1082 if (IS_92C_SERIAL(version)) { 1083 value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM); 1084 version = (enum version_8192c)(version | 1085 ((CHIP_BONDING_IDENTIFIER(value32) 1086 == CHIP_BONDING_92C_1T2R) ? 1087 RF_TYPE_1T2R : 0)); 1088 } 1089 } 1090 1091 switch (version) { 1092 case VERSION_B_CHIP_92C: 1093 versionid = "B_CHIP_92C"; 1094 break; 1095 case VERSION_B_CHIP_88C: 1096 versionid = "B_CHIP_88C"; 1097 break; 1098 case VERSION_A_CHIP_92C: 1099 versionid = "A_CHIP_92C"; 1100 break; 1101 case VERSION_A_CHIP_88C: 1102 versionid = "A_CHIP_88C"; 1103 break; 1104 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT: 1105 versionid = "A_CUT_92C_1T2R"; 1106 break; 1107 case VERSION_NORMAL_UMC_CHIP_92C_A_CUT: 1108 versionid = "A_CUT_92C"; 1109 break; 1110 case VERSION_NORMAL_UMC_CHIP_88C_A_CUT: 1111 versionid = "A_CUT_88C"; 1112 break; 1113 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT: 1114 versionid = "B_CUT_92C_1T2R"; 1115 break; 1116 case VERSION_NORMAL_UMC_CHIP_92C_B_CUT: 1117 versionid = "B_CUT_92C"; 1118 break; 1119 case VERSION_NORMAL_UMC_CHIP_88C_B_CUT: 1120 versionid = "B_CUT_88C"; 1121 break; 1122 default: 1123 versionid = "Unknown. Bug?"; 1124 break; 1125 } 1126 1127 pr_info("Chip Version ID: %s\n", versionid); 1128 1129 switch (version & 0x3) { 1130 case CHIP_88C: 1131 rtlphy->rf_type = RF_1T1R; 1132 break; 1133 case CHIP_92C: 1134 rtlphy->rf_type = RF_2T2R; 1135 break; 1136 case CHIP_92C_1T2R: 1137 rtlphy->rf_type = RF_1T2R; 1138 break; 1139 default: 1140 rtlphy->rf_type = RF_1T1R; 1141 pr_err("ERROR RF_Type is set!!\n"); 1142 break; 1143 } 1144 1145 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n", 1146 rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R"); 1147 1148 return version; 1149 } 1150 1151 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw, 1152 enum nl80211_iftype type) 1153 { 1154 struct rtl_priv *rtlpriv = rtl_priv(hw); 1155 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1156 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1157 u8 mode = MSR_NOLINK; 1158 1159 bt_msr &= 0xfc; 1160 1161 switch (type) { 1162 case NL80211_IFTYPE_UNSPECIFIED: 1163 mode = MSR_NOLINK; 1164 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1165 "Set Network type to NO LINK!\n"); 1166 break; 1167 case NL80211_IFTYPE_ADHOC: 1168 mode = MSR_ADHOC; 1169 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1170 "Set Network type to Ad Hoc!\n"); 1171 break; 1172 case NL80211_IFTYPE_STATION: 1173 mode = MSR_INFRA; 1174 ledaction = LED_CTL_LINK; 1175 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1176 "Set Network type to STA!\n"); 1177 break; 1178 case NL80211_IFTYPE_AP: 1179 mode = MSR_AP; 1180 ledaction = LED_CTL_LINK; 1181 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1182 "Set Network type to AP!\n"); 1183 break; 1184 case NL80211_IFTYPE_MESH_POINT: 1185 mode = MSR_ADHOC; 1186 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1187 "Set Network type to Mesh Point!\n"); 1188 break; 1189 default: 1190 pr_err("Network type %d not supported!\n", type); 1191 return 1; 1192 1193 } 1194 1195 /* MSR_INFRA == Link in infrastructure network; 1196 * MSR_ADHOC == Link in ad hoc network; 1197 * Therefore, check link state is necessary. 1198 * 1199 * MSR_AP == AP mode; link state does not matter here. 1200 */ 1201 if (mode != MSR_AP && 1202 rtlpriv->mac80211.link_state < MAC80211_LINKED) { 1203 mode = MSR_NOLINK; 1204 ledaction = LED_CTL_NO_LINK; 1205 } 1206 if (mode == MSR_NOLINK || mode == MSR_INFRA) { 1207 _rtl92ce_stop_tx_beacon(hw); 1208 _rtl92ce_enable_bcn_sub_func(hw); 1209 } else if (mode == MSR_ADHOC || mode == MSR_AP) { 1210 _rtl92ce_resume_tx_beacon(hw); 1211 _rtl92ce_disable_bcn_sub_func(hw); 1212 } else { 1213 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1214 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 1215 mode); 1216 } 1217 rtl_write_byte(rtlpriv, MSR, bt_msr | mode); 1218 1219 rtlpriv->cfg->ops->led_control(hw, ledaction); 1220 if (mode == MSR_AP) 1221 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1222 else 1223 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1224 return 0; 1225 } 1226 1227 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1228 { 1229 struct rtl_priv *rtlpriv = rtl_priv(hw); 1230 u32 reg_rcr; 1231 1232 if (rtlpriv->psc.rfpwr_state != ERFON) 1233 return; 1234 1235 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1236 1237 if (check_bssid) { 1238 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1239 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1240 (u8 *) (®_rcr)); 1241 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1242 } else if (!check_bssid) { 1243 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1244 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0); 1245 rtlpriv->cfg->ops->set_hw_reg(hw, 1246 HW_VAR_RCR, (u8 *) (®_rcr)); 1247 } 1248 1249 } 1250 1251 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1252 { 1253 struct rtl_priv *rtlpriv = rtl_priv(hw); 1254 1255 if (_rtl92ce_set_media_status(hw, type)) 1256 return -EOPNOTSUPP; 1257 1258 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1259 if (type != NL80211_IFTYPE_AP && 1260 type != NL80211_IFTYPE_MESH_POINT) 1261 rtl92ce_set_check_bssid(hw, true); 1262 } else { 1263 rtl92ce_set_check_bssid(hw, false); 1264 } 1265 1266 return 0; 1267 } 1268 1269 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ 1270 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci) 1271 { 1272 struct rtl_priv *rtlpriv = rtl_priv(hw); 1273 rtl92c_dm_init_edca_turbo(hw); 1274 switch (aci) { 1275 case AC1_BK: 1276 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 1277 break; 1278 case AC0_BE: 1279 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */ 1280 break; 1281 case AC2_VI: 1282 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 1283 break; 1284 case AC3_VO: 1285 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 1286 break; 1287 default: 1288 WARN_ONCE(true, "rtl8192ce: invalid aci: %d !\n", aci); 1289 break; 1290 } 1291 } 1292 1293 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw) 1294 { 1295 struct rtl_priv *rtlpriv = rtl_priv(hw); 1296 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1297 1298 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); 1299 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); 1300 rtlpci->irq_enabled = true; 1301 } 1302 1303 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw) 1304 { 1305 struct rtl_priv *rtlpriv = rtl_priv(hw); 1306 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1307 1308 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); 1309 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); 1310 rtlpci->irq_enabled = false; 1311 } 1312 1313 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw) 1314 { 1315 struct rtl_priv *rtlpriv = rtl_priv(hw); 1316 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1317 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1318 u8 u1b_tmp; 1319 u32 u4b_tmp; 1320 1321 rtlpriv->intf_ops->enable_aspm(hw); 1322 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1323 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 1324 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); 1325 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 1326 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 1327 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0); 1328 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) 1329 rtl92c_firmware_selfreset(hw); 1330 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51); 1331 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1332 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000); 1333 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL); 1334 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 1335 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) || 1336 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) { 1337 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 | 1338 (u1b_tmp << 8)); 1339 } else { 1340 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 | 1341 (u1b_tmp << 8)); 1342 } 1343 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790); 1344 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); 1345 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); 1346 if (!IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) 1347 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); 1348 if (rtlpcipriv->bt_coexist.bt_coexistence) { 1349 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL); 1350 u4b_tmp |= 0x03824800; 1351 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp); 1352 } else { 1353 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e); 1354 } 1355 1356 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); 1357 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10); 1358 } 1359 1360 void rtl92ce_card_disable(struct ieee80211_hw *hw) 1361 { 1362 struct rtl_priv *rtlpriv = rtl_priv(hw); 1363 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1364 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1365 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1366 enum nl80211_iftype opmode; 1367 1368 mac->link_state = MAC80211_NOLINK; 1369 opmode = NL80211_IFTYPE_UNSPECIFIED; 1370 _rtl92ce_set_media_status(hw, opmode); 1371 if (rtlpci->driver_is_goingto_unload || 1372 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1373 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1374 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1375 _rtl92ce_poweroff_adapter(hw); 1376 1377 /* after power off we should do iqk again */ 1378 rtlpriv->phy.iqk_initialized = false; 1379 } 1380 1381 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw, 1382 u32 *p_inta, u32 *p_intb) 1383 { 1384 struct rtl_priv *rtlpriv = rtl_priv(hw); 1385 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1386 1387 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 1388 rtl_write_dword(rtlpriv, ISR, *p_inta); 1389 1390 /* 1391 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; 1392 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb); 1393 */ 1394 } 1395 1396 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw) 1397 { 1398 1399 struct rtl_priv *rtlpriv = rtl_priv(hw); 1400 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1401 u16 bcn_interval, atim_window; 1402 1403 bcn_interval = mac->beacon_interval; 1404 atim_window = 2; /*FIX MERGE */ 1405 rtl92ce_disable_interrupt(hw); 1406 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1407 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1408 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 1409 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 1410 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 1411 rtl_write_byte(rtlpriv, 0x606, 0x30); 1412 rtl92ce_enable_interrupt(hw); 1413 } 1414 1415 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw) 1416 { 1417 struct rtl_priv *rtlpriv = rtl_priv(hw); 1418 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1419 u16 bcn_interval = mac->beacon_interval; 1420 1421 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, 1422 "beacon_interval:%d\n", bcn_interval); 1423 rtl92ce_disable_interrupt(hw); 1424 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1425 rtl92ce_enable_interrupt(hw); 1426 } 1427 1428 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw, 1429 u32 add_msr, u32 rm_msr) 1430 { 1431 struct rtl_priv *rtlpriv = rtl_priv(hw); 1432 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1433 1434 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n", 1435 add_msr, rm_msr); 1436 1437 if (add_msr) 1438 rtlpci->irq_mask[0] |= add_msr; 1439 if (rm_msr) 1440 rtlpci->irq_mask[0] &= (~rm_msr); 1441 rtl92ce_disable_interrupt(hw); 1442 rtl92ce_enable_interrupt(hw); 1443 } 1444 1445 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 1446 bool autoload_fail, 1447 u8 *hwinfo) 1448 { 1449 struct rtl_priv *rtlpriv = rtl_priv(hw); 1450 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1451 u8 rf_path, index, tempval; 1452 u16 i; 1453 1454 for (rf_path = 0; rf_path < 2; rf_path++) { 1455 for (i = 0; i < 3; i++) { 1456 if (!autoload_fail) { 1457 rtlefuse-> 1458 eeprom_chnlarea_txpwr_cck[rf_path][i] = 1459 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; 1460 rtlefuse-> 1461 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1462 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + 1463 i]; 1464 } else { 1465 rtlefuse-> 1466 eeprom_chnlarea_txpwr_cck[rf_path][i] = 1467 EEPROM_DEFAULT_TXPOWERLEVEL; 1468 rtlefuse-> 1469 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1470 EEPROM_DEFAULT_TXPOWERLEVEL; 1471 } 1472 } 1473 } 1474 1475 for (i = 0; i < 3; i++) { 1476 if (!autoload_fail) 1477 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i]; 1478 else 1479 tempval = EEPROM_DEFAULT_HT40_2SDIFF; 1480 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] = 1481 (tempval & 0xf); 1482 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] = 1483 ((tempval & 0xf0) >> 4); 1484 } 1485 1486 for (rf_path = 0; rf_path < 2; rf_path++) 1487 for (i = 0; i < 3; i++) 1488 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1489 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", 1490 rf_path, i, 1491 rtlefuse-> 1492 eeprom_chnlarea_txpwr_cck[rf_path][i]); 1493 for (rf_path = 0; rf_path < 2; rf_path++) 1494 for (i = 0; i < 3; i++) 1495 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1496 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 1497 rf_path, i, 1498 rtlefuse-> 1499 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]); 1500 for (rf_path = 0; rf_path < 2; rf_path++) 1501 for (i = 0; i < 3; i++) 1502 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1503 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 1504 rf_path, i, 1505 rtlefuse-> 1506 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]); 1507 1508 for (rf_path = 0; rf_path < 2; rf_path++) { 1509 for (i = 0; i < 14; i++) { 1510 index = rtl92c_get_chnl_group((u8)i); 1511 1512 rtlefuse->txpwrlevel_cck[rf_path][i] = 1513 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index]; 1514 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 1515 rtlefuse-> 1516 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index]; 1517 1518 if ((rtlefuse-> 1519 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] - 1520 rtlefuse-> 1521 eprom_chnl_txpwr_ht40_2sdf[rf_path][index]) 1522 > 0) { 1523 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 1524 rtlefuse-> 1525 eeprom_chnlarea_txpwr_ht40_1s[rf_path] 1526 [index] - 1527 rtlefuse-> 1528 eprom_chnl_txpwr_ht40_2sdf[rf_path] 1529 [index]; 1530 } else { 1531 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; 1532 } 1533 } 1534 1535 for (i = 0; i < 14; i++) { 1536 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1537 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", 1538 rf_path, i, 1539 rtlefuse->txpwrlevel_cck[rf_path][i], 1540 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 1541 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 1542 } 1543 } 1544 1545 for (i = 0; i < 3; i++) { 1546 if (!autoload_fail) { 1547 rtlefuse->eeprom_pwrlimit_ht40[i] = 1548 hwinfo[EEPROM_TXPWR_GROUP + i]; 1549 rtlefuse->eeprom_pwrlimit_ht20[i] = 1550 hwinfo[EEPROM_TXPWR_GROUP + 3 + i]; 1551 } else { 1552 rtlefuse->eeprom_pwrlimit_ht40[i] = 0; 1553 rtlefuse->eeprom_pwrlimit_ht20[i] = 0; 1554 } 1555 } 1556 1557 for (rf_path = 0; rf_path < 2; rf_path++) { 1558 for (i = 0; i < 14; i++) { 1559 index = rtl92c_get_chnl_group((u8)i); 1560 1561 if (rf_path == RF90_PATH_A) { 1562 rtlefuse->pwrgroup_ht20[rf_path][i] = 1563 (rtlefuse->eeprom_pwrlimit_ht20[index] 1564 & 0xf); 1565 rtlefuse->pwrgroup_ht40[rf_path][i] = 1566 (rtlefuse->eeprom_pwrlimit_ht40[index] 1567 & 0xf); 1568 } else if (rf_path == RF90_PATH_B) { 1569 rtlefuse->pwrgroup_ht20[rf_path][i] = 1570 ((rtlefuse->eeprom_pwrlimit_ht20[index] 1571 & 0xf0) >> 4); 1572 rtlefuse->pwrgroup_ht40[rf_path][i] = 1573 ((rtlefuse->eeprom_pwrlimit_ht40[index] 1574 & 0xf0) >> 4); 1575 } 1576 1577 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1578 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", 1579 rf_path, i, 1580 rtlefuse->pwrgroup_ht20[rf_path][i]); 1581 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1582 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", 1583 rf_path, i, 1584 rtlefuse->pwrgroup_ht40[rf_path][i]); 1585 } 1586 } 1587 1588 for (i = 0; i < 14; i++) { 1589 index = rtl92c_get_chnl_group((u8)i); 1590 1591 if (!autoload_fail) 1592 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; 1593 else 1594 tempval = EEPROM_DEFAULT_HT20_DIFF; 1595 1596 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 1597 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 1598 ((tempval >> 4) & 0xF); 1599 1600 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) 1601 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; 1602 1603 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) 1604 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; 1605 1606 index = rtl92c_get_chnl_group((u8)i); 1607 1608 if (!autoload_fail) 1609 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; 1610 else 1611 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 1612 1613 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); 1614 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 1615 ((tempval >> 4) & 0xF); 1616 } 1617 1618 rtlefuse->legacy_ht_txpowerdiff = 1619 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; 1620 1621 for (i = 0; i < 14; i++) 1622 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1623 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", 1624 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 1625 for (i = 0; i < 14; i++) 1626 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1627 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", 1628 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 1629 for (i = 0; i < 14; i++) 1630 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1631 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", 1632 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 1633 for (i = 0; i < 14; i++) 1634 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1635 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", 1636 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 1637 1638 if (!autoload_fail) 1639 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); 1640 else 1641 rtlefuse->eeprom_regulatory = 0; 1642 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1643 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 1644 1645 if (!autoload_fail) { 1646 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; 1647 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B]; 1648 } else { 1649 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; 1650 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI; 1651 } 1652 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 1653 rtlefuse->eeprom_tssi[RF90_PATH_A], 1654 rtlefuse->eeprom_tssi[RF90_PATH_B]); 1655 1656 if (!autoload_fail) 1657 tempval = hwinfo[EEPROM_THERMAL_METER]; 1658 else 1659 tempval = EEPROM_DEFAULT_THERMALMETER; 1660 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); 1661 1662 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) 1663 rtlefuse->apk_thermalmeterignore = true; 1664 1665 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 1666 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1667 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1668 } 1669 1670 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw) 1671 { 1672 struct rtl_priv *rtlpriv = rtl_priv(hw); 1673 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1674 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1675 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, 1676 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 1677 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 1678 COUNTRY_CODE_WORLD_WIDE_13}; 1679 u8 *hwinfo; 1680 1681 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 1682 if (!hwinfo) 1683 return; 1684 1685 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 1686 goto exit; 1687 1688 _rtl92ce_read_txpower_info_from_hwpg(hw, 1689 rtlefuse->autoload_failflag, 1690 hwinfo); 1691 1692 rtl8192ce_read_bt_coexist_info_from_hwpg(hw, 1693 rtlefuse->autoload_failflag, 1694 hwinfo); 1695 if (rtlhal->oem_id == RT_CID_DEFAULT) { 1696 switch (rtlefuse->eeprom_oemid) { 1697 case EEPROM_CID_DEFAULT: 1698 if (rtlefuse->eeprom_did == 0x8176) { 1699 if ((rtlefuse->eeprom_svid == 0x103C && 1700 rtlefuse->eeprom_smid == 0x1629)) 1701 rtlhal->oem_id = RT_CID_819X_HP; 1702 else 1703 rtlhal->oem_id = RT_CID_DEFAULT; 1704 } else { 1705 rtlhal->oem_id = RT_CID_DEFAULT; 1706 } 1707 break; 1708 case EEPROM_CID_TOSHIBA: 1709 rtlhal->oem_id = RT_CID_TOSHIBA; 1710 break; 1711 case EEPROM_CID_QMI: 1712 rtlhal->oem_id = RT_CID_819X_QMI; 1713 break; 1714 case EEPROM_CID_WHQL: 1715 default: 1716 rtlhal->oem_id = RT_CID_DEFAULT; 1717 break; 1718 } 1719 } 1720 exit: 1721 kfree(hwinfo); 1722 } 1723 1724 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw) 1725 { 1726 struct rtl_priv *rtlpriv = rtl_priv(hw); 1727 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1728 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1729 1730 switch (rtlhal->oem_id) { 1731 case RT_CID_819X_HP: 1732 pcipriv->ledctl.led_opendrain = true; 1733 break; 1734 case RT_CID_819X_LENOVO: 1735 case RT_CID_DEFAULT: 1736 case RT_CID_TOSHIBA: 1737 case RT_CID_CCX: 1738 case RT_CID_819X_ACER: 1739 case RT_CID_WHQL: 1740 default: 1741 break; 1742 } 1743 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1744 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 1745 } 1746 1747 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw) 1748 { 1749 struct rtl_priv *rtlpriv = rtl_priv(hw); 1750 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1751 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1752 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1753 u8 tmp_u1b; 1754 1755 rtlhal->version = _rtl92ce_read_chip_version(hw); 1756 if (get_rf_type(rtlphy) == RF_1T1R) 1757 rtlpriv->dm.rfpath_rxenable[0] = true; 1758 else 1759 rtlpriv->dm.rfpath_rxenable[0] = 1760 rtlpriv->dm.rfpath_rxenable[1] = true; 1761 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 1762 rtlhal->version); 1763 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 1764 if (tmp_u1b & BIT(4)) { 1765 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 1766 rtlefuse->epromtype = EEPROM_93C46; 1767 } else { 1768 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 1769 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 1770 } 1771 if (tmp_u1b & BIT(5)) { 1772 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1773 rtlefuse->autoload_failflag = false; 1774 _rtl92ce_read_adapter_info(hw); 1775 } else { 1776 pr_err("Autoload ERR!!\n"); 1777 } 1778 _rtl92ce_hal_customized_behavior(hw); 1779 } 1780 1781 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw, 1782 struct ieee80211_sta *sta) 1783 { 1784 struct rtl_priv *rtlpriv = rtl_priv(hw); 1785 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1786 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1787 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1788 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1789 u32 ratr_value; 1790 u8 ratr_index = 0; 1791 u8 nmode = mac->ht_enable; 1792 u16 shortgi_rate; 1793 u32 tmp_ratr_value; 1794 u8 curtxbw_40mhz = mac->bw_40; 1795 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1796 1 : 0; 1797 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1798 1 : 0; 1799 enum wireless_mode wirelessmode = mac->mode; 1800 u32 ratr_mask; 1801 1802 if (rtlhal->current_bandtype == BAND_ON_5G) 1803 ratr_value = sta->supp_rates[1] << 4; 1804 else 1805 ratr_value = sta->supp_rates[0]; 1806 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1807 ratr_value = 0xfff; 1808 1809 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1810 sta->ht_cap.mcs.rx_mask[0] << 12); 1811 switch (wirelessmode) { 1812 case WIRELESS_MODE_B: 1813 if (ratr_value & 0x0000000c) 1814 ratr_value &= 0x0000000d; 1815 else 1816 ratr_value &= 0x0000000f; 1817 break; 1818 case WIRELESS_MODE_G: 1819 ratr_value &= 0x00000FF5; 1820 break; 1821 case WIRELESS_MODE_N_24G: 1822 case WIRELESS_MODE_N_5G: 1823 nmode = 1; 1824 if (get_rf_type(rtlphy) == RF_1T2R || 1825 get_rf_type(rtlphy) == RF_1T1R) 1826 ratr_mask = 0x000ff005; 1827 else 1828 ratr_mask = 0x0f0ff005; 1829 1830 ratr_value &= ratr_mask; 1831 break; 1832 default: 1833 if (rtlphy->rf_type == RF_1T2R) 1834 ratr_value &= 0x000ff0ff; 1835 else 1836 ratr_value &= 0x0f0ff0ff; 1837 1838 break; 1839 } 1840 1841 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 1842 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) && 1843 (rtlpcipriv->bt_coexist.bt_cur_state) && 1844 (rtlpcipriv->bt_coexist.bt_ant_isolation) && 1845 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) || 1846 (rtlpcipriv->bt_coexist.bt_service == BT_BUSY))) 1847 ratr_value &= 0x0fffcfc0; 1848 else 1849 ratr_value &= 0x0FFFFFFF; 1850 1851 if (nmode && ((curtxbw_40mhz && 1852 curshortgi_40mhz) || (!curtxbw_40mhz && 1853 curshortgi_20mhz))) { 1854 1855 ratr_value |= 0x10000000; 1856 tmp_ratr_value = (ratr_value >> 12); 1857 1858 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 1859 if ((1 << shortgi_rate) & tmp_ratr_value) 1860 break; 1861 } 1862 1863 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 1864 (shortgi_rate << 4) | (shortgi_rate); 1865 } 1866 1867 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 1868 1869 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", 1870 rtl_read_dword(rtlpriv, REG_ARFR0)); 1871 } 1872 1873 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw, 1874 struct ieee80211_sta *sta, u8 rssi_level) 1875 { 1876 struct rtl_priv *rtlpriv = rtl_priv(hw); 1877 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1878 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1879 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1880 struct rtl_sta_info *sta_entry = NULL; 1881 u32 ratr_bitmap; 1882 u8 ratr_index; 1883 u8 curtxbw_40mhz = (sta->ht_cap.cap & 1884 IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0; 1885 u8 curshortgi_40mhz = (sta->ht_cap.cap & 1886 IEEE80211_HT_CAP_SGI_40) ? 1 : 0; 1887 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1888 1 : 0; 1889 enum wireless_mode wirelessmode = 0; 1890 bool shortgi = false; 1891 u8 rate_mask[5]; 1892 u8 macid = 0; 1893 1894 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 1895 wirelessmode = sta_entry->wireless_mode; 1896 if (mac->opmode == NL80211_IFTYPE_STATION || 1897 mac->opmode == NL80211_IFTYPE_MESH_POINT) 1898 curtxbw_40mhz = mac->bw_40; 1899 else if (mac->opmode == NL80211_IFTYPE_AP || 1900 mac->opmode == NL80211_IFTYPE_ADHOC) 1901 macid = sta->aid + 1; 1902 1903 if (rtlhal->current_bandtype == BAND_ON_5G) 1904 ratr_bitmap = sta->supp_rates[1] << 4; 1905 else 1906 ratr_bitmap = sta->supp_rates[0]; 1907 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1908 ratr_bitmap = 0xfff; 1909 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1910 sta->ht_cap.mcs.rx_mask[0] << 12); 1911 switch (wirelessmode) { 1912 case WIRELESS_MODE_B: 1913 ratr_index = RATR_INX_WIRELESS_B; 1914 if (ratr_bitmap & 0x0000000c) 1915 ratr_bitmap &= 0x0000000d; 1916 else 1917 ratr_bitmap &= 0x0000000f; 1918 break; 1919 case WIRELESS_MODE_G: 1920 ratr_index = RATR_INX_WIRELESS_GB; 1921 1922 if (rssi_level == 1) 1923 ratr_bitmap &= 0x00000f00; 1924 else if (rssi_level == 2) 1925 ratr_bitmap &= 0x00000ff0; 1926 else 1927 ratr_bitmap &= 0x00000ff5; 1928 break; 1929 case WIRELESS_MODE_A: 1930 ratr_index = RATR_INX_WIRELESS_A; 1931 ratr_bitmap &= 0x00000ff0; 1932 break; 1933 case WIRELESS_MODE_N_24G: 1934 case WIRELESS_MODE_N_5G: 1935 ratr_index = RATR_INX_WIRELESS_NGB; 1936 1937 if (rtlphy->rf_type == RF_1T2R || 1938 rtlphy->rf_type == RF_1T1R) { 1939 if (curtxbw_40mhz) { 1940 if (rssi_level == 1) 1941 ratr_bitmap &= 0x000f0000; 1942 else if (rssi_level == 2) 1943 ratr_bitmap &= 0x000ff000; 1944 else 1945 ratr_bitmap &= 0x000ff015; 1946 } else { 1947 if (rssi_level == 1) 1948 ratr_bitmap &= 0x000f0000; 1949 else if (rssi_level == 2) 1950 ratr_bitmap &= 0x000ff000; 1951 else 1952 ratr_bitmap &= 0x000ff005; 1953 } 1954 } else { 1955 if (curtxbw_40mhz) { 1956 if (rssi_level == 1) 1957 ratr_bitmap &= 0x0f0f0000; 1958 else if (rssi_level == 2) 1959 ratr_bitmap &= 0x0f0ff000; 1960 else 1961 ratr_bitmap &= 0x0f0ff015; 1962 } else { 1963 if (rssi_level == 1) 1964 ratr_bitmap &= 0x0f0f0000; 1965 else if (rssi_level == 2) 1966 ratr_bitmap &= 0x0f0ff000; 1967 else 1968 ratr_bitmap &= 0x0f0ff005; 1969 } 1970 } 1971 1972 if ((curtxbw_40mhz && curshortgi_40mhz) || 1973 (!curtxbw_40mhz && curshortgi_20mhz)) { 1974 1975 if (macid == 0) 1976 shortgi = true; 1977 else if (macid == 1) 1978 shortgi = false; 1979 } 1980 break; 1981 default: 1982 ratr_index = RATR_INX_WIRELESS_NGB; 1983 1984 if (rtlphy->rf_type == RF_1T2R) 1985 ratr_bitmap &= 0x000ff0ff; 1986 else 1987 ratr_bitmap &= 0x0f0ff0ff; 1988 break; 1989 } 1990 sta_entry->ratr_index = ratr_index; 1991 1992 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 1993 "ratr_bitmap :%x\n", ratr_bitmap); 1994 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 1995 (ratr_index << 28); 1996 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; 1997 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 1998 "Rate_index:%x, ratr_val:%x, %5phC\n", 1999 ratr_index, ratr_bitmap, rate_mask); 2000 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask); 2001 } 2002 2003 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw, 2004 struct ieee80211_sta *sta, u8 rssi_level) 2005 { 2006 struct rtl_priv *rtlpriv = rtl_priv(hw); 2007 2008 if (rtlpriv->dm.useramask) 2009 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level); 2010 else 2011 rtl92ce_update_hal_rate_table(hw, sta); 2012 } 2013 2014 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw) 2015 { 2016 struct rtl_priv *rtlpriv = rtl_priv(hw); 2017 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2018 u16 sifs_timer; 2019 2020 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2021 &mac->slot_time); 2022 if (!mac->ht_enable) 2023 sifs_timer = 0x0a0a; 2024 else 2025 sifs_timer = 0x1010; 2026 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2027 } 2028 2029 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2030 { 2031 struct rtl_priv *rtlpriv = rtl_priv(hw); 2032 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2033 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2034 enum rf_pwrstate e_rfpowerstate_toset; 2035 u8 u1tmp; 2036 bool actuallyset = false; 2037 unsigned long flag; 2038 2039 if (rtlpci->being_init_adapter) 2040 return false; 2041 2042 if (ppsc->swrf_processing) 2043 return false; 2044 2045 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2046 if (ppsc->rfchange_inprogress) { 2047 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2048 return false; 2049 } else { 2050 ppsc->rfchange_inprogress = true; 2051 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2052 } 2053 2054 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv, 2055 REG_MAC_PINMUX_CFG)&~(BIT(3))); 2056 2057 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); 2058 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; 2059 2060 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { 2061 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2062 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2063 2064 e_rfpowerstate_toset = ERFON; 2065 ppsc->hwradiooff = false; 2066 actuallyset = true; 2067 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) { 2068 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2069 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 2070 2071 e_rfpowerstate_toset = ERFOFF; 2072 ppsc->hwradiooff = true; 2073 actuallyset = true; 2074 } 2075 2076 if (actuallyset) { 2077 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2078 ppsc->rfchange_inprogress = false; 2079 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2080 } else { 2081 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 2082 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2083 2084 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2085 ppsc->rfchange_inprogress = false; 2086 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2087 } 2088 2089 *valid = 1; 2090 return !ppsc->hwradiooff; 2091 2092 } 2093 2094 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index, 2095 u8 *p_macaddr, bool is_group, u8 enc_algo, 2096 bool is_wepkey, bool clear_all) 2097 { 2098 struct rtl_priv *rtlpriv = rtl_priv(hw); 2099 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2100 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2101 u8 *macaddr = p_macaddr; 2102 u32 entry_id = 0; 2103 bool is_pairwise = false; 2104 2105 static u8 cam_const_addr[4][6] = { 2106 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2107 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2108 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2109 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2110 }; 2111 static u8 cam_const_broad[] = { 2112 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2113 }; 2114 2115 if (clear_all) { 2116 u8 idx = 0; 2117 u8 cam_offset = 0; 2118 u8 clear_number = 5; 2119 2120 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2121 2122 for (idx = 0; idx < clear_number; idx++) { 2123 rtl_cam_mark_invalid(hw, cam_offset + idx); 2124 rtl_cam_empty_entry(hw, cam_offset + idx); 2125 2126 if (idx < 5) { 2127 memset(rtlpriv->sec.key_buf[idx], 0, 2128 MAX_KEY_LEN); 2129 rtlpriv->sec.key_len[idx] = 0; 2130 } 2131 } 2132 2133 } else { 2134 switch (enc_algo) { 2135 case WEP40_ENCRYPTION: 2136 enc_algo = CAM_WEP40; 2137 break; 2138 case WEP104_ENCRYPTION: 2139 enc_algo = CAM_WEP104; 2140 break; 2141 case TKIP_ENCRYPTION: 2142 enc_algo = CAM_TKIP; 2143 break; 2144 case AESCCMP_ENCRYPTION: 2145 enc_algo = CAM_AES; 2146 break; 2147 default: 2148 pr_err("switch case %#x not processed\n", 2149 enc_algo); 2150 enc_algo = CAM_TKIP; 2151 break; 2152 } 2153 2154 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2155 macaddr = cam_const_addr[key_index]; 2156 entry_id = key_index; 2157 } else { 2158 if (is_group) { 2159 macaddr = cam_const_broad; 2160 entry_id = key_index; 2161 } else { 2162 if (mac->opmode == NL80211_IFTYPE_AP || 2163 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 2164 entry_id = rtl_cam_get_free_entry(hw, 2165 p_macaddr); 2166 if (entry_id >= TOTAL_CAM_ENTRY) { 2167 pr_err("Can not find free hw security cam entry\n"); 2168 return; 2169 } 2170 } else { 2171 entry_id = CAM_PAIRWISE_KEY_POSITION; 2172 } 2173 2174 key_index = PAIRWISE_KEYIDX; 2175 is_pairwise = true; 2176 } 2177 } 2178 2179 if (rtlpriv->sec.key_len[key_index] == 0) { 2180 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2181 "delete one entry, entry_id is %d\n", 2182 entry_id); 2183 if (mac->opmode == NL80211_IFTYPE_AP || 2184 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2185 rtl_cam_del_entry(hw, p_macaddr); 2186 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2187 } else { 2188 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 2189 "The insert KEY length is %d\n", 2190 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); 2191 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 2192 "The insert KEY is %x %x\n", 2193 rtlpriv->sec.key_buf[0][0], 2194 rtlpriv->sec.key_buf[0][1]); 2195 2196 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2197 "add one entry\n"); 2198 if (is_pairwise) { 2199 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, 2200 "Pairwise Key content", 2201 rtlpriv->sec.pairwise_key, 2202 rtlpriv->sec. 2203 key_len[PAIRWISE_KEYIDX]); 2204 2205 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2206 "set Pairwise key\n"); 2207 2208 rtl_cam_add_one_entry(hw, macaddr, key_index, 2209 entry_id, enc_algo, 2210 CAM_CONFIG_NO_USEDK, 2211 rtlpriv->sec. 2212 key_buf[key_index]); 2213 } else { 2214 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2215 "set group key\n"); 2216 2217 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2218 rtl_cam_add_one_entry(hw, 2219 rtlefuse->dev_addr, 2220 PAIRWISE_KEYIDX, 2221 CAM_PAIRWISE_KEY_POSITION, 2222 enc_algo, 2223 CAM_CONFIG_NO_USEDK, 2224 rtlpriv->sec.key_buf 2225 [entry_id]); 2226 } 2227 2228 rtl_cam_add_one_entry(hw, macaddr, key_index, 2229 entry_id, enc_algo, 2230 CAM_CONFIG_NO_USEDK, 2231 rtlpriv->sec.key_buf[entry_id]); 2232 } 2233 2234 } 2235 } 2236 } 2237 2238 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw) 2239 { 2240 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 2241 2242 rtlpcipriv->bt_coexist.bt_coexistence = 2243 rtlpcipriv->bt_coexist.eeprom_bt_coexist; 2244 rtlpcipriv->bt_coexist.bt_ant_num = 2245 rtlpcipriv->bt_coexist.eeprom_bt_ant_num; 2246 rtlpcipriv->bt_coexist.bt_coexist_type = 2247 rtlpcipriv->bt_coexist.eeprom_bt_type; 2248 2249 if (rtlpcipriv->bt_coexist.reg_bt_iso == 2) 2250 rtlpcipriv->bt_coexist.bt_ant_isolation = 2251 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol; 2252 else 2253 rtlpcipriv->bt_coexist.bt_ant_isolation = 2254 rtlpcipriv->bt_coexist.reg_bt_iso; 2255 2256 rtlpcipriv->bt_coexist.bt_radio_shared_type = 2257 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared; 2258 2259 if (rtlpcipriv->bt_coexist.bt_coexistence) { 2260 2261 if (rtlpcipriv->bt_coexist.reg_bt_sco == 1) 2262 rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION; 2263 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2) 2264 rtlpcipriv->bt_coexist.bt_service = BT_SCO; 2265 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4) 2266 rtlpcipriv->bt_coexist.bt_service = BT_BUSY; 2267 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5) 2268 rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY; 2269 else 2270 rtlpcipriv->bt_coexist.bt_service = BT_IDLE; 2271 2272 rtlpcipriv->bt_coexist.bt_edca_ul = 0; 2273 rtlpcipriv->bt_coexist.bt_edca_dl = 0; 2274 rtlpcipriv->bt_coexist.bt_rssi_state = 0xff; 2275 } 2276 } 2277 2278 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 2279 bool auto_load_fail, u8 *hwinfo) 2280 { 2281 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 2282 u8 val; 2283 2284 if (!auto_load_fail) { 2285 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 2286 ((hwinfo[RF_OPTION1] & 0xe0) >> 5); 2287 val = hwinfo[RF_OPTION4]; 2288 rtlpcipriv->bt_coexist.eeprom_bt_type = ((val & 0xe) >> 1); 2289 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (val & 0x1); 2290 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4); 2291 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = 2292 ((val & 0x20) >> 5); 2293 } else { 2294 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0; 2295 rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE; 2296 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2; 2297 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = 0; 2298 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED; 2299 } 2300 2301 rtl8192ce_bt_var_init(hw); 2302 } 2303 2304 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw) 2305 { 2306 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 2307 2308 /* 0:Low, 1:High, 2:From Efuse. */ 2309 rtlpcipriv->bt_coexist.reg_bt_iso = 2; 2310 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 2311 rtlpcipriv->bt_coexist.reg_bt_sco = 3; 2312 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 2313 rtlpcipriv->bt_coexist.reg_bt_sco = 0; 2314 } 2315 2316 2317 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw) 2318 { 2319 struct rtl_priv *rtlpriv = rtl_priv(hw); 2320 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2321 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 2322 2323 u8 u1_tmp; 2324 2325 if (rtlpcipriv->bt_coexist.bt_coexistence && 2326 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) || 2327 rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) { 2328 2329 if (rtlpcipriv->bt_coexist.bt_ant_isolation) 2330 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0); 2331 2332 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) & 2333 BIT_OFFSET_LEN_MASK_32(0, 1); 2334 u1_tmp = u1_tmp | 2335 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ? 2336 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) | 2337 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ? 2338 0 : BIT_OFFSET_LEN_MASK_32(2, 1)); 2339 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp); 2340 2341 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa); 2342 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040); 2343 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010); 2344 2345 /* Config to 1T1R. */ 2346 if (rtlphy->rf_type == RF_1T1R) { 2347 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE); 2348 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1)); 2349 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp); 2350 2351 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE); 2352 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1)); 2353 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp); 2354 } 2355 } 2356 } 2357 2358 void rtl92ce_suspend(struct ieee80211_hw *hw) 2359 { 2360 } 2361 2362 void rtl92ce_resume(struct ieee80211_hw *hw) 2363 { 2364 } 2365