1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
3 
4 #include "../wifi.h"
5 #include "../efuse.h"
6 #include "../base.h"
7 #include "../regd.h"
8 #include "../cam.h"
9 #include "../ps.h"
10 #include "../pci.h"
11 #include "reg.h"
12 #include "def.h"
13 #include "phy.h"
14 #include "../rtl8192c/dm_common.h"
15 #include "../rtl8192c/fw_common.h"
16 #include "../rtl8192c/phy_common.h"
17 #include "dm.h"
18 #include "led.h"
19 #include "hw.h"
20 
21 #define LLT_CONFIG	5
22 
23 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
24 				      u8 set_bits, u8 clear_bits)
25 {
26 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
27 	struct rtl_priv *rtlpriv = rtl_priv(hw);
28 
29 	rtlpci->reg_bcn_ctrl_val |= set_bits;
30 	rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
31 
32 	rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
33 }
34 
35 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
36 {
37 	struct rtl_priv *rtlpriv = rtl_priv(hw);
38 	u8 tmp1byte;
39 
40 	tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
41 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
42 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
43 	tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
44 	tmp1byte &= ~(BIT(0));
45 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
46 }
47 
48 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
49 {
50 	struct rtl_priv *rtlpriv = rtl_priv(hw);
51 	u8 tmp1byte;
52 
53 	tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
54 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
55 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
56 	tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
57 	tmp1byte |= BIT(0);
58 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
59 }
60 
61 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
62 {
63 	_rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
64 }
65 
66 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
67 {
68 	_rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
69 }
70 
71 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
72 {
73 	struct rtl_priv *rtlpriv = rtl_priv(hw);
74 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
75 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
76 
77 	switch (variable) {
78 	case HW_VAR_RCR:
79 		*((u32 *) (val)) = rtlpci->receive_config;
80 		break;
81 	case HW_VAR_RF_STATE:
82 		*((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
83 		break;
84 	case HW_VAR_FWLPS_RF_ON:{
85 			enum rf_pwrstate rfstate;
86 			u32 val_rcr;
87 
88 			rtlpriv->cfg->ops->get_hw_reg(hw,
89 						      HW_VAR_RF_STATE,
90 						      (u8 *)(&rfstate));
91 			if (rfstate == ERFOFF) {
92 				*((bool *) (val)) = true;
93 			} else {
94 				val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
95 				val_rcr &= 0x00070000;
96 				if (val_rcr)
97 					*((bool *) (val)) = false;
98 				else
99 					*((bool *) (val)) = true;
100 			}
101 			break;
102 		}
103 	case HW_VAR_FW_PSMODE_STATUS:
104 		*((bool *) (val)) = ppsc->fw_current_inpsmode;
105 		break;
106 	case HW_VAR_CORRECT_TSF:{
107 		u64 tsf;
108 		u32 *ptsf_low = (u32 *)&tsf;
109 		u32 *ptsf_high = ((u32 *)&tsf) + 1;
110 
111 		*ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
112 		*ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
113 
114 		*((u64 *) (val)) = tsf;
115 
116 		break;
117 		}
118 	case HAL_DEF_WOWLAN:
119 		break;
120 	default:
121 		pr_err("switch case %#x not processed\n", variable);
122 		break;
123 	}
124 }
125 
126 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
127 {
128 	struct rtl_priv *rtlpriv = rtl_priv(hw);
129 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
130 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
131 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
132 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
133 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
134 	u8 idx;
135 
136 	switch (variable) {
137 	case HW_VAR_ETHER_ADDR:{
138 			for (idx = 0; idx < ETH_ALEN; idx++) {
139 				rtl_write_byte(rtlpriv, (REG_MACID + idx),
140 					       val[idx]);
141 			}
142 			break;
143 		}
144 	case HW_VAR_BASIC_RATE:{
145 			u16 rate_cfg = ((u16 *) val)[0];
146 			u8 rate_index = 0;
147 
148 			rate_cfg &= 0x15f;
149 			rate_cfg |= 0x01;
150 			rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
151 			rtl_write_byte(rtlpriv, REG_RRSR + 1,
152 				       (rate_cfg >> 8) & 0xff);
153 			while (rate_cfg > 0x1) {
154 				rate_cfg = (rate_cfg >> 1);
155 				rate_index++;
156 			}
157 			rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
158 				       rate_index);
159 			break;
160 		}
161 	case HW_VAR_BSSID:{
162 			for (idx = 0; idx < ETH_ALEN; idx++) {
163 				rtl_write_byte(rtlpriv, (REG_BSSID + idx),
164 					       val[idx]);
165 			}
166 			break;
167 		}
168 	case HW_VAR_SIFS:{
169 			rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
170 			rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
171 
172 			rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
173 			rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
174 
175 			if (!mac->ht_enable)
176 				rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
177 					       0x0e0e);
178 			else
179 				rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
180 					       *((u16 *) val));
181 			break;
182 		}
183 	case HW_VAR_SLOT_TIME:{
184 			u8 e_aci;
185 
186 			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
187 				"HW_VAR_SLOT_TIME %x\n", val[0]);
188 
189 			rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
190 
191 			for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
192 				rtlpriv->cfg->ops->set_hw_reg(hw,
193 							      HW_VAR_AC_PARAM,
194 							      &e_aci);
195 			}
196 			break;
197 		}
198 	case HW_VAR_ACK_PREAMBLE:{
199 			u8 reg_tmp;
200 			u8 short_preamble = (bool)*val;
201 
202 			reg_tmp = (mac->cur_40_prime_sc) << 5;
203 			if (short_preamble)
204 				reg_tmp |= 0x80;
205 
206 			rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
207 			break;
208 		}
209 	case HW_VAR_AMPDU_MIN_SPACE:{
210 			u8 min_spacing_to_set;
211 			u8 sec_min_space;
212 
213 			min_spacing_to_set = *val;
214 			if (min_spacing_to_set <= 7) {
215 				sec_min_space = 0;
216 
217 				if (min_spacing_to_set < sec_min_space)
218 					min_spacing_to_set = sec_min_space;
219 
220 				mac->min_space_cfg = ((mac->min_space_cfg &
221 						       0xf8) |
222 						      min_spacing_to_set);
223 
224 				*val = min_spacing_to_set;
225 
226 				rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
227 					"Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
228 					mac->min_space_cfg);
229 
230 				rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
231 					       mac->min_space_cfg);
232 			}
233 			break;
234 		}
235 	case HW_VAR_SHORTGI_DENSITY:{
236 			u8 density_to_set;
237 
238 			density_to_set = *val;
239 			mac->min_space_cfg |= (density_to_set << 3);
240 
241 			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
242 				"Set HW_VAR_SHORTGI_DENSITY: %#x\n",
243 				mac->min_space_cfg);
244 
245 			rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
246 				       mac->min_space_cfg);
247 
248 			break;
249 		}
250 	case HW_VAR_AMPDU_FACTOR:{
251 			u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
252 			u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
253 
254 			u8 factor_toset;
255 			u8 *p_regtoset = NULL;
256 			u8 index = 0;
257 
258 			if ((rtlpriv->btcoexist.bt_coexistence) &&
259 			    (rtlpriv->btcoexist.bt_coexist_type ==
260 			    BT_CSR_BC4))
261 				p_regtoset = regtoset_bt;
262 			else
263 				p_regtoset = regtoset_normal;
264 
265 			factor_toset = *(val);
266 			if (factor_toset <= 3) {
267 				factor_toset = (1 << (factor_toset + 2));
268 				if (factor_toset > 0xf)
269 					factor_toset = 0xf;
270 
271 				for (index = 0; index < 4; index++) {
272 					if ((p_regtoset[index] & 0xf0) >
273 					    (factor_toset << 4))
274 						p_regtoset[index] =
275 						    (p_regtoset[index] & 0x0f) |
276 						    (factor_toset << 4);
277 
278 					if ((p_regtoset[index] & 0x0f) >
279 					    factor_toset)
280 						p_regtoset[index] =
281 						    (p_regtoset[index] & 0xf0) |
282 						    (factor_toset);
283 
284 					rtl_write_byte(rtlpriv,
285 						       (REG_AGGLEN_LMT + index),
286 						       p_regtoset[index]);
287 
288 				}
289 
290 				rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
291 					"Set HW_VAR_AMPDU_FACTOR: %#x\n",
292 					factor_toset);
293 			}
294 			break;
295 		}
296 	case HW_VAR_AC_PARAM:{
297 			u8 e_aci = *(val);
298 
299 			rtl92c_dm_init_edca_turbo(hw);
300 
301 			if (rtlpci->acm_method != EACMWAY2_SW)
302 				rtlpriv->cfg->ops->set_hw_reg(hw,
303 							      HW_VAR_ACM_CTRL,
304 							      (&e_aci));
305 			break;
306 		}
307 	case HW_VAR_ACM_CTRL:{
308 			u8 e_aci = *(val);
309 			union aci_aifsn *p_aci_aifsn =
310 			    (union aci_aifsn *)(&(mac->ac[0].aifs));
311 			u8 acm = p_aci_aifsn->f.acm;
312 			u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
313 
314 			acm_ctrl =
315 			    acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
316 
317 			if (acm) {
318 				switch (e_aci) {
319 				case AC0_BE:
320 					acm_ctrl |= ACMHW_BEQEN;
321 					break;
322 				case AC2_VI:
323 					acm_ctrl |= ACMHW_VIQEN;
324 					break;
325 				case AC3_VO:
326 					acm_ctrl |= ACMHW_VOQEN;
327 					break;
328 				default:
329 					rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
330 						"HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
331 						acm);
332 					break;
333 				}
334 			} else {
335 				switch (e_aci) {
336 				case AC0_BE:
337 					acm_ctrl &= (~ACMHW_BEQEN);
338 					break;
339 				case AC2_VI:
340 					acm_ctrl &= (~ACMHW_VIQEN);
341 					break;
342 				case AC3_VO:
343 					acm_ctrl &= (~ACMHW_VOQEN);
344 					break;
345 				default:
346 					pr_err("switch case %#x not processed\n",
347 					       e_aci);
348 					break;
349 				}
350 			}
351 
352 			rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
353 				"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
354 				acm_ctrl);
355 			rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
356 			break;
357 		}
358 	case HW_VAR_RCR:{
359 			rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
360 			rtlpci->receive_config = ((u32 *) (val))[0];
361 			break;
362 		}
363 	case HW_VAR_RETRY_LIMIT:{
364 			u8 retry_limit = val[0];
365 
366 			rtl_write_word(rtlpriv, REG_RL,
367 				       retry_limit << RETRY_LIMIT_SHORT_SHIFT |
368 				       retry_limit << RETRY_LIMIT_LONG_SHIFT);
369 			break;
370 		}
371 	case HW_VAR_DUAL_TSF_RST:
372 		rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
373 		break;
374 	case HW_VAR_EFUSE_BYTES:
375 		rtlefuse->efuse_usedbytes = *((u16 *) val);
376 		break;
377 	case HW_VAR_EFUSE_USAGE:
378 		rtlefuse->efuse_usedpercentage = *val;
379 		break;
380 	case HW_VAR_IO_CMD:
381 		rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
382 		break;
383 	case HW_VAR_WPA_CONFIG:
384 		rtl_write_byte(rtlpriv, REG_SECCFG, *val);
385 		break;
386 	case HW_VAR_SET_RPWM:{
387 			u8 rpwm_val;
388 
389 			rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
390 			udelay(1);
391 
392 			if (rpwm_val & BIT(7)) {
393 				rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
394 			} else {
395 				rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
396 					       *val | BIT(7));
397 			}
398 
399 			break;
400 		}
401 	case HW_VAR_H2C_FW_PWRMODE:{
402 			u8 psmode = *val;
403 
404 			if ((psmode != FW_PS_ACTIVE_MODE) &&
405 			    (!IS_92C_SERIAL(rtlhal->version))) {
406 				rtl92c_dm_rf_saving(hw, true);
407 			}
408 
409 			rtl92c_set_fw_pwrmode_cmd(hw, *val);
410 			break;
411 		}
412 	case HW_VAR_FW_PSMODE_STATUS:
413 		ppsc->fw_current_inpsmode = *((bool *) val);
414 		break;
415 	case HW_VAR_H2C_FW_JOINBSSRPT:{
416 			u8 mstatus = *val;
417 			u8 tmp_regcr, tmp_reg422;
418 			bool recover = false;
419 
420 			if (mstatus == RT_MEDIA_CONNECT) {
421 				rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
422 							      NULL);
423 
424 				tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
425 				rtl_write_byte(rtlpriv, REG_CR + 1,
426 					       (tmp_regcr | BIT(0)));
427 
428 				_rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
429 				_rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
430 
431 				tmp_reg422 =
432 				    rtl_read_byte(rtlpriv,
433 						  REG_FWHW_TXQ_CTRL + 2);
434 				if (tmp_reg422 & BIT(6))
435 					recover = true;
436 				rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
437 					       tmp_reg422 & (~BIT(6)));
438 
439 				rtl92c_set_fw_rsvdpagepkt(hw, NULL);
440 
441 				_rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
442 				_rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
443 
444 				if (recover) {
445 					rtl_write_byte(rtlpriv,
446 						       REG_FWHW_TXQ_CTRL + 2,
447 						       tmp_reg422);
448 				}
449 
450 				rtl_write_byte(rtlpriv, REG_CR + 1,
451 					       (tmp_regcr & ~(BIT(0))));
452 			}
453 			rtl92c_set_fw_joinbss_report_cmd(hw, *val);
454 
455 			break;
456 		}
457 	case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
458 		rtl92c_set_p2p_ps_offload_cmd(hw, *val);
459 		break;
460 	case HW_VAR_AID:{
461 			u16 u2btmp;
462 
463 			u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
464 			u2btmp &= 0xC000;
465 			rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
466 						mac->assoc_id));
467 
468 			break;
469 		}
470 	case HW_VAR_CORRECT_TSF:{
471 			u8 btype_ibss = val[0];
472 
473 			if (btype_ibss)
474 				_rtl92ce_stop_tx_beacon(hw);
475 
476 			_rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
477 
478 			rtl_write_dword(rtlpriv, REG_TSFTR,
479 					(u32) (mac->tsf & 0xffffffff));
480 			rtl_write_dword(rtlpriv, REG_TSFTR + 4,
481 					(u32) ((mac->tsf >> 32) & 0xffffffff));
482 
483 			_rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
484 
485 			if (btype_ibss)
486 				_rtl92ce_resume_tx_beacon(hw);
487 
488 			break;
489 
490 		}
491 	case HW_VAR_FW_LPS_ACTION: {
492 			bool enter_fwlps = *((bool *)val);
493 			u8 rpwm_val, fw_pwrmode;
494 			bool fw_current_inps;
495 
496 			if (enter_fwlps) {
497 				rpwm_val = 0x02;	/* RF off */
498 				fw_current_inps = true;
499 				rtlpriv->cfg->ops->set_hw_reg(hw,
500 						HW_VAR_FW_PSMODE_STATUS,
501 						(u8 *)(&fw_current_inps));
502 				rtlpriv->cfg->ops->set_hw_reg(hw,
503 						HW_VAR_H2C_FW_PWRMODE,
504 						&ppsc->fwctrl_psmode);
505 
506 				rtlpriv->cfg->ops->set_hw_reg(hw,
507 							      HW_VAR_SET_RPWM,
508 							      &rpwm_val);
509 			} else {
510 				rpwm_val = 0x0C;	/* RF on */
511 				fw_pwrmode = FW_PS_ACTIVE_MODE;
512 				fw_current_inps = false;
513 				rtlpriv->cfg->ops->set_hw_reg(hw,
514 							      HW_VAR_SET_RPWM,
515 							      &rpwm_val);
516 				rtlpriv->cfg->ops->set_hw_reg(hw,
517 						HW_VAR_H2C_FW_PWRMODE,
518 						&fw_pwrmode);
519 
520 				rtlpriv->cfg->ops->set_hw_reg(hw,
521 						HW_VAR_FW_PSMODE_STATUS,
522 						(u8 *)(&fw_current_inps));
523 			}
524 		break; }
525 	case HW_VAR_KEEP_ALIVE: {
526 		u8 array[2];
527 
528 		array[0] = 0xff;
529 		array[1] = *((u8 *)val);
530 		rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2, array);
531 		break; }
532 	default:
533 		pr_err("switch case %d not processed\n", variable);
534 		break;
535 	}
536 }
537 
538 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
539 {
540 	struct rtl_priv *rtlpriv = rtl_priv(hw);
541 	bool status = true;
542 	long count = 0;
543 	u32 value = _LLT_INIT_ADDR(address) |
544 	    _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
545 
546 	rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
547 
548 	do {
549 		value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
550 		if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
551 			break;
552 
553 		if (count > POLLING_LLT_THRESHOLD) {
554 			pr_err("Failed to polling write LLT done at address %d!\n",
555 			       address);
556 			status = false;
557 			break;
558 		}
559 	} while (++count);
560 
561 	return status;
562 }
563 
564 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
565 {
566 	struct rtl_priv *rtlpriv = rtl_priv(hw);
567 	unsigned short i;
568 	u8 txpktbuf_bndy;
569 	u8 maxpage;
570 	bool status;
571 
572 #if LLT_CONFIG == 1
573 	maxpage = 255;
574 	txpktbuf_bndy = 252;
575 #elif LLT_CONFIG == 2
576 	maxpage = 127;
577 	txpktbuf_bndy = 124;
578 #elif LLT_CONFIG == 3
579 	maxpage = 255;
580 	txpktbuf_bndy = 174;
581 #elif LLT_CONFIG == 4
582 	maxpage = 255;
583 	txpktbuf_bndy = 246;
584 #elif LLT_CONFIG == 5
585 	maxpage = 255;
586 	txpktbuf_bndy = 246;
587 #endif
588 
589 #if LLT_CONFIG == 1
590 	rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
591 	rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
592 #elif LLT_CONFIG == 2
593 	rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
594 #elif LLT_CONFIG == 3
595 	rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
596 #elif LLT_CONFIG == 4
597 	rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
598 #elif LLT_CONFIG == 5
599 	rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
600 
601 	rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
602 #endif
603 
604 	rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
605 	rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
606 
607 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
608 	rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
609 
610 	rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
611 	rtl_write_byte(rtlpriv, REG_PBP, 0x11);
612 	rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
613 
614 	for (i = 0; i < (txpktbuf_bndy - 1); i++) {
615 		status = _rtl92ce_llt_write(hw, i, i + 1);
616 		if (!status)
617 			return status;
618 	}
619 
620 	status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
621 	if (!status)
622 		return status;
623 
624 	for (i = txpktbuf_bndy; i < maxpage; i++) {
625 		status = _rtl92ce_llt_write(hw, i, (i + 1));
626 		if (!status)
627 			return status;
628 	}
629 
630 	status = _rtl92ce_llt_write(hw, maxpage, txpktbuf_bndy);
631 	if (!status)
632 		return status;
633 
634 	return true;
635 }
636 
637 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
638 {
639 	struct rtl_priv *rtlpriv = rtl_priv(hw);
640 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
641 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
642 	struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
643 
644 	if (rtlpci->up_first_time)
645 		return;
646 
647 	if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
648 		rtl92ce_sw_led_on(hw, pled0);
649 	else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
650 		rtl92ce_sw_led_on(hw, pled0);
651 	else
652 		rtl92ce_sw_led_off(hw, pled0);
653 }
654 
655 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
656 {
657 	struct rtl_priv *rtlpriv = rtl_priv(hw);
658 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
659 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
660 
661 	unsigned char bytetmp;
662 	unsigned short wordtmp;
663 	u16 retry;
664 
665 	rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
666 	if (rtlpriv->btcoexist.bt_coexistence) {
667 		u32 value32;
668 
669 		value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
670 		value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
671 		rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
672 	}
673 	rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
674 	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
675 
676 	if (rtlpriv->btcoexist.bt_coexistence) {
677 		u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
678 
679 		u4b_tmp &= (~0x00024800);
680 		rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
681 	}
682 
683 	bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
684 	udelay(2);
685 
686 	rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
687 	udelay(2);
688 
689 	bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
690 	udelay(2);
691 
692 	retry = 0;
693 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
694 		rtl_read_dword(rtlpriv, 0xEC), bytetmp);
695 
696 	while ((bytetmp & BIT(0)) && retry < 1000) {
697 		retry++;
698 		udelay(50);
699 		bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
700 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
701 			rtl_read_dword(rtlpriv, 0xEC), bytetmp);
702 		udelay(50);
703 	}
704 
705 	rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
706 
707 	rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
708 	udelay(2);
709 
710 	if (rtlpriv->btcoexist.bt_coexistence) {
711 		bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
712 		rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
713 	}
714 
715 	rtl_write_word(rtlpriv, REG_CR, 0x2ff);
716 
717 	if (!_rtl92ce_llt_table_init(hw))
718 		return false;
719 
720 	rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
721 	rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
722 
723 	rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
724 
725 	wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
726 	wordtmp &= 0xf;
727 	wordtmp |= 0xF771;
728 	rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
729 
730 	rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
731 	rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
732 	rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
733 
734 	rtl_write_byte(rtlpriv, 0x4d0, 0x0);
735 
736 	rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
737 			((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
738 			DMA_BIT_MASK(32));
739 	rtl_write_dword(rtlpriv, REG_MGQ_DESA,
740 			(u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
741 			DMA_BIT_MASK(32));
742 	rtl_write_dword(rtlpriv, REG_VOQ_DESA,
743 			(u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
744 	rtl_write_dword(rtlpriv, REG_VIQ_DESA,
745 			(u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
746 	rtl_write_dword(rtlpriv, REG_BEQ_DESA,
747 			(u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
748 	rtl_write_dword(rtlpriv, REG_BKQ_DESA,
749 			(u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
750 	rtl_write_dword(rtlpriv, REG_HQ_DESA,
751 			(u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
752 			DMA_BIT_MASK(32));
753 	rtl_write_dword(rtlpriv, REG_RX_DESA,
754 			(u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
755 			DMA_BIT_MASK(32));
756 
757 	if (IS_92C_SERIAL(rtlhal->version))
758 		rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
759 	else
760 		rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
761 
762 	rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
763 
764 	bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
765 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
766 	do {
767 		retry++;
768 		bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
769 	} while ((retry < 200) && (bytetmp & BIT(7)));
770 
771 	_rtl92ce_gen_refresh_led_state(hw);
772 
773 	rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
774 
775 	return true;
776 }
777 
778 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
779 {
780 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
781 	struct rtl_priv *rtlpriv = rtl_priv(hw);
782 	u8 reg_bw_opmode;
783 	u32 reg_prsr;
784 
785 	reg_bw_opmode = BW_OPMODE_20MHZ;
786 	reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
787 
788 	rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
789 
790 	rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
791 
792 	rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
793 
794 	rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
795 
796 	rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
797 
798 	rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
799 
800 	rtl_write_word(rtlpriv, REG_RL, 0x0707);
801 
802 	rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
803 
804 	rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
805 
806 	rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
807 	rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
808 	rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
809 	rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
810 
811 	if ((rtlpriv->btcoexist.bt_coexistence) &&
812 	    (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
813 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
814 	else
815 		rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
816 
817 	rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
818 
819 	rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
820 
821 	rtlpci->reg_bcn_ctrl_val = 0x1f;
822 	rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
823 
824 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
825 
826 	rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
827 
828 	rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
829 	rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
830 
831 	if ((rtlpriv->btcoexist.bt_coexistence) &&
832 	    (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) {
833 		rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
834 		rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
835 	} else {
836 		rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
837 		rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
838 	}
839 
840 	if ((rtlpriv->btcoexist.bt_coexistence) &&
841 	    (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
842 		rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
843 	else
844 		rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
845 
846 	rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
847 
848 	rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
849 	rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
850 
851 	rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
852 
853 	rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
854 
855 	rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
856 	rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
857 
858 }
859 
860 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
861 {
862 	struct rtl_priv *rtlpriv = rtl_priv(hw);
863 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
864 
865 	rtl_write_byte(rtlpriv, 0x34b, 0x93);
866 	rtl_write_word(rtlpriv, 0x350, 0x870c);
867 	rtl_write_byte(rtlpriv, 0x352, 0x1);
868 
869 	if (ppsc->support_backdoor)
870 		rtl_write_byte(rtlpriv, 0x349, 0x1b);
871 	else
872 		rtl_write_byte(rtlpriv, 0x349, 0x03);
873 
874 	rtl_write_word(rtlpriv, 0x350, 0x2718);
875 	rtl_write_byte(rtlpriv, 0x352, 0x1);
876 }
877 
878 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
879 {
880 	struct rtl_priv *rtlpriv = rtl_priv(hw);
881 	u8 sec_reg_value;
882 
883 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
884 		"PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
885 		rtlpriv->sec.pairwise_enc_algorithm,
886 		rtlpriv->sec.group_enc_algorithm);
887 
888 	if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
889 		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
890 			"not open hw encryption\n");
891 		return;
892 	}
893 
894 	sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
895 
896 	if (rtlpriv->sec.use_defaultkey) {
897 		sec_reg_value |= SCR_TXUSEDK;
898 		sec_reg_value |= SCR_RXUSEDK;
899 	}
900 
901 	sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
902 
903 	rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
904 
905 	rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
906 		"The SECR-value %x\n", sec_reg_value);
907 
908 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
909 
910 }
911 
912 int rtl92ce_hw_init(struct ieee80211_hw *hw)
913 {
914 	struct rtl_priv *rtlpriv = rtl_priv(hw);
915 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
916 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
917 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
918 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
919 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
920 	bool rtstatus = true;
921 	bool is92c;
922 	int err;
923 	u8 tmp_u1b;
924 	unsigned long flags;
925 
926 	rtlpci->being_init_adapter = true;
927 
928 	/* Since this function can take a very long time (up to 350 ms)
929 	 * and can be called with irqs disabled, reenable the irqs
930 	 * to let the other devices continue being serviced.
931 	 *
932 	 * It is safe doing so since our own interrupts will only be enabled
933 	 * in a subsequent step.
934 	 */
935 	local_save_flags(flags);
936 	local_irq_enable();
937 
938 	rtlhal->fw_ready = false;
939 	rtlpriv->intf_ops->disable_aspm(hw);
940 	rtstatus = _rtl92ce_init_mac(hw);
941 	if (!rtstatus) {
942 		pr_err("Init MAC failed\n");
943 		err = 1;
944 		goto exit;
945 	}
946 
947 	err = rtl92c_download_fw(hw);
948 	if (err) {
949 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
950 			"Failed to download FW. Init HW without FW now..\n");
951 		err = 1;
952 		goto exit;
953 	}
954 
955 	rtlhal->fw_ready = true;
956 	rtlhal->last_hmeboxnum = 0;
957 	rtl92c_phy_mac_config(hw);
958 	/* because last function modify RCR, so we update
959 	 * rcr var here, or TP will unstable for receive_config
960 	 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
961 	 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
962 	rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
963 	rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
964 	rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
965 	rtl92c_phy_bb_config(hw);
966 	rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
967 	rtl92c_phy_rf_config(hw);
968 	if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
969 	    !IS_92C_SERIAL(rtlhal->version)) {
970 		rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
971 		rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
972 	} else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
973 		rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
974 		rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
975 		rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
976 		rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
977 		rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
978 		rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
979 	}
980 	rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
981 						 RF_CHNLBW, RFREG_OFFSET_MASK);
982 	rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
983 						 RF_CHNLBW, RFREG_OFFSET_MASK);
984 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
985 	rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
986 	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
987 	_rtl92ce_hw_configure(hw);
988 	rtl_cam_reset_all_entry(hw);
989 	rtl92ce_enable_hw_security_config(hw);
990 
991 	ppsc->rfpwr_state = ERFON;
992 
993 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
994 	_rtl92ce_enable_aspm_back_door(hw);
995 	rtlpriv->intf_ops->enable_aspm(hw);
996 
997 	rtl8192ce_bt_hw_init(hw);
998 
999 	if (ppsc->rfpwr_state == ERFON) {
1000 		rtl92c_phy_set_rfpath_switch(hw, 1);
1001 		if (rtlphy->iqk_initialized) {
1002 			rtl92c_phy_iq_calibrate(hw, true);
1003 		} else {
1004 			rtl92c_phy_iq_calibrate(hw, false);
1005 			rtlphy->iqk_initialized = true;
1006 		}
1007 
1008 		rtl92c_dm_check_txpower_tracking(hw);
1009 		rtl92c_phy_lc_calibrate(hw);
1010 	}
1011 
1012 	is92c = IS_92C_SERIAL(rtlhal->version);
1013 	tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1014 	if (!(tmp_u1b & BIT(0))) {
1015 		rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1016 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
1017 	}
1018 
1019 	if (!(tmp_u1b & BIT(1)) && is92c) {
1020 		rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1021 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n");
1022 	}
1023 
1024 	if (!(tmp_u1b & BIT(4))) {
1025 		tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1026 		tmp_u1b &= 0x0F;
1027 		rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1028 		udelay(10);
1029 		rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1030 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
1031 	}
1032 	rtl92c_dm_init(hw);
1033 exit:
1034 	local_irq_restore(flags);
1035 	rtlpci->being_init_adapter = false;
1036 	return err;
1037 }
1038 
1039 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
1040 {
1041 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1042 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1043 	enum version_8192c version = VERSION_UNKNOWN;
1044 	u32 value32;
1045 	const char *versionid;
1046 
1047 	value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1048 	if (value32 & TRP_VAUX_EN) {
1049 		version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1050 			   VERSION_A_CHIP_88C;
1051 	} else {
1052 		version = (enum version_8192c) (CHIP_VER_B |
1053 				((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) |
1054 				((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1055 		if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 &
1056 		     CHIP_VER_RTL_MASK)) {
1057 			version = (enum version_8192c)(version |
1058 				   ((((value32 & CHIP_VER_RTL_MASK) == BIT(12))
1059 				   ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) |
1060 				   CHIP_VENDOR_UMC));
1061 		}
1062 		if (IS_92C_SERIAL(version)) {
1063 			value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
1064 			version = (enum version_8192c)(version |
1065 				   ((CHIP_BONDING_IDENTIFIER(value32)
1066 				   == CHIP_BONDING_92C_1T2R) ?
1067 				   RF_TYPE_1T2R : 0));
1068 		}
1069 	}
1070 
1071 	switch (version) {
1072 	case VERSION_B_CHIP_92C:
1073 		versionid = "B_CHIP_92C";
1074 		break;
1075 	case VERSION_B_CHIP_88C:
1076 		versionid = "B_CHIP_88C";
1077 		break;
1078 	case VERSION_A_CHIP_92C:
1079 		versionid = "A_CHIP_92C";
1080 		break;
1081 	case VERSION_A_CHIP_88C:
1082 		versionid = "A_CHIP_88C";
1083 		break;
1084 	case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
1085 		versionid = "A_CUT_92C_1T2R";
1086 		break;
1087 	case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
1088 		versionid = "A_CUT_92C";
1089 		break;
1090 	case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
1091 		versionid = "A_CUT_88C";
1092 		break;
1093 	case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
1094 		versionid = "B_CUT_92C_1T2R";
1095 		break;
1096 	case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
1097 		versionid = "B_CUT_92C";
1098 		break;
1099 	case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
1100 		versionid = "B_CUT_88C";
1101 		break;
1102 	default:
1103 		versionid = "Unknown. Bug?";
1104 		break;
1105 	}
1106 
1107 	pr_info("Chip Version ID: %s\n", versionid);
1108 
1109 	switch (version & 0x3) {
1110 	case CHIP_88C:
1111 		rtlphy->rf_type = RF_1T1R;
1112 		break;
1113 	case CHIP_92C:
1114 		rtlphy->rf_type = RF_2T2R;
1115 		break;
1116 	case CHIP_92C_1T2R:
1117 		rtlphy->rf_type = RF_1T2R;
1118 		break;
1119 	default:
1120 		rtlphy->rf_type = RF_1T1R;
1121 		pr_err("ERROR RF_Type is set!!\n");
1122 		break;
1123 	}
1124 
1125 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1126 		rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
1127 
1128 	return version;
1129 }
1130 
1131 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1132 				     enum nl80211_iftype type)
1133 {
1134 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1135 	u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1136 	enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1137 	u8 mode = MSR_NOLINK;
1138 
1139 	bt_msr &= 0xfc;
1140 
1141 	switch (type) {
1142 	case NL80211_IFTYPE_UNSPECIFIED:
1143 		mode = MSR_NOLINK;
1144 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1145 			"Set Network type to NO LINK!\n");
1146 		break;
1147 	case NL80211_IFTYPE_ADHOC:
1148 		mode = MSR_ADHOC;
1149 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1150 			"Set Network type to Ad Hoc!\n");
1151 		break;
1152 	case NL80211_IFTYPE_STATION:
1153 		mode = MSR_INFRA;
1154 		ledaction = LED_CTL_LINK;
1155 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1156 			"Set Network type to STA!\n");
1157 		break;
1158 	case NL80211_IFTYPE_AP:
1159 		mode = MSR_AP;
1160 		ledaction = LED_CTL_LINK;
1161 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1162 			"Set Network type to AP!\n");
1163 		break;
1164 	case NL80211_IFTYPE_MESH_POINT:
1165 		mode = MSR_ADHOC;
1166 		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1167 			"Set Network type to Mesh Point!\n");
1168 		break;
1169 	default:
1170 		pr_err("Network type %d not supported!\n", type);
1171 		return 1;
1172 
1173 	}
1174 
1175 	/* MSR_INFRA == Link in infrastructure network;
1176 	 * MSR_ADHOC == Link in ad hoc network;
1177 	 * Therefore, check link state is necessary.
1178 	 *
1179 	 * MSR_AP == AP mode; link state does not matter here.
1180 	 */
1181 	if (mode != MSR_AP &&
1182 	    rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1183 		mode = MSR_NOLINK;
1184 		ledaction = LED_CTL_NO_LINK;
1185 	}
1186 	if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1187 		_rtl92ce_stop_tx_beacon(hw);
1188 		_rtl92ce_enable_bcn_sub_func(hw);
1189 	} else if (mode == MSR_ADHOC || mode == MSR_AP) {
1190 		_rtl92ce_resume_tx_beacon(hw);
1191 		_rtl92ce_disable_bcn_sub_func(hw);
1192 	} else {
1193 		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1194 			"Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1195 			mode);
1196 	}
1197 	rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1198 
1199 	rtlpriv->cfg->ops->led_control(hw, ledaction);
1200 	if (mode == MSR_AP)
1201 		rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1202 	else
1203 		rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1204 	return 0;
1205 }
1206 
1207 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1208 {
1209 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1210 	u32 reg_rcr;
1211 
1212 	if (rtlpriv->psc.rfpwr_state != ERFON)
1213 		return;
1214 
1215 	rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1216 
1217 	if (check_bssid) {
1218 		reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1219 		rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1220 					      (u8 *) (&reg_rcr));
1221 		_rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1222 	} else if (!check_bssid) {
1223 		reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1224 		_rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1225 		rtlpriv->cfg->ops->set_hw_reg(hw,
1226 					      HW_VAR_RCR, (u8 *) (&reg_rcr));
1227 	}
1228 
1229 }
1230 
1231 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1232 {
1233 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1234 
1235 	if (_rtl92ce_set_media_status(hw, type))
1236 		return -EOPNOTSUPP;
1237 
1238 	if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1239 		if (type != NL80211_IFTYPE_AP &&
1240 		    type != NL80211_IFTYPE_MESH_POINT)
1241 			rtl92ce_set_check_bssid(hw, true);
1242 	} else {
1243 		rtl92ce_set_check_bssid(hw, false);
1244 	}
1245 
1246 	return 0;
1247 }
1248 
1249 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1250 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1251 {
1252 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1253 
1254 	rtl92c_dm_init_edca_turbo(hw);
1255 	switch (aci) {
1256 	case AC1_BK:
1257 		rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1258 		break;
1259 	case AC0_BE:
1260 		/* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1261 		break;
1262 	case AC2_VI:
1263 		rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1264 		break;
1265 	case AC3_VO:
1266 		rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1267 		break;
1268 	default:
1269 		WARN_ONCE(true, "rtl8192ce: invalid aci: %d !\n", aci);
1270 		break;
1271 	}
1272 }
1273 
1274 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1275 {
1276 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1277 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1278 
1279 	rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1280 	rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1281 	rtlpci->irq_enabled = true;
1282 }
1283 
1284 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1285 {
1286 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1287 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1288 
1289 	rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1290 	rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1291 	rtlpci->irq_enabled = false;
1292 }
1293 
1294 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1295 {
1296 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1297 	struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1298 	u8 u1b_tmp;
1299 	u32 u4b_tmp;
1300 
1301 	rtlpriv->intf_ops->enable_aspm(hw);
1302 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1303 	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1304 	rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1305 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1306 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1307 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1308 	if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7))
1309 		rtl92c_firmware_selfreset(hw);
1310 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1311 	rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1312 	rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1313 	u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1314 	if ((rtlpriv->btcoexist.bt_coexistence) &&
1315 	    ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
1316 	     (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8))) {
1317 		rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1318 				(u1b_tmp << 8));
1319 	} else {
1320 		rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1321 				(u1b_tmp << 8));
1322 	}
1323 	rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1324 	rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1325 	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1326 	if (!IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version))
1327 		rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1328 	if (rtlpriv->btcoexist.bt_coexistence) {
1329 		u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1330 		u4b_tmp |= 0x03824800;
1331 		rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1332 	} else {
1333 		rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1334 	}
1335 
1336 	rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1337 	rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1338 }
1339 
1340 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1341 {
1342 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1343 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1344 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1345 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1346 	enum nl80211_iftype opmode;
1347 
1348 	mac->link_state = MAC80211_NOLINK;
1349 	opmode = NL80211_IFTYPE_UNSPECIFIED;
1350 	_rtl92ce_set_media_status(hw, opmode);
1351 	if (rtlpci->driver_is_goingto_unload ||
1352 	    ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1353 		rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1354 	RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1355 	_rtl92ce_poweroff_adapter(hw);
1356 
1357 	/* after power off we should do iqk again */
1358 	rtlpriv->phy.iqk_initialized = false;
1359 }
1360 
1361 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1362 				  struct rtl_int *intvec)
1363 {
1364 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1365 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1366 
1367 	intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1368 	rtl_write_dword(rtlpriv, ISR, intvec->inta);
1369 }
1370 
1371 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1372 {
1373 
1374 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1375 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1376 	u16 bcn_interval, atim_window;
1377 
1378 	bcn_interval = mac->beacon_interval;
1379 	atim_window = 2;	/*FIX MERGE */
1380 	rtl92ce_disable_interrupt(hw);
1381 	rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1382 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1383 	rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1384 	rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1385 	rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1386 	rtl_write_byte(rtlpriv, 0x606, 0x30);
1387 	rtl92ce_enable_interrupt(hw);
1388 }
1389 
1390 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1391 {
1392 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1393 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1394 	u16 bcn_interval = mac->beacon_interval;
1395 
1396 	rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
1397 		"beacon_interval:%d\n", bcn_interval);
1398 	rtl92ce_disable_interrupt(hw);
1399 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1400 	rtl92ce_enable_interrupt(hw);
1401 }
1402 
1403 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1404 				   u32 add_msr, u32 rm_msr)
1405 {
1406 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1407 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1408 
1409 	rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1410 		add_msr, rm_msr);
1411 
1412 	if (add_msr)
1413 		rtlpci->irq_mask[0] |= add_msr;
1414 	if (rm_msr)
1415 		rtlpci->irq_mask[0] &= (~rm_msr);
1416 	rtl92ce_disable_interrupt(hw);
1417 	rtl92ce_enable_interrupt(hw);
1418 }
1419 
1420 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1421 						 bool autoload_fail,
1422 						 u8 *hwinfo)
1423 {
1424 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1425 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1426 	u8 rf_path, index, tempval;
1427 	u16 i;
1428 
1429 	for (rf_path = 0; rf_path < 2; rf_path++) {
1430 		for (i = 0; i < 3; i++) {
1431 			if (!autoload_fail) {
1432 				rtlefuse->
1433 				    eeprom_chnlarea_txpwr_cck[rf_path][i] =
1434 				    hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1435 				rtlefuse->
1436 				    eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1437 				    hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1438 					   i];
1439 			} else {
1440 				rtlefuse->
1441 				    eeprom_chnlarea_txpwr_cck[rf_path][i] =
1442 				    EEPROM_DEFAULT_TXPOWERLEVEL;
1443 				rtlefuse->
1444 				    eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1445 				    EEPROM_DEFAULT_TXPOWERLEVEL;
1446 			}
1447 		}
1448 	}
1449 
1450 	for (i = 0; i < 3; i++) {
1451 		if (!autoload_fail)
1452 			tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1453 		else
1454 			tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1455 		rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1456 		    (tempval & 0xf);
1457 		rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1458 		    ((tempval & 0xf0) >> 4);
1459 	}
1460 
1461 	for (rf_path = 0; rf_path < 2; rf_path++)
1462 		for (i = 0; i < 3; i++)
1463 			RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1464 				"RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1465 				rf_path, i,
1466 				rtlefuse->
1467 				eeprom_chnlarea_txpwr_cck[rf_path][i]);
1468 	for (rf_path = 0; rf_path < 2; rf_path++)
1469 		for (i = 0; i < 3; i++)
1470 			RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1471 				"RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1472 				rf_path, i,
1473 				rtlefuse->
1474 				eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
1475 	for (rf_path = 0; rf_path < 2; rf_path++)
1476 		for (i = 0; i < 3; i++)
1477 			RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1478 				"RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1479 				rf_path, i,
1480 				rtlefuse->
1481 				eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
1482 
1483 	for (rf_path = 0; rf_path < 2; rf_path++) {
1484 		for (i = 0; i < 14; i++) {
1485 			index = rtl92c_get_chnl_group((u8)i);
1486 
1487 			rtlefuse->txpwrlevel_cck[rf_path][i] =
1488 			    rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1489 			rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1490 			    rtlefuse->
1491 			    eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1492 
1493 			if ((rtlefuse->
1494 			     eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1495 			     rtlefuse->
1496 			     eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
1497 			    > 0) {
1498 				rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1499 				    rtlefuse->
1500 				    eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1501 				    [index] -
1502 				    rtlefuse->
1503 				    eprom_chnl_txpwr_ht40_2sdf[rf_path]
1504 				    [index];
1505 			} else {
1506 				rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1507 			}
1508 		}
1509 
1510 		for (i = 0; i < 14; i++) {
1511 			RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1512 				"RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1513 				rf_path, i,
1514 				rtlefuse->txpwrlevel_cck[rf_path][i],
1515 				rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1516 				rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1517 		}
1518 	}
1519 
1520 	for (i = 0; i < 3; i++) {
1521 		if (!autoload_fail) {
1522 			rtlefuse->eeprom_pwrlimit_ht40[i] =
1523 			    hwinfo[EEPROM_TXPWR_GROUP + i];
1524 			rtlefuse->eeprom_pwrlimit_ht20[i] =
1525 			    hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1526 		} else {
1527 			rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1528 			rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1529 		}
1530 	}
1531 
1532 	for (rf_path = 0; rf_path < 2; rf_path++) {
1533 		for (i = 0; i < 14; i++) {
1534 			index = rtl92c_get_chnl_group((u8)i);
1535 
1536 			if (rf_path == RF90_PATH_A) {
1537 				rtlefuse->pwrgroup_ht20[rf_path][i] =
1538 				    (rtlefuse->eeprom_pwrlimit_ht20[index]
1539 				     & 0xf);
1540 				rtlefuse->pwrgroup_ht40[rf_path][i] =
1541 				    (rtlefuse->eeprom_pwrlimit_ht40[index]
1542 				     & 0xf);
1543 			} else if (rf_path == RF90_PATH_B) {
1544 				rtlefuse->pwrgroup_ht20[rf_path][i] =
1545 				    ((rtlefuse->eeprom_pwrlimit_ht20[index]
1546 				      & 0xf0) >> 4);
1547 				rtlefuse->pwrgroup_ht40[rf_path][i] =
1548 				    ((rtlefuse->eeprom_pwrlimit_ht40[index]
1549 				      & 0xf0) >> 4);
1550 			}
1551 
1552 			RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1553 				"RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1554 				rf_path, i,
1555 				rtlefuse->pwrgroup_ht20[rf_path][i]);
1556 			RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1557 				"RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1558 				rf_path, i,
1559 				rtlefuse->pwrgroup_ht40[rf_path][i]);
1560 		}
1561 	}
1562 
1563 	for (i = 0; i < 14; i++) {
1564 		index = rtl92c_get_chnl_group((u8)i);
1565 
1566 		if (!autoload_fail)
1567 			tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1568 		else
1569 			tempval = EEPROM_DEFAULT_HT20_DIFF;
1570 
1571 		rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1572 		rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1573 		    ((tempval >> 4) & 0xF);
1574 
1575 		if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1576 			rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1577 
1578 		if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1579 			rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1580 
1581 		index = rtl92c_get_chnl_group((u8)i);
1582 
1583 		if (!autoload_fail)
1584 			tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1585 		else
1586 			tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1587 
1588 		rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1589 		rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1590 		    ((tempval >> 4) & 0xF);
1591 	}
1592 
1593 	rtlefuse->legacy_ht_txpowerdiff =
1594 	    rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1595 
1596 	for (i = 0; i < 14; i++)
1597 		RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1598 			"RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1599 			i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1600 	for (i = 0; i < 14; i++)
1601 		RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1602 			"RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1603 			i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1604 	for (i = 0; i < 14; i++)
1605 		RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1606 			"RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1607 			i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1608 	for (i = 0; i < 14; i++)
1609 		RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1610 			"RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1611 			i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1612 
1613 	if (!autoload_fail)
1614 		rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1615 	else
1616 		rtlefuse->eeprom_regulatory = 0;
1617 	RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1618 		"eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1619 
1620 	if (!autoload_fail) {
1621 		rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1622 		rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1623 	} else {
1624 		rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1625 		rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1626 	}
1627 	RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1628 		rtlefuse->eeprom_tssi[RF90_PATH_A],
1629 		rtlefuse->eeprom_tssi[RF90_PATH_B]);
1630 
1631 	if (!autoload_fail)
1632 		tempval = hwinfo[EEPROM_THERMAL_METER];
1633 	else
1634 		tempval = EEPROM_DEFAULT_THERMALMETER;
1635 	rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1636 
1637 	if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1638 		rtlefuse->apk_thermalmeterignore = true;
1639 
1640 	rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1641 	RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1642 		"thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1643 }
1644 
1645 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1646 {
1647 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1648 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1649 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1650 	int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1651 			EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1652 			EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1653 			COUNTRY_CODE_WORLD_WIDE_13};
1654 	u8 *hwinfo;
1655 
1656 	hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1657 	if (!hwinfo)
1658 		return;
1659 
1660 	if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1661 		goto exit;
1662 
1663 	_rtl92ce_read_txpower_info_from_hwpg(hw,
1664 					     rtlefuse->autoload_failflag,
1665 					     hwinfo);
1666 
1667 	rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1668 						 rtlefuse->autoload_failflag,
1669 						 hwinfo);
1670 	if (rtlhal->oem_id == RT_CID_DEFAULT) {
1671 		switch (rtlefuse->eeprom_oemid) {
1672 		case EEPROM_CID_DEFAULT:
1673 			if (rtlefuse->eeprom_did == 0x8176) {
1674 				if ((rtlefuse->eeprom_svid == 0x103C &&
1675 				     rtlefuse->eeprom_smid == 0x1629))
1676 					rtlhal->oem_id = RT_CID_819X_HP;
1677 				else
1678 					rtlhal->oem_id = RT_CID_DEFAULT;
1679 			} else {
1680 				rtlhal->oem_id = RT_CID_DEFAULT;
1681 			}
1682 			break;
1683 		case EEPROM_CID_TOSHIBA:
1684 			rtlhal->oem_id = RT_CID_TOSHIBA;
1685 			break;
1686 		case EEPROM_CID_QMI:
1687 			rtlhal->oem_id = RT_CID_819X_QMI;
1688 			break;
1689 		case EEPROM_CID_WHQL:
1690 		default:
1691 			rtlhal->oem_id = RT_CID_DEFAULT;
1692 			break;
1693 		}
1694 	}
1695 exit:
1696 	kfree(hwinfo);
1697 }
1698 
1699 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1700 {
1701 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1702 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1703 
1704 	switch (rtlhal->oem_id) {
1705 	case RT_CID_819X_HP:
1706 		rtlpriv->ledctl.led_opendrain = true;
1707 		break;
1708 	case RT_CID_819X_LENOVO:
1709 	case RT_CID_DEFAULT:
1710 	case RT_CID_TOSHIBA:
1711 	case RT_CID_CCX:
1712 	case RT_CID_819X_ACER:
1713 	case RT_CID_WHQL:
1714 	default:
1715 		break;
1716 	}
1717 	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1718 		"RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1719 }
1720 
1721 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1722 {
1723 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1724 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1725 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1726 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1727 	u8 tmp_u1b;
1728 
1729 	rtlhal->version = _rtl92ce_read_chip_version(hw);
1730 	if (get_rf_type(rtlphy) == RF_1T1R)
1731 		rtlpriv->dm.rfpath_rxenable[0] = true;
1732 	else
1733 		rtlpriv->dm.rfpath_rxenable[0] =
1734 		    rtlpriv->dm.rfpath_rxenable[1] = true;
1735 	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1736 		rtlhal->version);
1737 	tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1738 	if (tmp_u1b & BIT(4)) {
1739 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1740 		rtlefuse->epromtype = EEPROM_93C46;
1741 	} else {
1742 		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1743 		rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1744 	}
1745 	if (tmp_u1b & BIT(5)) {
1746 		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1747 		rtlefuse->autoload_failflag = false;
1748 		_rtl92ce_read_adapter_info(hw);
1749 	} else {
1750 		pr_err("Autoload ERR!!\n");
1751 	}
1752 	_rtl92ce_hal_customized_behavior(hw);
1753 }
1754 
1755 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1756 		struct ieee80211_sta *sta)
1757 {
1758 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1759 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1760 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1761 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1762 	u32 ratr_value;
1763 	u8 ratr_index = 0;
1764 	u8 nmode = mac->ht_enable;
1765 	u16 shortgi_rate;
1766 	u32 tmp_ratr_value;
1767 	u8 curtxbw_40mhz = mac->bw_40;
1768 	u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1769 			       1 : 0;
1770 	u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1771 			       1 : 0;
1772 	enum wireless_mode wirelessmode = mac->mode;
1773 	u32 ratr_mask;
1774 
1775 	if (rtlhal->current_bandtype == BAND_ON_5G)
1776 		ratr_value = sta->deflink.supp_rates[1] << 4;
1777 	else
1778 		ratr_value = sta->deflink.supp_rates[0];
1779 	if (mac->opmode == NL80211_IFTYPE_ADHOC)
1780 		ratr_value = 0xfff;
1781 
1782 	ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1783 			sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1784 	switch (wirelessmode) {
1785 	case WIRELESS_MODE_B:
1786 		if (ratr_value & 0x0000000c)
1787 			ratr_value &= 0x0000000d;
1788 		else
1789 			ratr_value &= 0x0000000f;
1790 		break;
1791 	case WIRELESS_MODE_G:
1792 		ratr_value &= 0x00000FF5;
1793 		break;
1794 	case WIRELESS_MODE_N_24G:
1795 	case WIRELESS_MODE_N_5G:
1796 		nmode = 1;
1797 		if (get_rf_type(rtlphy) == RF_1T2R ||
1798 		    get_rf_type(rtlphy) == RF_1T1R)
1799 			ratr_mask = 0x000ff005;
1800 		else
1801 			ratr_mask = 0x0f0ff005;
1802 
1803 		ratr_value &= ratr_mask;
1804 		break;
1805 	default:
1806 		if (rtlphy->rf_type == RF_1T2R)
1807 			ratr_value &= 0x000ff0ff;
1808 		else
1809 			ratr_value &= 0x0f0ff0ff;
1810 
1811 		break;
1812 	}
1813 
1814 	if ((rtlpriv->btcoexist.bt_coexistence) &&
1815 	    (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
1816 	    (rtlpriv->btcoexist.bt_cur_state) &&
1817 	    (rtlpriv->btcoexist.bt_ant_isolation) &&
1818 	    ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
1819 	    (rtlpriv->btcoexist.bt_service == BT_BUSY)))
1820 		ratr_value &= 0x0fffcfc0;
1821 	else
1822 		ratr_value &= 0x0FFFFFFF;
1823 
1824 	if (nmode && ((curtxbw_40mhz &&
1825 			 curshortgi_40mhz) || (!curtxbw_40mhz &&
1826 					       curshortgi_20mhz))) {
1827 
1828 		ratr_value |= 0x10000000;
1829 		tmp_ratr_value = (ratr_value >> 12);
1830 
1831 		for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1832 			if ((1 << shortgi_rate) & tmp_ratr_value)
1833 				break;
1834 		}
1835 
1836 		shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1837 		    (shortgi_rate << 4) | (shortgi_rate);
1838 	}
1839 
1840 	rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1841 
1842 	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1843 		rtl_read_dword(rtlpriv, REG_ARFR0));
1844 }
1845 
1846 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1847 		struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
1848 {
1849 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1850 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
1851 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1852 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1853 	struct rtl_sta_info *sta_entry = NULL;
1854 	u32 ratr_bitmap;
1855 	u8 ratr_index;
1856 	u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap &
1857 			    IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
1858 	u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap &
1859 			       IEEE80211_HT_CAP_SGI_40) ?  1 : 0;
1860 	u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1861 				1 : 0;
1862 	enum wireless_mode wirelessmode = 0;
1863 	bool shortgi = false;
1864 	u8 rate_mask[5];
1865 	u8 macid = 0;
1866 
1867 	sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1868 	wirelessmode = sta_entry->wireless_mode;
1869 	if (mac->opmode == NL80211_IFTYPE_STATION ||
1870 	    mac->opmode == NL80211_IFTYPE_MESH_POINT)
1871 		curtxbw_40mhz = mac->bw_40;
1872 	else if (mac->opmode == NL80211_IFTYPE_AP ||
1873 		mac->opmode == NL80211_IFTYPE_ADHOC)
1874 		macid = sta->aid + 1;
1875 
1876 	if (rtlhal->current_bandtype == BAND_ON_5G)
1877 		ratr_bitmap = sta->deflink.supp_rates[1] << 4;
1878 	else
1879 		ratr_bitmap = sta->deflink.supp_rates[0];
1880 	if (mac->opmode == NL80211_IFTYPE_ADHOC)
1881 		ratr_bitmap = 0xfff;
1882 	ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1883 			sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1884 	switch (wirelessmode) {
1885 	case WIRELESS_MODE_B:
1886 		ratr_index = RATR_INX_WIRELESS_B;
1887 		if (ratr_bitmap & 0x0000000c)
1888 			ratr_bitmap &= 0x0000000d;
1889 		else
1890 			ratr_bitmap &= 0x0000000f;
1891 		break;
1892 	case WIRELESS_MODE_G:
1893 		ratr_index = RATR_INX_WIRELESS_GB;
1894 
1895 		if (rssi_level == 1)
1896 			ratr_bitmap &= 0x00000f00;
1897 		else if (rssi_level == 2)
1898 			ratr_bitmap &= 0x00000ff0;
1899 		else
1900 			ratr_bitmap &= 0x00000ff5;
1901 		break;
1902 	case WIRELESS_MODE_A:
1903 		ratr_index = RATR_INX_WIRELESS_A;
1904 		ratr_bitmap &= 0x00000ff0;
1905 		break;
1906 	case WIRELESS_MODE_N_24G:
1907 	case WIRELESS_MODE_N_5G:
1908 		ratr_index = RATR_INX_WIRELESS_NGB;
1909 
1910 		if (rtlphy->rf_type == RF_1T2R ||
1911 		    rtlphy->rf_type == RF_1T1R) {
1912 			if (curtxbw_40mhz) {
1913 				if (rssi_level == 1)
1914 					ratr_bitmap &= 0x000f0000;
1915 				else if (rssi_level == 2)
1916 					ratr_bitmap &= 0x000ff000;
1917 				else
1918 					ratr_bitmap &= 0x000ff015;
1919 			} else {
1920 				if (rssi_level == 1)
1921 					ratr_bitmap &= 0x000f0000;
1922 				else if (rssi_level == 2)
1923 					ratr_bitmap &= 0x000ff000;
1924 				else
1925 					ratr_bitmap &= 0x000ff005;
1926 			}
1927 		} else {
1928 			if (curtxbw_40mhz) {
1929 				if (rssi_level == 1)
1930 					ratr_bitmap &= 0x0f0f0000;
1931 				else if (rssi_level == 2)
1932 					ratr_bitmap &= 0x0f0ff000;
1933 				else
1934 					ratr_bitmap &= 0x0f0ff015;
1935 			} else {
1936 				if (rssi_level == 1)
1937 					ratr_bitmap &= 0x0f0f0000;
1938 				else if (rssi_level == 2)
1939 					ratr_bitmap &= 0x0f0ff000;
1940 				else
1941 					ratr_bitmap &= 0x0f0ff005;
1942 			}
1943 		}
1944 
1945 		if ((curtxbw_40mhz && curshortgi_40mhz) ||
1946 		    (!curtxbw_40mhz && curshortgi_20mhz)) {
1947 
1948 			if (macid == 0)
1949 				shortgi = true;
1950 			else if (macid == 1)
1951 				shortgi = false;
1952 		}
1953 		break;
1954 	default:
1955 		ratr_index = RATR_INX_WIRELESS_NGB;
1956 
1957 		if (rtlphy->rf_type == RF_1T2R)
1958 			ratr_bitmap &= 0x000ff0ff;
1959 		else
1960 			ratr_bitmap &= 0x0f0ff0ff;
1961 		break;
1962 	}
1963 	sta_entry->ratr_index = ratr_index;
1964 
1965 	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
1966 		"ratr_bitmap :%x\n", ratr_bitmap);
1967 	*(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
1968 				     (ratr_index << 28);
1969 	rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1970 	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
1971 		"Rate_index:%x, ratr_val:%x, %5phC\n",
1972 		ratr_index, ratr_bitmap, rate_mask);
1973 	rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1974 }
1975 
1976 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
1977 		struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
1978 {
1979 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1980 
1981 	if (rtlpriv->dm.useramask)
1982 		rtl92ce_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
1983 	else
1984 		rtl92ce_update_hal_rate_table(hw, sta);
1985 }
1986 
1987 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1988 {
1989 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1990 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1991 	u16 sifs_timer;
1992 
1993 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
1994 				      &mac->slot_time);
1995 	if (!mac->ht_enable)
1996 		sifs_timer = 0x0a0a;
1997 	else
1998 		sifs_timer = 0x1010;
1999 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2000 }
2001 
2002 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2003 {
2004 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2005 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2006 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2007 	enum rf_pwrstate e_rfpowerstate_toset;
2008 	u8 u1tmp;
2009 	bool actuallyset = false;
2010 	unsigned long flag;
2011 
2012 	if (rtlpci->being_init_adapter)
2013 		return false;
2014 
2015 	if (ppsc->swrf_processing)
2016 		return false;
2017 
2018 	spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2019 	if (ppsc->rfchange_inprogress) {
2020 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2021 		return false;
2022 	} else {
2023 		ppsc->rfchange_inprogress = true;
2024 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2025 	}
2026 
2027 	rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2028 		       REG_MAC_PINMUX_CFG)&~(BIT(3)));
2029 
2030 	u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2031 	e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2032 
2033 	if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2034 		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2035 			"GPIOChangeRF  - HW Radio ON, RF ON\n");
2036 
2037 		e_rfpowerstate_toset = ERFON;
2038 		ppsc->hwradiooff = false;
2039 		actuallyset = true;
2040 	} else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2041 		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2042 			"GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2043 
2044 		e_rfpowerstate_toset = ERFOFF;
2045 		ppsc->hwradiooff = true;
2046 		actuallyset = true;
2047 	}
2048 
2049 	if (actuallyset) {
2050 		spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2051 		ppsc->rfchange_inprogress = false;
2052 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2053 	} else {
2054 		if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2055 			RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2056 
2057 		spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2058 		ppsc->rfchange_inprogress = false;
2059 		spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2060 	}
2061 
2062 	*valid = 1;
2063 	return !ppsc->hwradiooff;
2064 
2065 }
2066 
2067 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2068 		     u8 *p_macaddr, bool is_group, u8 enc_algo,
2069 		     bool is_wepkey, bool clear_all)
2070 {
2071 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2072 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2073 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2074 	u8 *macaddr = p_macaddr;
2075 	u32 entry_id = 0;
2076 	bool is_pairwise = false;
2077 
2078 	static u8 cam_const_addr[4][6] = {
2079 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2080 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2081 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2082 		{0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2083 	};
2084 	static u8 cam_const_broad[] = {
2085 		0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2086 	};
2087 
2088 	if (clear_all) {
2089 		u8 idx = 0;
2090 		u8 cam_offset = 0;
2091 		u8 clear_number = 5;
2092 
2093 		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2094 
2095 		for (idx = 0; idx < clear_number; idx++) {
2096 			rtl_cam_mark_invalid(hw, cam_offset + idx);
2097 			rtl_cam_empty_entry(hw, cam_offset + idx);
2098 
2099 			if (idx < 5) {
2100 				memset(rtlpriv->sec.key_buf[idx], 0,
2101 				       MAX_KEY_LEN);
2102 				rtlpriv->sec.key_len[idx] = 0;
2103 			}
2104 		}
2105 
2106 	} else {
2107 		switch (enc_algo) {
2108 		case WEP40_ENCRYPTION:
2109 			enc_algo = CAM_WEP40;
2110 			break;
2111 		case WEP104_ENCRYPTION:
2112 			enc_algo = CAM_WEP104;
2113 			break;
2114 		case TKIP_ENCRYPTION:
2115 			enc_algo = CAM_TKIP;
2116 			break;
2117 		case AESCCMP_ENCRYPTION:
2118 			enc_algo = CAM_AES;
2119 			break;
2120 		default:
2121 			pr_err("switch case %#x not processed\n",
2122 			       enc_algo);
2123 			enc_algo = CAM_TKIP;
2124 			break;
2125 		}
2126 
2127 		if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2128 			macaddr = cam_const_addr[key_index];
2129 			entry_id = key_index;
2130 		} else {
2131 			if (is_group) {
2132 				macaddr = cam_const_broad;
2133 				entry_id = key_index;
2134 			} else {
2135 				if (mac->opmode == NL80211_IFTYPE_AP ||
2136 				    mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2137 					entry_id = rtl_cam_get_free_entry(hw,
2138 								 p_macaddr);
2139 					if (entry_id >=  TOTAL_CAM_ENTRY) {
2140 						pr_err("Can not find free hw security cam entry\n");
2141 						return;
2142 					}
2143 				} else {
2144 					entry_id = CAM_PAIRWISE_KEY_POSITION;
2145 				}
2146 
2147 				key_index = PAIRWISE_KEYIDX;
2148 				is_pairwise = true;
2149 			}
2150 		}
2151 
2152 		if (rtlpriv->sec.key_len[key_index] == 0) {
2153 			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2154 				"delete one entry, entry_id is %d\n",
2155 				 entry_id);
2156 			if (mac->opmode == NL80211_IFTYPE_AP ||
2157 			    mac->opmode == NL80211_IFTYPE_MESH_POINT)
2158 				rtl_cam_del_entry(hw, p_macaddr);
2159 			rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2160 		} else {
2161 			rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
2162 				"The insert KEY length is %d\n",
2163 				rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2164 			rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
2165 				"The insert KEY is %x %x\n",
2166 				rtlpriv->sec.key_buf[0][0],
2167 				rtlpriv->sec.key_buf[0][1]);
2168 
2169 			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2170 				"add one entry\n");
2171 			if (is_pairwise) {
2172 				RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2173 					      "Pairwise Key content",
2174 					      rtlpriv->sec.pairwise_key,
2175 					      rtlpriv->sec.
2176 					      key_len[PAIRWISE_KEYIDX]);
2177 
2178 				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2179 					"set Pairwise key\n");
2180 
2181 				rtl_cam_add_one_entry(hw, macaddr, key_index,
2182 						      entry_id, enc_algo,
2183 						      CAM_CONFIG_NO_USEDK,
2184 						      rtlpriv->sec.
2185 						      key_buf[key_index]);
2186 			} else {
2187 				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2188 					"set group key\n");
2189 
2190 				if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2191 					rtl_cam_add_one_entry(hw,
2192 						rtlefuse->dev_addr,
2193 						PAIRWISE_KEYIDX,
2194 						CAM_PAIRWISE_KEY_POSITION,
2195 						enc_algo,
2196 						CAM_CONFIG_NO_USEDK,
2197 						rtlpriv->sec.key_buf
2198 						[entry_id]);
2199 				}
2200 
2201 				rtl_cam_add_one_entry(hw, macaddr, key_index,
2202 						entry_id, enc_algo,
2203 						CAM_CONFIG_NO_USEDK,
2204 						rtlpriv->sec.key_buf[entry_id]);
2205 			}
2206 
2207 		}
2208 	}
2209 }
2210 
2211 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2212 {
2213 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2214 
2215 	rtlpriv->btcoexist.bt_coexistence =
2216 			rtlpriv->btcoexist.eeprom_bt_coexist;
2217 	rtlpriv->btcoexist.bt_ant_num =
2218 			rtlpriv->btcoexist.eeprom_bt_ant_num;
2219 	rtlpriv->btcoexist.bt_coexist_type =
2220 			rtlpriv->btcoexist.eeprom_bt_type;
2221 
2222 	if (rtlpriv->btcoexist.reg_bt_iso == 2)
2223 		rtlpriv->btcoexist.bt_ant_isolation =
2224 			rtlpriv->btcoexist.eeprom_bt_ant_isol;
2225 	else
2226 		rtlpriv->btcoexist.bt_ant_isolation =
2227 			rtlpriv->btcoexist.reg_bt_iso;
2228 
2229 	rtlpriv->btcoexist.bt_radio_shared_type =
2230 			rtlpriv->btcoexist.eeprom_bt_radio_shared;
2231 
2232 	if (rtlpriv->btcoexist.bt_coexistence) {
2233 		if (rtlpriv->btcoexist.reg_bt_sco == 1)
2234 			rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION;
2235 		else if (rtlpriv->btcoexist.reg_bt_sco == 2)
2236 			rtlpriv->btcoexist.bt_service = BT_SCO;
2237 		else if (rtlpriv->btcoexist.reg_bt_sco == 4)
2238 			rtlpriv->btcoexist.bt_service = BT_BUSY;
2239 		else if (rtlpriv->btcoexist.reg_bt_sco == 5)
2240 			rtlpriv->btcoexist.bt_service = BT_OTHERBUSY;
2241 		else
2242 			rtlpriv->btcoexist.bt_service = BT_IDLE;
2243 
2244 		rtlpriv->btcoexist.bt_edca_ul = 0;
2245 		rtlpriv->btcoexist.bt_edca_dl = 0;
2246 		rtlpriv->btcoexist.bt_rssi_state = 0xff;
2247 	}
2248 }
2249 
2250 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2251 					      bool auto_load_fail, u8 *hwinfo)
2252 {
2253 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2254 	u8 val;
2255 
2256 	if (!auto_load_fail) {
2257 		rtlpriv->btcoexist.eeprom_bt_coexist =
2258 					((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2259 		val = hwinfo[RF_OPTION4];
2260 		rtlpriv->btcoexist.eeprom_bt_type = ((val & 0xe) >> 1);
2261 		rtlpriv->btcoexist.eeprom_bt_ant_num = (val & 0x1);
2262 		rtlpriv->btcoexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4);
2263 		rtlpriv->btcoexist.eeprom_bt_radio_shared =
2264 							 ((val & 0x20) >> 5);
2265 	} else {
2266 		rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2267 		rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE;
2268 		rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2269 		rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2270 		rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2271 	}
2272 
2273 	rtl8192ce_bt_var_init(hw);
2274 }
2275 
2276 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2277 {
2278 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2279 
2280 	/* 0:Low, 1:High, 2:From Efuse. */
2281 	rtlpriv->btcoexist.reg_bt_iso = 2;
2282 	/* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2283 	rtlpriv->btcoexist.reg_bt_sco = 3;
2284 	/* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2285 	rtlpriv->btcoexist.reg_bt_sco = 0;
2286 }
2287 
2288 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2289 {
2290 	struct rtl_priv *rtlpriv = rtl_priv(hw);
2291 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
2292 
2293 	u8 u1_tmp;
2294 
2295 	if (rtlpriv->btcoexist.bt_coexistence &&
2296 	    ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
2297 	      rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) {
2298 
2299 		if (rtlpriv->btcoexist.bt_ant_isolation)
2300 			rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2301 
2302 		u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) & BIT(0);
2303 		u1_tmp = u1_tmp |
2304 			 ((rtlpriv->btcoexist.bt_ant_isolation == 1) ?
2305 			 0 : BIT(1)) |
2306 			 ((rtlpriv->btcoexist.bt_service == BT_SCO) ?
2307 			 0 : BIT(2));
2308 		rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2309 
2310 		rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2311 		rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2312 		rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2313 
2314 		/* Config to 1T1R. */
2315 		if (rtlphy->rf_type == RF_1T1R) {
2316 			u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2317 			u1_tmp &= ~(BIT(1));
2318 			rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2319 
2320 			u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2321 			u1_tmp &= ~(BIT(1));
2322 			rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2323 		}
2324 	}
2325 }
2326 
2327 void rtl92ce_suspend(struct ieee80211_hw *hw)
2328 {
2329 }
2330 
2331 void rtl92ce_resume(struct ieee80211_hw *hw)
2332 {
2333 }
2334