1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../regd.h" 30 #include "../cam.h" 31 #include "../ps.h" 32 #include "../pci.h" 33 #include "reg.h" 34 #include "def.h" 35 #include "phy.h" 36 #include "../rtl8192c/dm_common.h" 37 #include "../rtl8192c/fw_common.h" 38 #include "../rtl8192c/phy_common.h" 39 #include "dm.h" 40 #include "led.h" 41 #include "hw.h" 42 43 #define LLT_CONFIG 5 44 45 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 46 u8 set_bits, u8 clear_bits) 47 { 48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 49 struct rtl_priv *rtlpriv = rtl_priv(hw); 50 51 rtlpci->reg_bcn_ctrl_val |= set_bits; 52 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 53 54 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 55 } 56 57 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw) 58 { 59 struct rtl_priv *rtlpriv = rtl_priv(hw); 60 u8 tmp1byte; 61 62 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 63 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 64 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 65 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 66 tmp1byte &= ~(BIT(0)); 67 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 68 } 69 70 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw) 71 { 72 struct rtl_priv *rtlpriv = rtl_priv(hw); 73 u8 tmp1byte; 74 75 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 76 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 77 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 78 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 79 tmp1byte |= BIT(0); 80 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 81 } 82 83 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw) 84 { 85 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1)); 86 } 87 88 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw) 89 { 90 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0); 91 } 92 93 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 94 { 95 struct rtl_priv *rtlpriv = rtl_priv(hw); 96 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 97 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 98 99 switch (variable) { 100 case HW_VAR_RCR: 101 *((u32 *) (val)) = rtlpci->receive_config; 102 break; 103 case HW_VAR_RF_STATE: 104 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 105 break; 106 case HW_VAR_FWLPS_RF_ON:{ 107 enum rf_pwrstate rfState; 108 u32 val_rcr; 109 110 rtlpriv->cfg->ops->get_hw_reg(hw, 111 HW_VAR_RF_STATE, 112 (u8 *) (&rfState)); 113 if (rfState == ERFOFF) { 114 *((bool *) (val)) = true; 115 } else { 116 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 117 val_rcr &= 0x00070000; 118 if (val_rcr) 119 *((bool *) (val)) = false; 120 else 121 *((bool *) (val)) = true; 122 } 123 break; 124 } 125 case HW_VAR_FW_PSMODE_STATUS: 126 *((bool *) (val)) = ppsc->fw_current_inpsmode; 127 break; 128 case HW_VAR_CORRECT_TSF:{ 129 u64 tsf; 130 u32 *ptsf_low = (u32 *)&tsf; 131 u32 *ptsf_high = ((u32 *)&tsf) + 1; 132 133 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 134 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 135 136 *((u64 *) (val)) = tsf; 137 138 break; 139 } 140 case HAL_DEF_WOWLAN: 141 break; 142 default: 143 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 144 "switch case %#x not processed\n", variable); 145 break; 146 } 147 } 148 149 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 150 { 151 struct rtl_priv *rtlpriv = rtl_priv(hw); 152 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 153 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 154 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 155 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 156 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 157 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 158 u8 idx; 159 160 switch (variable) { 161 case HW_VAR_ETHER_ADDR:{ 162 for (idx = 0; idx < ETH_ALEN; idx++) { 163 rtl_write_byte(rtlpriv, (REG_MACID + idx), 164 val[idx]); 165 } 166 break; 167 } 168 case HW_VAR_BASIC_RATE:{ 169 u16 rate_cfg = ((u16 *) val)[0]; 170 u8 rate_index = 0; 171 rate_cfg &= 0x15f; 172 rate_cfg |= 0x01; 173 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); 174 rtl_write_byte(rtlpriv, REG_RRSR + 1, 175 (rate_cfg >> 8) & 0xff); 176 while (rate_cfg > 0x1) { 177 rate_cfg = (rate_cfg >> 1); 178 rate_index++; 179 } 180 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 181 rate_index); 182 break; 183 } 184 case HW_VAR_BSSID:{ 185 for (idx = 0; idx < ETH_ALEN; idx++) { 186 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 187 val[idx]); 188 } 189 break; 190 } 191 case HW_VAR_SIFS:{ 192 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 193 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); 194 195 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 196 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 197 198 if (!mac->ht_enable) 199 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 200 0x0e0e); 201 else 202 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 203 *((u16 *) val)); 204 break; 205 } 206 case HW_VAR_SLOT_TIME:{ 207 u8 e_aci; 208 209 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 210 "HW_VAR_SLOT_TIME %x\n", val[0]); 211 212 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 213 214 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 215 rtlpriv->cfg->ops->set_hw_reg(hw, 216 HW_VAR_AC_PARAM, 217 &e_aci); 218 } 219 break; 220 } 221 case HW_VAR_ACK_PREAMBLE:{ 222 u8 reg_tmp; 223 u8 short_preamble = (bool)*val; 224 reg_tmp = (mac->cur_40_prime_sc) << 5; 225 if (short_preamble) 226 reg_tmp |= 0x80; 227 228 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 229 break; 230 } 231 case HW_VAR_AMPDU_MIN_SPACE:{ 232 u8 min_spacing_to_set; 233 u8 sec_min_space; 234 235 min_spacing_to_set = *val; 236 if (min_spacing_to_set <= 7) { 237 sec_min_space = 0; 238 239 if (min_spacing_to_set < sec_min_space) 240 min_spacing_to_set = sec_min_space; 241 242 mac->min_space_cfg = ((mac->min_space_cfg & 243 0xf8) | 244 min_spacing_to_set); 245 246 *val = min_spacing_to_set; 247 248 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 249 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 250 mac->min_space_cfg); 251 252 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 253 mac->min_space_cfg); 254 } 255 break; 256 } 257 case HW_VAR_SHORTGI_DENSITY:{ 258 u8 density_to_set; 259 260 density_to_set = *val; 261 mac->min_space_cfg |= (density_to_set << 3); 262 263 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 264 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 265 mac->min_space_cfg); 266 267 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 268 mac->min_space_cfg); 269 270 break; 271 } 272 case HW_VAR_AMPDU_FACTOR:{ 273 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; 274 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97}; 275 276 u8 factor_toset; 277 u8 *p_regtoset = NULL; 278 u8 index = 0; 279 280 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 281 (rtlpcipriv->bt_coexist.bt_coexist_type == 282 BT_CSR_BC4)) 283 p_regtoset = regtoset_bt; 284 else 285 p_regtoset = regtoset_normal; 286 287 factor_toset = *(val); 288 if (factor_toset <= 3) { 289 factor_toset = (1 << (factor_toset + 2)); 290 if (factor_toset > 0xf) 291 factor_toset = 0xf; 292 293 for (index = 0; index < 4; index++) { 294 if ((p_regtoset[index] & 0xf0) > 295 (factor_toset << 4)) 296 p_regtoset[index] = 297 (p_regtoset[index] & 0x0f) | 298 (factor_toset << 4); 299 300 if ((p_regtoset[index] & 0x0f) > 301 factor_toset) 302 p_regtoset[index] = 303 (p_regtoset[index] & 0xf0) | 304 (factor_toset); 305 306 rtl_write_byte(rtlpriv, 307 (REG_AGGLEN_LMT + index), 308 p_regtoset[index]); 309 310 } 311 312 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 313 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 314 factor_toset); 315 } 316 break; 317 } 318 case HW_VAR_AC_PARAM:{ 319 u8 e_aci = *(val); 320 rtl92c_dm_init_edca_turbo(hw); 321 322 if (rtlpci->acm_method != EACMWAY2_SW) 323 rtlpriv->cfg->ops->set_hw_reg(hw, 324 HW_VAR_ACM_CTRL, 325 (&e_aci)); 326 break; 327 } 328 case HW_VAR_ACM_CTRL:{ 329 u8 e_aci = *(val); 330 union aci_aifsn *p_aci_aifsn = 331 (union aci_aifsn *)(&(mac->ac[0].aifs)); 332 u8 acm = p_aci_aifsn->f.acm; 333 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 334 335 acm_ctrl = 336 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 337 338 if (acm) { 339 switch (e_aci) { 340 case AC0_BE: 341 acm_ctrl |= AcmHw_BeqEn; 342 break; 343 case AC2_VI: 344 acm_ctrl |= AcmHw_ViqEn; 345 break; 346 case AC3_VO: 347 acm_ctrl |= AcmHw_VoqEn; 348 break; 349 default: 350 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 351 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 352 acm); 353 break; 354 } 355 } else { 356 switch (e_aci) { 357 case AC0_BE: 358 acm_ctrl &= (~AcmHw_BeqEn); 359 break; 360 case AC2_VI: 361 acm_ctrl &= (~AcmHw_ViqEn); 362 break; 363 case AC3_VO: 364 acm_ctrl &= (~AcmHw_VoqEn); 365 break; 366 default: 367 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 368 "switch case %#x not processed\n", 369 e_aci); 370 break; 371 } 372 } 373 374 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 375 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 376 acm_ctrl); 377 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 378 break; 379 } 380 case HW_VAR_RCR:{ 381 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); 382 rtlpci->receive_config = ((u32 *) (val))[0]; 383 break; 384 } 385 case HW_VAR_RETRY_LIMIT:{ 386 u8 retry_limit = val[0]; 387 388 rtl_write_word(rtlpriv, REG_RL, 389 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 390 retry_limit << RETRY_LIMIT_LONG_SHIFT); 391 break; 392 } 393 case HW_VAR_DUAL_TSF_RST: 394 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 395 break; 396 case HW_VAR_EFUSE_BYTES: 397 rtlefuse->efuse_usedbytes = *((u16 *) val); 398 break; 399 case HW_VAR_EFUSE_USAGE: 400 rtlefuse->efuse_usedpercentage = *val; 401 break; 402 case HW_VAR_IO_CMD: 403 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val)); 404 break; 405 case HW_VAR_WPA_CONFIG: 406 rtl_write_byte(rtlpriv, REG_SECCFG, *val); 407 break; 408 case HW_VAR_SET_RPWM:{ 409 u8 rpwm_val; 410 411 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 412 udelay(1); 413 414 if (rpwm_val & BIT(7)) { 415 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val); 416 } else { 417 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 418 *val | BIT(7)); 419 } 420 421 break; 422 } 423 case HW_VAR_H2C_FW_PWRMODE:{ 424 u8 psmode = *val; 425 426 if ((psmode != FW_PS_ACTIVE_MODE) && 427 (!IS_92C_SERIAL(rtlhal->version))) { 428 rtl92c_dm_rf_saving(hw, true); 429 } 430 431 rtl92c_set_fw_pwrmode_cmd(hw, *val); 432 break; 433 } 434 case HW_VAR_FW_PSMODE_STATUS: 435 ppsc->fw_current_inpsmode = *((bool *) val); 436 break; 437 case HW_VAR_H2C_FW_JOINBSSRPT:{ 438 u8 mstatus = *val; 439 u8 tmp_regcr, tmp_reg422; 440 bool recover = false; 441 442 if (mstatus == RT_MEDIA_CONNECT) { 443 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, 444 NULL); 445 446 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 447 rtl_write_byte(rtlpriv, REG_CR + 1, 448 (tmp_regcr | BIT(0))); 449 450 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); 451 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0); 452 453 tmp_reg422 = 454 rtl_read_byte(rtlpriv, 455 REG_FWHW_TXQ_CTRL + 2); 456 if (tmp_reg422 & BIT(6)) 457 recover = true; 458 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 459 tmp_reg422 & (~BIT(6))); 460 461 rtl92c_set_fw_rsvdpagepkt(hw, NULL); 462 463 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); 464 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); 465 466 if (recover) { 467 rtl_write_byte(rtlpriv, 468 REG_FWHW_TXQ_CTRL + 2, 469 tmp_reg422); 470 } 471 472 rtl_write_byte(rtlpriv, REG_CR + 1, 473 (tmp_regcr & ~(BIT(0)))); 474 } 475 rtl92c_set_fw_joinbss_report_cmd(hw, *val); 476 477 break; 478 } 479 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: 480 rtl92c_set_p2p_ps_offload_cmd(hw, *val); 481 break; 482 case HW_VAR_AID:{ 483 u16 u2btmp; 484 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 485 u2btmp &= 0xC000; 486 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | 487 mac->assoc_id)); 488 489 break; 490 } 491 case HW_VAR_CORRECT_TSF:{ 492 u8 btype_ibss = val[0]; 493 494 if (btype_ibss) 495 _rtl92ce_stop_tx_beacon(hw); 496 497 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); 498 499 rtl_write_dword(rtlpriv, REG_TSFTR, 500 (u32) (mac->tsf & 0xffffffff)); 501 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 502 (u32) ((mac->tsf >> 32) & 0xffffffff)); 503 504 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); 505 506 if (btype_ibss) 507 _rtl92ce_resume_tx_beacon(hw); 508 509 break; 510 511 } 512 case HW_VAR_FW_LPS_ACTION: { 513 bool enter_fwlps = *((bool *)val); 514 u8 rpwm_val, fw_pwrmode; 515 bool fw_current_inps; 516 517 if (enter_fwlps) { 518 rpwm_val = 0x02; /* RF off */ 519 fw_current_inps = true; 520 rtlpriv->cfg->ops->set_hw_reg(hw, 521 HW_VAR_FW_PSMODE_STATUS, 522 (u8 *)(&fw_current_inps)); 523 rtlpriv->cfg->ops->set_hw_reg(hw, 524 HW_VAR_H2C_FW_PWRMODE, 525 &ppsc->fwctrl_psmode); 526 527 rtlpriv->cfg->ops->set_hw_reg(hw, 528 HW_VAR_SET_RPWM, 529 &rpwm_val); 530 } else { 531 rpwm_val = 0x0C; /* RF on */ 532 fw_pwrmode = FW_PS_ACTIVE_MODE; 533 fw_current_inps = false; 534 rtlpriv->cfg->ops->set_hw_reg(hw, 535 HW_VAR_SET_RPWM, 536 &rpwm_val); 537 rtlpriv->cfg->ops->set_hw_reg(hw, 538 HW_VAR_H2C_FW_PWRMODE, 539 &fw_pwrmode); 540 541 rtlpriv->cfg->ops->set_hw_reg(hw, 542 HW_VAR_FW_PSMODE_STATUS, 543 (u8 *)(&fw_current_inps)); 544 } 545 break; } 546 case HW_VAR_KEEP_ALIVE: { 547 u8 array[2]; 548 549 array[0] = 0xff; 550 array[1] = *((u8 *)val); 551 rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2, array); 552 break; } 553 default: 554 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 555 "switch case %d not processed\n", variable); 556 break; 557 } 558 } 559 560 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 561 { 562 struct rtl_priv *rtlpriv = rtl_priv(hw); 563 bool status = true; 564 long count = 0; 565 u32 value = _LLT_INIT_ADDR(address) | 566 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); 567 568 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 569 570 do { 571 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 572 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 573 break; 574 575 if (count > POLLING_LLT_THRESHOLD) { 576 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 577 "Failed to polling write LLT done at address %d!\n", 578 address); 579 status = false; 580 break; 581 } 582 } while (++count); 583 584 return status; 585 } 586 587 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw) 588 { 589 struct rtl_priv *rtlpriv = rtl_priv(hw); 590 unsigned short i; 591 u8 txpktbuf_bndy; 592 u8 maxPage; 593 bool status; 594 595 #if LLT_CONFIG == 1 596 maxPage = 255; 597 txpktbuf_bndy = 252; 598 #elif LLT_CONFIG == 2 599 maxPage = 127; 600 txpktbuf_bndy = 124; 601 #elif LLT_CONFIG == 3 602 maxPage = 255; 603 txpktbuf_bndy = 174; 604 #elif LLT_CONFIG == 4 605 maxPage = 255; 606 txpktbuf_bndy = 246; 607 #elif LLT_CONFIG == 5 608 maxPage = 255; 609 txpktbuf_bndy = 246; 610 #endif 611 612 #if LLT_CONFIG == 1 613 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c); 614 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c); 615 #elif LLT_CONFIG == 2 616 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010); 617 #elif LLT_CONFIG == 3 618 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484); 619 #elif LLT_CONFIG == 4 620 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c); 621 #elif LLT_CONFIG == 5 622 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000); 623 624 rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29); 625 #endif 626 627 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy)); 628 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 629 630 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 631 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 632 633 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); 634 rtl_write_byte(rtlpriv, REG_PBP, 0x11); 635 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 636 637 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 638 status = _rtl92ce_llt_write(hw, i, i + 1); 639 if (true != status) 640 return status; 641 } 642 643 status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 644 if (true != status) 645 return status; 646 647 for (i = txpktbuf_bndy; i < maxPage; i++) { 648 status = _rtl92ce_llt_write(hw, i, (i + 1)); 649 if (true != status) 650 return status; 651 } 652 653 status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy); 654 if (true != status) 655 return status; 656 657 return true; 658 } 659 660 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw) 661 { 662 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 663 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 664 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 665 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0); 666 667 if (rtlpci->up_first_time) 668 return; 669 670 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 671 rtl92ce_sw_led_on(hw, pLed0); 672 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 673 rtl92ce_sw_led_on(hw, pLed0); 674 else 675 rtl92ce_sw_led_off(hw, pLed0); 676 } 677 678 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw) 679 { 680 struct rtl_priv *rtlpriv = rtl_priv(hw); 681 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 682 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 683 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 684 685 unsigned char bytetmp; 686 unsigned short wordtmp; 687 u16 retry; 688 689 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 690 if (rtlpcipriv->bt_coexist.bt_coexistence) { 691 u32 value32; 692 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO); 693 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK); 694 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32); 695 } 696 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 697 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F); 698 699 if (rtlpcipriv->bt_coexist.bt_coexistence) { 700 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL); 701 702 u4b_tmp &= (~0x00024800); 703 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp); 704 } 705 706 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0); 707 udelay(2); 708 709 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); 710 udelay(2); 711 712 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); 713 udelay(2); 714 715 retry = 0; 716 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n", 717 rtl_read_dword(rtlpriv, 0xEC), bytetmp); 718 719 while ((bytetmp & BIT(0)) && retry < 1000) { 720 retry++; 721 udelay(50); 722 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); 723 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n", 724 rtl_read_dword(rtlpriv, 0xEC), bytetmp); 725 udelay(50); 726 } 727 728 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012); 729 730 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82); 731 udelay(2); 732 733 if (rtlpcipriv->bt_coexist.bt_coexistence) { 734 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd; 735 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp); 736 } 737 738 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 739 740 if (!_rtl92ce_llt_table_init(hw)) 741 return false; 742 743 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 744 rtl_write_byte(rtlpriv, REG_HISRE, 0xff); 745 746 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff); 747 748 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 749 wordtmp &= 0xf; 750 wordtmp |= 0xF771; 751 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 752 753 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 754 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 755 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); 756 757 rtl_write_byte(rtlpriv, 0x4d0, 0x0); 758 759 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 760 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) & 761 DMA_BIT_MASK(32)); 762 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 763 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma & 764 DMA_BIT_MASK(32)); 765 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 766 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 767 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 768 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 769 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 770 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 771 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 772 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 773 rtl_write_dword(rtlpriv, REG_HQ_DESA, 774 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma & 775 DMA_BIT_MASK(32)); 776 rtl_write_dword(rtlpriv, REG_RX_DESA, 777 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma & 778 DMA_BIT_MASK(32)); 779 780 if (IS_92C_SERIAL(rtlhal->version)) 781 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77); 782 else 783 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22); 784 785 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 786 787 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 788 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); 789 do { 790 retry++; 791 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 792 } while ((retry < 200) && (bytetmp & BIT(7))); 793 794 _rtl92ce_gen_refresh_led_state(hw); 795 796 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); 797 798 return true; 799 } 800 801 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw) 802 { 803 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 804 struct rtl_priv *rtlpriv = rtl_priv(hw); 805 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 806 u8 reg_bw_opmode; 807 u32 reg_prsr; 808 809 reg_bw_opmode = BW_OPMODE_20MHZ; 810 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 811 812 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); 813 814 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 815 816 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr); 817 818 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 819 820 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); 821 822 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); 823 824 rtl_write_word(rtlpriv, REG_RL, 0x0707); 825 826 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); 827 828 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 829 830 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 831 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 832 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 833 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 834 835 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 836 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) 837 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431); 838 else 839 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); 840 841 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); 842 843 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); 844 845 rtlpci->reg_bcn_ctrl_val = 0x1f; 846 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 847 848 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 849 850 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 851 852 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); 853 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 854 855 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 856 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) { 857 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 858 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402); 859 } else { 860 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 861 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 862 } 863 864 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 865 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) 866 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); 867 else 868 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666); 869 870 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); 871 872 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); 873 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); 874 875 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); 876 877 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); 878 879 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); 880 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); 881 882 } 883 884 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw) 885 { 886 struct rtl_priv *rtlpriv = rtl_priv(hw); 887 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 888 889 rtl_write_byte(rtlpriv, 0x34b, 0x93); 890 rtl_write_word(rtlpriv, 0x350, 0x870c); 891 rtl_write_byte(rtlpriv, 0x352, 0x1); 892 893 if (ppsc->support_backdoor) 894 rtl_write_byte(rtlpriv, 0x349, 0x1b); 895 else 896 rtl_write_byte(rtlpriv, 0x349, 0x03); 897 898 rtl_write_word(rtlpriv, 0x350, 0x2718); 899 rtl_write_byte(rtlpriv, 0x352, 0x1); 900 } 901 902 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw) 903 { 904 struct rtl_priv *rtlpriv = rtl_priv(hw); 905 u8 sec_reg_value; 906 907 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 908 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 909 rtlpriv->sec.pairwise_enc_algorithm, 910 rtlpriv->sec.group_enc_algorithm); 911 912 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 913 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 914 "not open hw encryption\n"); 915 return; 916 } 917 918 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable; 919 920 if (rtlpriv->sec.use_defaultkey) { 921 sec_reg_value |= SCR_TxUseDK; 922 sec_reg_value |= SCR_RxUseDK; 923 } 924 925 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 926 927 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 928 929 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 930 "The SECR-value %x\n", sec_reg_value); 931 932 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 933 934 } 935 936 int rtl92ce_hw_init(struct ieee80211_hw *hw) 937 { 938 struct rtl_priv *rtlpriv = rtl_priv(hw); 939 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 940 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 941 struct rtl_phy *rtlphy = &(rtlpriv->phy); 942 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 943 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 944 bool rtstatus = true; 945 bool is92c; 946 int err; 947 u8 tmp_u1b; 948 unsigned long flags; 949 950 rtlpci->being_init_adapter = true; 951 952 /* Since this function can take a very long time (up to 350 ms) 953 * and can be called with irqs disabled, reenable the irqs 954 * to let the other devices continue being serviced. 955 * 956 * It is safe doing so since our own interrupts will only be enabled 957 * in a subsequent step. 958 */ 959 local_save_flags(flags); 960 local_irq_enable(); 961 962 rtlhal->fw_ready = false; 963 rtlpriv->intf_ops->disable_aspm(hw); 964 rtstatus = _rtl92ce_init_mac(hw); 965 if (!rtstatus) { 966 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n"); 967 err = 1; 968 goto exit; 969 } 970 971 err = rtl92c_download_fw(hw); 972 if (err) { 973 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 974 "Failed to download FW. Init HW without FW now..\n"); 975 err = 1; 976 goto exit; 977 } 978 979 rtlhal->fw_ready = true; 980 rtlhal->last_hmeboxnum = 0; 981 rtl92c_phy_mac_config(hw); 982 /* because last function modify RCR, so we update 983 * rcr var here, or TP will unstable for receive_config 984 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 985 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/ 986 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); 987 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 988 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 989 rtl92c_phy_bb_config(hw); 990 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 991 rtl92c_phy_rf_config(hw); 992 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) && 993 !IS_92C_SERIAL(rtlhal->version)) { 994 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); 995 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); 996 } else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) { 997 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE); 998 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31); 999 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425); 1000 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200); 1001 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053); 1002 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201); 1003 } 1004 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 1005 RF_CHNLBW, RFREG_OFFSET_MASK); 1006 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 1007 RF_CHNLBW, RFREG_OFFSET_MASK); 1008 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1009 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1010 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); 1011 _rtl92ce_hw_configure(hw); 1012 rtl_cam_reset_all_entry(hw); 1013 rtl92ce_enable_hw_security_config(hw); 1014 1015 ppsc->rfpwr_state = ERFON; 1016 1017 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1018 _rtl92ce_enable_aspm_back_door(hw); 1019 rtlpriv->intf_ops->enable_aspm(hw); 1020 1021 rtl8192ce_bt_hw_init(hw); 1022 1023 if (ppsc->rfpwr_state == ERFON) { 1024 rtl92c_phy_set_rfpath_switch(hw, 1); 1025 if (rtlphy->iqk_initialized) { 1026 rtl92c_phy_iq_calibrate(hw, true); 1027 } else { 1028 rtl92c_phy_iq_calibrate(hw, false); 1029 rtlphy->iqk_initialized = true; 1030 } 1031 1032 rtl92c_dm_check_txpower_tracking(hw); 1033 rtl92c_phy_lc_calibrate(hw); 1034 } 1035 1036 is92c = IS_92C_SERIAL(rtlhal->version); 1037 tmp_u1b = efuse_read_1byte(hw, 0x1FA); 1038 if (!(tmp_u1b & BIT(0))) { 1039 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); 1040 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n"); 1041 } 1042 1043 if (!(tmp_u1b & BIT(1)) && is92c) { 1044 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05); 1045 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n"); 1046 } 1047 1048 if (!(tmp_u1b & BIT(4))) { 1049 tmp_u1b = rtl_read_byte(rtlpriv, 0x16); 1050 tmp_u1b &= 0x0F; 1051 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80); 1052 udelay(10); 1053 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90); 1054 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n"); 1055 } 1056 rtl92c_dm_init(hw); 1057 exit: 1058 local_irq_restore(flags); 1059 rtlpci->being_init_adapter = false; 1060 return err; 1061 } 1062 1063 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw) 1064 { 1065 struct rtl_priv *rtlpriv = rtl_priv(hw); 1066 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1067 enum version_8192c version = VERSION_UNKNOWN; 1068 u32 value32; 1069 const char *versionid; 1070 1071 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 1072 if (value32 & TRP_VAUX_EN) { 1073 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C : 1074 VERSION_A_CHIP_88C; 1075 } else { 1076 version = (enum version_8192c) (CHIP_VER_B | 1077 ((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) | 1078 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); 1079 if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 & 1080 CHIP_VER_RTL_MASK)) { 1081 version = (enum version_8192c)(version | 1082 ((((value32 & CHIP_VER_RTL_MASK) == BIT(12)) 1083 ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) | 1084 CHIP_VENDOR_UMC)); 1085 } 1086 if (IS_92C_SERIAL(version)) { 1087 value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM); 1088 version = (enum version_8192c)(version | 1089 ((CHIP_BONDING_IDENTIFIER(value32) 1090 == CHIP_BONDING_92C_1T2R) ? 1091 RF_TYPE_1T2R : 0)); 1092 } 1093 } 1094 1095 switch (version) { 1096 case VERSION_B_CHIP_92C: 1097 versionid = "B_CHIP_92C"; 1098 break; 1099 case VERSION_B_CHIP_88C: 1100 versionid = "B_CHIP_88C"; 1101 break; 1102 case VERSION_A_CHIP_92C: 1103 versionid = "A_CHIP_92C"; 1104 break; 1105 case VERSION_A_CHIP_88C: 1106 versionid = "A_CHIP_88C"; 1107 break; 1108 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT: 1109 versionid = "A_CUT_92C_1T2R"; 1110 break; 1111 case VERSION_NORMAL_UMC_CHIP_92C_A_CUT: 1112 versionid = "A_CUT_92C"; 1113 break; 1114 case VERSION_NORMAL_UMC_CHIP_88C_A_CUT: 1115 versionid = "A_CUT_88C"; 1116 break; 1117 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT: 1118 versionid = "B_CUT_92C_1T2R"; 1119 break; 1120 case VERSION_NORMAL_UMC_CHIP_92C_B_CUT: 1121 versionid = "B_CUT_92C"; 1122 break; 1123 case VERSION_NORMAL_UMC_CHIP_88C_B_CUT: 1124 versionid = "B_CUT_88C"; 1125 break; 1126 default: 1127 versionid = "Unknown. Bug?"; 1128 break; 1129 } 1130 1131 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, 1132 "Chip Version ID: %s\n", versionid); 1133 1134 switch (version & 0x3) { 1135 case CHIP_88C: 1136 rtlphy->rf_type = RF_1T1R; 1137 break; 1138 case CHIP_92C: 1139 rtlphy->rf_type = RF_2T2R; 1140 break; 1141 case CHIP_92C_1T2R: 1142 rtlphy->rf_type = RF_1T2R; 1143 break; 1144 default: 1145 rtlphy->rf_type = RF_1T1R; 1146 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1147 "ERROR RF_Type is set!!\n"); 1148 break; 1149 } 1150 1151 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n", 1152 rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R"); 1153 1154 return version; 1155 } 1156 1157 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw, 1158 enum nl80211_iftype type) 1159 { 1160 struct rtl_priv *rtlpriv = rtl_priv(hw); 1161 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1162 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1163 u8 mode = MSR_NOLINK; 1164 1165 bt_msr &= 0xfc; 1166 1167 switch (type) { 1168 case NL80211_IFTYPE_UNSPECIFIED: 1169 mode = MSR_NOLINK; 1170 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1171 "Set Network type to NO LINK!\n"); 1172 break; 1173 case NL80211_IFTYPE_ADHOC: 1174 mode = MSR_ADHOC; 1175 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1176 "Set Network type to Ad Hoc!\n"); 1177 break; 1178 case NL80211_IFTYPE_STATION: 1179 mode = MSR_INFRA; 1180 ledaction = LED_CTL_LINK; 1181 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1182 "Set Network type to STA!\n"); 1183 break; 1184 case NL80211_IFTYPE_AP: 1185 mode = MSR_AP; 1186 ledaction = LED_CTL_LINK; 1187 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1188 "Set Network type to AP!\n"); 1189 break; 1190 case NL80211_IFTYPE_MESH_POINT: 1191 mode = MSR_ADHOC; 1192 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1193 "Set Network type to Mesh Point!\n"); 1194 break; 1195 default: 1196 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1197 "Network type %d not supported!\n", type); 1198 return 1; 1199 1200 } 1201 1202 /* MSR_INFRA == Link in infrastructure network; 1203 * MSR_ADHOC == Link in ad hoc network; 1204 * Therefore, check link state is necessary. 1205 * 1206 * MSR_AP == AP mode; link state does not matter here. 1207 */ 1208 if (mode != MSR_AP && 1209 rtlpriv->mac80211.link_state < MAC80211_LINKED) { 1210 mode = MSR_NOLINK; 1211 ledaction = LED_CTL_NO_LINK; 1212 } 1213 if (mode == MSR_NOLINK || mode == MSR_INFRA) { 1214 _rtl92ce_stop_tx_beacon(hw); 1215 _rtl92ce_enable_bcn_sub_func(hw); 1216 } else if (mode == MSR_ADHOC || mode == MSR_AP) { 1217 _rtl92ce_resume_tx_beacon(hw); 1218 _rtl92ce_disable_bcn_sub_func(hw); 1219 } else { 1220 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1221 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 1222 mode); 1223 } 1224 rtl_write_byte(rtlpriv, MSR, bt_msr | mode); 1225 1226 rtlpriv->cfg->ops->led_control(hw, ledaction); 1227 if (mode == MSR_AP) 1228 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1229 else 1230 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1231 return 0; 1232 } 1233 1234 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1235 { 1236 struct rtl_priv *rtlpriv = rtl_priv(hw); 1237 u32 reg_rcr; 1238 1239 if (rtlpriv->psc.rfpwr_state != ERFON) 1240 return; 1241 1242 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1243 1244 if (check_bssid) { 1245 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1246 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1247 (u8 *) (®_rcr)); 1248 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1249 } else if (!check_bssid) { 1250 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1251 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0); 1252 rtlpriv->cfg->ops->set_hw_reg(hw, 1253 HW_VAR_RCR, (u8 *) (®_rcr)); 1254 } 1255 1256 } 1257 1258 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1259 { 1260 struct rtl_priv *rtlpriv = rtl_priv(hw); 1261 1262 if (_rtl92ce_set_media_status(hw, type)) 1263 return -EOPNOTSUPP; 1264 1265 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1266 if (type != NL80211_IFTYPE_AP && 1267 type != NL80211_IFTYPE_MESH_POINT) 1268 rtl92ce_set_check_bssid(hw, true); 1269 } else { 1270 rtl92ce_set_check_bssid(hw, false); 1271 } 1272 1273 return 0; 1274 } 1275 1276 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ 1277 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci) 1278 { 1279 struct rtl_priv *rtlpriv = rtl_priv(hw); 1280 rtl92c_dm_init_edca_turbo(hw); 1281 switch (aci) { 1282 case AC1_BK: 1283 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 1284 break; 1285 case AC0_BE: 1286 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */ 1287 break; 1288 case AC2_VI: 1289 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 1290 break; 1291 case AC3_VO: 1292 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 1293 break; 1294 default: 1295 RT_ASSERT(false, "invalid aci: %d !\n", aci); 1296 break; 1297 } 1298 } 1299 1300 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw) 1301 { 1302 struct rtl_priv *rtlpriv = rtl_priv(hw); 1303 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1304 1305 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); 1306 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); 1307 rtlpci->irq_enabled = true; 1308 } 1309 1310 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw) 1311 { 1312 struct rtl_priv *rtlpriv = rtl_priv(hw); 1313 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1314 1315 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); 1316 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); 1317 rtlpci->irq_enabled = false; 1318 } 1319 1320 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw) 1321 { 1322 struct rtl_priv *rtlpriv = rtl_priv(hw); 1323 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1324 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1325 u8 u1b_tmp; 1326 u32 u4b_tmp; 1327 1328 rtlpriv->intf_ops->enable_aspm(hw); 1329 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1330 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 1331 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); 1332 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 1333 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 1334 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0); 1335 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) 1336 rtl92c_firmware_selfreset(hw); 1337 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51); 1338 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1339 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000); 1340 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL); 1341 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 1342 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) || 1343 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) { 1344 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 | 1345 (u1b_tmp << 8)); 1346 } else { 1347 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 | 1348 (u1b_tmp << 8)); 1349 } 1350 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790); 1351 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); 1352 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); 1353 if (!IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) 1354 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); 1355 if (rtlpcipriv->bt_coexist.bt_coexistence) { 1356 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL); 1357 u4b_tmp |= 0x03824800; 1358 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp); 1359 } else { 1360 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e); 1361 } 1362 1363 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); 1364 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10); 1365 } 1366 1367 void rtl92ce_card_disable(struct ieee80211_hw *hw) 1368 { 1369 struct rtl_priv *rtlpriv = rtl_priv(hw); 1370 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1371 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1372 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1373 enum nl80211_iftype opmode; 1374 1375 mac->link_state = MAC80211_NOLINK; 1376 opmode = NL80211_IFTYPE_UNSPECIFIED; 1377 _rtl92ce_set_media_status(hw, opmode); 1378 if (rtlpci->driver_is_goingto_unload || 1379 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1380 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1381 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1382 _rtl92ce_poweroff_adapter(hw); 1383 1384 /* after power off we should do iqk again */ 1385 rtlpriv->phy.iqk_initialized = false; 1386 } 1387 1388 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw, 1389 u32 *p_inta, u32 *p_intb) 1390 { 1391 struct rtl_priv *rtlpriv = rtl_priv(hw); 1392 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1393 1394 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 1395 rtl_write_dword(rtlpriv, ISR, *p_inta); 1396 1397 /* 1398 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; 1399 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb); 1400 */ 1401 } 1402 1403 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw) 1404 { 1405 1406 struct rtl_priv *rtlpriv = rtl_priv(hw); 1407 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1408 u16 bcn_interval, atim_window; 1409 1410 bcn_interval = mac->beacon_interval; 1411 atim_window = 2; /*FIX MERGE */ 1412 rtl92ce_disable_interrupt(hw); 1413 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1414 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1415 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 1416 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 1417 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 1418 rtl_write_byte(rtlpriv, 0x606, 0x30); 1419 rtl92ce_enable_interrupt(hw); 1420 } 1421 1422 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw) 1423 { 1424 struct rtl_priv *rtlpriv = rtl_priv(hw); 1425 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1426 u16 bcn_interval = mac->beacon_interval; 1427 1428 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, 1429 "beacon_interval:%d\n", bcn_interval); 1430 rtl92ce_disable_interrupt(hw); 1431 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1432 rtl92ce_enable_interrupt(hw); 1433 } 1434 1435 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw, 1436 u32 add_msr, u32 rm_msr) 1437 { 1438 struct rtl_priv *rtlpriv = rtl_priv(hw); 1439 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1440 1441 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n", 1442 add_msr, rm_msr); 1443 1444 if (add_msr) 1445 rtlpci->irq_mask[0] |= add_msr; 1446 if (rm_msr) 1447 rtlpci->irq_mask[0] &= (~rm_msr); 1448 rtl92ce_disable_interrupt(hw); 1449 rtl92ce_enable_interrupt(hw); 1450 } 1451 1452 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 1453 bool autoload_fail, 1454 u8 *hwinfo) 1455 { 1456 struct rtl_priv *rtlpriv = rtl_priv(hw); 1457 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1458 u8 rf_path, index, tempval; 1459 u16 i; 1460 1461 for (rf_path = 0; rf_path < 2; rf_path++) { 1462 for (i = 0; i < 3; i++) { 1463 if (!autoload_fail) { 1464 rtlefuse-> 1465 eeprom_chnlarea_txpwr_cck[rf_path][i] = 1466 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; 1467 rtlefuse-> 1468 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1469 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + 1470 i]; 1471 } else { 1472 rtlefuse-> 1473 eeprom_chnlarea_txpwr_cck[rf_path][i] = 1474 EEPROM_DEFAULT_TXPOWERLEVEL; 1475 rtlefuse-> 1476 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1477 EEPROM_DEFAULT_TXPOWERLEVEL; 1478 } 1479 } 1480 } 1481 1482 for (i = 0; i < 3; i++) { 1483 if (!autoload_fail) 1484 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i]; 1485 else 1486 tempval = EEPROM_DEFAULT_HT40_2SDIFF; 1487 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] = 1488 (tempval & 0xf); 1489 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] = 1490 ((tempval & 0xf0) >> 4); 1491 } 1492 1493 for (rf_path = 0; rf_path < 2; rf_path++) 1494 for (i = 0; i < 3; i++) 1495 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1496 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", 1497 rf_path, i, 1498 rtlefuse-> 1499 eeprom_chnlarea_txpwr_cck[rf_path][i]); 1500 for (rf_path = 0; rf_path < 2; rf_path++) 1501 for (i = 0; i < 3; i++) 1502 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1503 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 1504 rf_path, i, 1505 rtlefuse-> 1506 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]); 1507 for (rf_path = 0; rf_path < 2; rf_path++) 1508 for (i = 0; i < 3; i++) 1509 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1510 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 1511 rf_path, i, 1512 rtlefuse-> 1513 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]); 1514 1515 for (rf_path = 0; rf_path < 2; rf_path++) { 1516 for (i = 0; i < 14; i++) { 1517 index = rtl92c_get_chnl_group((u8)i); 1518 1519 rtlefuse->txpwrlevel_cck[rf_path][i] = 1520 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index]; 1521 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 1522 rtlefuse-> 1523 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index]; 1524 1525 if ((rtlefuse-> 1526 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] - 1527 rtlefuse-> 1528 eprom_chnl_txpwr_ht40_2sdf[rf_path][index]) 1529 > 0) { 1530 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 1531 rtlefuse-> 1532 eeprom_chnlarea_txpwr_ht40_1s[rf_path] 1533 [index] - 1534 rtlefuse-> 1535 eprom_chnl_txpwr_ht40_2sdf[rf_path] 1536 [index]; 1537 } else { 1538 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; 1539 } 1540 } 1541 1542 for (i = 0; i < 14; i++) { 1543 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1544 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", 1545 rf_path, i, 1546 rtlefuse->txpwrlevel_cck[rf_path][i], 1547 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 1548 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 1549 } 1550 } 1551 1552 for (i = 0; i < 3; i++) { 1553 if (!autoload_fail) { 1554 rtlefuse->eeprom_pwrlimit_ht40[i] = 1555 hwinfo[EEPROM_TXPWR_GROUP + i]; 1556 rtlefuse->eeprom_pwrlimit_ht20[i] = 1557 hwinfo[EEPROM_TXPWR_GROUP + 3 + i]; 1558 } else { 1559 rtlefuse->eeprom_pwrlimit_ht40[i] = 0; 1560 rtlefuse->eeprom_pwrlimit_ht20[i] = 0; 1561 } 1562 } 1563 1564 for (rf_path = 0; rf_path < 2; rf_path++) { 1565 for (i = 0; i < 14; i++) { 1566 index = rtl92c_get_chnl_group((u8)i); 1567 1568 if (rf_path == RF90_PATH_A) { 1569 rtlefuse->pwrgroup_ht20[rf_path][i] = 1570 (rtlefuse->eeprom_pwrlimit_ht20[index] 1571 & 0xf); 1572 rtlefuse->pwrgroup_ht40[rf_path][i] = 1573 (rtlefuse->eeprom_pwrlimit_ht40[index] 1574 & 0xf); 1575 } else if (rf_path == RF90_PATH_B) { 1576 rtlefuse->pwrgroup_ht20[rf_path][i] = 1577 ((rtlefuse->eeprom_pwrlimit_ht20[index] 1578 & 0xf0) >> 4); 1579 rtlefuse->pwrgroup_ht40[rf_path][i] = 1580 ((rtlefuse->eeprom_pwrlimit_ht40[index] 1581 & 0xf0) >> 4); 1582 } 1583 1584 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1585 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", 1586 rf_path, i, 1587 rtlefuse->pwrgroup_ht20[rf_path][i]); 1588 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1589 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", 1590 rf_path, i, 1591 rtlefuse->pwrgroup_ht40[rf_path][i]); 1592 } 1593 } 1594 1595 for (i = 0; i < 14; i++) { 1596 index = rtl92c_get_chnl_group((u8)i); 1597 1598 if (!autoload_fail) 1599 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; 1600 else 1601 tempval = EEPROM_DEFAULT_HT20_DIFF; 1602 1603 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 1604 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 1605 ((tempval >> 4) & 0xF); 1606 1607 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) 1608 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; 1609 1610 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) 1611 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; 1612 1613 index = rtl92c_get_chnl_group((u8)i); 1614 1615 if (!autoload_fail) 1616 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; 1617 else 1618 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 1619 1620 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); 1621 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 1622 ((tempval >> 4) & 0xF); 1623 } 1624 1625 rtlefuse->legacy_ht_txpowerdiff = 1626 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; 1627 1628 for (i = 0; i < 14; i++) 1629 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1630 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", 1631 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 1632 for (i = 0; i < 14; i++) 1633 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1634 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", 1635 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 1636 for (i = 0; i < 14; i++) 1637 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1638 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", 1639 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 1640 for (i = 0; i < 14; i++) 1641 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1642 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", 1643 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 1644 1645 if (!autoload_fail) 1646 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); 1647 else 1648 rtlefuse->eeprom_regulatory = 0; 1649 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1650 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 1651 1652 if (!autoload_fail) { 1653 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; 1654 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B]; 1655 } else { 1656 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; 1657 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI; 1658 } 1659 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 1660 rtlefuse->eeprom_tssi[RF90_PATH_A], 1661 rtlefuse->eeprom_tssi[RF90_PATH_B]); 1662 1663 if (!autoload_fail) 1664 tempval = hwinfo[EEPROM_THERMAL_METER]; 1665 else 1666 tempval = EEPROM_DEFAULT_THERMALMETER; 1667 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); 1668 1669 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) 1670 rtlefuse->apk_thermalmeterignore = true; 1671 1672 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 1673 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1674 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1675 } 1676 1677 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw) 1678 { 1679 struct rtl_priv *rtlpriv = rtl_priv(hw); 1680 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1681 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1682 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, 1683 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 1684 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 1685 COUNTRY_CODE_WORLD_WIDE_13}; 1686 u8 *hwinfo; 1687 1688 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 1689 if (!hwinfo) 1690 return; 1691 1692 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 1693 goto exit; 1694 1695 _rtl92ce_read_txpower_info_from_hwpg(hw, 1696 rtlefuse->autoload_failflag, 1697 hwinfo); 1698 1699 rtl8192ce_read_bt_coexist_info_from_hwpg(hw, 1700 rtlefuse->autoload_failflag, 1701 hwinfo); 1702 if (rtlhal->oem_id == RT_CID_DEFAULT) { 1703 switch (rtlefuse->eeprom_oemid) { 1704 case EEPROM_CID_DEFAULT: 1705 if (rtlefuse->eeprom_did == 0x8176) { 1706 if ((rtlefuse->eeprom_svid == 0x103C && 1707 rtlefuse->eeprom_smid == 0x1629)) 1708 rtlhal->oem_id = RT_CID_819X_HP; 1709 else 1710 rtlhal->oem_id = RT_CID_DEFAULT; 1711 } else { 1712 rtlhal->oem_id = RT_CID_DEFAULT; 1713 } 1714 break; 1715 case EEPROM_CID_TOSHIBA: 1716 rtlhal->oem_id = RT_CID_TOSHIBA; 1717 break; 1718 case EEPROM_CID_QMI: 1719 rtlhal->oem_id = RT_CID_819X_QMI; 1720 break; 1721 case EEPROM_CID_WHQL: 1722 default: 1723 rtlhal->oem_id = RT_CID_DEFAULT; 1724 break; 1725 } 1726 } 1727 exit: 1728 kfree(hwinfo); 1729 } 1730 1731 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw) 1732 { 1733 struct rtl_priv *rtlpriv = rtl_priv(hw); 1734 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1735 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1736 1737 switch (rtlhal->oem_id) { 1738 case RT_CID_819X_HP: 1739 pcipriv->ledctl.led_opendrain = true; 1740 break; 1741 case RT_CID_819X_LENOVO: 1742 case RT_CID_DEFAULT: 1743 case RT_CID_TOSHIBA: 1744 case RT_CID_CCX: 1745 case RT_CID_819X_ACER: 1746 case RT_CID_WHQL: 1747 default: 1748 break; 1749 } 1750 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1751 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 1752 } 1753 1754 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw) 1755 { 1756 struct rtl_priv *rtlpriv = rtl_priv(hw); 1757 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1758 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1759 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1760 u8 tmp_u1b; 1761 1762 rtlhal->version = _rtl92ce_read_chip_version(hw); 1763 if (get_rf_type(rtlphy) == RF_1T1R) 1764 rtlpriv->dm.rfpath_rxenable[0] = true; 1765 else 1766 rtlpriv->dm.rfpath_rxenable[0] = 1767 rtlpriv->dm.rfpath_rxenable[1] = true; 1768 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 1769 rtlhal->version); 1770 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 1771 if (tmp_u1b & BIT(4)) { 1772 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 1773 rtlefuse->epromtype = EEPROM_93C46; 1774 } else { 1775 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 1776 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 1777 } 1778 if (tmp_u1b & BIT(5)) { 1779 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1780 rtlefuse->autoload_failflag = false; 1781 _rtl92ce_read_adapter_info(hw); 1782 } else { 1783 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n"); 1784 } 1785 _rtl92ce_hal_customized_behavior(hw); 1786 } 1787 1788 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw, 1789 struct ieee80211_sta *sta) 1790 { 1791 struct rtl_priv *rtlpriv = rtl_priv(hw); 1792 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1793 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1794 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1795 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1796 u32 ratr_value; 1797 u8 ratr_index = 0; 1798 u8 nmode = mac->ht_enable; 1799 u16 shortgi_rate; 1800 u32 tmp_ratr_value; 1801 u8 curtxbw_40mhz = mac->bw_40; 1802 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1803 1 : 0; 1804 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1805 1 : 0; 1806 enum wireless_mode wirelessmode = mac->mode; 1807 u32 ratr_mask; 1808 1809 if (rtlhal->current_bandtype == BAND_ON_5G) 1810 ratr_value = sta->supp_rates[1] << 4; 1811 else 1812 ratr_value = sta->supp_rates[0]; 1813 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1814 ratr_value = 0xfff; 1815 1816 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1817 sta->ht_cap.mcs.rx_mask[0] << 12); 1818 switch (wirelessmode) { 1819 case WIRELESS_MODE_B: 1820 if (ratr_value & 0x0000000c) 1821 ratr_value &= 0x0000000d; 1822 else 1823 ratr_value &= 0x0000000f; 1824 break; 1825 case WIRELESS_MODE_G: 1826 ratr_value &= 0x00000FF5; 1827 break; 1828 case WIRELESS_MODE_N_24G: 1829 case WIRELESS_MODE_N_5G: 1830 nmode = 1; 1831 if (get_rf_type(rtlphy) == RF_1T2R || 1832 get_rf_type(rtlphy) == RF_1T1R) 1833 ratr_mask = 0x000ff005; 1834 else 1835 ratr_mask = 0x0f0ff005; 1836 1837 ratr_value &= ratr_mask; 1838 break; 1839 default: 1840 if (rtlphy->rf_type == RF_1T2R) 1841 ratr_value &= 0x000ff0ff; 1842 else 1843 ratr_value &= 0x0f0ff0ff; 1844 1845 break; 1846 } 1847 1848 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 1849 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) && 1850 (rtlpcipriv->bt_coexist.bt_cur_state) && 1851 (rtlpcipriv->bt_coexist.bt_ant_isolation) && 1852 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) || 1853 (rtlpcipriv->bt_coexist.bt_service == BT_BUSY))) 1854 ratr_value &= 0x0fffcfc0; 1855 else 1856 ratr_value &= 0x0FFFFFFF; 1857 1858 if (nmode && ((curtxbw_40mhz && 1859 curshortgi_40mhz) || (!curtxbw_40mhz && 1860 curshortgi_20mhz))) { 1861 1862 ratr_value |= 0x10000000; 1863 tmp_ratr_value = (ratr_value >> 12); 1864 1865 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 1866 if ((1 << shortgi_rate) & tmp_ratr_value) 1867 break; 1868 } 1869 1870 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 1871 (shortgi_rate << 4) | (shortgi_rate); 1872 } 1873 1874 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 1875 1876 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", 1877 rtl_read_dword(rtlpriv, REG_ARFR0)); 1878 } 1879 1880 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw, 1881 struct ieee80211_sta *sta, u8 rssi_level) 1882 { 1883 struct rtl_priv *rtlpriv = rtl_priv(hw); 1884 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1885 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1886 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1887 struct rtl_sta_info *sta_entry = NULL; 1888 u32 ratr_bitmap; 1889 u8 ratr_index; 1890 u8 curtxbw_40mhz = (sta->ht_cap.cap & 1891 IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0; 1892 u8 curshortgi_40mhz = (sta->ht_cap.cap & 1893 IEEE80211_HT_CAP_SGI_40) ? 1 : 0; 1894 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1895 1 : 0; 1896 enum wireless_mode wirelessmode = 0; 1897 bool shortgi = false; 1898 u8 rate_mask[5]; 1899 u8 macid = 0; 1900 1901 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 1902 wirelessmode = sta_entry->wireless_mode; 1903 if (mac->opmode == NL80211_IFTYPE_STATION || 1904 mac->opmode == NL80211_IFTYPE_MESH_POINT) 1905 curtxbw_40mhz = mac->bw_40; 1906 else if (mac->opmode == NL80211_IFTYPE_AP || 1907 mac->opmode == NL80211_IFTYPE_ADHOC) 1908 macid = sta->aid + 1; 1909 1910 if (rtlhal->current_bandtype == BAND_ON_5G) 1911 ratr_bitmap = sta->supp_rates[1] << 4; 1912 else 1913 ratr_bitmap = sta->supp_rates[0]; 1914 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1915 ratr_bitmap = 0xfff; 1916 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1917 sta->ht_cap.mcs.rx_mask[0] << 12); 1918 switch (wirelessmode) { 1919 case WIRELESS_MODE_B: 1920 ratr_index = RATR_INX_WIRELESS_B; 1921 if (ratr_bitmap & 0x0000000c) 1922 ratr_bitmap &= 0x0000000d; 1923 else 1924 ratr_bitmap &= 0x0000000f; 1925 break; 1926 case WIRELESS_MODE_G: 1927 ratr_index = RATR_INX_WIRELESS_GB; 1928 1929 if (rssi_level == 1) 1930 ratr_bitmap &= 0x00000f00; 1931 else if (rssi_level == 2) 1932 ratr_bitmap &= 0x00000ff0; 1933 else 1934 ratr_bitmap &= 0x00000ff5; 1935 break; 1936 case WIRELESS_MODE_A: 1937 ratr_index = RATR_INX_WIRELESS_A; 1938 ratr_bitmap &= 0x00000ff0; 1939 break; 1940 case WIRELESS_MODE_N_24G: 1941 case WIRELESS_MODE_N_5G: 1942 ratr_index = RATR_INX_WIRELESS_NGB; 1943 1944 if (rtlphy->rf_type == RF_1T2R || 1945 rtlphy->rf_type == RF_1T1R) { 1946 if (curtxbw_40mhz) { 1947 if (rssi_level == 1) 1948 ratr_bitmap &= 0x000f0000; 1949 else if (rssi_level == 2) 1950 ratr_bitmap &= 0x000ff000; 1951 else 1952 ratr_bitmap &= 0x000ff015; 1953 } else { 1954 if (rssi_level == 1) 1955 ratr_bitmap &= 0x000f0000; 1956 else if (rssi_level == 2) 1957 ratr_bitmap &= 0x000ff000; 1958 else 1959 ratr_bitmap &= 0x000ff005; 1960 } 1961 } else { 1962 if (curtxbw_40mhz) { 1963 if (rssi_level == 1) 1964 ratr_bitmap &= 0x0f0f0000; 1965 else if (rssi_level == 2) 1966 ratr_bitmap &= 0x0f0ff000; 1967 else 1968 ratr_bitmap &= 0x0f0ff015; 1969 } else { 1970 if (rssi_level == 1) 1971 ratr_bitmap &= 0x0f0f0000; 1972 else if (rssi_level == 2) 1973 ratr_bitmap &= 0x0f0ff000; 1974 else 1975 ratr_bitmap &= 0x0f0ff005; 1976 } 1977 } 1978 1979 if ((curtxbw_40mhz && curshortgi_40mhz) || 1980 (!curtxbw_40mhz && curshortgi_20mhz)) { 1981 1982 if (macid == 0) 1983 shortgi = true; 1984 else if (macid == 1) 1985 shortgi = false; 1986 } 1987 break; 1988 default: 1989 ratr_index = RATR_INX_WIRELESS_NGB; 1990 1991 if (rtlphy->rf_type == RF_1T2R) 1992 ratr_bitmap &= 0x000ff0ff; 1993 else 1994 ratr_bitmap &= 0x0f0ff0ff; 1995 break; 1996 } 1997 sta_entry->ratr_index = ratr_index; 1998 1999 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2000 "ratr_bitmap :%x\n", ratr_bitmap); 2001 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 2002 (ratr_index << 28); 2003 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; 2004 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2005 "Rate_index:%x, ratr_val:%x, %5phC\n", 2006 ratr_index, ratr_bitmap, rate_mask); 2007 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask); 2008 } 2009 2010 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw, 2011 struct ieee80211_sta *sta, u8 rssi_level) 2012 { 2013 struct rtl_priv *rtlpriv = rtl_priv(hw); 2014 2015 if (rtlpriv->dm.useramask) 2016 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level); 2017 else 2018 rtl92ce_update_hal_rate_table(hw, sta); 2019 } 2020 2021 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw) 2022 { 2023 struct rtl_priv *rtlpriv = rtl_priv(hw); 2024 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2025 u16 sifs_timer; 2026 2027 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2028 &mac->slot_time); 2029 if (!mac->ht_enable) 2030 sifs_timer = 0x0a0a; 2031 else 2032 sifs_timer = 0x1010; 2033 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2034 } 2035 2036 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2037 { 2038 struct rtl_priv *rtlpriv = rtl_priv(hw); 2039 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2040 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2041 enum rf_pwrstate e_rfpowerstate_toset; 2042 u8 u1tmp; 2043 bool actuallyset = false; 2044 unsigned long flag; 2045 2046 if (rtlpci->being_init_adapter) 2047 return false; 2048 2049 if (ppsc->swrf_processing) 2050 return false; 2051 2052 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2053 if (ppsc->rfchange_inprogress) { 2054 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2055 return false; 2056 } else { 2057 ppsc->rfchange_inprogress = true; 2058 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2059 } 2060 2061 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv, 2062 REG_MAC_PINMUX_CFG)&~(BIT(3))); 2063 2064 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); 2065 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; 2066 2067 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { 2068 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2069 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2070 2071 e_rfpowerstate_toset = ERFON; 2072 ppsc->hwradiooff = false; 2073 actuallyset = true; 2074 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) { 2075 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2076 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 2077 2078 e_rfpowerstate_toset = ERFOFF; 2079 ppsc->hwradiooff = true; 2080 actuallyset = true; 2081 } 2082 2083 if (actuallyset) { 2084 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2085 ppsc->rfchange_inprogress = false; 2086 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2087 } else { 2088 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 2089 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2090 2091 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2092 ppsc->rfchange_inprogress = false; 2093 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2094 } 2095 2096 *valid = 1; 2097 return !ppsc->hwradiooff; 2098 2099 } 2100 2101 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index, 2102 u8 *p_macaddr, bool is_group, u8 enc_algo, 2103 bool is_wepkey, bool clear_all) 2104 { 2105 struct rtl_priv *rtlpriv = rtl_priv(hw); 2106 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2107 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2108 u8 *macaddr = p_macaddr; 2109 u32 entry_id = 0; 2110 bool is_pairwise = false; 2111 2112 static u8 cam_const_addr[4][6] = { 2113 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2114 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2115 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2116 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2117 }; 2118 static u8 cam_const_broad[] = { 2119 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2120 }; 2121 2122 if (clear_all) { 2123 u8 idx = 0; 2124 u8 cam_offset = 0; 2125 u8 clear_number = 5; 2126 2127 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2128 2129 for (idx = 0; idx < clear_number; idx++) { 2130 rtl_cam_mark_invalid(hw, cam_offset + idx); 2131 rtl_cam_empty_entry(hw, cam_offset + idx); 2132 2133 if (idx < 5) { 2134 memset(rtlpriv->sec.key_buf[idx], 0, 2135 MAX_KEY_LEN); 2136 rtlpriv->sec.key_len[idx] = 0; 2137 } 2138 } 2139 2140 } else { 2141 switch (enc_algo) { 2142 case WEP40_ENCRYPTION: 2143 enc_algo = CAM_WEP40; 2144 break; 2145 case WEP104_ENCRYPTION: 2146 enc_algo = CAM_WEP104; 2147 break; 2148 case TKIP_ENCRYPTION: 2149 enc_algo = CAM_TKIP; 2150 break; 2151 case AESCCMP_ENCRYPTION: 2152 enc_algo = CAM_AES; 2153 break; 2154 default: 2155 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2156 "switch case %#x not processed\n", enc_algo); 2157 enc_algo = CAM_TKIP; 2158 break; 2159 } 2160 2161 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2162 macaddr = cam_const_addr[key_index]; 2163 entry_id = key_index; 2164 } else { 2165 if (is_group) { 2166 macaddr = cam_const_broad; 2167 entry_id = key_index; 2168 } else { 2169 if (mac->opmode == NL80211_IFTYPE_AP || 2170 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 2171 entry_id = rtl_cam_get_free_entry(hw, 2172 p_macaddr); 2173 if (entry_id >= TOTAL_CAM_ENTRY) { 2174 RT_TRACE(rtlpriv, COMP_SEC, 2175 DBG_EMERG, 2176 "Can not find free hw security cam entry\n"); 2177 return; 2178 } 2179 } else { 2180 entry_id = CAM_PAIRWISE_KEY_POSITION; 2181 } 2182 2183 key_index = PAIRWISE_KEYIDX; 2184 is_pairwise = true; 2185 } 2186 } 2187 2188 if (rtlpriv->sec.key_len[key_index] == 0) { 2189 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2190 "delete one entry, entry_id is %d\n", 2191 entry_id); 2192 if (mac->opmode == NL80211_IFTYPE_AP || 2193 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2194 rtl_cam_del_entry(hw, p_macaddr); 2195 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2196 } else { 2197 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 2198 "The insert KEY length is %d\n", 2199 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); 2200 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 2201 "The insert KEY is %x %x\n", 2202 rtlpriv->sec.key_buf[0][0], 2203 rtlpriv->sec.key_buf[0][1]); 2204 2205 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2206 "add one entry\n"); 2207 if (is_pairwise) { 2208 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, 2209 "Pairwise Key content", 2210 rtlpriv->sec.pairwise_key, 2211 rtlpriv->sec. 2212 key_len[PAIRWISE_KEYIDX]); 2213 2214 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2215 "set Pairwise key\n"); 2216 2217 rtl_cam_add_one_entry(hw, macaddr, key_index, 2218 entry_id, enc_algo, 2219 CAM_CONFIG_NO_USEDK, 2220 rtlpriv->sec. 2221 key_buf[key_index]); 2222 } else { 2223 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2224 "set group key\n"); 2225 2226 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2227 rtl_cam_add_one_entry(hw, 2228 rtlefuse->dev_addr, 2229 PAIRWISE_KEYIDX, 2230 CAM_PAIRWISE_KEY_POSITION, 2231 enc_algo, 2232 CAM_CONFIG_NO_USEDK, 2233 rtlpriv->sec.key_buf 2234 [entry_id]); 2235 } 2236 2237 rtl_cam_add_one_entry(hw, macaddr, key_index, 2238 entry_id, enc_algo, 2239 CAM_CONFIG_NO_USEDK, 2240 rtlpriv->sec.key_buf[entry_id]); 2241 } 2242 2243 } 2244 } 2245 } 2246 2247 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw) 2248 { 2249 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 2250 2251 rtlpcipriv->bt_coexist.bt_coexistence = 2252 rtlpcipriv->bt_coexist.eeprom_bt_coexist; 2253 rtlpcipriv->bt_coexist.bt_ant_num = 2254 rtlpcipriv->bt_coexist.eeprom_bt_ant_num; 2255 rtlpcipriv->bt_coexist.bt_coexist_type = 2256 rtlpcipriv->bt_coexist.eeprom_bt_type; 2257 2258 if (rtlpcipriv->bt_coexist.reg_bt_iso == 2) 2259 rtlpcipriv->bt_coexist.bt_ant_isolation = 2260 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol; 2261 else 2262 rtlpcipriv->bt_coexist.bt_ant_isolation = 2263 rtlpcipriv->bt_coexist.reg_bt_iso; 2264 2265 rtlpcipriv->bt_coexist.bt_radio_shared_type = 2266 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared; 2267 2268 if (rtlpcipriv->bt_coexist.bt_coexistence) { 2269 2270 if (rtlpcipriv->bt_coexist.reg_bt_sco == 1) 2271 rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION; 2272 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2) 2273 rtlpcipriv->bt_coexist.bt_service = BT_SCO; 2274 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4) 2275 rtlpcipriv->bt_coexist.bt_service = BT_BUSY; 2276 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5) 2277 rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY; 2278 else 2279 rtlpcipriv->bt_coexist.bt_service = BT_IDLE; 2280 2281 rtlpcipriv->bt_coexist.bt_edca_ul = 0; 2282 rtlpcipriv->bt_coexist.bt_edca_dl = 0; 2283 rtlpcipriv->bt_coexist.bt_rssi_state = 0xff; 2284 } 2285 } 2286 2287 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 2288 bool auto_load_fail, u8 *hwinfo) 2289 { 2290 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 2291 u8 val; 2292 2293 if (!auto_load_fail) { 2294 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 2295 ((hwinfo[RF_OPTION1] & 0xe0) >> 5); 2296 val = hwinfo[RF_OPTION4]; 2297 rtlpcipriv->bt_coexist.eeprom_bt_type = ((val & 0xe) >> 1); 2298 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (val & 0x1); 2299 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4); 2300 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = 2301 ((val & 0x20) >> 5); 2302 } else { 2303 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0; 2304 rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE; 2305 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2; 2306 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = 0; 2307 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED; 2308 } 2309 2310 rtl8192ce_bt_var_init(hw); 2311 } 2312 2313 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw) 2314 { 2315 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 2316 2317 /* 0:Low, 1:High, 2:From Efuse. */ 2318 rtlpcipriv->bt_coexist.reg_bt_iso = 2; 2319 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 2320 rtlpcipriv->bt_coexist.reg_bt_sco = 3; 2321 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 2322 rtlpcipriv->bt_coexist.reg_bt_sco = 0; 2323 } 2324 2325 2326 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw) 2327 { 2328 struct rtl_priv *rtlpriv = rtl_priv(hw); 2329 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2330 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 2331 2332 u8 u1_tmp; 2333 2334 if (rtlpcipriv->bt_coexist.bt_coexistence && 2335 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) || 2336 rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) { 2337 2338 if (rtlpcipriv->bt_coexist.bt_ant_isolation) 2339 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0); 2340 2341 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) & 2342 BIT_OFFSET_LEN_MASK_32(0, 1); 2343 u1_tmp = u1_tmp | 2344 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ? 2345 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) | 2346 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ? 2347 0 : BIT_OFFSET_LEN_MASK_32(2, 1)); 2348 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp); 2349 2350 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa); 2351 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040); 2352 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010); 2353 2354 /* Config to 1T1R. */ 2355 if (rtlphy->rf_type == RF_1T1R) { 2356 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE); 2357 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1)); 2358 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp); 2359 2360 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE); 2361 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1)); 2362 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp); 2363 } 2364 } 2365 } 2366 2367 void rtl92ce_suspend(struct ieee80211_hw *hw) 2368 { 2369 } 2370 2371 void rtl92ce_resume(struct ieee80211_hw *hw) 2372 { 2373 } 2374