1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 *****************************************************************************/ 29 30 #include "../wifi.h" 31 #include "../efuse.h" 32 #include "../base.h" 33 #include "../regd.h" 34 #include "../cam.h" 35 #include "../ps.h" 36 #include "../pci.h" 37 #include "reg.h" 38 #include "def.h" 39 #include "phy.h" 40 #include "../rtl8192c/dm_common.h" 41 #include "../rtl8192c/fw_common.h" 42 #include "../rtl8192c/phy_common.h" 43 #include "dm.h" 44 #include "led.h" 45 #include "hw.h" 46 47 #define LLT_CONFIG 5 48 49 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 50 u8 set_bits, u8 clear_bits) 51 { 52 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 53 struct rtl_priv *rtlpriv = rtl_priv(hw); 54 55 rtlpci->reg_bcn_ctrl_val |= set_bits; 56 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 57 58 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 59 } 60 61 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw) 62 { 63 struct rtl_priv *rtlpriv = rtl_priv(hw); 64 u8 tmp1byte; 65 66 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 67 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 68 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 69 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 70 tmp1byte &= ~(BIT(0)); 71 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 72 } 73 74 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw) 75 { 76 struct rtl_priv *rtlpriv = rtl_priv(hw); 77 u8 tmp1byte; 78 79 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 80 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 81 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 82 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 83 tmp1byte |= BIT(0); 84 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 85 } 86 87 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw) 88 { 89 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1)); 90 } 91 92 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw) 93 { 94 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0); 95 } 96 97 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 98 { 99 struct rtl_priv *rtlpriv = rtl_priv(hw); 100 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 101 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 102 103 switch (variable) { 104 case HW_VAR_RCR: 105 *((u32 *) (val)) = rtlpci->receive_config; 106 break; 107 case HW_VAR_RF_STATE: 108 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 109 break; 110 case HW_VAR_FWLPS_RF_ON:{ 111 enum rf_pwrstate rfState; 112 u32 val_rcr; 113 114 rtlpriv->cfg->ops->get_hw_reg(hw, 115 HW_VAR_RF_STATE, 116 (u8 *) (&rfState)); 117 if (rfState == ERFOFF) { 118 *((bool *) (val)) = true; 119 } else { 120 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 121 val_rcr &= 0x00070000; 122 if (val_rcr) 123 *((bool *) (val)) = false; 124 else 125 *((bool *) (val)) = true; 126 } 127 break; 128 } 129 case HW_VAR_FW_PSMODE_STATUS: 130 *((bool *) (val)) = ppsc->fw_current_inpsmode; 131 break; 132 case HW_VAR_CORRECT_TSF:{ 133 u64 tsf; 134 u32 *ptsf_low = (u32 *)&tsf; 135 u32 *ptsf_high = ((u32 *)&tsf) + 1; 136 137 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 138 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 139 140 *((u64 *) (val)) = tsf; 141 142 break; 143 } 144 case HAL_DEF_WOWLAN: 145 break; 146 default: 147 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 148 "switch case %#x not processed\n", variable); 149 break; 150 } 151 } 152 153 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 154 { 155 struct rtl_priv *rtlpriv = rtl_priv(hw); 156 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 157 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 158 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 159 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 160 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 161 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 162 u8 idx; 163 164 switch (variable) { 165 case HW_VAR_ETHER_ADDR:{ 166 for (idx = 0; idx < ETH_ALEN; idx++) { 167 rtl_write_byte(rtlpriv, (REG_MACID + idx), 168 val[idx]); 169 } 170 break; 171 } 172 case HW_VAR_BASIC_RATE:{ 173 u16 rate_cfg = ((u16 *) val)[0]; 174 u8 rate_index = 0; 175 rate_cfg &= 0x15f; 176 rate_cfg |= 0x01; 177 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); 178 rtl_write_byte(rtlpriv, REG_RRSR + 1, 179 (rate_cfg >> 8) & 0xff); 180 while (rate_cfg > 0x1) { 181 rate_cfg = (rate_cfg >> 1); 182 rate_index++; 183 } 184 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 185 rate_index); 186 break; 187 } 188 case HW_VAR_BSSID:{ 189 for (idx = 0; idx < ETH_ALEN; idx++) { 190 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 191 val[idx]); 192 } 193 break; 194 } 195 case HW_VAR_SIFS:{ 196 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 197 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); 198 199 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 200 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 201 202 if (!mac->ht_enable) 203 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 204 0x0e0e); 205 else 206 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 207 *((u16 *) val)); 208 break; 209 } 210 case HW_VAR_SLOT_TIME:{ 211 u8 e_aci; 212 213 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 214 "HW_VAR_SLOT_TIME %x\n", val[0]); 215 216 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 217 218 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 219 rtlpriv->cfg->ops->set_hw_reg(hw, 220 HW_VAR_AC_PARAM, 221 &e_aci); 222 } 223 break; 224 } 225 case HW_VAR_ACK_PREAMBLE:{ 226 u8 reg_tmp; 227 u8 short_preamble = (bool)*val; 228 reg_tmp = (mac->cur_40_prime_sc) << 5; 229 if (short_preamble) 230 reg_tmp |= 0x80; 231 232 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 233 break; 234 } 235 case HW_VAR_AMPDU_MIN_SPACE:{ 236 u8 min_spacing_to_set; 237 u8 sec_min_space; 238 239 min_spacing_to_set = *val; 240 if (min_spacing_to_set <= 7) { 241 sec_min_space = 0; 242 243 if (min_spacing_to_set < sec_min_space) 244 min_spacing_to_set = sec_min_space; 245 246 mac->min_space_cfg = ((mac->min_space_cfg & 247 0xf8) | 248 min_spacing_to_set); 249 250 *val = min_spacing_to_set; 251 252 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 253 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 254 mac->min_space_cfg); 255 256 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 257 mac->min_space_cfg); 258 } 259 break; 260 } 261 case HW_VAR_SHORTGI_DENSITY:{ 262 u8 density_to_set; 263 264 density_to_set = *val; 265 mac->min_space_cfg |= (density_to_set << 3); 266 267 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 268 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 269 mac->min_space_cfg); 270 271 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 272 mac->min_space_cfg); 273 274 break; 275 } 276 case HW_VAR_AMPDU_FACTOR:{ 277 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; 278 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97}; 279 280 u8 factor_toset; 281 u8 *p_regtoset = NULL; 282 u8 index = 0; 283 284 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 285 (rtlpcipriv->bt_coexist.bt_coexist_type == 286 BT_CSR_BC4)) 287 p_regtoset = regtoset_bt; 288 else 289 p_regtoset = regtoset_normal; 290 291 factor_toset = *(val); 292 if (factor_toset <= 3) { 293 factor_toset = (1 << (factor_toset + 2)); 294 if (factor_toset > 0xf) 295 factor_toset = 0xf; 296 297 for (index = 0; index < 4; index++) { 298 if ((p_regtoset[index] & 0xf0) > 299 (factor_toset << 4)) 300 p_regtoset[index] = 301 (p_regtoset[index] & 0x0f) | 302 (factor_toset << 4); 303 304 if ((p_regtoset[index] & 0x0f) > 305 factor_toset) 306 p_regtoset[index] = 307 (p_regtoset[index] & 0xf0) | 308 (factor_toset); 309 310 rtl_write_byte(rtlpriv, 311 (REG_AGGLEN_LMT + index), 312 p_regtoset[index]); 313 314 } 315 316 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 317 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 318 factor_toset); 319 } 320 break; 321 } 322 case HW_VAR_AC_PARAM:{ 323 u8 e_aci = *(val); 324 rtl92c_dm_init_edca_turbo(hw); 325 326 if (rtlpci->acm_method != EACMWAY2_SW) 327 rtlpriv->cfg->ops->set_hw_reg(hw, 328 HW_VAR_ACM_CTRL, 329 (&e_aci)); 330 break; 331 } 332 case HW_VAR_ACM_CTRL:{ 333 u8 e_aci = *(val); 334 union aci_aifsn *p_aci_aifsn = 335 (union aci_aifsn *)(&(mac->ac[0].aifs)); 336 u8 acm = p_aci_aifsn->f.acm; 337 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 338 339 acm_ctrl = 340 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 341 342 if (acm) { 343 switch (e_aci) { 344 case AC0_BE: 345 acm_ctrl |= AcmHw_BeqEn; 346 break; 347 case AC2_VI: 348 acm_ctrl |= AcmHw_ViqEn; 349 break; 350 case AC3_VO: 351 acm_ctrl |= AcmHw_VoqEn; 352 break; 353 default: 354 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 355 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 356 acm); 357 break; 358 } 359 } else { 360 switch (e_aci) { 361 case AC0_BE: 362 acm_ctrl &= (~AcmHw_BeqEn); 363 break; 364 case AC2_VI: 365 acm_ctrl &= (~AcmHw_ViqEn); 366 break; 367 case AC3_VO: 368 acm_ctrl &= (~AcmHw_VoqEn); 369 break; 370 default: 371 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 372 "switch case %#x not processed\n", 373 e_aci); 374 break; 375 } 376 } 377 378 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 379 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 380 acm_ctrl); 381 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 382 break; 383 } 384 case HW_VAR_RCR:{ 385 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); 386 rtlpci->receive_config = ((u32 *) (val))[0]; 387 break; 388 } 389 case HW_VAR_RETRY_LIMIT:{ 390 u8 retry_limit = val[0]; 391 392 rtl_write_word(rtlpriv, REG_RL, 393 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 394 retry_limit << RETRY_LIMIT_LONG_SHIFT); 395 break; 396 } 397 case HW_VAR_DUAL_TSF_RST: 398 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 399 break; 400 case HW_VAR_EFUSE_BYTES: 401 rtlefuse->efuse_usedbytes = *((u16 *) val); 402 break; 403 case HW_VAR_EFUSE_USAGE: 404 rtlefuse->efuse_usedpercentage = *val; 405 break; 406 case HW_VAR_IO_CMD: 407 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val)); 408 break; 409 case HW_VAR_WPA_CONFIG: 410 rtl_write_byte(rtlpriv, REG_SECCFG, *val); 411 break; 412 case HW_VAR_SET_RPWM:{ 413 u8 rpwm_val; 414 415 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 416 udelay(1); 417 418 if (rpwm_val & BIT(7)) { 419 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val); 420 } else { 421 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 422 *val | BIT(7)); 423 } 424 425 break; 426 } 427 case HW_VAR_H2C_FW_PWRMODE:{ 428 u8 psmode = *val; 429 430 if ((psmode != FW_PS_ACTIVE_MODE) && 431 (!IS_92C_SERIAL(rtlhal->version))) { 432 rtl92c_dm_rf_saving(hw, true); 433 } 434 435 rtl92c_set_fw_pwrmode_cmd(hw, *val); 436 break; 437 } 438 case HW_VAR_FW_PSMODE_STATUS: 439 ppsc->fw_current_inpsmode = *((bool *) val); 440 break; 441 case HW_VAR_H2C_FW_JOINBSSRPT:{ 442 u8 mstatus = *val; 443 u8 tmp_regcr, tmp_reg422; 444 bool recover = false; 445 446 if (mstatus == RT_MEDIA_CONNECT) { 447 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, 448 NULL); 449 450 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 451 rtl_write_byte(rtlpriv, REG_CR + 1, 452 (tmp_regcr | BIT(0))); 453 454 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); 455 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0); 456 457 tmp_reg422 = 458 rtl_read_byte(rtlpriv, 459 REG_FWHW_TXQ_CTRL + 2); 460 if (tmp_reg422 & BIT(6)) 461 recover = true; 462 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 463 tmp_reg422 & (~BIT(6))); 464 465 rtl92c_set_fw_rsvdpagepkt(hw, NULL); 466 467 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); 468 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); 469 470 if (recover) { 471 rtl_write_byte(rtlpriv, 472 REG_FWHW_TXQ_CTRL + 2, 473 tmp_reg422); 474 } 475 476 rtl_write_byte(rtlpriv, REG_CR + 1, 477 (tmp_regcr & ~(BIT(0)))); 478 } 479 rtl92c_set_fw_joinbss_report_cmd(hw, *val); 480 481 break; 482 } 483 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: 484 rtl92c_set_p2p_ps_offload_cmd(hw, *val); 485 break; 486 case HW_VAR_AID:{ 487 u16 u2btmp; 488 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 489 u2btmp &= 0xC000; 490 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | 491 mac->assoc_id)); 492 493 break; 494 } 495 case HW_VAR_CORRECT_TSF:{ 496 u8 btype_ibss = val[0]; 497 498 if (btype_ibss) 499 _rtl92ce_stop_tx_beacon(hw); 500 501 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); 502 503 rtl_write_dword(rtlpriv, REG_TSFTR, 504 (u32) (mac->tsf & 0xffffffff)); 505 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 506 (u32) ((mac->tsf >> 32) & 0xffffffff)); 507 508 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); 509 510 if (btype_ibss) 511 _rtl92ce_resume_tx_beacon(hw); 512 513 break; 514 515 } 516 case HW_VAR_FW_LPS_ACTION: { 517 bool enter_fwlps = *((bool *)val); 518 u8 rpwm_val, fw_pwrmode; 519 bool fw_current_inps; 520 521 if (enter_fwlps) { 522 rpwm_val = 0x02; /* RF off */ 523 fw_current_inps = true; 524 rtlpriv->cfg->ops->set_hw_reg(hw, 525 HW_VAR_FW_PSMODE_STATUS, 526 (u8 *)(&fw_current_inps)); 527 rtlpriv->cfg->ops->set_hw_reg(hw, 528 HW_VAR_H2C_FW_PWRMODE, 529 &ppsc->fwctrl_psmode); 530 531 rtlpriv->cfg->ops->set_hw_reg(hw, 532 HW_VAR_SET_RPWM, 533 &rpwm_val); 534 } else { 535 rpwm_val = 0x0C; /* RF on */ 536 fw_pwrmode = FW_PS_ACTIVE_MODE; 537 fw_current_inps = false; 538 rtlpriv->cfg->ops->set_hw_reg(hw, 539 HW_VAR_SET_RPWM, 540 &rpwm_val); 541 rtlpriv->cfg->ops->set_hw_reg(hw, 542 HW_VAR_H2C_FW_PWRMODE, 543 &fw_pwrmode); 544 545 rtlpriv->cfg->ops->set_hw_reg(hw, 546 HW_VAR_FW_PSMODE_STATUS, 547 (u8 *)(&fw_current_inps)); 548 } 549 break; } 550 case HW_VAR_KEEP_ALIVE: { 551 u8 array[2]; 552 553 array[0] = 0xff; 554 array[1] = *((u8 *)val); 555 rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2, array); 556 break; } 557 default: 558 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 559 "switch case %d not processed\n", variable); 560 break; 561 } 562 } 563 564 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 565 { 566 struct rtl_priv *rtlpriv = rtl_priv(hw); 567 bool status = true; 568 long count = 0; 569 u32 value = _LLT_INIT_ADDR(address) | 570 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); 571 572 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 573 574 do { 575 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 576 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 577 break; 578 579 if (count > POLLING_LLT_THRESHOLD) { 580 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 581 "Failed to polling write LLT done at address %d!\n", 582 address); 583 status = false; 584 break; 585 } 586 } while (++count); 587 588 return status; 589 } 590 591 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw) 592 { 593 struct rtl_priv *rtlpriv = rtl_priv(hw); 594 unsigned short i; 595 u8 txpktbuf_bndy; 596 u8 maxPage; 597 bool status; 598 599 #if LLT_CONFIG == 1 600 maxPage = 255; 601 txpktbuf_bndy = 252; 602 #elif LLT_CONFIG == 2 603 maxPage = 127; 604 txpktbuf_bndy = 124; 605 #elif LLT_CONFIG == 3 606 maxPage = 255; 607 txpktbuf_bndy = 174; 608 #elif LLT_CONFIG == 4 609 maxPage = 255; 610 txpktbuf_bndy = 246; 611 #elif LLT_CONFIG == 5 612 maxPage = 255; 613 txpktbuf_bndy = 246; 614 #endif 615 616 #if LLT_CONFIG == 1 617 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c); 618 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c); 619 #elif LLT_CONFIG == 2 620 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010); 621 #elif LLT_CONFIG == 3 622 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484); 623 #elif LLT_CONFIG == 4 624 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c); 625 #elif LLT_CONFIG == 5 626 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000); 627 628 rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29); 629 #endif 630 631 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy)); 632 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 633 634 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 635 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 636 637 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); 638 rtl_write_byte(rtlpriv, REG_PBP, 0x11); 639 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 640 641 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 642 status = _rtl92ce_llt_write(hw, i, i + 1); 643 if (true != status) 644 return status; 645 } 646 647 status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 648 if (true != status) 649 return status; 650 651 for (i = txpktbuf_bndy; i < maxPage; i++) { 652 status = _rtl92ce_llt_write(hw, i, (i + 1)); 653 if (true != status) 654 return status; 655 } 656 657 status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy); 658 if (true != status) 659 return status; 660 661 return true; 662 } 663 664 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw) 665 { 666 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 667 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 668 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 669 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0); 670 671 if (rtlpci->up_first_time) 672 return; 673 674 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 675 rtl92ce_sw_led_on(hw, pLed0); 676 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 677 rtl92ce_sw_led_on(hw, pLed0); 678 else 679 rtl92ce_sw_led_off(hw, pLed0); 680 } 681 682 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw) 683 { 684 struct rtl_priv *rtlpriv = rtl_priv(hw); 685 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 686 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 687 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 688 689 unsigned char bytetmp; 690 unsigned short wordtmp; 691 u16 retry; 692 693 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 694 if (rtlpcipriv->bt_coexist.bt_coexistence) { 695 u32 value32; 696 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO); 697 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK); 698 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32); 699 } 700 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 701 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F); 702 703 if (rtlpcipriv->bt_coexist.bt_coexistence) { 704 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL); 705 706 u4b_tmp &= (~0x00024800); 707 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp); 708 } 709 710 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0); 711 udelay(2); 712 713 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); 714 udelay(2); 715 716 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); 717 udelay(2); 718 719 retry = 0; 720 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n", 721 rtl_read_dword(rtlpriv, 0xEC), bytetmp); 722 723 while ((bytetmp & BIT(0)) && retry < 1000) { 724 retry++; 725 udelay(50); 726 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); 727 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n", 728 rtl_read_dword(rtlpriv, 0xEC), bytetmp); 729 udelay(50); 730 } 731 732 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012); 733 734 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82); 735 udelay(2); 736 737 if (rtlpcipriv->bt_coexist.bt_coexistence) { 738 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd; 739 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp); 740 } 741 742 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 743 744 if (!_rtl92ce_llt_table_init(hw)) 745 return false; 746 747 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 748 rtl_write_byte(rtlpriv, REG_HISRE, 0xff); 749 750 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff); 751 752 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 753 wordtmp &= 0xf; 754 wordtmp |= 0xF771; 755 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 756 757 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 758 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 759 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); 760 761 rtl_write_byte(rtlpriv, 0x4d0, 0x0); 762 763 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 764 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) & 765 DMA_BIT_MASK(32)); 766 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 767 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma & 768 DMA_BIT_MASK(32)); 769 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 770 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 771 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 772 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 773 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 774 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 775 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 776 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 777 rtl_write_dword(rtlpriv, REG_HQ_DESA, 778 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma & 779 DMA_BIT_MASK(32)); 780 rtl_write_dword(rtlpriv, REG_RX_DESA, 781 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma & 782 DMA_BIT_MASK(32)); 783 784 if (IS_92C_SERIAL(rtlhal->version)) 785 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77); 786 else 787 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22); 788 789 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 790 791 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 792 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); 793 do { 794 retry++; 795 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 796 } while ((retry < 200) && (bytetmp & BIT(7))); 797 798 _rtl92ce_gen_refresh_led_state(hw); 799 800 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); 801 802 return true; 803 } 804 805 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw) 806 { 807 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 808 struct rtl_priv *rtlpriv = rtl_priv(hw); 809 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 810 u8 reg_bw_opmode; 811 u32 reg_prsr; 812 813 reg_bw_opmode = BW_OPMODE_20MHZ; 814 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 815 816 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); 817 818 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 819 820 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr); 821 822 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 823 824 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); 825 826 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); 827 828 rtl_write_word(rtlpriv, REG_RL, 0x0707); 829 830 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); 831 832 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 833 834 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 835 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 836 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 837 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 838 839 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 840 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) 841 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431); 842 else 843 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); 844 845 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); 846 847 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); 848 849 rtlpci->reg_bcn_ctrl_val = 0x1f; 850 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 851 852 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 853 854 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 855 856 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); 857 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 858 859 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 860 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) { 861 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 862 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402); 863 } else { 864 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 865 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 866 } 867 868 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 869 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) 870 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); 871 else 872 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666); 873 874 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); 875 876 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); 877 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); 878 879 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); 880 881 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); 882 883 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); 884 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); 885 886 } 887 888 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw) 889 { 890 struct rtl_priv *rtlpriv = rtl_priv(hw); 891 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 892 893 rtl_write_byte(rtlpriv, 0x34b, 0x93); 894 rtl_write_word(rtlpriv, 0x350, 0x870c); 895 rtl_write_byte(rtlpriv, 0x352, 0x1); 896 897 if (ppsc->support_backdoor) 898 rtl_write_byte(rtlpriv, 0x349, 0x1b); 899 else 900 rtl_write_byte(rtlpriv, 0x349, 0x03); 901 902 rtl_write_word(rtlpriv, 0x350, 0x2718); 903 rtl_write_byte(rtlpriv, 0x352, 0x1); 904 } 905 906 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw) 907 { 908 struct rtl_priv *rtlpriv = rtl_priv(hw); 909 u8 sec_reg_value; 910 911 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 912 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 913 rtlpriv->sec.pairwise_enc_algorithm, 914 rtlpriv->sec.group_enc_algorithm); 915 916 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 917 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 918 "not open hw encryption\n"); 919 return; 920 } 921 922 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable; 923 924 if (rtlpriv->sec.use_defaultkey) { 925 sec_reg_value |= SCR_TxUseDK; 926 sec_reg_value |= SCR_RxUseDK; 927 } 928 929 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 930 931 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 932 933 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 934 "The SECR-value %x\n", sec_reg_value); 935 936 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 937 938 } 939 940 int rtl92ce_hw_init(struct ieee80211_hw *hw) 941 { 942 struct rtl_priv *rtlpriv = rtl_priv(hw); 943 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 944 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 945 struct rtl_phy *rtlphy = &(rtlpriv->phy); 946 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 947 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 948 bool rtstatus = true; 949 bool is92c; 950 int err; 951 u8 tmp_u1b; 952 unsigned long flags; 953 954 rtlpci->being_init_adapter = true; 955 956 /* Since this function can take a very long time (up to 350 ms) 957 * and can be called with irqs disabled, reenable the irqs 958 * to let the other devices continue being serviced. 959 * 960 * It is safe doing so since our own interrupts will only be enabled 961 * in a subsequent step. 962 */ 963 local_save_flags(flags); 964 local_irq_enable(); 965 966 rtlhal->fw_ready = false; 967 rtlpriv->intf_ops->disable_aspm(hw); 968 rtstatus = _rtl92ce_init_mac(hw); 969 if (!rtstatus) { 970 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n"); 971 err = 1; 972 goto exit; 973 } 974 975 err = rtl92c_download_fw(hw); 976 if (err) { 977 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 978 "Failed to download FW. Init HW without FW now..\n"); 979 err = 1; 980 goto exit; 981 } 982 983 rtlhal->fw_ready = true; 984 rtlhal->last_hmeboxnum = 0; 985 rtl92c_phy_mac_config(hw); 986 /* because last function modify RCR, so we update 987 * rcr var here, or TP will unstable for receive_config 988 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 989 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/ 990 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); 991 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 992 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 993 rtl92c_phy_bb_config(hw); 994 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 995 rtl92c_phy_rf_config(hw); 996 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) && 997 !IS_92C_SERIAL(rtlhal->version)) { 998 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); 999 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); 1000 } else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) { 1001 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE); 1002 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31); 1003 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425); 1004 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200); 1005 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053); 1006 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201); 1007 } 1008 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 1009 RF_CHNLBW, RFREG_OFFSET_MASK); 1010 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 1011 RF_CHNLBW, RFREG_OFFSET_MASK); 1012 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1013 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1014 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); 1015 _rtl92ce_hw_configure(hw); 1016 rtl_cam_reset_all_entry(hw); 1017 rtl92ce_enable_hw_security_config(hw); 1018 1019 ppsc->rfpwr_state = ERFON; 1020 1021 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1022 _rtl92ce_enable_aspm_back_door(hw); 1023 rtlpriv->intf_ops->enable_aspm(hw); 1024 1025 rtl8192ce_bt_hw_init(hw); 1026 1027 if (ppsc->rfpwr_state == ERFON) { 1028 rtl92c_phy_set_rfpath_switch(hw, 1); 1029 if (rtlphy->iqk_initialized) { 1030 rtl92c_phy_iq_calibrate(hw, true); 1031 } else { 1032 rtl92c_phy_iq_calibrate(hw, false); 1033 rtlphy->iqk_initialized = true; 1034 } 1035 1036 rtl92c_dm_check_txpower_tracking(hw); 1037 rtl92c_phy_lc_calibrate(hw); 1038 } 1039 1040 is92c = IS_92C_SERIAL(rtlhal->version); 1041 tmp_u1b = efuse_read_1byte(hw, 0x1FA); 1042 if (!(tmp_u1b & BIT(0))) { 1043 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); 1044 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n"); 1045 } 1046 1047 if (!(tmp_u1b & BIT(1)) && is92c) { 1048 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05); 1049 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n"); 1050 } 1051 1052 if (!(tmp_u1b & BIT(4))) { 1053 tmp_u1b = rtl_read_byte(rtlpriv, 0x16); 1054 tmp_u1b &= 0x0F; 1055 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80); 1056 udelay(10); 1057 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90); 1058 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n"); 1059 } 1060 rtl92c_dm_init(hw); 1061 exit: 1062 local_irq_restore(flags); 1063 rtlpci->being_init_adapter = false; 1064 return err; 1065 } 1066 1067 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw) 1068 { 1069 struct rtl_priv *rtlpriv = rtl_priv(hw); 1070 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1071 enum version_8192c version = VERSION_UNKNOWN; 1072 u32 value32; 1073 const char *versionid; 1074 1075 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 1076 if (value32 & TRP_VAUX_EN) { 1077 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C : 1078 VERSION_A_CHIP_88C; 1079 } else { 1080 version = (enum version_8192c) (CHIP_VER_B | 1081 ((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) | 1082 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); 1083 if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 & 1084 CHIP_VER_RTL_MASK)) { 1085 version = (enum version_8192c)(version | 1086 ((((value32 & CHIP_VER_RTL_MASK) == BIT(12)) 1087 ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) | 1088 CHIP_VENDOR_UMC)); 1089 } 1090 if (IS_92C_SERIAL(version)) { 1091 value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM); 1092 version = (enum version_8192c)(version | 1093 ((CHIP_BONDING_IDENTIFIER(value32) 1094 == CHIP_BONDING_92C_1T2R) ? 1095 RF_TYPE_1T2R : 0)); 1096 } 1097 } 1098 1099 switch (version) { 1100 case VERSION_B_CHIP_92C: 1101 versionid = "B_CHIP_92C"; 1102 break; 1103 case VERSION_B_CHIP_88C: 1104 versionid = "B_CHIP_88C"; 1105 break; 1106 case VERSION_A_CHIP_92C: 1107 versionid = "A_CHIP_92C"; 1108 break; 1109 case VERSION_A_CHIP_88C: 1110 versionid = "A_CHIP_88C"; 1111 break; 1112 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT: 1113 versionid = "A_CUT_92C_1T2R"; 1114 break; 1115 case VERSION_NORMAL_UMC_CHIP_92C_A_CUT: 1116 versionid = "A_CUT_92C"; 1117 break; 1118 case VERSION_NORMAL_UMC_CHIP_88C_A_CUT: 1119 versionid = "A_CUT_88C"; 1120 break; 1121 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT: 1122 versionid = "B_CUT_92C_1T2R"; 1123 break; 1124 case VERSION_NORMAL_UMC_CHIP_92C_B_CUT: 1125 versionid = "B_CUT_92C"; 1126 break; 1127 case VERSION_NORMAL_UMC_CHIP_88C_B_CUT: 1128 versionid = "B_CUT_88C"; 1129 break; 1130 default: 1131 versionid = "Unknown. Bug?"; 1132 break; 1133 } 1134 1135 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, 1136 "Chip Version ID: %s\n", versionid); 1137 1138 switch (version & 0x3) { 1139 case CHIP_88C: 1140 rtlphy->rf_type = RF_1T1R; 1141 break; 1142 case CHIP_92C: 1143 rtlphy->rf_type = RF_2T2R; 1144 break; 1145 case CHIP_92C_1T2R: 1146 rtlphy->rf_type = RF_1T2R; 1147 break; 1148 default: 1149 rtlphy->rf_type = RF_1T1R; 1150 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1151 "ERROR RF_Type is set!!\n"); 1152 break; 1153 } 1154 1155 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n", 1156 rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R"); 1157 1158 return version; 1159 } 1160 1161 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw, 1162 enum nl80211_iftype type) 1163 { 1164 struct rtl_priv *rtlpriv = rtl_priv(hw); 1165 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1166 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1167 u8 mode = MSR_NOLINK; 1168 1169 bt_msr &= 0xfc; 1170 1171 switch (type) { 1172 case NL80211_IFTYPE_UNSPECIFIED: 1173 mode = MSR_NOLINK; 1174 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1175 "Set Network type to NO LINK!\n"); 1176 break; 1177 case NL80211_IFTYPE_ADHOC: 1178 mode = MSR_ADHOC; 1179 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1180 "Set Network type to Ad Hoc!\n"); 1181 break; 1182 case NL80211_IFTYPE_STATION: 1183 mode = MSR_INFRA; 1184 ledaction = LED_CTL_LINK; 1185 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1186 "Set Network type to STA!\n"); 1187 break; 1188 case NL80211_IFTYPE_AP: 1189 mode = MSR_AP; 1190 ledaction = LED_CTL_LINK; 1191 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1192 "Set Network type to AP!\n"); 1193 break; 1194 case NL80211_IFTYPE_MESH_POINT: 1195 mode = MSR_ADHOC; 1196 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1197 "Set Network type to Mesh Point!\n"); 1198 break; 1199 default: 1200 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 1201 "Network type %d not supported!\n", type); 1202 return 1; 1203 1204 } 1205 1206 /* MSR_INFRA == Link in infrastructure network; 1207 * MSR_ADHOC == Link in ad hoc network; 1208 * Therefore, check link state is necessary. 1209 * 1210 * MSR_AP == AP mode; link state does not matter here. 1211 */ 1212 if (mode != MSR_AP && 1213 rtlpriv->mac80211.link_state < MAC80211_LINKED) { 1214 mode = MSR_NOLINK; 1215 ledaction = LED_CTL_NO_LINK; 1216 } 1217 if (mode == MSR_NOLINK || mode == MSR_INFRA) { 1218 _rtl92ce_stop_tx_beacon(hw); 1219 _rtl92ce_enable_bcn_sub_func(hw); 1220 } else if (mode == MSR_ADHOC || mode == MSR_AP) { 1221 _rtl92ce_resume_tx_beacon(hw); 1222 _rtl92ce_disable_bcn_sub_func(hw); 1223 } else { 1224 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1225 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 1226 mode); 1227 } 1228 rtl_write_byte(rtlpriv, MSR, bt_msr | mode); 1229 1230 rtlpriv->cfg->ops->led_control(hw, ledaction); 1231 if (mode == MSR_AP) 1232 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1233 else 1234 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1235 return 0; 1236 } 1237 1238 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1239 { 1240 struct rtl_priv *rtlpriv = rtl_priv(hw); 1241 u32 reg_rcr; 1242 1243 if (rtlpriv->psc.rfpwr_state != ERFON) 1244 return; 1245 1246 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1247 1248 if (check_bssid) { 1249 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1250 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1251 (u8 *) (®_rcr)); 1252 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1253 } else if (!check_bssid) { 1254 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1255 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0); 1256 rtlpriv->cfg->ops->set_hw_reg(hw, 1257 HW_VAR_RCR, (u8 *) (®_rcr)); 1258 } 1259 1260 } 1261 1262 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1263 { 1264 struct rtl_priv *rtlpriv = rtl_priv(hw); 1265 1266 if (_rtl92ce_set_media_status(hw, type)) 1267 return -EOPNOTSUPP; 1268 1269 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1270 if (type != NL80211_IFTYPE_AP && 1271 type != NL80211_IFTYPE_MESH_POINT) 1272 rtl92ce_set_check_bssid(hw, true); 1273 } else { 1274 rtl92ce_set_check_bssid(hw, false); 1275 } 1276 1277 return 0; 1278 } 1279 1280 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ 1281 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci) 1282 { 1283 struct rtl_priv *rtlpriv = rtl_priv(hw); 1284 rtl92c_dm_init_edca_turbo(hw); 1285 switch (aci) { 1286 case AC1_BK: 1287 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 1288 break; 1289 case AC0_BE: 1290 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */ 1291 break; 1292 case AC2_VI: 1293 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 1294 break; 1295 case AC3_VO: 1296 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 1297 break; 1298 default: 1299 RT_ASSERT(false, "invalid aci: %d !\n", aci); 1300 break; 1301 } 1302 } 1303 1304 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw) 1305 { 1306 struct rtl_priv *rtlpriv = rtl_priv(hw); 1307 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1308 1309 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); 1310 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); 1311 rtlpci->irq_enabled = true; 1312 } 1313 1314 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw) 1315 { 1316 struct rtl_priv *rtlpriv = rtl_priv(hw); 1317 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1318 1319 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); 1320 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); 1321 rtlpci->irq_enabled = false; 1322 } 1323 1324 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw) 1325 { 1326 struct rtl_priv *rtlpriv = rtl_priv(hw); 1327 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1328 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1329 u8 u1b_tmp; 1330 u32 u4b_tmp; 1331 1332 rtlpriv->intf_ops->enable_aspm(hw); 1333 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1334 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 1335 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); 1336 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 1337 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 1338 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0); 1339 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) 1340 rtl92c_firmware_selfreset(hw); 1341 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51); 1342 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1343 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000); 1344 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL); 1345 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 1346 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) || 1347 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) { 1348 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 | 1349 (u1b_tmp << 8)); 1350 } else { 1351 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 | 1352 (u1b_tmp << 8)); 1353 } 1354 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790); 1355 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); 1356 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); 1357 if (!IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) 1358 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); 1359 if (rtlpcipriv->bt_coexist.bt_coexistence) { 1360 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL); 1361 u4b_tmp |= 0x03824800; 1362 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp); 1363 } else { 1364 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e); 1365 } 1366 1367 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); 1368 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10); 1369 } 1370 1371 void rtl92ce_card_disable(struct ieee80211_hw *hw) 1372 { 1373 struct rtl_priv *rtlpriv = rtl_priv(hw); 1374 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1375 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1376 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1377 enum nl80211_iftype opmode; 1378 1379 mac->link_state = MAC80211_NOLINK; 1380 opmode = NL80211_IFTYPE_UNSPECIFIED; 1381 _rtl92ce_set_media_status(hw, opmode); 1382 if (rtlpci->driver_is_goingto_unload || 1383 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1384 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1385 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1386 _rtl92ce_poweroff_adapter(hw); 1387 1388 /* after power off we should do iqk again */ 1389 rtlpriv->phy.iqk_initialized = false; 1390 } 1391 1392 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw, 1393 u32 *p_inta, u32 *p_intb) 1394 { 1395 struct rtl_priv *rtlpriv = rtl_priv(hw); 1396 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1397 1398 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 1399 rtl_write_dword(rtlpriv, ISR, *p_inta); 1400 1401 /* 1402 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; 1403 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb); 1404 */ 1405 } 1406 1407 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw) 1408 { 1409 1410 struct rtl_priv *rtlpriv = rtl_priv(hw); 1411 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1412 u16 bcn_interval, atim_window; 1413 1414 bcn_interval = mac->beacon_interval; 1415 atim_window = 2; /*FIX MERGE */ 1416 rtl92ce_disable_interrupt(hw); 1417 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1418 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1419 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 1420 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 1421 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 1422 rtl_write_byte(rtlpriv, 0x606, 0x30); 1423 rtl92ce_enable_interrupt(hw); 1424 } 1425 1426 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw) 1427 { 1428 struct rtl_priv *rtlpriv = rtl_priv(hw); 1429 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1430 u16 bcn_interval = mac->beacon_interval; 1431 1432 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, 1433 "beacon_interval:%d\n", bcn_interval); 1434 rtl92ce_disable_interrupt(hw); 1435 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1436 rtl92ce_enable_interrupt(hw); 1437 } 1438 1439 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw, 1440 u32 add_msr, u32 rm_msr) 1441 { 1442 struct rtl_priv *rtlpriv = rtl_priv(hw); 1443 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1444 1445 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n", 1446 add_msr, rm_msr); 1447 1448 if (add_msr) 1449 rtlpci->irq_mask[0] |= add_msr; 1450 if (rm_msr) 1451 rtlpci->irq_mask[0] &= (~rm_msr); 1452 rtl92ce_disable_interrupt(hw); 1453 rtl92ce_enable_interrupt(hw); 1454 } 1455 1456 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 1457 bool autoload_fail, 1458 u8 *hwinfo) 1459 { 1460 struct rtl_priv *rtlpriv = rtl_priv(hw); 1461 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1462 u8 rf_path, index, tempval; 1463 u16 i; 1464 1465 for (rf_path = 0; rf_path < 2; rf_path++) { 1466 for (i = 0; i < 3; i++) { 1467 if (!autoload_fail) { 1468 rtlefuse-> 1469 eeprom_chnlarea_txpwr_cck[rf_path][i] = 1470 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; 1471 rtlefuse-> 1472 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1473 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + 1474 i]; 1475 } else { 1476 rtlefuse-> 1477 eeprom_chnlarea_txpwr_cck[rf_path][i] = 1478 EEPROM_DEFAULT_TXPOWERLEVEL; 1479 rtlefuse-> 1480 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1481 EEPROM_DEFAULT_TXPOWERLEVEL; 1482 } 1483 } 1484 } 1485 1486 for (i = 0; i < 3; i++) { 1487 if (!autoload_fail) 1488 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i]; 1489 else 1490 tempval = EEPROM_DEFAULT_HT40_2SDIFF; 1491 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] = 1492 (tempval & 0xf); 1493 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] = 1494 ((tempval & 0xf0) >> 4); 1495 } 1496 1497 for (rf_path = 0; rf_path < 2; rf_path++) 1498 for (i = 0; i < 3; i++) 1499 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1500 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", 1501 rf_path, i, 1502 rtlefuse-> 1503 eeprom_chnlarea_txpwr_cck[rf_path][i]); 1504 for (rf_path = 0; rf_path < 2; rf_path++) 1505 for (i = 0; i < 3; i++) 1506 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1507 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 1508 rf_path, i, 1509 rtlefuse-> 1510 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]); 1511 for (rf_path = 0; rf_path < 2; rf_path++) 1512 for (i = 0; i < 3; i++) 1513 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1514 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 1515 rf_path, i, 1516 rtlefuse-> 1517 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]); 1518 1519 for (rf_path = 0; rf_path < 2; rf_path++) { 1520 for (i = 0; i < 14; i++) { 1521 index = rtl92c_get_chnl_group((u8)i); 1522 1523 rtlefuse->txpwrlevel_cck[rf_path][i] = 1524 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index]; 1525 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 1526 rtlefuse-> 1527 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index]; 1528 1529 if ((rtlefuse-> 1530 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] - 1531 rtlefuse-> 1532 eprom_chnl_txpwr_ht40_2sdf[rf_path][index]) 1533 > 0) { 1534 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 1535 rtlefuse-> 1536 eeprom_chnlarea_txpwr_ht40_1s[rf_path] 1537 [index] - 1538 rtlefuse-> 1539 eprom_chnl_txpwr_ht40_2sdf[rf_path] 1540 [index]; 1541 } else { 1542 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; 1543 } 1544 } 1545 1546 for (i = 0; i < 14; i++) { 1547 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1548 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", 1549 rf_path, i, 1550 rtlefuse->txpwrlevel_cck[rf_path][i], 1551 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 1552 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 1553 } 1554 } 1555 1556 for (i = 0; i < 3; i++) { 1557 if (!autoload_fail) { 1558 rtlefuse->eeprom_pwrlimit_ht40[i] = 1559 hwinfo[EEPROM_TXPWR_GROUP + i]; 1560 rtlefuse->eeprom_pwrlimit_ht20[i] = 1561 hwinfo[EEPROM_TXPWR_GROUP + 3 + i]; 1562 } else { 1563 rtlefuse->eeprom_pwrlimit_ht40[i] = 0; 1564 rtlefuse->eeprom_pwrlimit_ht20[i] = 0; 1565 } 1566 } 1567 1568 for (rf_path = 0; rf_path < 2; rf_path++) { 1569 for (i = 0; i < 14; i++) { 1570 index = rtl92c_get_chnl_group((u8)i); 1571 1572 if (rf_path == RF90_PATH_A) { 1573 rtlefuse->pwrgroup_ht20[rf_path][i] = 1574 (rtlefuse->eeprom_pwrlimit_ht20[index] 1575 & 0xf); 1576 rtlefuse->pwrgroup_ht40[rf_path][i] = 1577 (rtlefuse->eeprom_pwrlimit_ht40[index] 1578 & 0xf); 1579 } else if (rf_path == RF90_PATH_B) { 1580 rtlefuse->pwrgroup_ht20[rf_path][i] = 1581 ((rtlefuse->eeprom_pwrlimit_ht20[index] 1582 & 0xf0) >> 4); 1583 rtlefuse->pwrgroup_ht40[rf_path][i] = 1584 ((rtlefuse->eeprom_pwrlimit_ht40[index] 1585 & 0xf0) >> 4); 1586 } 1587 1588 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1589 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", 1590 rf_path, i, 1591 rtlefuse->pwrgroup_ht20[rf_path][i]); 1592 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1593 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", 1594 rf_path, i, 1595 rtlefuse->pwrgroup_ht40[rf_path][i]); 1596 } 1597 } 1598 1599 for (i = 0; i < 14; i++) { 1600 index = rtl92c_get_chnl_group((u8)i); 1601 1602 if (!autoload_fail) 1603 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; 1604 else 1605 tempval = EEPROM_DEFAULT_HT20_DIFF; 1606 1607 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 1608 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 1609 ((tempval >> 4) & 0xF); 1610 1611 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) 1612 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; 1613 1614 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) 1615 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; 1616 1617 index = rtl92c_get_chnl_group((u8)i); 1618 1619 if (!autoload_fail) 1620 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; 1621 else 1622 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 1623 1624 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); 1625 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 1626 ((tempval >> 4) & 0xF); 1627 } 1628 1629 rtlefuse->legacy_ht_txpowerdiff = 1630 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; 1631 1632 for (i = 0; i < 14; i++) 1633 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1634 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", 1635 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 1636 for (i = 0; i < 14; i++) 1637 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1638 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", 1639 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 1640 for (i = 0; i < 14; i++) 1641 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1642 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", 1643 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 1644 for (i = 0; i < 14; i++) 1645 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1646 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", 1647 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 1648 1649 if (!autoload_fail) 1650 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); 1651 else 1652 rtlefuse->eeprom_regulatory = 0; 1653 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1654 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 1655 1656 if (!autoload_fail) { 1657 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; 1658 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B]; 1659 } else { 1660 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; 1661 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI; 1662 } 1663 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 1664 rtlefuse->eeprom_tssi[RF90_PATH_A], 1665 rtlefuse->eeprom_tssi[RF90_PATH_B]); 1666 1667 if (!autoload_fail) 1668 tempval = hwinfo[EEPROM_THERMAL_METER]; 1669 else 1670 tempval = EEPROM_DEFAULT_THERMALMETER; 1671 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); 1672 1673 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) 1674 rtlefuse->apk_thermalmeterignore = true; 1675 1676 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 1677 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1678 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1679 } 1680 1681 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw) 1682 { 1683 struct rtl_priv *rtlpriv = rtl_priv(hw); 1684 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1685 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1686 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, 1687 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 1688 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 1689 COUNTRY_CODE_WORLD_WIDE_13}; 1690 u8 *hwinfo; 1691 1692 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 1693 if (!hwinfo) 1694 return; 1695 1696 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 1697 goto exit; 1698 1699 _rtl92ce_read_txpower_info_from_hwpg(hw, 1700 rtlefuse->autoload_failflag, 1701 hwinfo); 1702 1703 rtl8192ce_read_bt_coexist_info_from_hwpg(hw, 1704 rtlefuse->autoload_failflag, 1705 hwinfo); 1706 if (rtlhal->oem_id == RT_CID_DEFAULT) { 1707 switch (rtlefuse->eeprom_oemid) { 1708 case EEPROM_CID_DEFAULT: 1709 if (rtlefuse->eeprom_did == 0x8176) { 1710 if ((rtlefuse->eeprom_svid == 0x103C && 1711 rtlefuse->eeprom_smid == 0x1629)) 1712 rtlhal->oem_id = RT_CID_819X_HP; 1713 else 1714 rtlhal->oem_id = RT_CID_DEFAULT; 1715 } else { 1716 rtlhal->oem_id = RT_CID_DEFAULT; 1717 } 1718 break; 1719 case EEPROM_CID_TOSHIBA: 1720 rtlhal->oem_id = RT_CID_TOSHIBA; 1721 break; 1722 case EEPROM_CID_QMI: 1723 rtlhal->oem_id = RT_CID_819X_QMI; 1724 break; 1725 case EEPROM_CID_WHQL: 1726 default: 1727 rtlhal->oem_id = RT_CID_DEFAULT; 1728 break; 1729 } 1730 } 1731 exit: 1732 kfree(hwinfo); 1733 } 1734 1735 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw) 1736 { 1737 struct rtl_priv *rtlpriv = rtl_priv(hw); 1738 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); 1739 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1740 1741 switch (rtlhal->oem_id) { 1742 case RT_CID_819X_HP: 1743 pcipriv->ledctl.led_opendrain = true; 1744 break; 1745 case RT_CID_819X_LENOVO: 1746 case RT_CID_DEFAULT: 1747 case RT_CID_TOSHIBA: 1748 case RT_CID_CCX: 1749 case RT_CID_819X_ACER: 1750 case RT_CID_WHQL: 1751 default: 1752 break; 1753 } 1754 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1755 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 1756 } 1757 1758 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw) 1759 { 1760 struct rtl_priv *rtlpriv = rtl_priv(hw); 1761 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1762 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1763 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1764 u8 tmp_u1b; 1765 1766 rtlhal->version = _rtl92ce_read_chip_version(hw); 1767 if (get_rf_type(rtlphy) == RF_1T1R) 1768 rtlpriv->dm.rfpath_rxenable[0] = true; 1769 else 1770 rtlpriv->dm.rfpath_rxenable[0] = 1771 rtlpriv->dm.rfpath_rxenable[1] = true; 1772 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 1773 rtlhal->version); 1774 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 1775 if (tmp_u1b & BIT(4)) { 1776 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 1777 rtlefuse->epromtype = EEPROM_93C46; 1778 } else { 1779 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 1780 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 1781 } 1782 if (tmp_u1b & BIT(5)) { 1783 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1784 rtlefuse->autoload_failflag = false; 1785 _rtl92ce_read_adapter_info(hw); 1786 } else { 1787 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n"); 1788 } 1789 _rtl92ce_hal_customized_behavior(hw); 1790 } 1791 1792 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw, 1793 struct ieee80211_sta *sta) 1794 { 1795 struct rtl_priv *rtlpriv = rtl_priv(hw); 1796 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 1797 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1798 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1799 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1800 u32 ratr_value; 1801 u8 ratr_index = 0; 1802 u8 nmode = mac->ht_enable; 1803 u16 shortgi_rate; 1804 u32 tmp_ratr_value; 1805 u8 curtxbw_40mhz = mac->bw_40; 1806 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1807 1 : 0; 1808 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1809 1 : 0; 1810 enum wireless_mode wirelessmode = mac->mode; 1811 u32 ratr_mask; 1812 1813 if (rtlhal->current_bandtype == BAND_ON_5G) 1814 ratr_value = sta->supp_rates[1] << 4; 1815 else 1816 ratr_value = sta->supp_rates[0]; 1817 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1818 ratr_value = 0xfff; 1819 1820 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1821 sta->ht_cap.mcs.rx_mask[0] << 12); 1822 switch (wirelessmode) { 1823 case WIRELESS_MODE_B: 1824 if (ratr_value & 0x0000000c) 1825 ratr_value &= 0x0000000d; 1826 else 1827 ratr_value &= 0x0000000f; 1828 break; 1829 case WIRELESS_MODE_G: 1830 ratr_value &= 0x00000FF5; 1831 break; 1832 case WIRELESS_MODE_N_24G: 1833 case WIRELESS_MODE_N_5G: 1834 nmode = 1; 1835 if (get_rf_type(rtlphy) == RF_1T2R || 1836 get_rf_type(rtlphy) == RF_1T1R) 1837 ratr_mask = 0x000ff005; 1838 else 1839 ratr_mask = 0x0f0ff005; 1840 1841 ratr_value &= ratr_mask; 1842 break; 1843 default: 1844 if (rtlphy->rf_type == RF_1T2R) 1845 ratr_value &= 0x000ff0ff; 1846 else 1847 ratr_value &= 0x0f0ff0ff; 1848 1849 break; 1850 } 1851 1852 if ((rtlpcipriv->bt_coexist.bt_coexistence) && 1853 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) && 1854 (rtlpcipriv->bt_coexist.bt_cur_state) && 1855 (rtlpcipriv->bt_coexist.bt_ant_isolation) && 1856 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) || 1857 (rtlpcipriv->bt_coexist.bt_service == BT_BUSY))) 1858 ratr_value &= 0x0fffcfc0; 1859 else 1860 ratr_value &= 0x0FFFFFFF; 1861 1862 if (nmode && ((curtxbw_40mhz && 1863 curshortgi_40mhz) || (!curtxbw_40mhz && 1864 curshortgi_20mhz))) { 1865 1866 ratr_value |= 0x10000000; 1867 tmp_ratr_value = (ratr_value >> 12); 1868 1869 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 1870 if ((1 << shortgi_rate) & tmp_ratr_value) 1871 break; 1872 } 1873 1874 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 1875 (shortgi_rate << 4) | (shortgi_rate); 1876 } 1877 1878 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 1879 1880 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", 1881 rtl_read_dword(rtlpriv, REG_ARFR0)); 1882 } 1883 1884 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw, 1885 struct ieee80211_sta *sta, u8 rssi_level) 1886 { 1887 struct rtl_priv *rtlpriv = rtl_priv(hw); 1888 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1889 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1890 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1891 struct rtl_sta_info *sta_entry = NULL; 1892 u32 ratr_bitmap; 1893 u8 ratr_index; 1894 u8 curtxbw_40mhz = (sta->ht_cap.cap & 1895 IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0; 1896 u8 curshortgi_40mhz = (sta->ht_cap.cap & 1897 IEEE80211_HT_CAP_SGI_40) ? 1 : 0; 1898 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1899 1 : 0; 1900 enum wireless_mode wirelessmode = 0; 1901 bool shortgi = false; 1902 u8 rate_mask[5]; 1903 u8 macid = 0; 1904 1905 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 1906 wirelessmode = sta_entry->wireless_mode; 1907 if (mac->opmode == NL80211_IFTYPE_STATION || 1908 mac->opmode == NL80211_IFTYPE_MESH_POINT) 1909 curtxbw_40mhz = mac->bw_40; 1910 else if (mac->opmode == NL80211_IFTYPE_AP || 1911 mac->opmode == NL80211_IFTYPE_ADHOC) 1912 macid = sta->aid + 1; 1913 1914 if (rtlhal->current_bandtype == BAND_ON_5G) 1915 ratr_bitmap = sta->supp_rates[1] << 4; 1916 else 1917 ratr_bitmap = sta->supp_rates[0]; 1918 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1919 ratr_bitmap = 0xfff; 1920 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1921 sta->ht_cap.mcs.rx_mask[0] << 12); 1922 switch (wirelessmode) { 1923 case WIRELESS_MODE_B: 1924 ratr_index = RATR_INX_WIRELESS_B; 1925 if (ratr_bitmap & 0x0000000c) 1926 ratr_bitmap &= 0x0000000d; 1927 else 1928 ratr_bitmap &= 0x0000000f; 1929 break; 1930 case WIRELESS_MODE_G: 1931 ratr_index = RATR_INX_WIRELESS_GB; 1932 1933 if (rssi_level == 1) 1934 ratr_bitmap &= 0x00000f00; 1935 else if (rssi_level == 2) 1936 ratr_bitmap &= 0x00000ff0; 1937 else 1938 ratr_bitmap &= 0x00000ff5; 1939 break; 1940 case WIRELESS_MODE_A: 1941 ratr_index = RATR_INX_WIRELESS_A; 1942 ratr_bitmap &= 0x00000ff0; 1943 break; 1944 case WIRELESS_MODE_N_24G: 1945 case WIRELESS_MODE_N_5G: 1946 ratr_index = RATR_INX_WIRELESS_NGB; 1947 1948 if (rtlphy->rf_type == RF_1T2R || 1949 rtlphy->rf_type == RF_1T1R) { 1950 if (curtxbw_40mhz) { 1951 if (rssi_level == 1) 1952 ratr_bitmap &= 0x000f0000; 1953 else if (rssi_level == 2) 1954 ratr_bitmap &= 0x000ff000; 1955 else 1956 ratr_bitmap &= 0x000ff015; 1957 } else { 1958 if (rssi_level == 1) 1959 ratr_bitmap &= 0x000f0000; 1960 else if (rssi_level == 2) 1961 ratr_bitmap &= 0x000ff000; 1962 else 1963 ratr_bitmap &= 0x000ff005; 1964 } 1965 } else { 1966 if (curtxbw_40mhz) { 1967 if (rssi_level == 1) 1968 ratr_bitmap &= 0x0f0f0000; 1969 else if (rssi_level == 2) 1970 ratr_bitmap &= 0x0f0ff000; 1971 else 1972 ratr_bitmap &= 0x0f0ff015; 1973 } else { 1974 if (rssi_level == 1) 1975 ratr_bitmap &= 0x0f0f0000; 1976 else if (rssi_level == 2) 1977 ratr_bitmap &= 0x0f0ff000; 1978 else 1979 ratr_bitmap &= 0x0f0ff005; 1980 } 1981 } 1982 1983 if ((curtxbw_40mhz && curshortgi_40mhz) || 1984 (!curtxbw_40mhz && curshortgi_20mhz)) { 1985 1986 if (macid == 0) 1987 shortgi = true; 1988 else if (macid == 1) 1989 shortgi = false; 1990 } 1991 break; 1992 default: 1993 ratr_index = RATR_INX_WIRELESS_NGB; 1994 1995 if (rtlphy->rf_type == RF_1T2R) 1996 ratr_bitmap &= 0x000ff0ff; 1997 else 1998 ratr_bitmap &= 0x0f0ff0ff; 1999 break; 2000 } 2001 sta_entry->ratr_index = ratr_index; 2002 2003 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2004 "ratr_bitmap :%x\n", ratr_bitmap); 2005 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 2006 (ratr_index << 28); 2007 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; 2008 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 2009 "Rate_index:%x, ratr_val:%x, %5phC\n", 2010 ratr_index, ratr_bitmap, rate_mask); 2011 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask); 2012 } 2013 2014 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw, 2015 struct ieee80211_sta *sta, u8 rssi_level) 2016 { 2017 struct rtl_priv *rtlpriv = rtl_priv(hw); 2018 2019 if (rtlpriv->dm.useramask) 2020 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level); 2021 else 2022 rtl92ce_update_hal_rate_table(hw, sta); 2023 } 2024 2025 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw) 2026 { 2027 struct rtl_priv *rtlpriv = rtl_priv(hw); 2028 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2029 u16 sifs_timer; 2030 2031 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2032 &mac->slot_time); 2033 if (!mac->ht_enable) 2034 sifs_timer = 0x0a0a; 2035 else 2036 sifs_timer = 0x1010; 2037 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2038 } 2039 2040 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2041 { 2042 struct rtl_priv *rtlpriv = rtl_priv(hw); 2043 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2044 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2045 enum rf_pwrstate e_rfpowerstate_toset; 2046 u8 u1tmp; 2047 bool actuallyset = false; 2048 unsigned long flag; 2049 2050 if (rtlpci->being_init_adapter) 2051 return false; 2052 2053 if (ppsc->swrf_processing) 2054 return false; 2055 2056 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2057 if (ppsc->rfchange_inprogress) { 2058 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2059 return false; 2060 } else { 2061 ppsc->rfchange_inprogress = true; 2062 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2063 } 2064 2065 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv, 2066 REG_MAC_PINMUX_CFG)&~(BIT(3))); 2067 2068 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); 2069 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; 2070 2071 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { 2072 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2073 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2074 2075 e_rfpowerstate_toset = ERFON; 2076 ppsc->hwradiooff = false; 2077 actuallyset = true; 2078 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) { 2079 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2080 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 2081 2082 e_rfpowerstate_toset = ERFOFF; 2083 ppsc->hwradiooff = true; 2084 actuallyset = true; 2085 } 2086 2087 if (actuallyset) { 2088 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2089 ppsc->rfchange_inprogress = false; 2090 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2091 } else { 2092 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 2093 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2094 2095 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2096 ppsc->rfchange_inprogress = false; 2097 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2098 } 2099 2100 *valid = 1; 2101 return !ppsc->hwradiooff; 2102 2103 } 2104 2105 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index, 2106 u8 *p_macaddr, bool is_group, u8 enc_algo, 2107 bool is_wepkey, bool clear_all) 2108 { 2109 struct rtl_priv *rtlpriv = rtl_priv(hw); 2110 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2111 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2112 u8 *macaddr = p_macaddr; 2113 u32 entry_id = 0; 2114 bool is_pairwise = false; 2115 2116 static u8 cam_const_addr[4][6] = { 2117 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2118 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2119 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2120 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2121 }; 2122 static u8 cam_const_broad[] = { 2123 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2124 }; 2125 2126 if (clear_all) { 2127 u8 idx = 0; 2128 u8 cam_offset = 0; 2129 u8 clear_number = 5; 2130 2131 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2132 2133 for (idx = 0; idx < clear_number; idx++) { 2134 rtl_cam_mark_invalid(hw, cam_offset + idx); 2135 rtl_cam_empty_entry(hw, cam_offset + idx); 2136 2137 if (idx < 5) { 2138 memset(rtlpriv->sec.key_buf[idx], 0, 2139 MAX_KEY_LEN); 2140 rtlpriv->sec.key_len[idx] = 0; 2141 } 2142 } 2143 2144 } else { 2145 switch (enc_algo) { 2146 case WEP40_ENCRYPTION: 2147 enc_algo = CAM_WEP40; 2148 break; 2149 case WEP104_ENCRYPTION: 2150 enc_algo = CAM_WEP104; 2151 break; 2152 case TKIP_ENCRYPTION: 2153 enc_algo = CAM_TKIP; 2154 break; 2155 case AESCCMP_ENCRYPTION: 2156 enc_algo = CAM_AES; 2157 break; 2158 default: 2159 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 2160 "switch case %#x not processed\n", enc_algo); 2161 enc_algo = CAM_TKIP; 2162 break; 2163 } 2164 2165 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2166 macaddr = cam_const_addr[key_index]; 2167 entry_id = key_index; 2168 } else { 2169 if (is_group) { 2170 macaddr = cam_const_broad; 2171 entry_id = key_index; 2172 } else { 2173 if (mac->opmode == NL80211_IFTYPE_AP || 2174 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 2175 entry_id = rtl_cam_get_free_entry(hw, 2176 p_macaddr); 2177 if (entry_id >= TOTAL_CAM_ENTRY) { 2178 RT_TRACE(rtlpriv, COMP_SEC, 2179 DBG_EMERG, 2180 "Can not find free hw security cam entry\n"); 2181 return; 2182 } 2183 } else { 2184 entry_id = CAM_PAIRWISE_KEY_POSITION; 2185 } 2186 2187 key_index = PAIRWISE_KEYIDX; 2188 is_pairwise = true; 2189 } 2190 } 2191 2192 if (rtlpriv->sec.key_len[key_index] == 0) { 2193 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2194 "delete one entry, entry_id is %d\n", 2195 entry_id); 2196 if (mac->opmode == NL80211_IFTYPE_AP || 2197 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2198 rtl_cam_del_entry(hw, p_macaddr); 2199 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2200 } else { 2201 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 2202 "The insert KEY length is %d\n", 2203 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); 2204 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 2205 "The insert KEY is %x %x\n", 2206 rtlpriv->sec.key_buf[0][0], 2207 rtlpriv->sec.key_buf[0][1]); 2208 2209 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2210 "add one entry\n"); 2211 if (is_pairwise) { 2212 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, 2213 "Pairwise Key content", 2214 rtlpriv->sec.pairwise_key, 2215 rtlpriv->sec. 2216 key_len[PAIRWISE_KEYIDX]); 2217 2218 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2219 "set Pairwise key\n"); 2220 2221 rtl_cam_add_one_entry(hw, macaddr, key_index, 2222 entry_id, enc_algo, 2223 CAM_CONFIG_NO_USEDK, 2224 rtlpriv->sec. 2225 key_buf[key_index]); 2226 } else { 2227 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2228 "set group key\n"); 2229 2230 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2231 rtl_cam_add_one_entry(hw, 2232 rtlefuse->dev_addr, 2233 PAIRWISE_KEYIDX, 2234 CAM_PAIRWISE_KEY_POSITION, 2235 enc_algo, 2236 CAM_CONFIG_NO_USEDK, 2237 rtlpriv->sec.key_buf 2238 [entry_id]); 2239 } 2240 2241 rtl_cam_add_one_entry(hw, macaddr, key_index, 2242 entry_id, enc_algo, 2243 CAM_CONFIG_NO_USEDK, 2244 rtlpriv->sec.key_buf[entry_id]); 2245 } 2246 2247 } 2248 } 2249 } 2250 2251 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw) 2252 { 2253 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 2254 2255 rtlpcipriv->bt_coexist.bt_coexistence = 2256 rtlpcipriv->bt_coexist.eeprom_bt_coexist; 2257 rtlpcipriv->bt_coexist.bt_ant_num = 2258 rtlpcipriv->bt_coexist.eeprom_bt_ant_num; 2259 rtlpcipriv->bt_coexist.bt_coexist_type = 2260 rtlpcipriv->bt_coexist.eeprom_bt_type; 2261 2262 if (rtlpcipriv->bt_coexist.reg_bt_iso == 2) 2263 rtlpcipriv->bt_coexist.bt_ant_isolation = 2264 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol; 2265 else 2266 rtlpcipriv->bt_coexist.bt_ant_isolation = 2267 rtlpcipriv->bt_coexist.reg_bt_iso; 2268 2269 rtlpcipriv->bt_coexist.bt_radio_shared_type = 2270 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared; 2271 2272 if (rtlpcipriv->bt_coexist.bt_coexistence) { 2273 2274 if (rtlpcipriv->bt_coexist.reg_bt_sco == 1) 2275 rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION; 2276 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2) 2277 rtlpcipriv->bt_coexist.bt_service = BT_SCO; 2278 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4) 2279 rtlpcipriv->bt_coexist.bt_service = BT_BUSY; 2280 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5) 2281 rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY; 2282 else 2283 rtlpcipriv->bt_coexist.bt_service = BT_IDLE; 2284 2285 rtlpcipriv->bt_coexist.bt_edca_ul = 0; 2286 rtlpcipriv->bt_coexist.bt_edca_dl = 0; 2287 rtlpcipriv->bt_coexist.bt_rssi_state = 0xff; 2288 } 2289 } 2290 2291 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 2292 bool auto_load_fail, u8 *hwinfo) 2293 { 2294 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 2295 u8 val; 2296 2297 if (!auto_load_fail) { 2298 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 2299 ((hwinfo[RF_OPTION1] & 0xe0) >> 5); 2300 val = hwinfo[RF_OPTION4]; 2301 rtlpcipriv->bt_coexist.eeprom_bt_type = ((val & 0xe) >> 1); 2302 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (val & 0x1); 2303 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4); 2304 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = 2305 ((val & 0x20) >> 5); 2306 } else { 2307 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0; 2308 rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE; 2309 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2; 2310 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = 0; 2311 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED; 2312 } 2313 2314 rtl8192ce_bt_var_init(hw); 2315 } 2316 2317 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw) 2318 { 2319 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 2320 2321 /* 0:Low, 1:High, 2:From Efuse. */ 2322 rtlpcipriv->bt_coexist.reg_bt_iso = 2; 2323 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 2324 rtlpcipriv->bt_coexist.reg_bt_sco = 3; 2325 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 2326 rtlpcipriv->bt_coexist.reg_bt_sco = 0; 2327 } 2328 2329 2330 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw) 2331 { 2332 struct rtl_priv *rtlpriv = rtl_priv(hw); 2333 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2334 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 2335 2336 u8 u1_tmp; 2337 2338 if (rtlpcipriv->bt_coexist.bt_coexistence && 2339 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) || 2340 rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) { 2341 2342 if (rtlpcipriv->bt_coexist.bt_ant_isolation) 2343 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0); 2344 2345 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) & 2346 BIT_OFFSET_LEN_MASK_32(0, 1); 2347 u1_tmp = u1_tmp | 2348 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ? 2349 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) | 2350 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ? 2351 0 : BIT_OFFSET_LEN_MASK_32(2, 1)); 2352 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp); 2353 2354 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa); 2355 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040); 2356 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010); 2357 2358 /* Config to 1T1R. */ 2359 if (rtlphy->rf_type == RF_1T1R) { 2360 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE); 2361 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1)); 2362 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp); 2363 2364 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE); 2365 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1)); 2366 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp); 2367 } 2368 } 2369 } 2370 2371 void rtl92ce_suspend(struct ieee80211_hw *hw) 2372 { 2373 } 2374 2375 void rtl92ce_resume(struct ieee80211_hw *hw) 2376 { 2377 } 2378