1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #include "../wifi.h" 27 #include "../efuse.h" 28 #include "../base.h" 29 #include "../regd.h" 30 #include "../cam.h" 31 #include "../ps.h" 32 #include "../pci.h" 33 #include "reg.h" 34 #include "def.h" 35 #include "phy.h" 36 #include "../rtl8192c/dm_common.h" 37 #include "../rtl8192c/fw_common.h" 38 #include "../rtl8192c/phy_common.h" 39 #include "dm.h" 40 #include "led.h" 41 #include "hw.h" 42 43 #define LLT_CONFIG 5 44 45 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw, 46 u8 set_bits, u8 clear_bits) 47 { 48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 49 struct rtl_priv *rtlpriv = rtl_priv(hw); 50 51 rtlpci->reg_bcn_ctrl_val |= set_bits; 52 rtlpci->reg_bcn_ctrl_val &= ~clear_bits; 53 54 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); 55 } 56 57 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw) 58 { 59 struct rtl_priv *rtlpriv = rtl_priv(hw); 60 u8 tmp1byte; 61 62 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 63 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); 64 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); 65 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 66 tmp1byte &= ~(BIT(0)); 67 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 68 } 69 70 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw) 71 { 72 struct rtl_priv *rtlpriv = rtl_priv(hw); 73 u8 tmp1byte; 74 75 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); 76 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); 77 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 78 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); 79 tmp1byte |= BIT(0); 80 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); 81 } 82 83 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw) 84 { 85 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1)); 86 } 87 88 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw) 89 { 90 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0); 91 } 92 93 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 94 { 95 struct rtl_priv *rtlpriv = rtl_priv(hw); 96 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 97 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 98 99 switch (variable) { 100 case HW_VAR_RCR: 101 *((u32 *) (val)) = rtlpci->receive_config; 102 break; 103 case HW_VAR_RF_STATE: 104 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; 105 break; 106 case HW_VAR_FWLPS_RF_ON:{ 107 enum rf_pwrstate rfState; 108 u32 val_rcr; 109 110 rtlpriv->cfg->ops->get_hw_reg(hw, 111 HW_VAR_RF_STATE, 112 (u8 *) (&rfState)); 113 if (rfState == ERFOFF) { 114 *((bool *) (val)) = true; 115 } else { 116 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); 117 val_rcr &= 0x00070000; 118 if (val_rcr) 119 *((bool *) (val)) = false; 120 else 121 *((bool *) (val)) = true; 122 } 123 break; 124 } 125 case HW_VAR_FW_PSMODE_STATUS: 126 *((bool *) (val)) = ppsc->fw_current_inpsmode; 127 break; 128 case HW_VAR_CORRECT_TSF:{ 129 u64 tsf; 130 u32 *ptsf_low = (u32 *)&tsf; 131 u32 *ptsf_high = ((u32 *)&tsf) + 1; 132 133 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); 134 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); 135 136 *((u64 *) (val)) = tsf; 137 138 break; 139 } 140 case HAL_DEF_WOWLAN: 141 break; 142 default: 143 pr_err("switch case %#x not processed\n", variable); 144 break; 145 } 146 } 147 148 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) 149 { 150 struct rtl_priv *rtlpriv = rtl_priv(hw); 151 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 152 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 153 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 154 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 155 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 156 u8 idx; 157 158 switch (variable) { 159 case HW_VAR_ETHER_ADDR:{ 160 for (idx = 0; idx < ETH_ALEN; idx++) { 161 rtl_write_byte(rtlpriv, (REG_MACID + idx), 162 val[idx]); 163 } 164 break; 165 } 166 case HW_VAR_BASIC_RATE:{ 167 u16 rate_cfg = ((u16 *) val)[0]; 168 u8 rate_index = 0; 169 rate_cfg &= 0x15f; 170 rate_cfg |= 0x01; 171 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); 172 rtl_write_byte(rtlpriv, REG_RRSR + 1, 173 (rate_cfg >> 8) & 0xff); 174 while (rate_cfg > 0x1) { 175 rate_cfg = (rate_cfg >> 1); 176 rate_index++; 177 } 178 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 179 rate_index); 180 break; 181 } 182 case HW_VAR_BSSID:{ 183 for (idx = 0; idx < ETH_ALEN; idx++) { 184 rtl_write_byte(rtlpriv, (REG_BSSID + idx), 185 val[idx]); 186 } 187 break; 188 } 189 case HW_VAR_SIFS:{ 190 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); 191 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); 192 193 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); 194 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); 195 196 if (!mac->ht_enable) 197 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 198 0x0e0e); 199 else 200 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 201 *((u16 *) val)); 202 break; 203 } 204 case HW_VAR_SLOT_TIME:{ 205 u8 e_aci; 206 207 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 208 "HW_VAR_SLOT_TIME %x\n", val[0]); 209 210 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); 211 212 for (e_aci = 0; e_aci < AC_MAX; e_aci++) { 213 rtlpriv->cfg->ops->set_hw_reg(hw, 214 HW_VAR_AC_PARAM, 215 &e_aci); 216 } 217 break; 218 } 219 case HW_VAR_ACK_PREAMBLE:{ 220 u8 reg_tmp; 221 u8 short_preamble = (bool)*val; 222 reg_tmp = (mac->cur_40_prime_sc) << 5; 223 if (short_preamble) 224 reg_tmp |= 0x80; 225 226 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); 227 break; 228 } 229 case HW_VAR_AMPDU_MIN_SPACE:{ 230 u8 min_spacing_to_set; 231 u8 sec_min_space; 232 233 min_spacing_to_set = *val; 234 if (min_spacing_to_set <= 7) { 235 sec_min_space = 0; 236 237 if (min_spacing_to_set < sec_min_space) 238 min_spacing_to_set = sec_min_space; 239 240 mac->min_space_cfg = ((mac->min_space_cfg & 241 0xf8) | 242 min_spacing_to_set); 243 244 *val = min_spacing_to_set; 245 246 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 247 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", 248 mac->min_space_cfg); 249 250 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 251 mac->min_space_cfg); 252 } 253 break; 254 } 255 case HW_VAR_SHORTGI_DENSITY:{ 256 u8 density_to_set; 257 258 density_to_set = *val; 259 mac->min_space_cfg |= (density_to_set << 3); 260 261 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 262 "Set HW_VAR_SHORTGI_DENSITY: %#x\n", 263 mac->min_space_cfg); 264 265 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 266 mac->min_space_cfg); 267 268 break; 269 } 270 case HW_VAR_AMPDU_FACTOR:{ 271 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; 272 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97}; 273 274 u8 factor_toset; 275 u8 *p_regtoset = NULL; 276 u8 index = 0; 277 278 if ((rtlpriv->btcoexist.bt_coexistence) && 279 (rtlpriv->btcoexist.bt_coexist_type == 280 BT_CSR_BC4)) 281 p_regtoset = regtoset_bt; 282 else 283 p_regtoset = regtoset_normal; 284 285 factor_toset = *(val); 286 if (factor_toset <= 3) { 287 factor_toset = (1 << (factor_toset + 2)); 288 if (factor_toset > 0xf) 289 factor_toset = 0xf; 290 291 for (index = 0; index < 4; index++) { 292 if ((p_regtoset[index] & 0xf0) > 293 (factor_toset << 4)) 294 p_regtoset[index] = 295 (p_regtoset[index] & 0x0f) | 296 (factor_toset << 4); 297 298 if ((p_regtoset[index] & 0x0f) > 299 factor_toset) 300 p_regtoset[index] = 301 (p_regtoset[index] & 0xf0) | 302 (factor_toset); 303 304 rtl_write_byte(rtlpriv, 305 (REG_AGGLEN_LMT + index), 306 p_regtoset[index]); 307 308 } 309 310 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 311 "Set HW_VAR_AMPDU_FACTOR: %#x\n", 312 factor_toset); 313 } 314 break; 315 } 316 case HW_VAR_AC_PARAM:{ 317 u8 e_aci = *(val); 318 rtl92c_dm_init_edca_turbo(hw); 319 320 if (rtlpci->acm_method != EACMWAY2_SW) 321 rtlpriv->cfg->ops->set_hw_reg(hw, 322 HW_VAR_ACM_CTRL, 323 (&e_aci)); 324 break; 325 } 326 case HW_VAR_ACM_CTRL:{ 327 u8 e_aci = *(val); 328 union aci_aifsn *p_aci_aifsn = 329 (union aci_aifsn *)(&(mac->ac[0].aifs)); 330 u8 acm = p_aci_aifsn->f.acm; 331 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); 332 333 acm_ctrl = 334 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); 335 336 if (acm) { 337 switch (e_aci) { 338 case AC0_BE: 339 acm_ctrl |= AcmHw_BeqEn; 340 break; 341 case AC2_VI: 342 acm_ctrl |= AcmHw_ViqEn; 343 break; 344 case AC3_VO: 345 acm_ctrl |= AcmHw_VoqEn; 346 break; 347 default: 348 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 349 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", 350 acm); 351 break; 352 } 353 } else { 354 switch (e_aci) { 355 case AC0_BE: 356 acm_ctrl &= (~AcmHw_BeqEn); 357 break; 358 case AC2_VI: 359 acm_ctrl &= (~AcmHw_ViqEn); 360 break; 361 case AC3_VO: 362 acm_ctrl &= (~AcmHw_VoqEn); 363 break; 364 default: 365 pr_err("switch case %#x not processed\n", 366 e_aci); 367 break; 368 } 369 } 370 371 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, 372 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", 373 acm_ctrl); 374 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); 375 break; 376 } 377 case HW_VAR_RCR:{ 378 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); 379 rtlpci->receive_config = ((u32 *) (val))[0]; 380 break; 381 } 382 case HW_VAR_RETRY_LIMIT:{ 383 u8 retry_limit = val[0]; 384 385 rtl_write_word(rtlpriv, REG_RL, 386 retry_limit << RETRY_LIMIT_SHORT_SHIFT | 387 retry_limit << RETRY_LIMIT_LONG_SHIFT); 388 break; 389 } 390 case HW_VAR_DUAL_TSF_RST: 391 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); 392 break; 393 case HW_VAR_EFUSE_BYTES: 394 rtlefuse->efuse_usedbytes = *((u16 *) val); 395 break; 396 case HW_VAR_EFUSE_USAGE: 397 rtlefuse->efuse_usedpercentage = *val; 398 break; 399 case HW_VAR_IO_CMD: 400 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val)); 401 break; 402 case HW_VAR_WPA_CONFIG: 403 rtl_write_byte(rtlpriv, REG_SECCFG, *val); 404 break; 405 case HW_VAR_SET_RPWM:{ 406 u8 rpwm_val; 407 408 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); 409 udelay(1); 410 411 if (rpwm_val & BIT(7)) { 412 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val); 413 } else { 414 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, 415 *val | BIT(7)); 416 } 417 418 break; 419 } 420 case HW_VAR_H2C_FW_PWRMODE:{ 421 u8 psmode = *val; 422 423 if ((psmode != FW_PS_ACTIVE_MODE) && 424 (!IS_92C_SERIAL(rtlhal->version))) { 425 rtl92c_dm_rf_saving(hw, true); 426 } 427 428 rtl92c_set_fw_pwrmode_cmd(hw, *val); 429 break; 430 } 431 case HW_VAR_FW_PSMODE_STATUS: 432 ppsc->fw_current_inpsmode = *((bool *) val); 433 break; 434 case HW_VAR_H2C_FW_JOINBSSRPT:{ 435 u8 mstatus = *val; 436 u8 tmp_regcr, tmp_reg422; 437 bool recover = false; 438 439 if (mstatus == RT_MEDIA_CONNECT) { 440 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, 441 NULL); 442 443 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); 444 rtl_write_byte(rtlpriv, REG_CR + 1, 445 (tmp_regcr | BIT(0))); 446 447 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); 448 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0); 449 450 tmp_reg422 = 451 rtl_read_byte(rtlpriv, 452 REG_FWHW_TXQ_CTRL + 2); 453 if (tmp_reg422 & BIT(6)) 454 recover = true; 455 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 456 tmp_reg422 & (~BIT(6))); 457 458 rtl92c_set_fw_rsvdpagepkt(hw, NULL); 459 460 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); 461 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); 462 463 if (recover) { 464 rtl_write_byte(rtlpriv, 465 REG_FWHW_TXQ_CTRL + 2, 466 tmp_reg422); 467 } 468 469 rtl_write_byte(rtlpriv, REG_CR + 1, 470 (tmp_regcr & ~(BIT(0)))); 471 } 472 rtl92c_set_fw_joinbss_report_cmd(hw, *val); 473 474 break; 475 } 476 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: 477 rtl92c_set_p2p_ps_offload_cmd(hw, *val); 478 break; 479 case HW_VAR_AID:{ 480 u16 u2btmp; 481 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); 482 u2btmp &= 0xC000; 483 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | 484 mac->assoc_id)); 485 486 break; 487 } 488 case HW_VAR_CORRECT_TSF:{ 489 u8 btype_ibss = val[0]; 490 491 if (btype_ibss) 492 _rtl92ce_stop_tx_beacon(hw); 493 494 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); 495 496 rtl_write_dword(rtlpriv, REG_TSFTR, 497 (u32) (mac->tsf & 0xffffffff)); 498 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 499 (u32) ((mac->tsf >> 32) & 0xffffffff)); 500 501 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); 502 503 if (btype_ibss) 504 _rtl92ce_resume_tx_beacon(hw); 505 506 break; 507 508 } 509 case HW_VAR_FW_LPS_ACTION: { 510 bool enter_fwlps = *((bool *)val); 511 u8 rpwm_val, fw_pwrmode; 512 bool fw_current_inps; 513 514 if (enter_fwlps) { 515 rpwm_val = 0x02; /* RF off */ 516 fw_current_inps = true; 517 rtlpriv->cfg->ops->set_hw_reg(hw, 518 HW_VAR_FW_PSMODE_STATUS, 519 (u8 *)(&fw_current_inps)); 520 rtlpriv->cfg->ops->set_hw_reg(hw, 521 HW_VAR_H2C_FW_PWRMODE, 522 &ppsc->fwctrl_psmode); 523 524 rtlpriv->cfg->ops->set_hw_reg(hw, 525 HW_VAR_SET_RPWM, 526 &rpwm_val); 527 } else { 528 rpwm_val = 0x0C; /* RF on */ 529 fw_pwrmode = FW_PS_ACTIVE_MODE; 530 fw_current_inps = false; 531 rtlpriv->cfg->ops->set_hw_reg(hw, 532 HW_VAR_SET_RPWM, 533 &rpwm_val); 534 rtlpriv->cfg->ops->set_hw_reg(hw, 535 HW_VAR_H2C_FW_PWRMODE, 536 &fw_pwrmode); 537 538 rtlpriv->cfg->ops->set_hw_reg(hw, 539 HW_VAR_FW_PSMODE_STATUS, 540 (u8 *)(&fw_current_inps)); 541 } 542 break; } 543 case HW_VAR_KEEP_ALIVE: { 544 u8 array[2]; 545 546 array[0] = 0xff; 547 array[1] = *((u8 *)val); 548 rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2, array); 549 break; } 550 default: 551 pr_err("switch case %d not processed\n", variable); 552 break; 553 } 554 } 555 556 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) 557 { 558 struct rtl_priv *rtlpriv = rtl_priv(hw); 559 bool status = true; 560 long count = 0; 561 u32 value = _LLT_INIT_ADDR(address) | 562 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); 563 564 rtl_write_dword(rtlpriv, REG_LLT_INIT, value); 565 566 do { 567 value = rtl_read_dword(rtlpriv, REG_LLT_INIT); 568 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) 569 break; 570 571 if (count > POLLING_LLT_THRESHOLD) { 572 pr_err("Failed to polling write LLT done at address %d!\n", 573 address); 574 status = false; 575 break; 576 } 577 } while (++count); 578 579 return status; 580 } 581 582 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw) 583 { 584 struct rtl_priv *rtlpriv = rtl_priv(hw); 585 unsigned short i; 586 u8 txpktbuf_bndy; 587 u8 maxPage; 588 bool status; 589 590 #if LLT_CONFIG == 1 591 maxPage = 255; 592 txpktbuf_bndy = 252; 593 #elif LLT_CONFIG == 2 594 maxPage = 127; 595 txpktbuf_bndy = 124; 596 #elif LLT_CONFIG == 3 597 maxPage = 255; 598 txpktbuf_bndy = 174; 599 #elif LLT_CONFIG == 4 600 maxPage = 255; 601 txpktbuf_bndy = 246; 602 #elif LLT_CONFIG == 5 603 maxPage = 255; 604 txpktbuf_bndy = 246; 605 #endif 606 607 #if LLT_CONFIG == 1 608 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c); 609 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c); 610 #elif LLT_CONFIG == 2 611 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010); 612 #elif LLT_CONFIG == 3 613 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484); 614 #elif LLT_CONFIG == 4 615 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c); 616 #elif LLT_CONFIG == 5 617 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000); 618 619 rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29); 620 #endif 621 622 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy)); 623 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); 624 625 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); 626 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); 627 628 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); 629 rtl_write_byte(rtlpriv, REG_PBP, 0x11); 630 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); 631 632 for (i = 0; i < (txpktbuf_bndy - 1); i++) { 633 status = _rtl92ce_llt_write(hw, i, i + 1); 634 if (true != status) 635 return status; 636 } 637 638 status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); 639 if (true != status) 640 return status; 641 642 for (i = txpktbuf_bndy; i < maxPage; i++) { 643 status = _rtl92ce_llt_write(hw, i, (i + 1)); 644 if (true != status) 645 return status; 646 } 647 648 status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy); 649 if (true != status) 650 return status; 651 652 return true; 653 } 654 655 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw) 656 { 657 struct rtl_priv *rtlpriv = rtl_priv(hw); 658 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 659 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 660 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0; 661 662 if (rtlpci->up_first_time) 663 return; 664 665 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) 666 rtl92ce_sw_led_on(hw, pled0); 667 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) 668 rtl92ce_sw_led_on(hw, pled0); 669 else 670 rtl92ce_sw_led_off(hw, pled0); 671 } 672 673 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw) 674 { 675 struct rtl_priv *rtlpriv = rtl_priv(hw); 676 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 677 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 678 679 unsigned char bytetmp; 680 unsigned short wordtmp; 681 u16 retry; 682 683 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); 684 if (rtlpriv->btcoexist.bt_coexistence) { 685 u32 value32; 686 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO); 687 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK); 688 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32); 689 } 690 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); 691 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F); 692 693 if (rtlpriv->btcoexist.bt_coexistence) { 694 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL); 695 696 u4b_tmp &= (~0x00024800); 697 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp); 698 } 699 700 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0); 701 udelay(2); 702 703 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); 704 udelay(2); 705 706 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); 707 udelay(2); 708 709 retry = 0; 710 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n", 711 rtl_read_dword(rtlpriv, 0xEC), bytetmp); 712 713 while ((bytetmp & BIT(0)) && retry < 1000) { 714 retry++; 715 udelay(50); 716 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); 717 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n", 718 rtl_read_dword(rtlpriv, 0xEC), bytetmp); 719 udelay(50); 720 } 721 722 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012); 723 724 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82); 725 udelay(2); 726 727 if (rtlpriv->btcoexist.bt_coexistence) { 728 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd; 729 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp); 730 } 731 732 rtl_write_word(rtlpriv, REG_CR, 0x2ff); 733 734 if (!_rtl92ce_llt_table_init(hw)) 735 return false; 736 737 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); 738 rtl_write_byte(rtlpriv, REG_HISRE, 0xff); 739 740 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff); 741 742 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); 743 wordtmp &= 0xf; 744 wordtmp |= 0xF771; 745 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); 746 747 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); 748 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 749 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); 750 751 rtl_write_byte(rtlpriv, 0x4d0, 0x0); 752 753 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, 754 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) & 755 DMA_BIT_MASK(32)); 756 rtl_write_dword(rtlpriv, REG_MGQ_DESA, 757 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma & 758 DMA_BIT_MASK(32)); 759 rtl_write_dword(rtlpriv, REG_VOQ_DESA, 760 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); 761 rtl_write_dword(rtlpriv, REG_VIQ_DESA, 762 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); 763 rtl_write_dword(rtlpriv, REG_BEQ_DESA, 764 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); 765 rtl_write_dword(rtlpriv, REG_BKQ_DESA, 766 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); 767 rtl_write_dword(rtlpriv, REG_HQ_DESA, 768 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma & 769 DMA_BIT_MASK(32)); 770 rtl_write_dword(rtlpriv, REG_RX_DESA, 771 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma & 772 DMA_BIT_MASK(32)); 773 774 if (IS_92C_SERIAL(rtlhal->version)) 775 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77); 776 else 777 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22); 778 779 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); 780 781 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 782 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); 783 do { 784 retry++; 785 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); 786 } while ((retry < 200) && (bytetmp & BIT(7))); 787 788 _rtl92ce_gen_refresh_led_state(hw); 789 790 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); 791 792 return true; 793 } 794 795 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw) 796 { 797 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 798 struct rtl_priv *rtlpriv = rtl_priv(hw); 799 u8 reg_bw_opmode; 800 u32 reg_prsr; 801 802 reg_bw_opmode = BW_OPMODE_20MHZ; 803 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 804 805 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); 806 807 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); 808 809 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr); 810 811 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); 812 813 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); 814 815 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); 816 817 rtl_write_word(rtlpriv, REG_RL, 0x0707); 818 819 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); 820 821 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); 822 823 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); 824 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); 825 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); 826 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); 827 828 if ((rtlpriv->btcoexist.bt_coexistence) && 829 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) 830 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431); 831 else 832 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); 833 834 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); 835 836 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); 837 838 rtlpci->reg_bcn_ctrl_val = 0x1f; 839 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); 840 841 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 842 843 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); 844 845 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); 846 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); 847 848 if ((rtlpriv->btcoexist.bt_coexistence) && 849 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) { 850 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 851 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402); 852 } else { 853 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 854 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); 855 } 856 857 if ((rtlpriv->btcoexist.bt_coexistence) && 858 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) 859 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); 860 else 861 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666); 862 863 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); 864 865 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); 866 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); 867 868 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); 869 870 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); 871 872 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); 873 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); 874 875 } 876 877 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw) 878 { 879 struct rtl_priv *rtlpriv = rtl_priv(hw); 880 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 881 882 rtl_write_byte(rtlpriv, 0x34b, 0x93); 883 rtl_write_word(rtlpriv, 0x350, 0x870c); 884 rtl_write_byte(rtlpriv, 0x352, 0x1); 885 886 if (ppsc->support_backdoor) 887 rtl_write_byte(rtlpriv, 0x349, 0x1b); 888 else 889 rtl_write_byte(rtlpriv, 0x349, 0x03); 890 891 rtl_write_word(rtlpriv, 0x350, 0x2718); 892 rtl_write_byte(rtlpriv, 0x352, 0x1); 893 } 894 895 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw) 896 { 897 struct rtl_priv *rtlpriv = rtl_priv(hw); 898 u8 sec_reg_value; 899 900 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 901 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", 902 rtlpriv->sec.pairwise_enc_algorithm, 903 rtlpriv->sec.group_enc_algorithm); 904 905 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { 906 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 907 "not open hw encryption\n"); 908 return; 909 } 910 911 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable; 912 913 if (rtlpriv->sec.use_defaultkey) { 914 sec_reg_value |= SCR_TxUseDK; 915 sec_reg_value |= SCR_RxUseDK; 916 } 917 918 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); 919 920 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); 921 922 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 923 "The SECR-value %x\n", sec_reg_value); 924 925 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); 926 927 } 928 929 int rtl92ce_hw_init(struct ieee80211_hw *hw) 930 { 931 struct rtl_priv *rtlpriv = rtl_priv(hw); 932 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 933 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 934 struct rtl_phy *rtlphy = &(rtlpriv->phy); 935 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 936 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 937 bool rtstatus = true; 938 bool is92c; 939 int err; 940 u8 tmp_u1b; 941 unsigned long flags; 942 943 rtlpci->being_init_adapter = true; 944 945 /* Since this function can take a very long time (up to 350 ms) 946 * and can be called with irqs disabled, reenable the irqs 947 * to let the other devices continue being serviced. 948 * 949 * It is safe doing so since our own interrupts will only be enabled 950 * in a subsequent step. 951 */ 952 local_save_flags(flags); 953 local_irq_enable(); 954 955 rtlhal->fw_ready = false; 956 rtlpriv->intf_ops->disable_aspm(hw); 957 rtstatus = _rtl92ce_init_mac(hw); 958 if (!rtstatus) { 959 pr_err("Init MAC failed\n"); 960 err = 1; 961 goto exit; 962 } 963 964 err = rtl92c_download_fw(hw); 965 if (err) { 966 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 967 "Failed to download FW. Init HW without FW now..\n"); 968 err = 1; 969 goto exit; 970 } 971 972 rtlhal->fw_ready = true; 973 rtlhal->last_hmeboxnum = 0; 974 rtl92c_phy_mac_config(hw); 975 /* because last function modify RCR, so we update 976 * rcr var here, or TP will unstable for receive_config 977 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx 978 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/ 979 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); 980 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); 981 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); 982 rtl92c_phy_bb_config(hw); 983 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 984 rtl92c_phy_rf_config(hw); 985 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) && 986 !IS_92C_SERIAL(rtlhal->version)) { 987 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); 988 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); 989 } else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) { 990 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE); 991 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31); 992 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425); 993 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200); 994 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053); 995 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201); 996 } 997 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 998 RF_CHNLBW, RFREG_OFFSET_MASK); 999 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, 1000 RF_CHNLBW, RFREG_OFFSET_MASK); 1001 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); 1002 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); 1003 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); 1004 _rtl92ce_hw_configure(hw); 1005 rtl_cam_reset_all_entry(hw); 1006 rtl92ce_enable_hw_security_config(hw); 1007 1008 ppsc->rfpwr_state = ERFON; 1009 1010 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); 1011 _rtl92ce_enable_aspm_back_door(hw); 1012 rtlpriv->intf_ops->enable_aspm(hw); 1013 1014 rtl8192ce_bt_hw_init(hw); 1015 1016 if (ppsc->rfpwr_state == ERFON) { 1017 rtl92c_phy_set_rfpath_switch(hw, 1); 1018 if (rtlphy->iqk_initialized) { 1019 rtl92c_phy_iq_calibrate(hw, true); 1020 } else { 1021 rtl92c_phy_iq_calibrate(hw, false); 1022 rtlphy->iqk_initialized = true; 1023 } 1024 1025 rtl92c_dm_check_txpower_tracking(hw); 1026 rtl92c_phy_lc_calibrate(hw); 1027 } 1028 1029 is92c = IS_92C_SERIAL(rtlhal->version); 1030 tmp_u1b = efuse_read_1byte(hw, 0x1FA); 1031 if (!(tmp_u1b & BIT(0))) { 1032 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); 1033 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n"); 1034 } 1035 1036 if (!(tmp_u1b & BIT(1)) && is92c) { 1037 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05); 1038 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n"); 1039 } 1040 1041 if (!(tmp_u1b & BIT(4))) { 1042 tmp_u1b = rtl_read_byte(rtlpriv, 0x16); 1043 tmp_u1b &= 0x0F; 1044 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80); 1045 udelay(10); 1046 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90); 1047 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n"); 1048 } 1049 rtl92c_dm_init(hw); 1050 exit: 1051 local_irq_restore(flags); 1052 rtlpci->being_init_adapter = false; 1053 return err; 1054 } 1055 1056 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw) 1057 { 1058 struct rtl_priv *rtlpriv = rtl_priv(hw); 1059 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1060 enum version_8192c version = VERSION_UNKNOWN; 1061 u32 value32; 1062 const char *versionid; 1063 1064 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); 1065 if (value32 & TRP_VAUX_EN) { 1066 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C : 1067 VERSION_A_CHIP_88C; 1068 } else { 1069 version = (enum version_8192c) (CHIP_VER_B | 1070 ((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) | 1071 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); 1072 if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 & 1073 CHIP_VER_RTL_MASK)) { 1074 version = (enum version_8192c)(version | 1075 ((((value32 & CHIP_VER_RTL_MASK) == BIT(12)) 1076 ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) | 1077 CHIP_VENDOR_UMC)); 1078 } 1079 if (IS_92C_SERIAL(version)) { 1080 value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM); 1081 version = (enum version_8192c)(version | 1082 ((CHIP_BONDING_IDENTIFIER(value32) 1083 == CHIP_BONDING_92C_1T2R) ? 1084 RF_TYPE_1T2R : 0)); 1085 } 1086 } 1087 1088 switch (version) { 1089 case VERSION_B_CHIP_92C: 1090 versionid = "B_CHIP_92C"; 1091 break; 1092 case VERSION_B_CHIP_88C: 1093 versionid = "B_CHIP_88C"; 1094 break; 1095 case VERSION_A_CHIP_92C: 1096 versionid = "A_CHIP_92C"; 1097 break; 1098 case VERSION_A_CHIP_88C: 1099 versionid = "A_CHIP_88C"; 1100 break; 1101 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT: 1102 versionid = "A_CUT_92C_1T2R"; 1103 break; 1104 case VERSION_NORMAL_UMC_CHIP_92C_A_CUT: 1105 versionid = "A_CUT_92C"; 1106 break; 1107 case VERSION_NORMAL_UMC_CHIP_88C_A_CUT: 1108 versionid = "A_CUT_88C"; 1109 break; 1110 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT: 1111 versionid = "B_CUT_92C_1T2R"; 1112 break; 1113 case VERSION_NORMAL_UMC_CHIP_92C_B_CUT: 1114 versionid = "B_CUT_92C"; 1115 break; 1116 case VERSION_NORMAL_UMC_CHIP_88C_B_CUT: 1117 versionid = "B_CUT_88C"; 1118 break; 1119 default: 1120 versionid = "Unknown. Bug?"; 1121 break; 1122 } 1123 1124 pr_info("Chip Version ID: %s\n", versionid); 1125 1126 switch (version & 0x3) { 1127 case CHIP_88C: 1128 rtlphy->rf_type = RF_1T1R; 1129 break; 1130 case CHIP_92C: 1131 rtlphy->rf_type = RF_2T2R; 1132 break; 1133 case CHIP_92C_1T2R: 1134 rtlphy->rf_type = RF_1T2R; 1135 break; 1136 default: 1137 rtlphy->rf_type = RF_1T1R; 1138 pr_err("ERROR RF_Type is set!!\n"); 1139 break; 1140 } 1141 1142 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n", 1143 rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R"); 1144 1145 return version; 1146 } 1147 1148 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw, 1149 enum nl80211_iftype type) 1150 { 1151 struct rtl_priv *rtlpriv = rtl_priv(hw); 1152 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1153 enum led_ctl_mode ledaction = LED_CTL_NO_LINK; 1154 u8 mode = MSR_NOLINK; 1155 1156 bt_msr &= 0xfc; 1157 1158 switch (type) { 1159 case NL80211_IFTYPE_UNSPECIFIED: 1160 mode = MSR_NOLINK; 1161 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1162 "Set Network type to NO LINK!\n"); 1163 break; 1164 case NL80211_IFTYPE_ADHOC: 1165 mode = MSR_ADHOC; 1166 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1167 "Set Network type to Ad Hoc!\n"); 1168 break; 1169 case NL80211_IFTYPE_STATION: 1170 mode = MSR_INFRA; 1171 ledaction = LED_CTL_LINK; 1172 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1173 "Set Network type to STA!\n"); 1174 break; 1175 case NL80211_IFTYPE_AP: 1176 mode = MSR_AP; 1177 ledaction = LED_CTL_LINK; 1178 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1179 "Set Network type to AP!\n"); 1180 break; 1181 case NL80211_IFTYPE_MESH_POINT: 1182 mode = MSR_ADHOC; 1183 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1184 "Set Network type to Mesh Point!\n"); 1185 break; 1186 default: 1187 pr_err("Network type %d not supported!\n", type); 1188 return 1; 1189 1190 } 1191 1192 /* MSR_INFRA == Link in infrastructure network; 1193 * MSR_ADHOC == Link in ad hoc network; 1194 * Therefore, check link state is necessary. 1195 * 1196 * MSR_AP == AP mode; link state does not matter here. 1197 */ 1198 if (mode != MSR_AP && 1199 rtlpriv->mac80211.link_state < MAC80211_LINKED) { 1200 mode = MSR_NOLINK; 1201 ledaction = LED_CTL_NO_LINK; 1202 } 1203 if (mode == MSR_NOLINK || mode == MSR_INFRA) { 1204 _rtl92ce_stop_tx_beacon(hw); 1205 _rtl92ce_enable_bcn_sub_func(hw); 1206 } else if (mode == MSR_ADHOC || mode == MSR_AP) { 1207 _rtl92ce_resume_tx_beacon(hw); 1208 _rtl92ce_disable_bcn_sub_func(hw); 1209 } else { 1210 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 1211 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n", 1212 mode); 1213 } 1214 rtl_write_byte(rtlpriv, MSR, bt_msr | mode); 1215 1216 rtlpriv->cfg->ops->led_control(hw, ledaction); 1217 if (mode == MSR_AP) 1218 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); 1219 else 1220 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); 1221 return 0; 1222 } 1223 1224 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) 1225 { 1226 struct rtl_priv *rtlpriv = rtl_priv(hw); 1227 u32 reg_rcr; 1228 1229 if (rtlpriv->psc.rfpwr_state != ERFON) 1230 return; 1231 1232 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); 1233 1234 if (check_bssid) { 1235 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1236 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1237 (u8 *) (®_rcr)); 1238 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); 1239 } else if (!check_bssid) { 1240 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); 1241 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0); 1242 rtlpriv->cfg->ops->set_hw_reg(hw, 1243 HW_VAR_RCR, (u8 *) (®_rcr)); 1244 } 1245 1246 } 1247 1248 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) 1249 { 1250 struct rtl_priv *rtlpriv = rtl_priv(hw); 1251 1252 if (_rtl92ce_set_media_status(hw, type)) 1253 return -EOPNOTSUPP; 1254 1255 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { 1256 if (type != NL80211_IFTYPE_AP && 1257 type != NL80211_IFTYPE_MESH_POINT) 1258 rtl92ce_set_check_bssid(hw, true); 1259 } else { 1260 rtl92ce_set_check_bssid(hw, false); 1261 } 1262 1263 return 0; 1264 } 1265 1266 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ 1267 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci) 1268 { 1269 struct rtl_priv *rtlpriv = rtl_priv(hw); 1270 rtl92c_dm_init_edca_turbo(hw); 1271 switch (aci) { 1272 case AC1_BK: 1273 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); 1274 break; 1275 case AC0_BE: 1276 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */ 1277 break; 1278 case AC2_VI: 1279 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); 1280 break; 1281 case AC3_VO: 1282 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); 1283 break; 1284 default: 1285 WARN_ONCE(true, "rtl8192ce: invalid aci: %d !\n", aci); 1286 break; 1287 } 1288 } 1289 1290 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw) 1291 { 1292 struct rtl_priv *rtlpriv = rtl_priv(hw); 1293 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1294 1295 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); 1296 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); 1297 rtlpci->irq_enabled = true; 1298 } 1299 1300 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw) 1301 { 1302 struct rtl_priv *rtlpriv = rtl_priv(hw); 1303 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1304 1305 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); 1306 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); 1307 rtlpci->irq_enabled = false; 1308 } 1309 1310 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw) 1311 { 1312 struct rtl_priv *rtlpriv = rtl_priv(hw); 1313 struct rtl_hal *rtlhal = rtl_hal(rtlpriv); 1314 u8 u1b_tmp; 1315 u32 u4b_tmp; 1316 1317 rtlpriv->intf_ops->enable_aspm(hw); 1318 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 1319 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); 1320 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); 1321 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 1322 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 1323 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0); 1324 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) 1325 rtl92c_firmware_selfreset(hw); 1326 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51); 1327 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1328 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000); 1329 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL); 1330 if ((rtlpriv->btcoexist.bt_coexistence) && 1331 ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) || 1332 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8))) { 1333 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 | 1334 (u1b_tmp << 8)); 1335 } else { 1336 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 | 1337 (u1b_tmp << 8)); 1338 } 1339 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790); 1340 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); 1341 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); 1342 if (!IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) 1343 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); 1344 if (rtlpriv->btcoexist.bt_coexistence) { 1345 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL); 1346 u4b_tmp |= 0x03824800; 1347 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp); 1348 } else { 1349 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e); 1350 } 1351 1352 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); 1353 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10); 1354 } 1355 1356 void rtl92ce_card_disable(struct ieee80211_hw *hw) 1357 { 1358 struct rtl_priv *rtlpriv = rtl_priv(hw); 1359 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1360 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1361 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1362 enum nl80211_iftype opmode; 1363 1364 mac->link_state = MAC80211_NOLINK; 1365 opmode = NL80211_IFTYPE_UNSPECIFIED; 1366 _rtl92ce_set_media_status(hw, opmode); 1367 if (rtlpci->driver_is_goingto_unload || 1368 ppsc->rfoff_reason > RF_CHANGE_BY_PS) 1369 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); 1370 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 1371 _rtl92ce_poweroff_adapter(hw); 1372 1373 /* after power off we should do iqk again */ 1374 rtlpriv->phy.iqk_initialized = false; 1375 } 1376 1377 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw, 1378 u32 *p_inta, u32 *p_intb, 1379 u32 *p_intc, u32 *p_intd) 1380 { 1381 struct rtl_priv *rtlpriv = rtl_priv(hw); 1382 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1383 1384 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; 1385 rtl_write_dword(rtlpriv, ISR, *p_inta); 1386 1387 /* 1388 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; 1389 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb); 1390 */ 1391 } 1392 1393 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw) 1394 { 1395 1396 struct rtl_priv *rtlpriv = rtl_priv(hw); 1397 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1398 u16 bcn_interval, atim_window; 1399 1400 bcn_interval = mac->beacon_interval; 1401 atim_window = 2; /*FIX MERGE */ 1402 rtl92ce_disable_interrupt(hw); 1403 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); 1404 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1405 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); 1406 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); 1407 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); 1408 rtl_write_byte(rtlpriv, 0x606, 0x30); 1409 rtl92ce_enable_interrupt(hw); 1410 } 1411 1412 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw) 1413 { 1414 struct rtl_priv *rtlpriv = rtl_priv(hw); 1415 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1416 u16 bcn_interval = mac->beacon_interval; 1417 1418 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, 1419 "beacon_interval:%d\n", bcn_interval); 1420 rtl92ce_disable_interrupt(hw); 1421 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); 1422 rtl92ce_enable_interrupt(hw); 1423 } 1424 1425 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw, 1426 u32 add_msr, u32 rm_msr) 1427 { 1428 struct rtl_priv *rtlpriv = rtl_priv(hw); 1429 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1430 1431 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n", 1432 add_msr, rm_msr); 1433 1434 if (add_msr) 1435 rtlpci->irq_mask[0] |= add_msr; 1436 if (rm_msr) 1437 rtlpci->irq_mask[0] &= (~rm_msr); 1438 rtl92ce_disable_interrupt(hw); 1439 rtl92ce_enable_interrupt(hw); 1440 } 1441 1442 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 1443 bool autoload_fail, 1444 u8 *hwinfo) 1445 { 1446 struct rtl_priv *rtlpriv = rtl_priv(hw); 1447 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1448 u8 rf_path, index, tempval; 1449 u16 i; 1450 1451 for (rf_path = 0; rf_path < 2; rf_path++) { 1452 for (i = 0; i < 3; i++) { 1453 if (!autoload_fail) { 1454 rtlefuse-> 1455 eeprom_chnlarea_txpwr_cck[rf_path][i] = 1456 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; 1457 rtlefuse-> 1458 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1459 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + 1460 i]; 1461 } else { 1462 rtlefuse-> 1463 eeprom_chnlarea_txpwr_cck[rf_path][i] = 1464 EEPROM_DEFAULT_TXPOWERLEVEL; 1465 rtlefuse-> 1466 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = 1467 EEPROM_DEFAULT_TXPOWERLEVEL; 1468 } 1469 } 1470 } 1471 1472 for (i = 0; i < 3; i++) { 1473 if (!autoload_fail) 1474 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i]; 1475 else 1476 tempval = EEPROM_DEFAULT_HT40_2SDIFF; 1477 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] = 1478 (tempval & 0xf); 1479 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] = 1480 ((tempval & 0xf0) >> 4); 1481 } 1482 1483 for (rf_path = 0; rf_path < 2; rf_path++) 1484 for (i = 0; i < 3; i++) 1485 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1486 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", 1487 rf_path, i, 1488 rtlefuse-> 1489 eeprom_chnlarea_txpwr_cck[rf_path][i]); 1490 for (rf_path = 0; rf_path < 2; rf_path++) 1491 for (i = 0; i < 3; i++) 1492 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1493 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", 1494 rf_path, i, 1495 rtlefuse-> 1496 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]); 1497 for (rf_path = 0; rf_path < 2; rf_path++) 1498 for (i = 0; i < 3; i++) 1499 RTPRINT(rtlpriv, FINIT, INIT_EEPROM, 1500 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", 1501 rf_path, i, 1502 rtlefuse-> 1503 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]); 1504 1505 for (rf_path = 0; rf_path < 2; rf_path++) { 1506 for (i = 0; i < 14; i++) { 1507 index = rtl92c_get_chnl_group((u8)i); 1508 1509 rtlefuse->txpwrlevel_cck[rf_path][i] = 1510 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index]; 1511 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = 1512 rtlefuse-> 1513 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index]; 1514 1515 if ((rtlefuse-> 1516 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] - 1517 rtlefuse-> 1518 eprom_chnl_txpwr_ht40_2sdf[rf_path][index]) 1519 > 0) { 1520 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 1521 rtlefuse-> 1522 eeprom_chnlarea_txpwr_ht40_1s[rf_path] 1523 [index] - 1524 rtlefuse-> 1525 eprom_chnl_txpwr_ht40_2sdf[rf_path] 1526 [index]; 1527 } else { 1528 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; 1529 } 1530 } 1531 1532 for (i = 0; i < 14; i++) { 1533 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1534 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", 1535 rf_path, i, 1536 rtlefuse->txpwrlevel_cck[rf_path][i], 1537 rtlefuse->txpwrlevel_ht40_1s[rf_path][i], 1538 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); 1539 } 1540 } 1541 1542 for (i = 0; i < 3; i++) { 1543 if (!autoload_fail) { 1544 rtlefuse->eeprom_pwrlimit_ht40[i] = 1545 hwinfo[EEPROM_TXPWR_GROUP + i]; 1546 rtlefuse->eeprom_pwrlimit_ht20[i] = 1547 hwinfo[EEPROM_TXPWR_GROUP + 3 + i]; 1548 } else { 1549 rtlefuse->eeprom_pwrlimit_ht40[i] = 0; 1550 rtlefuse->eeprom_pwrlimit_ht20[i] = 0; 1551 } 1552 } 1553 1554 for (rf_path = 0; rf_path < 2; rf_path++) { 1555 for (i = 0; i < 14; i++) { 1556 index = rtl92c_get_chnl_group((u8)i); 1557 1558 if (rf_path == RF90_PATH_A) { 1559 rtlefuse->pwrgroup_ht20[rf_path][i] = 1560 (rtlefuse->eeprom_pwrlimit_ht20[index] 1561 & 0xf); 1562 rtlefuse->pwrgroup_ht40[rf_path][i] = 1563 (rtlefuse->eeprom_pwrlimit_ht40[index] 1564 & 0xf); 1565 } else if (rf_path == RF90_PATH_B) { 1566 rtlefuse->pwrgroup_ht20[rf_path][i] = 1567 ((rtlefuse->eeprom_pwrlimit_ht20[index] 1568 & 0xf0) >> 4); 1569 rtlefuse->pwrgroup_ht40[rf_path][i] = 1570 ((rtlefuse->eeprom_pwrlimit_ht40[index] 1571 & 0xf0) >> 4); 1572 } 1573 1574 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1575 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", 1576 rf_path, i, 1577 rtlefuse->pwrgroup_ht20[rf_path][i]); 1578 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1579 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", 1580 rf_path, i, 1581 rtlefuse->pwrgroup_ht40[rf_path][i]); 1582 } 1583 } 1584 1585 for (i = 0; i < 14; i++) { 1586 index = rtl92c_get_chnl_group((u8)i); 1587 1588 if (!autoload_fail) 1589 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; 1590 else 1591 tempval = EEPROM_DEFAULT_HT20_DIFF; 1592 1593 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); 1594 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = 1595 ((tempval >> 4) & 0xF); 1596 1597 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) 1598 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; 1599 1600 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) 1601 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; 1602 1603 index = rtl92c_get_chnl_group((u8)i); 1604 1605 if (!autoload_fail) 1606 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; 1607 else 1608 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; 1609 1610 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); 1611 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = 1612 ((tempval >> 4) & 0xF); 1613 } 1614 1615 rtlefuse->legacy_ht_txpowerdiff = 1616 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; 1617 1618 for (i = 0; i < 14; i++) 1619 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1620 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", 1621 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); 1622 for (i = 0; i < 14; i++) 1623 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1624 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", 1625 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); 1626 for (i = 0; i < 14; i++) 1627 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1628 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", 1629 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); 1630 for (i = 0; i < 14; i++) 1631 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1632 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", 1633 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); 1634 1635 if (!autoload_fail) 1636 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); 1637 else 1638 rtlefuse->eeprom_regulatory = 0; 1639 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1640 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); 1641 1642 if (!autoload_fail) { 1643 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; 1644 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B]; 1645 } else { 1646 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; 1647 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI; 1648 } 1649 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n", 1650 rtlefuse->eeprom_tssi[RF90_PATH_A], 1651 rtlefuse->eeprom_tssi[RF90_PATH_B]); 1652 1653 if (!autoload_fail) 1654 tempval = hwinfo[EEPROM_THERMAL_METER]; 1655 else 1656 tempval = EEPROM_DEFAULT_THERMALMETER; 1657 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); 1658 1659 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) 1660 rtlefuse->apk_thermalmeterignore = true; 1661 1662 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 1663 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, 1664 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); 1665 } 1666 1667 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw) 1668 { 1669 struct rtl_priv *rtlpriv = rtl_priv(hw); 1670 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1671 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1672 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, 1673 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR, 1674 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, 1675 COUNTRY_CODE_WORLD_WIDE_13}; 1676 u8 *hwinfo; 1677 1678 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); 1679 if (!hwinfo) 1680 return; 1681 1682 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) 1683 goto exit; 1684 1685 _rtl92ce_read_txpower_info_from_hwpg(hw, 1686 rtlefuse->autoload_failflag, 1687 hwinfo); 1688 1689 rtl8192ce_read_bt_coexist_info_from_hwpg(hw, 1690 rtlefuse->autoload_failflag, 1691 hwinfo); 1692 if (rtlhal->oem_id == RT_CID_DEFAULT) { 1693 switch (rtlefuse->eeprom_oemid) { 1694 case EEPROM_CID_DEFAULT: 1695 if (rtlefuse->eeprom_did == 0x8176) { 1696 if ((rtlefuse->eeprom_svid == 0x103C && 1697 rtlefuse->eeprom_smid == 0x1629)) 1698 rtlhal->oem_id = RT_CID_819X_HP; 1699 else 1700 rtlhal->oem_id = RT_CID_DEFAULT; 1701 } else { 1702 rtlhal->oem_id = RT_CID_DEFAULT; 1703 } 1704 break; 1705 case EEPROM_CID_TOSHIBA: 1706 rtlhal->oem_id = RT_CID_TOSHIBA; 1707 break; 1708 case EEPROM_CID_QMI: 1709 rtlhal->oem_id = RT_CID_819X_QMI; 1710 break; 1711 case EEPROM_CID_WHQL: 1712 default: 1713 rtlhal->oem_id = RT_CID_DEFAULT; 1714 break; 1715 } 1716 } 1717 exit: 1718 kfree(hwinfo); 1719 } 1720 1721 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw) 1722 { 1723 struct rtl_priv *rtlpriv = rtl_priv(hw); 1724 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1725 1726 switch (rtlhal->oem_id) { 1727 case RT_CID_819X_HP: 1728 rtlpriv->ledctl.led_opendrain = true; 1729 break; 1730 case RT_CID_819X_LENOVO: 1731 case RT_CID_DEFAULT: 1732 case RT_CID_TOSHIBA: 1733 case RT_CID_CCX: 1734 case RT_CID_819X_ACER: 1735 case RT_CID_WHQL: 1736 default: 1737 break; 1738 } 1739 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1740 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); 1741 } 1742 1743 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw) 1744 { 1745 struct rtl_priv *rtlpriv = rtl_priv(hw); 1746 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 1747 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1748 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1749 u8 tmp_u1b; 1750 1751 rtlhal->version = _rtl92ce_read_chip_version(hw); 1752 if (get_rf_type(rtlphy) == RF_1T1R) 1753 rtlpriv->dm.rfpath_rxenable[0] = true; 1754 else 1755 rtlpriv->dm.rfpath_rxenable[0] = 1756 rtlpriv->dm.rfpath_rxenable[1] = true; 1757 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", 1758 rtlhal->version); 1759 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 1760 if (tmp_u1b & BIT(4)) { 1761 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); 1762 rtlefuse->epromtype = EEPROM_93C46; 1763 } else { 1764 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); 1765 rtlefuse->epromtype = EEPROM_BOOT_EFUSE; 1766 } 1767 if (tmp_u1b & BIT(5)) { 1768 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); 1769 rtlefuse->autoload_failflag = false; 1770 _rtl92ce_read_adapter_info(hw); 1771 } else { 1772 pr_err("Autoload ERR!!\n"); 1773 } 1774 _rtl92ce_hal_customized_behavior(hw); 1775 } 1776 1777 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw, 1778 struct ieee80211_sta *sta) 1779 { 1780 struct rtl_priv *rtlpriv = rtl_priv(hw); 1781 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1782 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1783 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1784 u32 ratr_value; 1785 u8 ratr_index = 0; 1786 u8 nmode = mac->ht_enable; 1787 u16 shortgi_rate; 1788 u32 tmp_ratr_value; 1789 u8 curtxbw_40mhz = mac->bw_40; 1790 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? 1791 1 : 0; 1792 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1793 1 : 0; 1794 enum wireless_mode wirelessmode = mac->mode; 1795 u32 ratr_mask; 1796 1797 if (rtlhal->current_bandtype == BAND_ON_5G) 1798 ratr_value = sta->supp_rates[1] << 4; 1799 else 1800 ratr_value = sta->supp_rates[0]; 1801 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1802 ratr_value = 0xfff; 1803 1804 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1805 sta->ht_cap.mcs.rx_mask[0] << 12); 1806 switch (wirelessmode) { 1807 case WIRELESS_MODE_B: 1808 if (ratr_value & 0x0000000c) 1809 ratr_value &= 0x0000000d; 1810 else 1811 ratr_value &= 0x0000000f; 1812 break; 1813 case WIRELESS_MODE_G: 1814 ratr_value &= 0x00000FF5; 1815 break; 1816 case WIRELESS_MODE_N_24G: 1817 case WIRELESS_MODE_N_5G: 1818 nmode = 1; 1819 if (get_rf_type(rtlphy) == RF_1T2R || 1820 get_rf_type(rtlphy) == RF_1T1R) 1821 ratr_mask = 0x000ff005; 1822 else 1823 ratr_mask = 0x0f0ff005; 1824 1825 ratr_value &= ratr_mask; 1826 break; 1827 default: 1828 if (rtlphy->rf_type == RF_1T2R) 1829 ratr_value &= 0x000ff0ff; 1830 else 1831 ratr_value &= 0x0f0ff0ff; 1832 1833 break; 1834 } 1835 1836 if ((rtlpriv->btcoexist.bt_coexistence) && 1837 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) && 1838 (rtlpriv->btcoexist.bt_cur_state) && 1839 (rtlpriv->btcoexist.bt_ant_isolation) && 1840 ((rtlpriv->btcoexist.bt_service == BT_SCO) || 1841 (rtlpriv->btcoexist.bt_service == BT_BUSY))) 1842 ratr_value &= 0x0fffcfc0; 1843 else 1844 ratr_value &= 0x0FFFFFFF; 1845 1846 if (nmode && ((curtxbw_40mhz && 1847 curshortgi_40mhz) || (!curtxbw_40mhz && 1848 curshortgi_20mhz))) { 1849 1850 ratr_value |= 0x10000000; 1851 tmp_ratr_value = (ratr_value >> 12); 1852 1853 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { 1854 if ((1 << shortgi_rate) & tmp_ratr_value) 1855 break; 1856 } 1857 1858 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | 1859 (shortgi_rate << 4) | (shortgi_rate); 1860 } 1861 1862 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); 1863 1864 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", 1865 rtl_read_dword(rtlpriv, REG_ARFR0)); 1866 } 1867 1868 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw, 1869 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) 1870 { 1871 struct rtl_priv *rtlpriv = rtl_priv(hw); 1872 struct rtl_phy *rtlphy = &(rtlpriv->phy); 1873 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1874 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1875 struct rtl_sta_info *sta_entry = NULL; 1876 u32 ratr_bitmap; 1877 u8 ratr_index; 1878 u8 curtxbw_40mhz = (sta->ht_cap.cap & 1879 IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0; 1880 u8 curshortgi_40mhz = (sta->ht_cap.cap & 1881 IEEE80211_HT_CAP_SGI_40) ? 1 : 0; 1882 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? 1883 1 : 0; 1884 enum wireless_mode wirelessmode = 0; 1885 bool shortgi = false; 1886 u8 rate_mask[5]; 1887 u8 macid = 0; 1888 1889 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 1890 wirelessmode = sta_entry->wireless_mode; 1891 if (mac->opmode == NL80211_IFTYPE_STATION || 1892 mac->opmode == NL80211_IFTYPE_MESH_POINT) 1893 curtxbw_40mhz = mac->bw_40; 1894 else if (mac->opmode == NL80211_IFTYPE_AP || 1895 mac->opmode == NL80211_IFTYPE_ADHOC) 1896 macid = sta->aid + 1; 1897 1898 if (rtlhal->current_bandtype == BAND_ON_5G) 1899 ratr_bitmap = sta->supp_rates[1] << 4; 1900 else 1901 ratr_bitmap = sta->supp_rates[0]; 1902 if (mac->opmode == NL80211_IFTYPE_ADHOC) 1903 ratr_bitmap = 0xfff; 1904 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | 1905 sta->ht_cap.mcs.rx_mask[0] << 12); 1906 switch (wirelessmode) { 1907 case WIRELESS_MODE_B: 1908 ratr_index = RATR_INX_WIRELESS_B; 1909 if (ratr_bitmap & 0x0000000c) 1910 ratr_bitmap &= 0x0000000d; 1911 else 1912 ratr_bitmap &= 0x0000000f; 1913 break; 1914 case WIRELESS_MODE_G: 1915 ratr_index = RATR_INX_WIRELESS_GB; 1916 1917 if (rssi_level == 1) 1918 ratr_bitmap &= 0x00000f00; 1919 else if (rssi_level == 2) 1920 ratr_bitmap &= 0x00000ff0; 1921 else 1922 ratr_bitmap &= 0x00000ff5; 1923 break; 1924 case WIRELESS_MODE_A: 1925 ratr_index = RATR_INX_WIRELESS_A; 1926 ratr_bitmap &= 0x00000ff0; 1927 break; 1928 case WIRELESS_MODE_N_24G: 1929 case WIRELESS_MODE_N_5G: 1930 ratr_index = RATR_INX_WIRELESS_NGB; 1931 1932 if (rtlphy->rf_type == RF_1T2R || 1933 rtlphy->rf_type == RF_1T1R) { 1934 if (curtxbw_40mhz) { 1935 if (rssi_level == 1) 1936 ratr_bitmap &= 0x000f0000; 1937 else if (rssi_level == 2) 1938 ratr_bitmap &= 0x000ff000; 1939 else 1940 ratr_bitmap &= 0x000ff015; 1941 } else { 1942 if (rssi_level == 1) 1943 ratr_bitmap &= 0x000f0000; 1944 else if (rssi_level == 2) 1945 ratr_bitmap &= 0x000ff000; 1946 else 1947 ratr_bitmap &= 0x000ff005; 1948 } 1949 } else { 1950 if (curtxbw_40mhz) { 1951 if (rssi_level == 1) 1952 ratr_bitmap &= 0x0f0f0000; 1953 else if (rssi_level == 2) 1954 ratr_bitmap &= 0x0f0ff000; 1955 else 1956 ratr_bitmap &= 0x0f0ff015; 1957 } else { 1958 if (rssi_level == 1) 1959 ratr_bitmap &= 0x0f0f0000; 1960 else if (rssi_level == 2) 1961 ratr_bitmap &= 0x0f0ff000; 1962 else 1963 ratr_bitmap &= 0x0f0ff005; 1964 } 1965 } 1966 1967 if ((curtxbw_40mhz && curshortgi_40mhz) || 1968 (!curtxbw_40mhz && curshortgi_20mhz)) { 1969 1970 if (macid == 0) 1971 shortgi = true; 1972 else if (macid == 1) 1973 shortgi = false; 1974 } 1975 break; 1976 default: 1977 ratr_index = RATR_INX_WIRELESS_NGB; 1978 1979 if (rtlphy->rf_type == RF_1T2R) 1980 ratr_bitmap &= 0x000ff0ff; 1981 else 1982 ratr_bitmap &= 0x0f0ff0ff; 1983 break; 1984 } 1985 sta_entry->ratr_index = ratr_index; 1986 1987 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 1988 "ratr_bitmap :%x\n", ratr_bitmap); 1989 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | 1990 (ratr_index << 28); 1991 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; 1992 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 1993 "Rate_index:%x, ratr_val:%x, %5phC\n", 1994 ratr_index, ratr_bitmap, rate_mask); 1995 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask); 1996 } 1997 1998 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw, 1999 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) 2000 { 2001 struct rtl_priv *rtlpriv = rtl_priv(hw); 2002 2003 if (rtlpriv->dm.useramask) 2004 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level, update_bw); 2005 else 2006 rtl92ce_update_hal_rate_table(hw, sta); 2007 } 2008 2009 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw) 2010 { 2011 struct rtl_priv *rtlpriv = rtl_priv(hw); 2012 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2013 u16 sifs_timer; 2014 2015 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, 2016 &mac->slot_time); 2017 if (!mac->ht_enable) 2018 sifs_timer = 0x0a0a; 2019 else 2020 sifs_timer = 0x1010; 2021 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); 2022 } 2023 2024 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) 2025 { 2026 struct rtl_priv *rtlpriv = rtl_priv(hw); 2027 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2028 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2029 enum rf_pwrstate e_rfpowerstate_toset; 2030 u8 u1tmp; 2031 bool actuallyset = false; 2032 unsigned long flag; 2033 2034 if (rtlpci->being_init_adapter) 2035 return false; 2036 2037 if (ppsc->swrf_processing) 2038 return false; 2039 2040 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2041 if (ppsc->rfchange_inprogress) { 2042 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2043 return false; 2044 } else { 2045 ppsc->rfchange_inprogress = true; 2046 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2047 } 2048 2049 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv, 2050 REG_MAC_PINMUX_CFG)&~(BIT(3))); 2051 2052 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); 2053 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; 2054 2055 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { 2056 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2057 "GPIOChangeRF - HW Radio ON, RF ON\n"); 2058 2059 e_rfpowerstate_toset = ERFON; 2060 ppsc->hwradiooff = false; 2061 actuallyset = true; 2062 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) { 2063 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2064 "GPIOChangeRF - HW Radio OFF, RF OFF\n"); 2065 2066 e_rfpowerstate_toset = ERFOFF; 2067 ppsc->hwradiooff = true; 2068 actuallyset = true; 2069 } 2070 2071 if (actuallyset) { 2072 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2073 ppsc->rfchange_inprogress = false; 2074 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2075 } else { 2076 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) 2077 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); 2078 2079 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 2080 ppsc->rfchange_inprogress = false; 2081 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2082 } 2083 2084 *valid = 1; 2085 return !ppsc->hwradiooff; 2086 2087 } 2088 2089 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index, 2090 u8 *p_macaddr, bool is_group, u8 enc_algo, 2091 bool is_wepkey, bool clear_all) 2092 { 2093 struct rtl_priv *rtlpriv = rtl_priv(hw); 2094 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 2095 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 2096 u8 *macaddr = p_macaddr; 2097 u32 entry_id = 0; 2098 bool is_pairwise = false; 2099 2100 static u8 cam_const_addr[4][6] = { 2101 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 2102 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, 2103 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, 2104 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} 2105 }; 2106 static u8 cam_const_broad[] = { 2107 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2108 }; 2109 2110 if (clear_all) { 2111 u8 idx = 0; 2112 u8 cam_offset = 0; 2113 u8 clear_number = 5; 2114 2115 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); 2116 2117 for (idx = 0; idx < clear_number; idx++) { 2118 rtl_cam_mark_invalid(hw, cam_offset + idx); 2119 rtl_cam_empty_entry(hw, cam_offset + idx); 2120 2121 if (idx < 5) { 2122 memset(rtlpriv->sec.key_buf[idx], 0, 2123 MAX_KEY_LEN); 2124 rtlpriv->sec.key_len[idx] = 0; 2125 } 2126 } 2127 2128 } else { 2129 switch (enc_algo) { 2130 case WEP40_ENCRYPTION: 2131 enc_algo = CAM_WEP40; 2132 break; 2133 case WEP104_ENCRYPTION: 2134 enc_algo = CAM_WEP104; 2135 break; 2136 case TKIP_ENCRYPTION: 2137 enc_algo = CAM_TKIP; 2138 break; 2139 case AESCCMP_ENCRYPTION: 2140 enc_algo = CAM_AES; 2141 break; 2142 default: 2143 pr_err("switch case %#x not processed\n", 2144 enc_algo); 2145 enc_algo = CAM_TKIP; 2146 break; 2147 } 2148 2149 if (is_wepkey || rtlpriv->sec.use_defaultkey) { 2150 macaddr = cam_const_addr[key_index]; 2151 entry_id = key_index; 2152 } else { 2153 if (is_group) { 2154 macaddr = cam_const_broad; 2155 entry_id = key_index; 2156 } else { 2157 if (mac->opmode == NL80211_IFTYPE_AP || 2158 mac->opmode == NL80211_IFTYPE_MESH_POINT) { 2159 entry_id = rtl_cam_get_free_entry(hw, 2160 p_macaddr); 2161 if (entry_id >= TOTAL_CAM_ENTRY) { 2162 pr_err("Can not find free hw security cam entry\n"); 2163 return; 2164 } 2165 } else { 2166 entry_id = CAM_PAIRWISE_KEY_POSITION; 2167 } 2168 2169 key_index = PAIRWISE_KEYIDX; 2170 is_pairwise = true; 2171 } 2172 } 2173 2174 if (rtlpriv->sec.key_len[key_index] == 0) { 2175 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2176 "delete one entry, entry_id is %d\n", 2177 entry_id); 2178 if (mac->opmode == NL80211_IFTYPE_AP || 2179 mac->opmode == NL80211_IFTYPE_MESH_POINT) 2180 rtl_cam_del_entry(hw, p_macaddr); 2181 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); 2182 } else { 2183 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 2184 "The insert KEY length is %d\n", 2185 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); 2186 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, 2187 "The insert KEY is %x %x\n", 2188 rtlpriv->sec.key_buf[0][0], 2189 rtlpriv->sec.key_buf[0][1]); 2190 2191 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2192 "add one entry\n"); 2193 if (is_pairwise) { 2194 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, 2195 "Pairwise Key content", 2196 rtlpriv->sec.pairwise_key, 2197 rtlpriv->sec. 2198 key_len[PAIRWISE_KEYIDX]); 2199 2200 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2201 "set Pairwise key\n"); 2202 2203 rtl_cam_add_one_entry(hw, macaddr, key_index, 2204 entry_id, enc_algo, 2205 CAM_CONFIG_NO_USEDK, 2206 rtlpriv->sec. 2207 key_buf[key_index]); 2208 } else { 2209 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 2210 "set group key\n"); 2211 2212 if (mac->opmode == NL80211_IFTYPE_ADHOC) { 2213 rtl_cam_add_one_entry(hw, 2214 rtlefuse->dev_addr, 2215 PAIRWISE_KEYIDX, 2216 CAM_PAIRWISE_KEY_POSITION, 2217 enc_algo, 2218 CAM_CONFIG_NO_USEDK, 2219 rtlpriv->sec.key_buf 2220 [entry_id]); 2221 } 2222 2223 rtl_cam_add_one_entry(hw, macaddr, key_index, 2224 entry_id, enc_algo, 2225 CAM_CONFIG_NO_USEDK, 2226 rtlpriv->sec.key_buf[entry_id]); 2227 } 2228 2229 } 2230 } 2231 } 2232 2233 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw) 2234 { 2235 struct rtl_priv *rtlpriv = rtl_priv(hw); 2236 2237 rtlpriv->btcoexist.bt_coexistence = 2238 rtlpriv->btcoexist.eeprom_bt_coexist; 2239 rtlpriv->btcoexist.bt_ant_num = 2240 rtlpriv->btcoexist.eeprom_bt_ant_num; 2241 rtlpriv->btcoexist.bt_coexist_type = 2242 rtlpriv->btcoexist.eeprom_bt_type; 2243 2244 if (rtlpriv->btcoexist.reg_bt_iso == 2) 2245 rtlpriv->btcoexist.bt_ant_isolation = 2246 rtlpriv->btcoexist.eeprom_bt_ant_isol; 2247 else 2248 rtlpriv->btcoexist.bt_ant_isolation = 2249 rtlpriv->btcoexist.reg_bt_iso; 2250 2251 rtlpriv->btcoexist.bt_radio_shared_type = 2252 rtlpriv->btcoexist.eeprom_bt_radio_shared; 2253 2254 if (rtlpriv->btcoexist.bt_coexistence) { 2255 if (rtlpriv->btcoexist.reg_bt_sco == 1) 2256 rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION; 2257 else if (rtlpriv->btcoexist.reg_bt_sco == 2) 2258 rtlpriv->btcoexist.bt_service = BT_SCO; 2259 else if (rtlpriv->btcoexist.reg_bt_sco == 4) 2260 rtlpriv->btcoexist.bt_service = BT_BUSY; 2261 else if (rtlpriv->btcoexist.reg_bt_sco == 5) 2262 rtlpriv->btcoexist.bt_service = BT_OTHERBUSY; 2263 else 2264 rtlpriv->btcoexist.bt_service = BT_IDLE; 2265 2266 rtlpriv->btcoexist.bt_edca_ul = 0; 2267 rtlpriv->btcoexist.bt_edca_dl = 0; 2268 rtlpriv->btcoexist.bt_rssi_state = 0xff; 2269 } 2270 } 2271 2272 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, 2273 bool auto_load_fail, u8 *hwinfo) 2274 { 2275 struct rtl_priv *rtlpriv = rtl_priv(hw); 2276 u8 val; 2277 2278 if (!auto_load_fail) { 2279 rtlpriv->btcoexist.eeprom_bt_coexist = 2280 ((hwinfo[RF_OPTION1] & 0xe0) >> 5); 2281 val = hwinfo[RF_OPTION4]; 2282 rtlpriv->btcoexist.eeprom_bt_type = ((val & 0xe) >> 1); 2283 rtlpriv->btcoexist.eeprom_bt_ant_num = (val & 0x1); 2284 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4); 2285 rtlpriv->btcoexist.eeprom_bt_radio_shared = 2286 ((val & 0x20) >> 5); 2287 } else { 2288 rtlpriv->btcoexist.eeprom_bt_coexist = 0; 2289 rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE; 2290 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2; 2291 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0; 2292 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED; 2293 } 2294 2295 rtl8192ce_bt_var_init(hw); 2296 } 2297 2298 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw) 2299 { 2300 struct rtl_priv *rtlpriv = rtl_priv(hw); 2301 2302 /* 0:Low, 1:High, 2:From Efuse. */ 2303 rtlpriv->btcoexist.reg_bt_iso = 2; 2304 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ 2305 rtlpriv->btcoexist.reg_bt_sco = 3; 2306 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ 2307 rtlpriv->btcoexist.reg_bt_sco = 0; 2308 } 2309 2310 2311 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw) 2312 { 2313 struct rtl_priv *rtlpriv = rtl_priv(hw); 2314 struct rtl_phy *rtlphy = &(rtlpriv->phy); 2315 2316 u8 u1_tmp; 2317 2318 if (rtlpriv->btcoexist.bt_coexistence && 2319 ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) || 2320 rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) { 2321 2322 if (rtlpriv->btcoexist.bt_ant_isolation) 2323 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0); 2324 2325 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) & 2326 BIT_OFFSET_LEN_MASK_32(0, 1); 2327 u1_tmp = u1_tmp | 2328 ((rtlpriv->btcoexist.bt_ant_isolation == 1) ? 2329 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) | 2330 ((rtlpriv->btcoexist.bt_service == BT_SCO) ? 2331 0 : BIT_OFFSET_LEN_MASK_32(2, 1)); 2332 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp); 2333 2334 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa); 2335 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040); 2336 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010); 2337 2338 /* Config to 1T1R. */ 2339 if (rtlphy->rf_type == RF_1T1R) { 2340 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE); 2341 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1)); 2342 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp); 2343 2344 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE); 2345 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1)); 2346 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp); 2347 } 2348 } 2349 } 2350 2351 void rtl92ce_suspend(struct ieee80211_hw *hw) 2352 { 2353 } 2354 2355 void rtl92ce_resume(struct ieee80211_hw *hw) 2356 { 2357 } 2358